1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
9 * @hw: pointer to the HW struct
10 * @module_typeid: module pointer location in words from the NVM beginning
11 * @offset: byte offset from the module beginning
12 * @length: length of the section to be read (in bytes from the offset)
13 * @data: command buffer (size [bytes] = length)
14 * @last_command: tells if this is the last command in a series
15 * @read_shadow_ram: tell if this is a shadow RAM read
16 * @cd: pointer to command details structure or NULL
18 * Read the NVM using the admin queue commands (0x0701)
21 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
22 void *data, bool last_command, bool read_shadow_ram,
25 struct ice_aq_desc desc;
26 struct ice_aqc_nvm *cmd;
28 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
30 cmd = &desc.params.nvm;
32 if (offset > ICE_AQC_NVM_MAX_OFFSET)
35 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
37 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
38 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
40 /* If this is the last command in a series, set the proper flag. */
42 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
43 cmd->module_typeid = CPU_TO_LE16(module_typeid);
44 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
45 cmd->offset_high = (offset >> 16) & 0xFF;
46 cmd->length = CPU_TO_LE16(length);
48 return ice_aq_send_cmd(hw, &desc, data, length, cd);
52 * ice_read_flat_nvm - Read portion of NVM by flat offset
53 * @hw: pointer to the HW struct
54 * @offset: offset from beginning of NVM
55 * @length: (in) number of bytes to read; (out) number of bytes actually read
56 * @data: buffer to return data in (sized to fit the specified length)
57 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
59 * Reads a portion of the NVM, as a flat memory space. This function correctly
60 * breaks read requests across Shadow RAM sectors and ensures that no single
61 * read request exceeds the maximum 4KB read for a single AdminQ command.
63 * Returns a status code on failure. Note that the data pointer may be
64 * partially updated if some reads succeed before a failure.
67 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
70 enum ice_status status;
75 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
79 /* Verify the length of the read if this is for the Shadow RAM */
80 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) {
81 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested data is beyond Shadow RAM limit\n");
86 u32 read_size, sector_offset;
88 /* ice_aq_read_nvm cannot read more than 4KB at a time.
89 * Additionally, a read from the Shadow RAM may not cross over
90 * a sector boundary. Conveniently, the sector size is also
93 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
94 read_size = MIN_T(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
97 last_cmd = !(bytes_read + read_size < inlen);
99 /* ice_aq_read_nvm takes the length as a u16. Our read_size is
100 * calculated using a u32, but the ICE_AQ_MAX_BUF_LEN maximum
101 * size guarantees that it will fit within the 2 bytes.
103 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
104 offset, (u16)read_size,
105 data + bytes_read, last_cmd,
106 read_shadow_ram, NULL);
110 bytes_read += read_size;
114 *length = bytes_read;
119 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
120 * @hw: pointer to the HW structure
121 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
122 * @data: word read from the Shadow RAM
124 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
126 static enum ice_status
127 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
129 u32 bytes = sizeof(u16);
130 enum ice_status status;
133 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
135 /* Note that ice_read_flat_nvm checks if the read is past the Shadow
136 * RAM size, and ensures we don't read across a Shadow RAM sector
139 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
140 (_FORCE_ u8 *)&data_local, true);
144 *data = LE16_TO_CPU(data_local);
149 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
150 * @hw: pointer to the HW structure
151 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
152 * @words: (in) number of words to read; (out) number of words actually read
153 * @data: words read from the Shadow RAM
155 * Reads 16 bit words (data buf) from the Shadow RAM. Ownership of the NVM is
156 * taken before reading the buffer and later released.
158 static enum ice_status
159 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
161 u32 bytes = *words * 2, i;
162 enum ice_status status;
164 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
166 /* ice_read_flat_nvm takes into account the 4KB AdminQ and Shadow RAM
167 * sector restrictions necessary when reading from the NVM.
169 status = ice_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true);
171 /* Report the number of words successfully read */
174 /* Byte swap the words up to the amount we actually read */
175 for (i = 0; i < *words; i++)
176 data[i] = LE16_TO_CPU(((_FORCE_ __le16 *)data)[i]);
182 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
183 * @hw: pointer to the HW structure
184 * @access: NVM access type (read or write)
186 * This function will request NVM ownership.
189 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
191 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
193 if (hw->flash.blank_nvm_mode)
196 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
200 * ice_release_nvm - Generic request for releasing the NVM ownership
201 * @hw: pointer to the HW structure
203 * This function will release NVM ownership.
205 void ice_release_nvm(struct ice_hw *hw)
207 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
209 if (hw->flash.blank_nvm_mode)
212 ice_release_res(hw, ICE_NVM_RES_ID);
216 * ice_get_flash_bank_offset - Get offset into requested flash bank
217 * @hw: pointer to the HW structure
218 * @bank: whether to read from the active or inactive flash bank
219 * @module: the module to read from
221 * Based on the module, lookup the module offset from the beginning of the
224 * Returns the flash offset. Note that a value of zero is invalid and must be
225 * treated as an error.
227 static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
229 struct ice_bank_info *banks = &hw->flash.banks;
230 enum ice_flash_bank active_bank;
231 bool second_bank_active;
235 case ICE_SR_1ST_NVM_BANK_PTR:
236 offset = banks->nvm_ptr;
237 size = banks->nvm_size;
238 active_bank = banks->nvm_bank;
240 case ICE_SR_1ST_OROM_BANK_PTR:
241 offset = banks->orom_ptr;
242 size = banks->orom_size;
243 active_bank = banks->orom_bank;
245 case ICE_SR_NETLIST_BANK_PTR:
246 offset = banks->netlist_ptr;
247 size = banks->netlist_size;
248 active_bank = banks->netlist_bank;
251 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module);
255 switch (active_bank) {
256 case ICE_1ST_FLASH_BANK:
257 second_bank_active = false;
259 case ICE_2ND_FLASH_BANK:
260 second_bank_active = true;
263 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n",
268 /* The second flash bank is stored immediately following the first
269 * bank. Based on whether the 1st or 2nd bank is active, and whether
270 * we want the active or inactive bank, calculate the desired offset.
273 case ICE_ACTIVE_FLASH_BANK:
274 return offset + (second_bank_active ? size : 0);
275 case ICE_INACTIVE_FLASH_BANK:
276 return offset + (second_bank_active ? 0 : size);
279 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);
284 * ice_read_flash_module - Read a word from one of the main NVM modules
285 * @hw: pointer to the HW structure
286 * @bank: which bank of the module to read
287 * @module: the module to read
288 * @offset: the offset into the module in words
289 * @data: storage for the word read from the flash
291 * Read data from the specified flash module. The bank parameter indicates
292 * whether or not to read from the active bank or the inactive bank of that
295 * The word will be read using flat NVM access, and relies on the
296 * hw->flash.banks data being setup by ice_determine_active_flash_banks()
297 * during initialization.
299 static enum ice_status
300 ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,
301 u32 offset, u16 *data)
303 u32 bytes = sizeof(u16);
304 enum ice_status status;
308 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
310 start = ice_get_flash_bank_offset(hw, bank, module);
312 ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n",
314 return ICE_ERR_PARAM;
317 status = ice_acquire_nvm(hw, ICE_RES_READ);
321 status = ice_read_flat_nvm(hw, start + offset * sizeof(u16), &bytes,
322 (_FORCE_ u8 *)&data_local, false);
324 *data = LE16_TO_CPU(data_local);
332 * ice_read_nvm_module - Read from the active main NVM module
333 * @hw: pointer to the HW structure
334 * @bank: whether to read from active or inactive NVM module
335 * @offset: offset into the NVM module to read, in words
336 * @data: storage for returned word value
338 * Read the specified word from the active NVM module. This includes the CSS
339 * header at the start of the NVM module.
341 static enum ice_status
342 ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
344 return ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset, data);
348 * ice_read_orom_module - Read from the active Option ROM module
349 * @hw: pointer to the HW structure
350 * @bank: whether to read from active or inactive OROM module
351 * @offset: offset into the OROM module to read, in words
352 * @data: storage for returned word value
354 * Read the specified word from the active Option ROM module of the flash.
355 * Note that unlike the NVM module, the CSS data is stored at the end of the
356 * module instead of at the beginning.
358 static enum ice_status
359 ice_read_orom_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
361 return ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, offset, data);
365 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
366 * @hw: pointer to the HW structure
367 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
368 * @data: word read from the Shadow RAM
370 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
372 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
374 enum ice_status status;
376 status = ice_acquire_nvm(hw, ICE_RES_READ);
378 status = ice_read_sr_word_aq(hw, offset, data);
386 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
387 * @hw: pointer to hardware structure
388 * @module_tlv: pointer to module TLV to return
389 * @module_tlv_len: pointer to module TLV length to return
390 * @module_type: module type requested
392 * Finds the requested sub module TLV type from the Preserved Field
393 * Area (PFA) and returns the TLV pointer and length. The caller can
394 * use these to read the variable length TLV value.
397 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
400 enum ice_status status;
401 u16 pfa_len, pfa_ptr;
404 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
405 if (status != ICE_SUCCESS) {
406 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
409 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
410 if (status != ICE_SUCCESS) {
411 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
414 /* Starting with first TLV after PFA length, iterate through the list
415 * of TLVs to find the requested one.
417 next_tlv = pfa_ptr + 1;
418 while (next_tlv < pfa_ptr + pfa_len) {
419 u16 tlv_sub_module_type;
423 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
424 if (status != ICE_SUCCESS) {
425 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
428 /* Read TLV length */
429 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
430 if (status != ICE_SUCCESS) {
431 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
434 if (tlv_sub_module_type == module_type) {
436 *module_tlv = next_tlv;
437 *module_tlv_len = tlv_len;
440 return ICE_ERR_INVAL_SIZE;
442 /* Check next TLV, i.e. current TLV pointer + length + 2 words
443 * (for current TLV's type and length)
445 next_tlv = next_tlv + tlv_len + 2;
447 /* Module does not exist */
448 return ICE_ERR_DOES_NOT_EXIST;
452 * ice_read_pba_string - Reads part number string from NVM
453 * @hw: pointer to hardware structure
454 * @pba_num: stores the part number string from the NVM
455 * @pba_num_size: part number string buffer length
457 * Reads the part number string from the NVM.
460 ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
462 u16 pba_tlv, pba_tlv_len;
463 enum ice_status status;
464 u16 pba_word, pba_size;
467 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
468 ICE_SR_PBA_BLOCK_PTR);
469 if (status != ICE_SUCCESS) {
470 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
474 /* pba_size is the next word */
475 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
476 if (status != ICE_SUCCESS) {
477 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
481 if (pba_tlv_len < pba_size) {
482 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
483 return ICE_ERR_INVAL_SIZE;
486 /* Subtract one to get PBA word count (PBA Size word is included in
490 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
491 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
492 return ICE_ERR_PARAM;
495 for (i = 0; i < pba_size; i++) {
496 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
497 if (status != ICE_SUCCESS) {
498 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
502 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
503 pba_num[(i * 2) + 1] = pba_word & 0xFF;
505 pba_num[(pba_size * 2)] = '\0';
511 * ice_get_nvm_srev - Read the security revision from the NVM CSS header
512 * @hw: pointer to the HW struct
513 * @bank: whether to read from the active or inactive flash bank
514 * @srev: storage for security revision
516 * Read the security revision out of the CSS header of the active NVM module
519 static enum ice_status ice_get_nvm_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)
521 enum ice_status status;
524 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_L, &srev_l);
528 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_H, &srev_h);
532 *srev = srev_h << 16 | srev_l;
538 * ice_get_nvm_ver_info - Read NVM version information
539 * @hw: pointer to the HW struct
540 * @nvm: pointer to NVM info structure
542 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling
543 * in the nvm info structure.
545 static enum ice_status
546 ice_get_nvm_ver_info(struct ice_hw *hw, struct ice_nvm_info *nvm)
548 u16 eetrack_lo, eetrack_hi, ver;
549 enum ice_status status;
551 status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &ver);
553 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
556 nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
557 nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
559 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
561 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
564 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
566 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
570 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
572 status = ice_get_nvm_srev(hw, ICE_ACTIVE_FLASH_BANK, &nvm->srev);
574 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM security revision.\n");
580 * ice_get_orom_srev - Read the security revision from the OROM CSS header
581 * @hw: pointer to the HW struct
582 * @bank: whether to read from active or inactive flash module
583 * @srev: storage for security revision
585 * Read the security revision out of the CSS header of the active OROM module
588 static enum ice_status ice_get_orom_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)
590 enum ice_status status;
594 if (hw->flash.banks.orom_size < ICE_NVM_OROM_TRAILER_LENGTH) {
595 ice_debug(hw, ICE_DBG_NVM, "Unexpected Option ROM Size of %u\n",
596 hw->flash.banks.orom_size);
600 /* calculate how far into the Option ROM the CSS header starts. Note
601 * that ice_read_orom_module takes a word offset so we need to
604 css_start = (hw->flash.banks.orom_size - ICE_NVM_OROM_TRAILER_LENGTH) / 2;
606 status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_L, &srev_l);
610 status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_H, &srev_h);
614 *srev = srev_h << 16 | srev_l;
620 * ice_get_orom_ver_info - Read Option ROM version information
621 * @hw: pointer to the HW struct
622 * @orom: pointer to Option ROM info structure
624 * Read the Combo Image version data from the Boot Configuration TLV and fill
625 * in the option ROM version data.
627 static enum ice_status
628 ice_get_orom_ver_info(struct ice_hw *hw, struct ice_orom_info *orom)
630 u16 combo_hi, combo_lo, boot_cfg_tlv, boot_cfg_tlv_len;
631 enum ice_status status;
634 status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len,
635 ICE_SR_BOOT_CFG_PTR);
637 ice_debug(hw, ICE_DBG_INIT, "Failed to read Boot Configuration Block TLV.\n");
641 /* Boot Configuration Block must have length at least 2 words
642 * (Combo Image Version High and Combo Image Version Low)
644 if (boot_cfg_tlv_len < 2) {
645 ice_debug(hw, ICE_DBG_INIT, "Invalid Boot Configuration Block TLV size.\n");
646 return ICE_ERR_INVAL_SIZE;
649 status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OROM_VER_OFF),
652 ice_debug(hw, ICE_DBG_INIT, "Failed to read OROM_VER hi.\n");
656 status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OROM_VER_OFF + 1),
659 ice_debug(hw, ICE_DBG_INIT, "Failed to read OROM_VER lo.\n");
663 combo_ver = ((u32)combo_hi << 16) | combo_lo;
665 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >>
667 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK);
668 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >>
669 ICE_OROM_VER_BUILD_SHIFT);
671 status = ice_get_orom_srev(hw, ICE_ACTIVE_FLASH_BANK, &orom->srev);
673 ice_debug(hw, ICE_DBG_NVM, "Failed to read Option ROM security revision.\n");
679 * ice_discover_flash_size - Discover the available flash size.
680 * @hw: pointer to the HW struct
682 * The device flash could be up to 16MB in size. However, it is possible that
683 * the actual size is smaller. Use bisection to determine the accessible size
686 static enum ice_status ice_discover_flash_size(struct ice_hw *hw)
688 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
689 enum ice_status status;
691 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
693 status = ice_acquire_nvm(hw, ICE_RES_READ);
697 while ((max_size - min_size) > 1) {
698 u32 offset = (max_size + min_size) / 2;
702 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
703 if (status == ICE_ERR_AQ_ERROR &&
704 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
705 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
707 status = ICE_SUCCESS;
709 } else if (!status) {
710 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
714 /* an unexpected error occurred */
715 goto err_read_flat_nvm;
719 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
721 hw->flash.flash_size = max_size;
730 * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word
731 * @hw: pointer to the HW structure
732 * @offset: the word offset of the Shadow RAM word to read
733 * @pointer: pointer value read from Shadow RAM
735 * Read the given Shadow RAM word, and convert it to a pointer value specified
736 * in bytes. This function assumes the specified offset is a valid pointer
739 * Each pointer word specifies whether it is stored in word size or 4KB
740 * sector size by using the highest bit. The reported pointer value will be in
741 * bytes, intended for flat NVM reads.
743 static enum ice_status
744 ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
746 enum ice_status status;
749 status = ice_read_sr_word(hw, offset, &value);
753 /* Determine if the pointer is in 4KB or word units */
754 if (value & ICE_SR_NVM_PTR_4KB_UNITS)
755 *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;
757 *pointer = value * 2;
763 * ice_read_sr_area_size - Read an area size from a Shadow RAM word
764 * @hw: pointer to the HW structure
765 * @offset: the word offset of the Shadow RAM to read
766 * @size: size value read from the Shadow RAM
768 * Read the given Shadow RAM word, and convert it to an area size value
769 * specified in bytes. This function assumes the specified offset is a valid
772 * Each area size word is specified in 4KB sector units. This function reports
773 * the size in bytes, intended for flat NVM reads.
775 static enum ice_status
776 ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
778 enum ice_status status;
781 status = ice_read_sr_word(hw, offset, &value);
785 /* Area sizes are always specified in 4KB units */
786 *size = value * 4 * 1024;
792 * ice_determine_active_flash_banks - Discover active bank for each module
793 * @hw: pointer to the HW struct
795 * Read the Shadow RAM control word and determine which banks are active for
796 * the NVM, OROM, and Netlist modules. Also read and calculate the associated
797 * pointer and size. These values are then cached into the ice_flash_info
798 * structure for later use in order to calculate the correct offset to read
799 * from the active module.
801 static enum ice_status
802 ice_determine_active_flash_banks(struct ice_hw *hw)
804 struct ice_bank_info *banks = &hw->flash.banks;
805 enum ice_status status;
808 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
810 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
814 /* Check that the control word indicates validity */
815 if ((ctrl_word & ICE_SR_CTRL_WORD_1_M) >> ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) {
816 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
820 if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))
821 banks->nvm_bank = ICE_1ST_FLASH_BANK;
823 banks->nvm_bank = ICE_2ND_FLASH_BANK;
825 if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))
826 banks->orom_bank = ICE_1ST_FLASH_BANK;
828 banks->orom_bank = ICE_2ND_FLASH_BANK;
830 if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))
831 banks->netlist_bank = ICE_1ST_FLASH_BANK;
833 banks->netlist_bank = ICE_2ND_FLASH_BANK;
835 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
837 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
841 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
843 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
847 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
849 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
853 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
855 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
859 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
861 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
865 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
867 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
875 * ice_init_nvm - initializes NVM setting
876 * @hw: pointer to the HW struct
878 * This function reads and populates NVM settings such as Shadow RAM size,
879 * max_timeout, and blank_nvm_mode
881 enum ice_status ice_init_nvm(struct ice_hw *hw)
883 struct ice_flash_info *flash = &hw->flash;
884 enum ice_status status;
888 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
890 /* The SR size is stored regardless of the NVM programming mode
891 * as the blank mode may be used in the factory line.
893 gens_stat = rd32(hw, GLNVM_GENS);
894 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
896 /* Switching to words (sr_size contains power of 2) */
897 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
899 /* Check if we are in the normal or blank NVM programming mode */
900 fla = rd32(hw, GLNVM_FLA);
901 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
902 flash->blank_nvm_mode = false;
904 /* Blank programming mode */
905 flash->blank_nvm_mode = true;
906 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
907 return ICE_ERR_NVM_BLANK_MODE;
910 status = ice_discover_flash_size(hw);
912 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");
916 status = ice_determine_active_flash_banks(hw);
918 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
922 status = ice_get_nvm_ver_info(hw, &flash->nvm);
924 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
928 status = ice_get_orom_ver_info(hw, &flash->orom);
930 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
938 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
939 * @hw: pointer to the HW structure
940 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
941 * @words: (in) number of words to read; (out) number of words actually read
942 * @data: words read from the Shadow RAM
944 * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
945 * method. The buf read is preceded by the NVM ownership take
946 * and followed by the release.
949 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
951 enum ice_status status;
953 status = ice_acquire_nvm(hw, ICE_RES_READ);
955 status = ice_read_sr_buf_aq(hw, offset, words, data);
963 * ice_nvm_validate_checksum
964 * @hw: pointer to the HW struct
966 * Verify NVM PFA checksum validity (0x0706)
968 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
970 struct ice_aqc_nvm_checksum *cmd;
971 struct ice_aq_desc desc;
972 enum ice_status status;
974 status = ice_acquire_nvm(hw, ICE_RES_READ);
978 cmd = &desc.params.nvm_checksum;
980 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
981 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
983 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
987 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
988 status = ICE_ERR_NVM_CHECKSUM;
994 * ice_nvm_access_get_features - Return the NVM access features structure
995 * @cmd: NVM access command to process
996 * @data: storage for the driver NVM features
998 * Fill in the data section of the NVM access request with a copy of the NVM
999 * features structure.
1002 ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
1003 union ice_nvm_access_data *data)
1005 /* The provided data_size must be at least as large as our NVM
1006 * features structure. A larger size should not be treated as an
1007 * error, to allow future extensions to the features structure to
1008 * work on older drivers.
1010 if (cmd->data_size < sizeof(struct ice_nvm_features))
1011 return ICE_ERR_NO_MEMORY;
1013 /* Initialize the data buffer to zeros */
1014 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
1016 /* Fill in the features data */
1017 data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
1018 data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
1019 data->drv_features.size = sizeof(struct ice_nvm_features);
1020 data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
1026 * ice_nvm_access_get_module - Helper function to read module value
1027 * @cmd: NVM access command structure
1029 * Reads the module value out of the NVM access config field.
1031 u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)
1033 return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
1037 * ice_nvm_access_get_flags - Helper function to read flags value
1038 * @cmd: NVM access command structure
1040 * Reads the flags value out of the NVM access config field.
1042 u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)
1044 return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
1048 * ice_nvm_access_get_adapter - Helper function to read adapter info
1049 * @cmd: NVM access command structure
1051 * Read the adapter info value out of the NVM access config field.
1053 u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)
1055 return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
1056 ICE_NVM_CFG_ADAPTER_INFO_S);
1060 * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
1061 * @cmd: NVM access command structure
1063 * Validates that an NVM access structure is request to read or write a valid
1064 * register offset. First validates that the module and flags are correct, and
1065 * then ensures that the register offset is one of the accepted registers.
1067 static enum ice_status
1068 ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
1070 u32 module, flags, offset;
1073 module = ice_nvm_access_get_module(cmd);
1074 flags = ice_nvm_access_get_flags(cmd);
1075 offset = cmd->offset;
1077 /* Make sure the module and flags indicate a read/write request */
1078 if (module != ICE_NVM_REG_RW_MODULE ||
1079 flags != ICE_NVM_REG_RW_FLAGS ||
1080 cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))
1081 return ICE_ERR_PARAM;
1085 case GL_HICR_EN: /* Note, this register is read only */
1088 case GLGEN_CSR_DEBUG_C:
1090 case GLPCI_LBARCTRL:
1099 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
1100 if (offset == (u32)GL_HIDA(i))
1103 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
1104 if (offset == (u32)GL_HIBA(i))
1107 /* All other register offsets are not valid */
1108 return ICE_ERR_OUT_OF_RANGE;
1112 * ice_nvm_access_read - Handle an NVM read request
1113 * @hw: pointer to the HW struct
1114 * @cmd: NVM access command to process
1115 * @data: storage for the register value read
1117 * Process an NVM access request to read a register.
1120 ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1121 union ice_nvm_access_data *data)
1123 enum ice_status status;
1125 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1127 /* Always initialize the output data, even on failure */
1128 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
1130 /* Make sure this is a valid read/write access request */
1131 status = ice_validate_nvm_rw_reg(cmd);
1135 ice_debug(hw, ICE_DBG_NVM, "NVM access: reading register %08x\n",
1138 /* Read the register and store the contents in the data field */
1139 data->regval = rd32(hw, cmd->offset);
1145 * ice_nvm_access_write - Handle an NVM write request
1146 * @hw: pointer to the HW struct
1147 * @cmd: NVM access command to process
1148 * @data: NVM access data to write
1150 * Process an NVM access request to write a register.
1153 ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1154 union ice_nvm_access_data *data)
1156 enum ice_status status;
1158 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1160 /* Make sure this is a valid read/write access request */
1161 status = ice_validate_nvm_rw_reg(cmd);
1165 /* Reject requests to write to read-only registers */
1166 switch (cmd->offset) {
1169 return ICE_ERR_OUT_OF_RANGE;
1174 ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n",
1175 cmd->offset, data->regval);
1177 /* Write the data field to the specified register */
1178 wr32(hw, cmd->offset, data->regval);
1184 * ice_handle_nvm_access - Handle an NVM access request
1185 * @hw: pointer to the HW struct
1186 * @cmd: NVM access command info
1187 * @data: pointer to read or return data
1189 * Process an NVM access request. Read the command structure information and
1190 * determine if it is valid. If not, report an error indicating the command
1193 * For valid commands, perform the necessary function, copying the data into
1194 * the provided data buffer.
1197 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1198 union ice_nvm_access_data *data)
1200 u32 module, flags, adapter_info;
1202 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1204 /* Extended flags are currently reserved and must be zero */
1205 if ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)
1206 return ICE_ERR_PARAM;
1208 /* Adapter info must match the HW device ID */
1209 adapter_info = ice_nvm_access_get_adapter(cmd);
1210 if (adapter_info != hw->device_id)
1211 return ICE_ERR_PARAM;
1213 switch (cmd->command) {
1214 case ICE_NVM_CMD_READ:
1215 module = ice_nvm_access_get_module(cmd);
1216 flags = ice_nvm_access_get_flags(cmd);
1218 /* Getting the driver's NVM features structure shares the same
1219 * command type as reading a register. Read the config field
1220 * to determine if this is a request to get features.
1222 if (module == ICE_NVM_GET_FEATURES_MODULE &&
1223 flags == ICE_NVM_GET_FEATURES_FLAGS &&
1225 return ice_nvm_access_get_features(cmd, data);
1227 return ice_nvm_access_read(hw, cmd, data);
1228 case ICE_NVM_CMD_WRITE:
1229 return ice_nvm_access_write(hw, cmd, data);
1231 return ICE_ERR_PARAM;