1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
5 #include "ice_common.h"
7 #define GL_MNG_DEF_DEVID 0x000B611C
11 * @hw: pointer to the HW struct
12 * @module_typeid: module pointer location in words from the NVM beginning
13 * @offset: byte offset from the module beginning
14 * @length: length of the section to be read (in bytes from the offset)
15 * @data: command buffer (size [bytes] = length)
16 * @last_command: tells if this is the last command in a series
17 * @read_shadow_ram: tell if this is a shadow RAM read
18 * @cd: pointer to command details structure or NULL
20 * Read the NVM using the admin queue commands (0x0701)
23 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
24 void *data, bool last_command, bool read_shadow_ram,
27 struct ice_aq_desc desc;
28 struct ice_aqc_nvm *cmd;
30 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
32 cmd = &desc.params.nvm;
34 if (offset > ICE_AQC_NVM_MAX_OFFSET)
37 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
39 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
40 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
42 /* If this is the last command in a series, set the proper flag. */
44 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
45 cmd->module_typeid = CPU_TO_LE16(module_typeid);
46 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
47 cmd->offset_high = (offset >> 16) & 0xFF;
48 cmd->length = CPU_TO_LE16(length);
50 return ice_aq_send_cmd(hw, &desc, data, length, cd);
54 * ice_read_flat_nvm - Read portion of NVM by flat offset
55 * @hw: pointer to the HW struct
56 * @offset: offset from beginning of NVM
57 * @length: (in) number of bytes to read; (out) number of bytes actually read
58 * @data: buffer to return data in (sized to fit the specified length)
59 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
61 * Reads a portion of the NVM, as a flat memory space. This function correctly
62 * breaks read requests across Shadow RAM sectors and ensures that no single
63 * read request exceeds the maximum 4KB read for a single AdminQ command.
65 * Returns a status code on failure. Note that the data pointer may be
66 * partially updated if some reads succeed before a failure.
69 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
72 enum ice_status status;
77 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
81 /* Verify the length of the read if this is for the Shadow RAM */
82 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) {
83 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested data is beyond Shadow RAM limit\n");
88 u32 read_size, sector_offset;
90 /* ice_aq_read_nvm cannot read more than 4KB at a time.
91 * Additionally, a read from the Shadow RAM may not cross over
92 * a sector boundary. Conveniently, the sector size is also
95 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
96 read_size = MIN_T(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
99 last_cmd = !(bytes_read + read_size < inlen);
101 /* ice_aq_read_nvm takes the length as a u16. Our read_size is
102 * calculated using a u32, but the ICE_AQ_MAX_BUF_LEN maximum
103 * size guarantees that it will fit within the 2 bytes.
105 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
106 offset, (u16)read_size,
107 data + bytes_read, last_cmd,
108 read_shadow_ram, NULL);
112 bytes_read += read_size;
116 *length = bytes_read;
121 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
122 * @hw: pointer to the HW structure
123 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
124 * @data: word read from the Shadow RAM
126 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
128 static enum ice_status
129 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
131 u32 bytes = sizeof(u16);
132 enum ice_status status;
135 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
137 /* Note that ice_read_flat_nvm checks if the read is past the Shadow
138 * RAM size, and ensures we don't read across a Shadow RAM sector
141 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
142 (_FORCE_ u8 *)&data_local, true);
146 *data = LE16_TO_CPU(data_local);
151 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
152 * @hw: pointer to the HW structure
153 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
154 * @words: (in) number of words to read; (out) number of words actually read
155 * @data: words read from the Shadow RAM
157 * Reads 16 bit words (data buf) from the Shadow RAM. Ownership of the NVM is
158 * taken before reading the buffer and later released.
160 static enum ice_status
161 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
163 u32 bytes = *words * 2, i;
164 enum ice_status status;
166 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
168 /* ice_read_flat_nvm takes into account the 4KB AdminQ and Shadow RAM
169 * sector restrictions necessary when reading from the NVM.
171 status = ice_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true);
173 /* Report the number of words successfully read */
176 /* Byte swap the words up to the amount we actually read */
177 for (i = 0; i < *words; i++)
178 data[i] = LE16_TO_CPU(((_FORCE_ __le16 *)data)[i]);
184 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
185 * @hw: pointer to the HW structure
186 * @access: NVM access type (read or write)
188 * This function will request NVM ownership.
191 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
193 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
195 if (hw->flash.blank_nvm_mode)
198 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
202 * ice_release_nvm - Generic request for releasing the NVM ownership
203 * @hw: pointer to the HW structure
205 * This function will release NVM ownership.
207 void ice_release_nvm(struct ice_hw *hw)
209 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
211 if (hw->flash.blank_nvm_mode)
214 ice_release_res(hw, ICE_NVM_RES_ID);
218 * ice_get_flash_bank_offset - Get offset into requested flash bank
219 * @hw: pointer to the HW structure
220 * @bank: whether to read from the active or inactive flash bank
221 * @module: the module to read from
223 * Based on the module, lookup the module offset from the beginning of the
226 * Returns the flash offset. Note that a value of zero is invalid and must be
227 * treated as an error.
229 static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
231 struct ice_bank_info *banks = &hw->flash.banks;
232 enum ice_flash_bank active_bank;
233 bool second_bank_active;
237 case ICE_SR_1ST_NVM_BANK_PTR:
238 offset = banks->nvm_ptr;
239 size = banks->nvm_size;
240 active_bank = banks->nvm_bank;
242 case ICE_SR_1ST_OROM_BANK_PTR:
243 offset = banks->orom_ptr;
244 size = banks->orom_size;
245 active_bank = banks->orom_bank;
247 case ICE_SR_NETLIST_BANK_PTR:
248 offset = banks->netlist_ptr;
249 size = banks->netlist_size;
250 active_bank = banks->netlist_bank;
253 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module);
257 switch (active_bank) {
258 case ICE_1ST_FLASH_BANK:
259 second_bank_active = false;
261 case ICE_2ND_FLASH_BANK:
262 second_bank_active = true;
265 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n",
270 /* The second flash bank is stored immediately following the first
271 * bank. Based on whether the 1st or 2nd bank is active, and whether
272 * we want the active or inactive bank, calculate the desired offset.
275 case ICE_ACTIVE_FLASH_BANK:
276 return offset + (second_bank_active ? size : 0);
277 case ICE_INACTIVE_FLASH_BANK:
278 return offset + (second_bank_active ? 0 : size);
281 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);
286 * ice_read_flash_module - Read a word from one of the main NVM modules
287 * @hw: pointer to the HW structure
288 * @bank: which bank of the module to read
289 * @module: the module to read
290 * @offset: the offset into the module in bytes
291 * @data: storage for the word read from the flash
292 * @length: bytes of data to read
294 * Read data from the specified flash module. The bank parameter indicates
295 * whether or not to read from the active bank or the inactive bank of that
298 * The word will be read using flat NVM access, and relies on the
299 * hw->flash.banks data being setup by ice_determine_active_flash_banks()
300 * during initialization.
302 static enum ice_status
303 ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,
304 u32 offset, u8 *data, u32 length)
306 enum ice_status status;
309 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
311 start = ice_get_flash_bank_offset(hw, bank, module);
313 ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n",
315 return ICE_ERR_PARAM;
318 status = ice_acquire_nvm(hw, ICE_RES_READ);
322 status = ice_read_flat_nvm(hw, start + offset, &length, data, false);
330 * ice_read_nvm_module - Read from the active main NVM module
331 * @hw: pointer to the HW structure
332 * @bank: whether to read from active or inactive NVM module
333 * @offset: offset into the NVM module to read, in words
334 * @data: storage for returned word value
336 * Read the specified word from the active NVM module. This includes the CSS
337 * header at the start of the NVM module.
339 static enum ice_status
340 ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
342 enum ice_status status;
345 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16),
346 (_FORCE_ u8 *)&data_local, sizeof(u16));
348 *data = LE16_TO_CPU(data_local);
354 * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank
355 * @hw: pointer to the HW structure
356 * @bank: whether to read from the active or inactive NVM module
357 * @offset: offset into the Shadow RAM copy to read, in words
358 * @data: storage for returned word value
360 * Read the specified word from the copy of the Shadow RAM found in the
361 * specified NVM module.
363 static enum ice_status
364 ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
366 return ice_read_nvm_module(hw, bank, ICE_NVM_SR_COPY_WORD_OFFSET + offset, data);
370 * ice_read_orom_module - Read from the active Option ROM module
371 * @hw: pointer to the HW structure
372 * @bank: whether to read from active or inactive OROM module
373 * @offset: offset into the OROM module to read, in words
374 * @data: storage for returned word value
376 * Read the specified word from the active Option ROM module of the flash.
377 * Note that unlike the NVM module, the CSS data is stored at the end of the
378 * module instead of at the beginning.
380 static enum ice_status
381 ice_read_orom_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
383 enum ice_status status;
386 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, offset * sizeof(u16),
387 (_FORCE_ u8 *)&data_local, sizeof(u16));
389 *data = LE16_TO_CPU(data_local);
395 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
396 * @hw: pointer to the HW structure
397 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
398 * @data: word read from the Shadow RAM
400 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
402 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
404 enum ice_status status;
406 status = ice_acquire_nvm(hw, ICE_RES_READ);
408 status = ice_read_sr_word_aq(hw, offset, data);
416 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
417 * @hw: pointer to hardware structure
418 * @module_tlv: pointer to module TLV to return
419 * @module_tlv_len: pointer to module TLV length to return
420 * @module_type: module type requested
422 * Finds the requested sub module TLV type from the Preserved Field
423 * Area (PFA) and returns the TLV pointer and length. The caller can
424 * use these to read the variable length TLV value.
427 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
430 enum ice_status status;
431 u16 pfa_len, pfa_ptr;
434 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
435 if (status != ICE_SUCCESS) {
436 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
439 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
440 if (status != ICE_SUCCESS) {
441 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
444 /* Starting with first TLV after PFA length, iterate through the list
445 * of TLVs to find the requested one.
447 next_tlv = pfa_ptr + 1;
448 while (next_tlv < pfa_ptr + pfa_len) {
449 u16 tlv_sub_module_type;
453 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
454 if (status != ICE_SUCCESS) {
455 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
458 /* Read TLV length */
459 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
460 if (status != ICE_SUCCESS) {
461 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
464 if (tlv_sub_module_type == module_type) {
466 *module_tlv = next_tlv;
467 *module_tlv_len = tlv_len;
470 return ICE_ERR_INVAL_SIZE;
472 /* Check next TLV, i.e. current TLV pointer + length + 2 words
473 * (for current TLV's type and length)
475 next_tlv = next_tlv + tlv_len + 2;
477 /* Module does not exist */
478 return ICE_ERR_DOES_NOT_EXIST;
482 * ice_read_pba_string - Reads part number string from NVM
483 * @hw: pointer to hardware structure
484 * @pba_num: stores the part number string from the NVM
485 * @pba_num_size: part number string buffer length
487 * Reads the part number string from the NVM.
490 ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
492 u16 pba_tlv, pba_tlv_len;
493 enum ice_status status;
494 u16 pba_word, pba_size;
497 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
498 ICE_SR_PBA_BLOCK_PTR);
499 if (status != ICE_SUCCESS) {
500 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
504 /* pba_size is the next word */
505 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
506 if (status != ICE_SUCCESS) {
507 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
511 if (pba_tlv_len < pba_size) {
512 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
513 return ICE_ERR_INVAL_SIZE;
516 /* Subtract one to get PBA word count (PBA Size word is included in
520 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
521 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
522 return ICE_ERR_PARAM;
525 for (i = 0; i < pba_size; i++) {
526 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
527 if (status != ICE_SUCCESS) {
528 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
532 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
533 pba_num[(i * 2) + 1] = pba_word & 0xFF;
535 pba_num[(pba_size * 2)] = '\0';
541 * ice_get_nvm_srev - Read the security revision from the NVM CSS header
542 * @hw: pointer to the HW struct
543 * @bank: whether to read from the active or inactive flash bank
544 * @srev: storage for security revision
546 * Read the security revision out of the CSS header of the active NVM module
549 static enum ice_status ice_get_nvm_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)
551 enum ice_status status;
554 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_L, &srev_l);
558 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_H, &srev_h);
562 *srev = srev_h << 16 | srev_l;
568 * ice_get_nvm_ver_info - Read NVM version information
569 * @hw: pointer to the HW struct
570 * @bank: whether to read from the active or inactive flash bank
571 * @nvm: pointer to NVM info structure
573 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling
574 * in the nvm info structure.
576 static enum ice_status
577 ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm)
579 u16 eetrack_lo, eetrack_hi, ver;
580 enum ice_status status;
582 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver);
584 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
588 nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
589 nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
591 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
593 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
596 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
598 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
602 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
604 status = ice_get_nvm_srev(hw, bank, &nvm->srev);
606 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM security revision.\n");
612 * ice_get_inactive_nvm_ver - Read Option ROM version from the inactive bank
613 * @hw: pointer to the HW structure
614 * @nvm: storage for Option ROM version information
616 * Reads the NVM EETRACK ID, Map version, and security revision of the
617 * inactive NVM bank. Used to access version data for a pending update that
618 * has not yet been activated.
620 enum ice_status ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm)
622 return ice_get_nvm_ver_info(hw, ICE_INACTIVE_FLASH_BANK, nvm);
626 * ice_get_orom_srev - Read the security revision from the OROM CSS header
627 * @hw: pointer to the HW struct
628 * @bank: whether to read from active or inactive flash module
629 * @srev: storage for security revision
631 * Read the security revision out of the CSS header of the active OROM module
634 static enum ice_status ice_get_orom_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)
636 enum ice_status status;
640 if (hw->flash.banks.orom_size < ICE_NVM_OROM_TRAILER_LENGTH) {
641 ice_debug(hw, ICE_DBG_NVM, "Unexpected Option ROM Size of %u\n",
642 hw->flash.banks.orom_size);
646 /* calculate how far into the Option ROM the CSS header starts. Note
647 * that ice_read_orom_module takes a word offset so we need to
650 css_start = (hw->flash.banks.orom_size - ICE_NVM_OROM_TRAILER_LENGTH) / 2;
652 status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_L, &srev_l);
656 status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_H, &srev_h);
660 *srev = srev_h << 16 | srev_l;
666 * ice_get_orom_civd_data - Get the combo version information from Option ROM
667 * @hw: pointer to the HW struct
668 * @bank: whether to read from the active or inactive flash module
669 * @civd: storage for the Option ROM CIVD data.
671 * Searches through the Option ROM flash contents to locate the CIVD data for
674 static enum ice_status
675 ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank,
676 struct ice_orom_civd_info *civd)
678 struct ice_orom_civd_info tmp;
679 enum ice_status status;
682 /* The CIVD section is located in the Option ROM aligned to 512 bytes.
683 * The first 4 bytes must contain the ASCII characters "$CIV".
684 * A simple modulo 256 sum of all of the bytes of the structure must
687 for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) {
690 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR,
691 offset, (u8 *)&tmp, sizeof(tmp));
693 ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM CIVD data\n");
697 /* Skip forward until we find a matching signature */
698 if (memcmp("$CIV", tmp.signature, sizeof(tmp.signature)) != 0)
701 /* Verify that the simple checksum is zero */
702 for (i = 0; i < sizeof(tmp); i++)
703 sum += ((u8 *)&tmp)[i];
706 ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n",
719 * ice_get_orom_ver_info - Read Option ROM version information
720 * @hw: pointer to the HW struct
721 * @bank: whether to read from the active or inactive flash module
722 * @orom: pointer to Option ROM info structure
724 * Read Option ROM version and security revision from the Option ROM flash
727 static enum ice_status
728 ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom)
730 struct ice_orom_civd_info civd;
731 enum ice_status status;
734 status = ice_get_orom_civd_data(hw, bank, &civd);
736 ice_debug(hw, ICE_DBG_NVM, "Failed to locate valid Option ROM CIVD data\n");
740 combo_ver = LE32_TO_CPU(civd.combo_ver);
742 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >> ICE_OROM_VER_SHIFT);
743 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK);
744 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >> ICE_OROM_VER_BUILD_SHIFT);
746 status = ice_get_orom_srev(hw, bank, &orom->srev);
748 ice_debug(hw, ICE_DBG_NVM, "Failed to read Option ROM security revision.\n");
756 * ice_get_inactive_orom_ver - Read Option ROM version from the inactive bank
757 * @hw: pointer to the HW structure
758 * @orom: storage for Option ROM version information
760 * Reads the Option ROM version and security revision data for the inactive
761 * section of flash. Used to access version data for a pending update that has
762 * not yet been activated.
764 enum ice_status ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom)
766 return ice_get_orom_ver_info(hw, ICE_INACTIVE_FLASH_BANK, orom);
770 * ice_discover_flash_size - Discover the available flash size.
771 * @hw: pointer to the HW struct
773 * The device flash could be up to 16MB in size. However, it is possible that
774 * the actual size is smaller. Use bisection to determine the accessible size
777 static enum ice_status ice_discover_flash_size(struct ice_hw *hw)
779 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
780 enum ice_status status;
782 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
784 status = ice_acquire_nvm(hw, ICE_RES_READ);
788 while ((max_size - min_size) > 1) {
789 u32 offset = (max_size + min_size) / 2;
793 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
794 if (status == ICE_ERR_AQ_ERROR &&
795 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
796 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
798 status = ICE_SUCCESS;
800 } else if (!status) {
801 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
805 /* an unexpected error occurred */
806 goto err_read_flat_nvm;
810 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
812 hw->flash.flash_size = max_size;
821 * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word
822 * @hw: pointer to the HW structure
823 * @offset: the word offset of the Shadow RAM word to read
824 * @pointer: pointer value read from Shadow RAM
826 * Read the given Shadow RAM word, and convert it to a pointer value specified
827 * in bytes. This function assumes the specified offset is a valid pointer
830 * Each pointer word specifies whether it is stored in word size or 4KB
831 * sector size by using the highest bit. The reported pointer value will be in
832 * bytes, intended for flat NVM reads.
834 static enum ice_status
835 ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
837 enum ice_status status;
840 status = ice_read_sr_word(hw, offset, &value);
844 /* Determine if the pointer is in 4KB or word units */
845 if (value & ICE_SR_NVM_PTR_4KB_UNITS)
846 *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;
848 *pointer = value * 2;
854 * ice_read_sr_area_size - Read an area size from a Shadow RAM word
855 * @hw: pointer to the HW structure
856 * @offset: the word offset of the Shadow RAM to read
857 * @size: size value read from the Shadow RAM
859 * Read the given Shadow RAM word, and convert it to an area size value
860 * specified in bytes. This function assumes the specified offset is a valid
863 * Each area size word is specified in 4KB sector units. This function reports
864 * the size in bytes, intended for flat NVM reads.
866 static enum ice_status
867 ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
869 enum ice_status status;
872 status = ice_read_sr_word(hw, offset, &value);
876 /* Area sizes are always specified in 4KB units */
877 *size = value * 4 * 1024;
883 * ice_determine_active_flash_banks - Discover active bank for each module
884 * @hw: pointer to the HW struct
886 * Read the Shadow RAM control word and determine which banks are active for
887 * the NVM, OROM, and Netlist modules. Also read and calculate the associated
888 * pointer and size. These values are then cached into the ice_flash_info
889 * structure for later use in order to calculate the correct offset to read
890 * from the active module.
892 static enum ice_status
893 ice_determine_active_flash_banks(struct ice_hw *hw)
895 struct ice_bank_info *banks = &hw->flash.banks;
896 enum ice_status status;
899 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
901 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
905 /* Check that the control word indicates validity */
906 if ((ctrl_word & ICE_SR_CTRL_WORD_1_M) >> ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) {
907 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
911 if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))
912 banks->nvm_bank = ICE_1ST_FLASH_BANK;
914 banks->nvm_bank = ICE_2ND_FLASH_BANK;
916 if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))
917 banks->orom_bank = ICE_1ST_FLASH_BANK;
919 banks->orom_bank = ICE_2ND_FLASH_BANK;
921 if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))
922 banks->netlist_bank = ICE_1ST_FLASH_BANK;
924 banks->netlist_bank = ICE_2ND_FLASH_BANK;
926 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
928 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
932 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
934 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
938 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
940 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
944 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
946 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
950 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
952 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
956 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
958 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
966 * ice_init_nvm - initializes NVM setting
967 * @hw: pointer to the HW struct
969 * This function reads and populates NVM settings such as Shadow RAM size,
970 * max_timeout, and blank_nvm_mode
972 enum ice_status ice_init_nvm(struct ice_hw *hw)
974 struct ice_flash_info *flash = &hw->flash;
975 enum ice_status status;
979 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
981 /* The SR size is stored regardless of the NVM programming mode
982 * as the blank mode may be used in the factory line.
984 gens_stat = rd32(hw, GLNVM_GENS);
985 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
987 /* Switching to words (sr_size contains power of 2) */
988 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
990 /* Check if we are in the normal or blank NVM programming mode */
991 fla = rd32(hw, GLNVM_FLA);
992 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
993 flash->blank_nvm_mode = false;
995 /* Blank programming mode */
996 flash->blank_nvm_mode = true;
997 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
998 return ICE_ERR_NVM_BLANK_MODE;
1001 status = ice_discover_flash_size(hw);
1003 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");
1007 status = ice_determine_active_flash_banks(hw);
1009 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
1013 status = ice_get_nvm_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->nvm);
1015 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
1019 status = ice_get_orom_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->orom);
1021 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
1027 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
1028 * @hw: pointer to the HW structure
1029 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
1030 * @words: (in) number of words to read; (out) number of words actually read
1031 * @data: words read from the Shadow RAM
1033 * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
1034 * method. The buf read is preceded by the NVM ownership take
1035 * and followed by the release.
1038 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
1040 enum ice_status status;
1042 status = ice_acquire_nvm(hw, ICE_RES_READ);
1044 status = ice_read_sr_buf_aq(hw, offset, words, data);
1045 ice_release_nvm(hw);
1052 * ice_nvm_validate_checksum
1053 * @hw: pointer to the HW struct
1055 * Verify NVM PFA checksum validity (0x0706)
1057 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
1059 struct ice_aqc_nvm_checksum *cmd;
1060 struct ice_aq_desc desc;
1061 enum ice_status status;
1063 status = ice_acquire_nvm(hw, ICE_RES_READ);
1067 cmd = &desc.params.nvm_checksum;
1069 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
1070 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
1072 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1073 ice_release_nvm(hw);
1076 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
1077 status = ICE_ERR_NVM_CHECKSUM;
1083 * ice_nvm_recalculate_checksum
1084 * @hw: pointer to the HW struct
1086 * Recalculate NVM PFA checksum (0x0706)
1088 enum ice_status ice_nvm_recalculate_checksum(struct ice_hw *hw)
1090 struct ice_aqc_nvm_checksum *cmd;
1091 struct ice_aq_desc desc;
1092 enum ice_status status;
1094 status = ice_acquire_nvm(hw, ICE_RES_READ);
1098 cmd = &desc.params.nvm_checksum;
1100 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
1101 cmd->flags = ICE_AQC_NVM_CHECKSUM_RECALC;
1103 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1105 ice_release_nvm(hw);
1111 * ice_nvm_access_get_features - Return the NVM access features structure
1112 * @cmd: NVM access command to process
1113 * @data: storage for the driver NVM features
1115 * Fill in the data section of the NVM access request with a copy of the NVM
1116 * features structure.
1119 ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
1120 union ice_nvm_access_data *data)
1122 /* The provided data_size must be at least as large as our NVM
1123 * features structure. A larger size should not be treated as an
1124 * error, to allow future extensions to the features structure to
1125 * work on older drivers.
1127 if (cmd->data_size < sizeof(struct ice_nvm_features))
1128 return ICE_ERR_NO_MEMORY;
1130 /* Initialize the data buffer to zeros */
1131 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
1133 /* Fill in the features data */
1134 data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
1135 data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
1136 data->drv_features.size = sizeof(struct ice_nvm_features);
1137 data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
1143 * ice_nvm_access_get_module - Helper function to read module value
1144 * @cmd: NVM access command structure
1146 * Reads the module value out of the NVM access config field.
1148 u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)
1150 return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
1154 * ice_nvm_access_get_flags - Helper function to read flags value
1155 * @cmd: NVM access command structure
1157 * Reads the flags value out of the NVM access config field.
1159 u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)
1161 return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
1165 * ice_nvm_access_get_adapter - Helper function to read adapter info
1166 * @cmd: NVM access command structure
1168 * Read the adapter info value out of the NVM access config field.
1170 u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)
1172 return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
1173 ICE_NVM_CFG_ADAPTER_INFO_S);
1177 * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
1178 * @cmd: NVM access command structure
1180 * Validates that an NVM access structure is request to read or write a valid
1181 * register offset. First validates that the module and flags are correct, and
1182 * then ensures that the register offset is one of the accepted registers.
1184 static enum ice_status
1185 ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
1187 u32 module, flags, offset;
1190 module = ice_nvm_access_get_module(cmd);
1191 flags = ice_nvm_access_get_flags(cmd);
1192 offset = cmd->offset;
1194 /* Make sure the module and flags indicate a read/write request */
1195 if (module != ICE_NVM_REG_RW_MODULE ||
1196 flags != ICE_NVM_REG_RW_FLAGS ||
1197 cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))
1198 return ICE_ERR_PARAM;
1202 case GL_HICR_EN: /* Note, this register is read only */
1205 case GLGEN_CSR_DEBUG_C:
1207 case GLPCI_LBARCTRL:
1208 case GL_MNG_DEF_DEVID:
1217 for (i = 0; i <= GL_HIDA_MAX_INDEX; i++)
1218 if (offset == (u32)GL_HIDA(i))
1221 for (i = 0; i <= GL_HIBA_MAX_INDEX; i++)
1222 if (offset == (u32)GL_HIBA(i))
1225 /* All other register offsets are not valid */
1226 return ICE_ERR_OUT_OF_RANGE;
1230 * ice_nvm_access_read - Handle an NVM read request
1231 * @hw: pointer to the HW struct
1232 * @cmd: NVM access command to process
1233 * @data: storage for the register value read
1235 * Process an NVM access request to read a register.
1238 ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1239 union ice_nvm_access_data *data)
1241 enum ice_status status;
1243 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1245 /* Always initialize the output data, even on failure */
1246 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
1248 /* Make sure this is a valid read/write access request */
1249 status = ice_validate_nvm_rw_reg(cmd);
1253 ice_debug(hw, ICE_DBG_NVM, "NVM access: reading register %08x\n",
1256 /* Read the register and store the contents in the data field */
1257 data->regval = rd32(hw, cmd->offset);
1263 * ice_nvm_access_write - Handle an NVM write request
1264 * @hw: pointer to the HW struct
1265 * @cmd: NVM access command to process
1266 * @data: NVM access data to write
1268 * Process an NVM access request to write a register.
1271 ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1272 union ice_nvm_access_data *data)
1274 enum ice_status status;
1276 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1278 /* Make sure this is a valid read/write access request */
1279 status = ice_validate_nvm_rw_reg(cmd);
1283 /* Reject requests to write to read-only registers */
1284 switch (cmd->offset) {
1287 return ICE_ERR_OUT_OF_RANGE;
1292 ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n",
1293 cmd->offset, data->regval);
1295 /* Write the data field to the specified register */
1296 wr32(hw, cmd->offset, data->regval);
1302 * ice_handle_nvm_access - Handle an NVM access request
1303 * @hw: pointer to the HW struct
1304 * @cmd: NVM access command info
1305 * @data: pointer to read or return data
1307 * Process an NVM access request. Read the command structure information and
1308 * determine if it is valid. If not, report an error indicating the command
1311 * For valid commands, perform the necessary function, copying the data into
1312 * the provided data buffer.
1315 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1316 union ice_nvm_access_data *data)
1318 u32 module, flags, adapter_info;
1320 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1322 /* Extended flags are currently reserved and must be zero */
1323 if ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)
1324 return ICE_ERR_PARAM;
1326 /* Adapter info must match the HW device ID */
1327 adapter_info = ice_nvm_access_get_adapter(cmd);
1328 if (adapter_info != hw->device_id)
1329 return ICE_ERR_PARAM;
1331 switch (cmd->command) {
1332 case ICE_NVM_CMD_READ:
1333 module = ice_nvm_access_get_module(cmd);
1334 flags = ice_nvm_access_get_flags(cmd);
1336 /* Getting the driver's NVM features structure shares the same
1337 * command type as reading a register. Read the config field
1338 * to determine if this is a request to get features.
1340 if (module == ICE_NVM_GET_FEATURES_MODULE &&
1341 flags == ICE_NVM_GET_FEATURES_FLAGS &&
1343 return ice_nvm_access_get_features(cmd, data);
1345 return ice_nvm_access_read(hw, cmd, data);
1346 case ICE_NVM_CMD_WRITE:
1347 return ice_nvm_access_write(hw, cmd, data);
1349 return ICE_ERR_PARAM;