1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
9 * @hw: pointer to the HW struct
10 * @module_typeid: module pointer location in words from the NVM beginning
11 * @offset: byte offset from the module beginning
12 * @length: length of the section to be read (in bytes from the offset)
13 * @data: command buffer (size [bytes] = length)
14 * @last_command: tells if this is the last command in a series
15 * @read_shadow_ram: tell if this is a shadow RAM read
16 * @cd: pointer to command details structure or NULL
18 * Read the NVM using the admin queue commands (0x0701)
21 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
22 void *data, bool last_command, bool read_shadow_ram,
25 struct ice_aq_desc desc;
26 struct ice_aqc_nvm *cmd;
28 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
30 cmd = &desc.params.nvm;
32 if (offset > ICE_AQC_NVM_MAX_OFFSET)
35 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
37 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
38 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
40 /* If this is the last command in a series, set the proper flag. */
42 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
43 cmd->module_typeid = CPU_TO_LE16(module_typeid);
44 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
45 cmd->offset_high = (offset >> 16) & 0xFF;
46 cmd->length = CPU_TO_LE16(length);
48 return ice_aq_send_cmd(hw, &desc, data, length, cd);
52 * ice_read_flat_nvm - Read portion of NVM by flat offset
53 * @hw: pointer to the HW struct
54 * @offset: offset from beginning of NVM
55 * @length: (in) number of bytes to read; (out) number of bytes actually read
56 * @data: buffer to return data in (sized to fit the specified length)
57 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
59 * Reads a portion of the NVM, as a flat memory space. This function correctly
60 * breaks read requests across Shadow RAM sectors and ensures that no single
61 * read request exceeds the maximum 4KB read for a single AdminQ command.
63 * Returns a status code on failure. Note that the data pointer may be
64 * partially updated if some reads succeed before a failure.
67 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
70 enum ice_status status;
75 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
79 /* Verify the length of the read if this is for the Shadow RAM */
80 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) {
81 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested data is beyond Shadow RAM limit\n");
86 u32 read_size, sector_offset;
88 /* ice_aq_read_nvm cannot read more than 4KB at a time.
89 * Additionally, a read from the Shadow RAM may not cross over
90 * a sector boundary. Conveniently, the sector size is also
93 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
94 read_size = MIN_T(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
97 last_cmd = !(bytes_read + read_size < inlen);
99 /* ice_aq_read_nvm takes the length as a u16. Our read_size is
100 * calculated using a u32, but the ICE_AQ_MAX_BUF_LEN maximum
101 * size guarantees that it will fit within the 2 bytes.
103 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
104 offset, (u16)read_size,
105 data + bytes_read, last_cmd,
106 read_shadow_ram, NULL);
110 bytes_read += read_size;
114 *length = bytes_read;
119 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
120 * @hw: pointer to the HW structure
121 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
122 * @data: word read from the Shadow RAM
124 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
126 static enum ice_status
127 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
129 u32 bytes = sizeof(u16);
130 enum ice_status status;
133 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
135 /* Note that ice_read_flat_nvm checks if the read is past the Shadow
136 * RAM size, and ensures we don't read across a Shadow RAM sector
139 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
140 (_FORCE_ u8 *)&data_local, true);
144 *data = LE16_TO_CPU(data_local);
149 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
150 * @hw: pointer to the HW structure
151 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
152 * @words: (in) number of words to read; (out) number of words actually read
153 * @data: words read from the Shadow RAM
155 * Reads 16 bit words (data buf) from the Shadow RAM. Ownership of the NVM is
156 * taken before reading the buffer and later released.
158 static enum ice_status
159 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
161 u32 bytes = *words * 2, i;
162 enum ice_status status;
164 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
166 /* ice_read_flat_nvm takes into account the 4KB AdminQ and Shadow RAM
167 * sector restrictions necessary when reading from the NVM.
169 status = ice_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true);
171 /* Report the number of words successfully read */
174 /* Byte swap the words up to the amount we actually read */
175 for (i = 0; i < *words; i++)
176 data[i] = LE16_TO_CPU(((_FORCE_ __le16 *)data)[i]);
182 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
183 * @hw: pointer to the HW structure
184 * @access: NVM access type (read or write)
186 * This function will request NVM ownership.
189 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
191 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
193 if (hw->flash.blank_nvm_mode)
196 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
200 * ice_release_nvm - Generic request for releasing the NVM ownership
201 * @hw: pointer to the HW structure
203 * This function will release NVM ownership.
205 void ice_release_nvm(struct ice_hw *hw)
207 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
209 if (hw->flash.blank_nvm_mode)
212 ice_release_res(hw, ICE_NVM_RES_ID);
216 * ice_read_flash_module - Read a word from one of the main NVM modules
217 * @hw: pointer to the HW structure
218 * @bank: which bank of the module to read
219 * @module: the module to read
220 * @offset: the offset into the module in words
221 * @data: storage for the word read from the flash
223 * Read a word from the specified bank of the module. The bank must be either
224 * the 1st or 2nd bank. The word will be read using flat NVM access, and
225 * relies on the hw->flash.banks data being setup by
226 * ice_determine_active_flash_banks() during initialization.
228 static enum ice_status
229 ice_read_flash_module(struct ice_hw *hw, enum ice_flash_bank bank, u16 module,
230 u32 offset, u16 *data)
232 struct ice_bank_info *banks = &hw->flash.banks;
233 u32 bytes = sizeof(u16);
234 enum ice_status status;
239 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
242 case ICE_1ST_FLASH_BANK:
245 case ICE_2ND_FLASH_BANK:
248 case ICE_INVALID_FLASH_BANK:
250 ice_debug(hw, ICE_DBG_NVM, "Unexpected flash bank %u\n", bank);
251 return ICE_ERR_PARAM;
255 case ICE_SR_1ST_NVM_BANK_PTR:
256 start = banks->nvm_ptr + (second_bank ? banks->nvm_size : 0);
258 case ICE_SR_1ST_OROM_BANK_PTR:
259 start = banks->orom_ptr + (second_bank ? banks->orom_size : 0);
261 case ICE_SR_NETLIST_BANK_PTR:
262 start = banks->netlist_ptr + (second_bank ? banks->netlist_size : 0);
265 ice_debug(hw, ICE_DBG_NVM, "Unexpected flash module 0x%04x\n", module);
266 return ICE_ERR_PARAM;
269 status = ice_acquire_nvm(hw, ICE_RES_READ);
273 status = ice_read_flat_nvm(hw, start + offset * sizeof(u16), &bytes,
274 (_FORCE_ u8 *)&data_local, false);
276 *data = LE16_TO_CPU(data_local);
284 * ice_read_active_nvm_module - Read from the active main NVM module
285 * @hw: pointer to the HW structure
286 * @offset: offset into the NVM module to read, in words
287 * @data: storage for returned word value
289 * Read the specified word from the active NVM module. This includes the CSS
290 * header at the start of the NVM module.
292 static enum ice_status
293 ice_read_active_nvm_module(struct ice_hw *hw, u32 offset, u16 *data)
295 return ice_read_flash_module(hw, hw->flash.banks.nvm_bank,
296 ICE_SR_1ST_NVM_BANK_PTR, offset, data);
300 * ice_read_active_orom_module - Read from the active Option ROM module
301 * @hw: pointer to the HW structure
302 * @offset: offset into the OROM module to read, in words
303 * @data: storage for returned word value
305 * Read the specified word from the active Option ROM module of the flash.
306 * Note that unlike the NVM module, the CSS data is stored at the end of the
307 * module instead of at the beginning.
309 static enum ice_status
310 ice_read_active_orom_module(struct ice_hw *hw, u32 offset, u16 *data)
312 return ice_read_flash_module(hw, hw->flash.banks.orom_bank,
313 ICE_SR_1ST_OROM_BANK_PTR, offset, data);
317 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
318 * @hw: pointer to the HW structure
319 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
320 * @data: word read from the Shadow RAM
322 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
324 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
326 enum ice_status status;
328 status = ice_acquire_nvm(hw, ICE_RES_READ);
330 status = ice_read_sr_word_aq(hw, offset, data);
338 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
339 * @hw: pointer to hardware structure
340 * @module_tlv: pointer to module TLV to return
341 * @module_tlv_len: pointer to module TLV length to return
342 * @module_type: module type requested
344 * Finds the requested sub module TLV type from the Preserved Field
345 * Area (PFA) and returns the TLV pointer and length. The caller can
346 * use these to read the variable length TLV value.
349 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
352 enum ice_status status;
353 u16 pfa_len, pfa_ptr;
356 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
357 if (status != ICE_SUCCESS) {
358 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
361 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
362 if (status != ICE_SUCCESS) {
363 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
366 /* Starting with first TLV after PFA length, iterate through the list
367 * of TLVs to find the requested one.
369 next_tlv = pfa_ptr + 1;
370 while (next_tlv < pfa_ptr + pfa_len) {
371 u16 tlv_sub_module_type;
375 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
376 if (status != ICE_SUCCESS) {
377 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
380 /* Read TLV length */
381 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
382 if (status != ICE_SUCCESS) {
383 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
386 if (tlv_sub_module_type == module_type) {
388 *module_tlv = next_tlv;
389 *module_tlv_len = tlv_len;
392 return ICE_ERR_INVAL_SIZE;
394 /* Check next TLV, i.e. current TLV pointer + length + 2 words
395 * (for current TLV's type and length)
397 next_tlv = next_tlv + tlv_len + 2;
399 /* Module does not exist */
400 return ICE_ERR_DOES_NOT_EXIST;
404 * ice_read_pba_string - Reads part number string from NVM
405 * @hw: pointer to hardware structure
406 * @pba_num: stores the part number string from the NVM
407 * @pba_num_size: part number string buffer length
409 * Reads the part number string from the NVM.
412 ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
414 u16 pba_tlv, pba_tlv_len;
415 enum ice_status status;
416 u16 pba_word, pba_size;
419 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
420 ICE_SR_PBA_BLOCK_PTR);
421 if (status != ICE_SUCCESS) {
422 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
426 /* pba_size is the next word */
427 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
428 if (status != ICE_SUCCESS) {
429 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
433 if (pba_tlv_len < pba_size) {
434 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
435 return ICE_ERR_INVAL_SIZE;
438 /* Subtract one to get PBA word count (PBA Size word is included in
442 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
443 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
444 return ICE_ERR_PARAM;
447 for (i = 0; i < pba_size; i++) {
448 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
449 if (status != ICE_SUCCESS) {
450 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
454 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
455 pba_num[(i * 2) + 1] = pba_word & 0xFF;
457 pba_num[(pba_size * 2)] = '\0';
463 * ice_get_nvm_srev - Read the security revision from the NVM CSS header
464 * @hw: pointer to the HW struct
465 * @srev: storage for security revision
467 * Read the security revision out of the CSS header of the active NVM module
470 static enum ice_status ice_get_nvm_srev(struct ice_hw *hw, u32 *srev)
472 enum ice_status status;
475 status = ice_read_active_nvm_module(hw, ICE_NVM_CSS_SREV_L, &srev_l);
479 status = ice_read_active_nvm_module(hw, ICE_NVM_CSS_SREV_H, &srev_h);
483 *srev = srev_h << 16 | srev_l;
489 * ice_get_nvm_ver_info - Read NVM version information
490 * @hw: pointer to the HW struct
491 * @nvm: pointer to NVM info structure
493 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling
494 * in the nvm info structure.
496 static enum ice_status
497 ice_get_nvm_ver_info(struct ice_hw *hw, struct ice_nvm_info *nvm)
499 u16 eetrack_lo, eetrack_hi, ver;
500 enum ice_status status;
502 status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &ver);
504 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
507 nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
508 nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
510 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
512 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
515 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
517 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
521 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
523 status = ice_get_nvm_srev(hw, &nvm->srev);
525 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM security revision.\n");
531 * ice_get_orom_srev - Read the security revision from the OROM CSS header
532 * @hw: pointer to the HW struct
533 * @srev: storage for security revision
535 * Read the security revision out of the CSS header of the active OROM module
538 static enum ice_status ice_get_orom_srev(struct ice_hw *hw, u32 *srev)
540 enum ice_status status;
544 if (hw->flash.banks.orom_size < ICE_NVM_OROM_TRAILER_LENGTH) {
545 ice_debug(hw, ICE_DBG_NVM, "Unexpected Option ROM Size of %u\n",
546 hw->flash.banks.orom_size);
550 /* calculate how far into the Option ROM the CSS header starts. Note
551 * that ice_read_active_orom_module takes a word offset so we need to
554 css_start = (hw->flash.banks.orom_size - ICE_NVM_OROM_TRAILER_LENGTH) / 2;
556 status = ice_read_active_orom_module(hw, css_start + ICE_NVM_CSS_SREV_L, &srev_l);
560 status = ice_read_active_orom_module(hw, css_start + ICE_NVM_CSS_SREV_H, &srev_h);
564 *srev = srev_h << 16 | srev_l;
570 * ice_get_orom_ver_info - Read Option ROM version information
571 * @hw: pointer to the HW struct
572 * @orom: pointer to Option ROM info structure
574 * Read the Combo Image version data from the Boot Configuration TLV and fill
575 * in the option ROM version data.
577 static enum ice_status
578 ice_get_orom_ver_info(struct ice_hw *hw, struct ice_orom_info *orom)
580 u16 combo_hi, combo_lo, boot_cfg_tlv, boot_cfg_tlv_len;
581 enum ice_status status;
584 status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len,
585 ICE_SR_BOOT_CFG_PTR);
587 ice_debug(hw, ICE_DBG_INIT, "Failed to read Boot Configuration Block TLV.\n");
591 /* Boot Configuration Block must have length at least 2 words
592 * (Combo Image Version High and Combo Image Version Low)
594 if (boot_cfg_tlv_len < 2) {
595 ice_debug(hw, ICE_DBG_INIT, "Invalid Boot Configuration Block TLV size.\n");
596 return ICE_ERR_INVAL_SIZE;
599 status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OROM_VER_OFF),
602 ice_debug(hw, ICE_DBG_INIT, "Failed to read OROM_VER hi.\n");
606 status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OROM_VER_OFF + 1),
609 ice_debug(hw, ICE_DBG_INIT, "Failed to read OROM_VER lo.\n");
613 combo_ver = ((u32)combo_hi << 16) | combo_lo;
615 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >>
617 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK);
618 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >>
619 ICE_OROM_VER_BUILD_SHIFT);
621 status = ice_get_orom_srev(hw, &orom->srev);
623 ice_debug(hw, ICE_DBG_NVM, "Failed to read Option ROM security revision.\n");
629 * ice_discover_flash_size - Discover the available flash size.
630 * @hw: pointer to the HW struct
632 * The device flash could be up to 16MB in size. However, it is possible that
633 * the actual size is smaller. Use bisection to determine the accessible size
636 static enum ice_status ice_discover_flash_size(struct ice_hw *hw)
638 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
639 enum ice_status status;
641 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
643 status = ice_acquire_nvm(hw, ICE_RES_READ);
647 while ((max_size - min_size) > 1) {
648 u32 offset = (max_size + min_size) / 2;
652 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
653 if (status == ICE_ERR_AQ_ERROR &&
654 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
655 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
657 status = ICE_SUCCESS;
659 } else if (!status) {
660 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
664 /* an unexpected error occurred */
665 goto err_read_flat_nvm;
669 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
671 hw->flash.flash_size = max_size;
680 * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word
681 * @hw: pointer to the HW structure
682 * @offset: the word offset of the Shadow RAM word to read
683 * @pointer: pointer value read from Shadow RAM
685 * Read the given Shadow RAM word, and convert it to a pointer value specified
686 * in bytes. This function assumes the specified offset is a valid pointer
689 * Each pointer word specifies whether it is stored in word size or 4KB
690 * sector size by using the highest bit. The reported pointer value will be in
691 * bytes, intended for flat NVM reads.
693 static enum ice_status
694 ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
696 enum ice_status status;
699 status = ice_read_sr_word(hw, offset, &value);
703 /* Determine if the pointer is in 4KB or word units */
704 if (value & ICE_SR_NVM_PTR_4KB_UNITS)
705 *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;
707 *pointer = value * 2;
713 * ice_read_sr_area_size - Read an area size from a Shadow RAM word
714 * @hw: pointer to the HW structure
715 * @offset: the word offset of the Shadow RAM to read
716 * @size: size value read from the Shadow RAM
718 * Read the given Shadow RAM word, and convert it to an area size value
719 * specified in bytes. This function assumes the specified offset is a valid
722 * Each area size word is specified in 4KB sector units. This function reports
723 * the size in bytes, intended for flat NVM reads.
725 static enum ice_status
726 ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
728 enum ice_status status;
731 status = ice_read_sr_word(hw, offset, &value);
735 /* Area sizes are always specified in 4KB units */
736 *size = value * 4 * 1024;
742 * ice_determine_active_flash_banks - Discover active bank for each module
743 * @hw: pointer to the HW struct
745 * Read the Shadow RAM control word and determine which banks are active for
746 * the NVM, OROM, and Netlist modules. Also read and calculate the associated
747 * pointer and size. These values are then cached into the ice_flash_info
748 * structure for later use in order to calculate the correct offset to read
749 * from the active module.
751 static enum ice_status
752 ice_determine_active_flash_banks(struct ice_hw *hw)
754 struct ice_bank_info *banks = &hw->flash.banks;
755 enum ice_status status;
758 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
760 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
764 /* Check that the control word indicates validity */
765 if ((ctrl_word & ICE_SR_CTRL_WORD_1_M) >> ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) {
766 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
770 if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))
771 banks->nvm_bank = ICE_1ST_FLASH_BANK;
773 banks->nvm_bank = ICE_2ND_FLASH_BANK;
775 if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))
776 banks->orom_bank = ICE_1ST_FLASH_BANK;
778 banks->orom_bank = ICE_2ND_FLASH_BANK;
780 if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))
781 banks->netlist_bank = ICE_1ST_FLASH_BANK;
783 banks->netlist_bank = ICE_2ND_FLASH_BANK;
785 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
787 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
791 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
793 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
797 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
799 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
803 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
805 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
809 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
811 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
815 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
817 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
825 * ice_init_nvm - initializes NVM setting
826 * @hw: pointer to the HW struct
828 * This function reads and populates NVM settings such as Shadow RAM size,
829 * max_timeout, and blank_nvm_mode
831 enum ice_status ice_init_nvm(struct ice_hw *hw)
833 struct ice_flash_info *flash = &hw->flash;
834 enum ice_status status;
838 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
840 /* The SR size is stored regardless of the NVM programming mode
841 * as the blank mode may be used in the factory line.
843 gens_stat = rd32(hw, GLNVM_GENS);
844 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
846 /* Switching to words (sr_size contains power of 2) */
847 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
849 /* Check if we are in the normal or blank NVM programming mode */
850 fla = rd32(hw, GLNVM_FLA);
851 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
852 flash->blank_nvm_mode = false;
854 /* Blank programming mode */
855 flash->blank_nvm_mode = true;
856 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
857 return ICE_ERR_NVM_BLANK_MODE;
860 status = ice_discover_flash_size(hw);
862 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");
866 status = ice_determine_active_flash_banks(hw);
868 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
872 status = ice_get_nvm_ver_info(hw, &flash->nvm);
874 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
878 status = ice_get_orom_ver_info(hw, &flash->orom);
880 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
888 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
889 * @hw: pointer to the HW structure
890 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
891 * @words: (in) number of words to read; (out) number of words actually read
892 * @data: words read from the Shadow RAM
894 * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
895 * method. The buf read is preceded by the NVM ownership take
896 * and followed by the release.
899 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
901 enum ice_status status;
903 status = ice_acquire_nvm(hw, ICE_RES_READ);
905 status = ice_read_sr_buf_aq(hw, offset, words, data);
913 * ice_nvm_validate_checksum
914 * @hw: pointer to the HW struct
916 * Verify NVM PFA checksum validity (0x0706)
918 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
920 struct ice_aqc_nvm_checksum *cmd;
921 struct ice_aq_desc desc;
922 enum ice_status status;
924 status = ice_acquire_nvm(hw, ICE_RES_READ);
928 cmd = &desc.params.nvm_checksum;
930 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
931 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
933 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
937 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
938 status = ICE_ERR_NVM_CHECKSUM;
944 * ice_nvm_access_get_features - Return the NVM access features structure
945 * @cmd: NVM access command to process
946 * @data: storage for the driver NVM features
948 * Fill in the data section of the NVM access request with a copy of the NVM
949 * features structure.
952 ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
953 union ice_nvm_access_data *data)
955 /* The provided data_size must be at least as large as our NVM
956 * features structure. A larger size should not be treated as an
957 * error, to allow future extensions to the features structure to
958 * work on older drivers.
960 if (cmd->data_size < sizeof(struct ice_nvm_features))
961 return ICE_ERR_NO_MEMORY;
963 /* Initialize the data buffer to zeros */
964 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
966 /* Fill in the features data */
967 data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
968 data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
969 data->drv_features.size = sizeof(struct ice_nvm_features);
970 data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
976 * ice_nvm_access_get_module - Helper function to read module value
977 * @cmd: NVM access command structure
979 * Reads the module value out of the NVM access config field.
981 u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)
983 return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
987 * ice_nvm_access_get_flags - Helper function to read flags value
988 * @cmd: NVM access command structure
990 * Reads the flags value out of the NVM access config field.
992 u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)
994 return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
998 * ice_nvm_access_get_adapter - Helper function to read adapter info
999 * @cmd: NVM access command structure
1001 * Read the adapter info value out of the NVM access config field.
1003 u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)
1005 return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
1006 ICE_NVM_CFG_ADAPTER_INFO_S);
1010 * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
1011 * @cmd: NVM access command structure
1013 * Validates that an NVM access structure is request to read or write a valid
1014 * register offset. First validates that the module and flags are correct, and
1015 * then ensures that the register offset is one of the accepted registers.
1017 static enum ice_status
1018 ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
1020 u32 module, flags, offset;
1023 module = ice_nvm_access_get_module(cmd);
1024 flags = ice_nvm_access_get_flags(cmd);
1025 offset = cmd->offset;
1027 /* Make sure the module and flags indicate a read/write request */
1028 if (module != ICE_NVM_REG_RW_MODULE ||
1029 flags != ICE_NVM_REG_RW_FLAGS ||
1030 cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))
1031 return ICE_ERR_PARAM;
1035 case GL_HICR_EN: /* Note, this register is read only */
1038 case GLGEN_CSR_DEBUG_C:
1040 case GLPCI_LBARCTRL:
1049 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
1050 if (offset == (u32)GL_HIDA(i))
1053 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
1054 if (offset == (u32)GL_HIBA(i))
1057 /* All other register offsets are not valid */
1058 return ICE_ERR_OUT_OF_RANGE;
1062 * ice_nvm_access_read - Handle an NVM read request
1063 * @hw: pointer to the HW struct
1064 * @cmd: NVM access command to process
1065 * @data: storage for the register value read
1067 * Process an NVM access request to read a register.
1070 ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1071 union ice_nvm_access_data *data)
1073 enum ice_status status;
1075 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1077 /* Always initialize the output data, even on failure */
1078 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
1080 /* Make sure this is a valid read/write access request */
1081 status = ice_validate_nvm_rw_reg(cmd);
1085 ice_debug(hw, ICE_DBG_NVM, "NVM access: reading register %08x\n",
1088 /* Read the register and store the contents in the data field */
1089 data->regval = rd32(hw, cmd->offset);
1095 * ice_nvm_access_write - Handle an NVM write request
1096 * @hw: pointer to the HW struct
1097 * @cmd: NVM access command to process
1098 * @data: NVM access data to write
1100 * Process an NVM access request to write a register.
1103 ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1104 union ice_nvm_access_data *data)
1106 enum ice_status status;
1108 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1110 /* Make sure this is a valid read/write access request */
1111 status = ice_validate_nvm_rw_reg(cmd);
1115 /* Reject requests to write to read-only registers */
1116 switch (cmd->offset) {
1119 return ICE_ERR_OUT_OF_RANGE;
1124 ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n",
1125 cmd->offset, data->regval);
1127 /* Write the data field to the specified register */
1128 wr32(hw, cmd->offset, data->regval);
1134 * ice_handle_nvm_access - Handle an NVM access request
1135 * @hw: pointer to the HW struct
1136 * @cmd: NVM access command info
1137 * @data: pointer to read or return data
1139 * Process an NVM access request. Read the command structure information and
1140 * determine if it is valid. If not, report an error indicating the command
1143 * For valid commands, perform the necessary function, copying the data into
1144 * the provided data buffer.
1147 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1148 union ice_nvm_access_data *data)
1150 u32 module, flags, adapter_info;
1152 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1154 /* Extended flags are currently reserved and must be zero */
1155 if ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)
1156 return ICE_ERR_PARAM;
1158 /* Adapter info must match the HW device ID */
1159 adapter_info = ice_nvm_access_get_adapter(cmd);
1160 if (adapter_info != hw->device_id)
1161 return ICE_ERR_PARAM;
1163 switch (cmd->command) {
1164 case ICE_NVM_CMD_READ:
1165 module = ice_nvm_access_get_module(cmd);
1166 flags = ice_nvm_access_get_flags(cmd);
1168 /* Getting the driver's NVM features structure shares the same
1169 * command type as reading a register. Read the config field
1170 * to determine if this is a request to get features.
1172 if (module == ICE_NVM_GET_FEATURES_MODULE &&
1173 flags == ICE_NVM_GET_FEATURES_FLAGS &&
1175 return ice_nvm_access_get_features(cmd, data);
1177 return ice_nvm_access_read(hw, cmd, data);
1178 case ICE_NVM_CMD_WRITE:
1179 return ice_nvm_access_write(hw, cmd, data);
1181 return ICE_ERR_PARAM;