1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
5 #include "ice_common.h"
10 * @hw: pointer to the HW struct
11 * @module_typeid: module pointer location in words from the NVM beginning
12 * @offset: byte offset from the module beginning
13 * @length: length of the section to be read (in bytes from the offset)
14 * @data: command buffer (size [bytes] = length)
15 * @last_command: tells if this is the last command in a series
16 * @cd: pointer to command details structure or NULL
18 * Read the NVM using the admin queue commands (0x0701)
20 static enum ice_status
21 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
22 void *data, bool last_command, struct ice_sq_cd *cd)
24 struct ice_aq_desc desc;
25 struct ice_aqc_nvm *cmd;
27 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_read_nvm");
29 cmd = &desc.params.nvm;
31 /* In offset the highest byte must be zeroed. */
32 if (offset & 0xFF000000)
35 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
37 /* If this is the last command in a series, set the proper flag. */
39 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
40 cmd->module_typeid = CPU_TO_LE16(module_typeid);
41 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
42 cmd->offset_high = (offset >> 16) & 0xFF;
43 cmd->length = CPU_TO_LE16(length);
45 return ice_aq_send_cmd(hw, &desc, data, length, cd);
49 * ice_check_sr_access_params - verify params for Shadow RAM R/W operations.
50 * @hw: pointer to the HW structure
51 * @offset: offset in words from module start
52 * @words: number of words to access
54 static enum ice_status
55 ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words)
57 if ((offset + words) > hw->nvm.sr_words) {
58 ice_debug(hw, ICE_DBG_NVM,
59 "NVM error: offset beyond SR lmt.\n");
63 if (words > ICE_SR_SECTOR_SIZE_IN_WORDS) {
64 /* We can access only up to 4KB (one sector), in one AQ write */
65 ice_debug(hw, ICE_DBG_NVM,
66 "NVM error: tried to access %d words, limit is %d.\n",
67 words, ICE_SR_SECTOR_SIZE_IN_WORDS);
71 if (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) !=
72 (offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) {
73 /* A single access cannot spread over two sectors */
74 ice_debug(hw, ICE_DBG_NVM,
75 "NVM error: cannot spread over two sectors.\n");
83 * ice_read_sr_aq - Read Shadow RAM.
84 * @hw: pointer to the HW structure
85 * @offset: offset in words from module start
86 * @words: number of words to read
87 * @data: buffer for words reads from Shadow RAM
88 * @last_command: tells the AdminQ that this is the last command
90 * Reads 16-bit word buffers from the Shadow RAM using the admin command.
92 static enum ice_status
93 ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,
96 enum ice_status status;
98 ice_debug(hw, ICE_DBG_TRACE, "ice_read_sr_aq");
100 status = ice_check_sr_access_params(hw, offset, words);
102 /* values in "offset" and "words" parameters are sized as words
103 * (16 bits) but ice_aq_read_nvm expects these values in bytes.
104 * So do this conversion while calling ice_aq_read_nvm.
107 status = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data,
114 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
115 * @hw: pointer to the HW structure
116 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
117 * @data: word read from the Shadow RAM
119 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method.
121 static enum ice_status
122 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
124 enum ice_status status;
126 ice_debug(hw, ICE_DBG_TRACE, "ice_read_sr_word_aq");
128 status = ice_read_sr_aq(hw, offset, 1, data, true);
130 *data = LE16_TO_CPU(*(__le16 *)data);
137 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
138 * @hw: pointer to the HW structure
139 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
140 * @words: (in) number of words to read; (out) number of words actually read
141 * @data: words read from the Shadow RAM
143 * Reads 16 bit words (data buf) from the SR using the ice_read_sr_aq
144 * method. Ownership of the NVM is taken before reading the buffer and later
147 static enum ice_status
148 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
150 enum ice_status status;
151 bool last_cmd = false;
155 ice_debug(hw, ICE_DBG_TRACE, "ice_read_sr_buf_aq");
158 u16 read_size, off_w;
160 /* Calculate number of bytes we should read in this step.
161 * It's not allowed to read more than one page at a time or
162 * to cross page boundaries.
164 off_w = offset % ICE_SR_SECTOR_SIZE_IN_WORDS;
167 (ICE_SR_SECTOR_SIZE_IN_WORDS - off_w)) :
168 MIN_T(u16, (*words - words_read),
169 ICE_SR_SECTOR_SIZE_IN_WORDS);
171 /* Check if this is last command, if so set proper flag */
172 if ((words_read + read_size) >= *words)
175 status = ice_read_sr_aq(hw, offset, read_size,
176 data + words_read, last_cmd);
178 goto read_nvm_buf_aq_exit;
180 /* Increment counter for words already read and move offset to
183 words_read += read_size;
185 } while (words_read < *words);
187 for (i = 0; i < *words; i++)
188 data[i] = LE16_TO_CPU(((__le16 *)data)[i]);
190 read_nvm_buf_aq_exit:
196 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
197 * @hw: pointer to the HW structure
198 * @access: NVM access type (read or write)
200 * This function will request NVM ownership.
202 static enum ice_status
203 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
205 ice_debug(hw, ICE_DBG_TRACE, "ice_acquire_nvm");
207 if (hw->nvm.blank_nvm_mode)
210 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
214 * ice_release_nvm - Generic request for releasing the NVM ownership
215 * @hw: pointer to the HW structure
217 * This function will release NVM ownership.
219 static void ice_release_nvm(struct ice_hw *hw)
221 ice_debug(hw, ICE_DBG_TRACE, "ice_release_nvm");
223 if (hw->nvm.blank_nvm_mode)
226 ice_release_res(hw, ICE_NVM_RES_ID);
230 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
231 * @hw: pointer to the HW structure
232 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
233 * @data: word read from the Shadow RAM
235 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
237 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
239 enum ice_status status;
241 status = ice_acquire_nvm(hw, ICE_RES_READ);
243 status = ice_read_sr_word_aq(hw, offset, data);
251 * ice_init_nvm - initializes NVM setting
252 * @hw: pointer to the HW struct
254 * This function reads and populates NVM settings such as Shadow RAM size,
255 * max_timeout, and blank_nvm_mode
257 enum ice_status ice_init_nvm(struct ice_hw *hw)
259 struct ice_nvm_info *nvm = &hw->nvm;
260 u16 oem_hi, oem_lo, cfg_ptr;
261 u16 eetrack_lo, eetrack_hi;
262 enum ice_status status = ICE_SUCCESS;
266 ice_debug(hw, ICE_DBG_TRACE, "ice_init_nvm");
268 /* The SR size is stored regardless of the NVM programming mode
269 * as the blank mode may be used in the factory line.
271 gens_stat = rd32(hw, GLNVM_GENS);
272 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
274 /* Switching to words (sr_size contains power of 2) */
275 nvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
277 /* Check if we are in the normal or blank NVM programming mode */
278 fla = rd32(hw, GLNVM_FLA);
279 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
280 nvm->blank_nvm_mode = false;
281 } else { /* Blank programming mode */
282 nvm->blank_nvm_mode = true;
283 status = ICE_ERR_NVM_BLANK_MODE;
284 ice_debug(hw, ICE_DBG_NVM,
285 "NVM init error: unsupported blank mode.\n");
289 status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &hw->nvm.ver);
291 ice_debug(hw, ICE_DBG_INIT,
292 "Failed to read DEV starter version.\n");
296 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
298 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK lo.\n");
301 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
303 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK hi.\n");
307 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
309 status = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);
311 ice_debug(hw, ICE_DBG_INIT, "Failed to read BOOT_CONFIG_PTR.\n");
315 status = ice_read_sr_word(hw, (cfg_ptr + ICE_NVM_OEM_VER_OFF), &oem_hi);
317 ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER hi.\n");
321 status = ice_read_sr_word(hw, (cfg_ptr + (ICE_NVM_OEM_VER_OFF + 1)),
324 ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER lo.\n");
328 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;
334 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
335 * @hw: pointer to the HW structure
336 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
337 * @words: (in) number of words to read; (out) number of words actually read
338 * @data: words read from the Shadow RAM
340 * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
341 * method. The buf read is preceded by the NVM ownership take
342 * and followed by the release.
345 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
347 enum ice_status status;
349 status = ice_acquire_nvm(hw, ICE_RES_READ);
351 status = ice_read_sr_buf_aq(hw, offset, words, data);
360 * ice_nvm_validate_checksum
361 * @hw: pointer to the HW struct
363 * Verify NVM PFA checksum validity (0x0706)
365 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
367 struct ice_aqc_nvm_checksum *cmd;
368 struct ice_aq_desc desc;
369 enum ice_status status;
371 status = ice_acquire_nvm(hw, ICE_RES_READ);
375 cmd = &desc.params.nvm_checksum;
377 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
378 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
380 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
384 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
385 status = ICE_ERR_NVM_CHECKSUM;