1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
9 * @hw: pointer to the HW struct
10 * @module_typeid: module pointer location in words from the NVM beginning
11 * @offset: byte offset from the module beginning
12 * @length: length of the section to be read (in bytes from the offset)
13 * @data: command buffer (size [bytes] = length)
14 * @last_command: tells if this is the last command in a series
15 * @read_shadow_ram: tell if this is a shadow RAM read
16 * @cd: pointer to command details structure or NULL
18 * Read the NVM using the admin queue commands (0x0701)
21 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
22 void *data, bool last_command, bool read_shadow_ram,
25 struct ice_aq_desc desc;
26 struct ice_aqc_nvm *cmd;
28 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
30 cmd = &desc.params.nvm;
32 if (offset > ICE_AQC_NVM_MAX_OFFSET)
35 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
37 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
38 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
40 /* If this is the last command in a series, set the proper flag. */
42 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
43 cmd->module_typeid = CPU_TO_LE16(module_typeid);
44 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
45 cmd->offset_high = (offset >> 16) & 0xFF;
46 cmd->length = CPU_TO_LE16(length);
48 return ice_aq_send_cmd(hw, &desc, data, length, cd);
52 * ice_read_flat_nvm - Read portion of NVM by flat offset
53 * @hw: pointer to the HW struct
54 * @offset: offset from beginning of NVM
55 * @length: (in) number of bytes to read; (out) number of bytes actually read
56 * @data: buffer to return data in (sized to fit the specified length)
57 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
59 * Reads a portion of the NVM, as a flat memory space. This function correctly
60 * breaks read requests across Shadow RAM sectors and ensures that no single
61 * read request exceeds the maximum 4Kb read for a single AdminQ command.
63 * Returns a status code on failure. Note that the data pointer may be
64 * partially updated if some reads succeed before a failure.
67 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
70 enum ice_status status;
75 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
79 /* Verify the length of the read if this is for the Shadow RAM */
80 if (read_shadow_ram && ((offset + inlen) > (hw->nvm.sr_words * 2u))) {
81 ice_debug(hw, ICE_DBG_NVM,
82 "NVM error: requested data is beyond Shadow RAM limit\n");
87 u32 read_size, sector_offset;
89 /* ice_aq_read_nvm cannot read more than 4Kb at a time.
90 * Additionally, a read from the Shadow RAM may not cross over
91 * a sector boundary. Conveniently, the sector size is also
94 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
95 read_size = MIN_T(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
98 last_cmd = !(bytes_read + read_size < inlen);
100 /* ice_aq_read_nvm takes the length as a u16. Our read_size is
101 * calculated using a u32, but the ICE_AQ_MAX_BUF_LEN maximum
102 * size guarantees that it will fit within the 2 bytes.
104 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
105 offset, (u16)read_size,
106 data + bytes_read, last_cmd,
107 read_shadow_ram, NULL);
111 bytes_read += read_size;
115 *length = bytes_read;
120 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
121 * @hw: pointer to the HW structure
122 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
123 * @data: word read from the Shadow RAM
125 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
127 static enum ice_status
128 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
130 u32 bytes = sizeof(u16);
131 enum ice_status status;
134 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
136 /* Note that ice_read_flat_nvm checks if the read is past the Shadow
137 * RAM size, and ensures we don't read across a Shadow RAM sector
140 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
141 (u8 *)&data_local, true);
145 *data = LE16_TO_CPU(data_local);
150 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
151 * @hw: pointer to the HW structure
152 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
153 * @words: (in) number of words to read; (out) number of words actually read
154 * @data: words read from the Shadow RAM
156 * Reads 16 bit words (data buf) from the Shadow RAM. Ownership of the NVM is
157 * taken before reading the buffer and later released.
159 static enum ice_status
160 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
162 u32 bytes = *words * 2, i;
163 enum ice_status status;
165 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
167 /* ice_read_flat_nvm takes into account the 4Kb AdminQ and Shadow RAM
168 * sector restrictions necessary when reading from the NVM.
170 status = ice_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true);
172 /* Report the number of words successfully read */
175 /* Byte swap the words up to the amount we actually read */
176 for (i = 0; i < *words; i++)
177 data[i] = LE16_TO_CPU(((_FORCE_ __le16 *)data)[i]);
183 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
184 * @hw: pointer to the HW structure
185 * @access: NVM access type (read or write)
187 * This function will request NVM ownership.
190 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
192 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
194 if (hw->nvm.blank_nvm_mode)
197 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
201 * ice_release_nvm - Generic request for releasing the NVM ownership
202 * @hw: pointer to the HW structure
204 * This function will release NVM ownership.
206 void ice_release_nvm(struct ice_hw *hw)
208 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
210 if (hw->nvm.blank_nvm_mode)
213 ice_release_res(hw, ICE_NVM_RES_ID);
217 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
218 * @hw: pointer to the HW structure
219 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
220 * @data: word read from the Shadow RAM
222 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
224 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
226 enum ice_status status;
228 status = ice_acquire_nvm(hw, ICE_RES_READ);
230 status = ice_read_sr_word_aq(hw, offset, data);
238 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
239 * @hw: pointer to hardware structure
240 * @module_tlv: pointer to module TLV to return
241 * @module_tlv_len: pointer to module TLV length to return
242 * @module_type: module type requested
244 * Finds the requested sub module TLV type from the Preserved Field
245 * Area (PFA) and returns the TLV pointer and length. The caller can
246 * use these to read the variable length TLV value.
249 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
252 enum ice_status status;
253 u16 pfa_len, pfa_ptr;
256 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
257 if (status != ICE_SUCCESS) {
258 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
261 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
262 if (status != ICE_SUCCESS) {
263 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
266 /* Starting with first TLV after PFA length, iterate through the list
267 * of TLVs to find the requested one.
269 next_tlv = pfa_ptr + 1;
270 while (next_tlv < pfa_ptr + pfa_len) {
271 u16 tlv_sub_module_type;
275 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
276 if (status != ICE_SUCCESS) {
277 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
280 /* Read TLV length */
281 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
282 if (status != ICE_SUCCESS) {
283 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
286 if (tlv_sub_module_type == module_type) {
288 *module_tlv = next_tlv;
289 *module_tlv_len = tlv_len;
292 return ICE_ERR_INVAL_SIZE;
294 /* Check next TLV, i.e. current TLV pointer + length + 2 words
295 * (for current TLV's type and length)
297 next_tlv = next_tlv + tlv_len + 2;
299 /* Module does not exist */
300 return ICE_ERR_DOES_NOT_EXIST;
304 * ice_read_pba_string - Reads part number string from NVM
305 * @hw: pointer to hardware structure
306 * @pba_num: stores the part number string from the NVM
307 * @pba_num_size: part number string buffer length
309 * Reads the part number string from the NVM.
312 ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
314 u16 pba_tlv, pba_tlv_len;
315 enum ice_status status;
316 u16 pba_word, pba_size;
319 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
320 ICE_SR_PBA_BLOCK_PTR);
321 if (status != ICE_SUCCESS) {
322 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
326 /* pba_size is the next word */
327 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
328 if (status != ICE_SUCCESS) {
329 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
333 if (pba_tlv_len < pba_size) {
334 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
335 return ICE_ERR_INVAL_SIZE;
338 /* Subtract one to get PBA word count (PBA Size word is included in
342 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
343 ice_debug(hw, ICE_DBG_INIT,
344 "Buffer too small for PBA data.\n");
345 return ICE_ERR_PARAM;
348 for (i = 0; i < pba_size; i++) {
349 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
350 if (status != ICE_SUCCESS) {
351 ice_debug(hw, ICE_DBG_INIT,
352 "Failed to read PBA Block word %d.\n", i);
356 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
357 pba_num[(i * 2) + 1] = pba_word & 0xFF;
359 pba_num[(pba_size * 2)] = '\0';
365 * ice_get_orom_ver_info - Read Option ROM version information
366 * @hw: pointer to the HW struct
368 * Read the Combo Image version data from the Boot Configuration TLV and fill
369 * in the option ROM version data.
371 static enum ice_status ice_get_orom_ver_info(struct ice_hw *hw)
373 u16 combo_hi, combo_lo, boot_cfg_tlv, boot_cfg_tlv_len;
374 struct ice_orom_info *orom = &hw->nvm.orom;
375 enum ice_status status;
378 status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len,
379 ICE_SR_BOOT_CFG_PTR);
381 ice_debug(hw, ICE_DBG_INIT,
382 "Failed to read Boot Configuration Block TLV.\n");
386 /* Boot Configuration Block must have length at least 2 words
387 * (Combo Image Version High and Combo Image Version Low)
389 if (boot_cfg_tlv_len < 2) {
390 ice_debug(hw, ICE_DBG_INIT,
391 "Invalid Boot Configuration Block TLV size.\n");
392 return ICE_ERR_INVAL_SIZE;
395 status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OROM_VER_OFF),
398 ice_debug(hw, ICE_DBG_INIT, "Failed to read OROM_VER hi.\n");
402 status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OROM_VER_OFF + 1),
405 ice_debug(hw, ICE_DBG_INIT, "Failed to read OROM_VER lo.\n");
409 combo_ver = ((u32)combo_hi << 16) | combo_lo;
411 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >>
413 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK);
414 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >>
415 ICE_OROM_VER_BUILD_SHIFT);
421 * ice_discover_flash_size - Discover the available flash size.
422 * @hw: pointer to the HW struct
424 * The device flash could be up to 16MB in size. However, it is possible that
425 * the actual size is smaller. Use bisection to determine the accessible size
428 static enum ice_status ice_discover_flash_size(struct ice_hw *hw)
430 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
431 enum ice_status status;
433 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
435 status = ice_acquire_nvm(hw, ICE_RES_READ);
439 while ((max_size - min_size) > 1) {
440 u32 offset = (max_size + min_size) / 2;
444 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
445 if (status == ICE_ERR_AQ_ERROR &&
446 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
447 ice_debug(hw, ICE_DBG_NVM,
448 "%s: New upper bound of %u bytes\n",
450 status = ICE_SUCCESS;
452 } else if (!status) {
453 ice_debug(hw, ICE_DBG_NVM,
454 "%s: New lower bound of %u bytes\n",
458 /* an unexpected error occurred */
459 goto err_read_flat_nvm;
463 ice_debug(hw, ICE_DBG_NVM,
464 "Predicted flash size is %u bytes\n", max_size);
466 hw->nvm.flash_size = max_size;
475 * ice_init_nvm - initializes NVM setting
476 * @hw: pointer to the HW struct
478 * This function reads and populates NVM settings such as Shadow RAM size,
479 * max_timeout, and blank_nvm_mode
481 enum ice_status ice_init_nvm(struct ice_hw *hw)
483 struct ice_nvm_info *nvm = &hw->nvm;
484 u16 eetrack_lo, eetrack_hi, ver;
485 enum ice_status status;
489 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
491 /* The SR size is stored regardless of the NVM programming mode
492 * as the blank mode may be used in the factory line.
494 gens_stat = rd32(hw, GLNVM_GENS);
495 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
497 /* Switching to words (sr_size contains power of 2) */
498 nvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
500 /* Check if we are in the normal or blank NVM programming mode */
501 fla = rd32(hw, GLNVM_FLA);
502 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
503 nvm->blank_nvm_mode = false;
505 /* Blank programming mode */
506 nvm->blank_nvm_mode = true;
507 ice_debug(hw, ICE_DBG_NVM,
508 "NVM init error: unsupported blank mode.\n");
509 return ICE_ERR_NVM_BLANK_MODE;
512 status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &ver);
514 ice_debug(hw, ICE_DBG_INIT,
515 "Failed to read DEV starter version.\n");
518 nvm->major_ver = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
519 nvm->minor_ver = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
521 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
523 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK lo.\n");
526 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
528 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK hi.\n");
532 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
534 status = ice_discover_flash_size(hw);
536 ice_debug(hw, ICE_DBG_NVM,
537 "NVM init error: failed to discover flash size.\n");
541 switch (hw->device_id) {
542 /* the following devices do not have boot_cfg_tlv yet */
543 case ICE_DEV_ID_E822C_BACKPLANE:
544 case ICE_DEV_ID_E822C_QSFP:
545 case ICE_DEV_ID_E822C_10G_BASE_T:
546 case ICE_DEV_ID_E822C_SGMII:
547 case ICE_DEV_ID_E822C_SFP:
548 case ICE_DEV_ID_E822L_BACKPLANE:
549 case ICE_DEV_ID_E822L_SFP:
550 case ICE_DEV_ID_E822L_10G_BASE_T:
551 case ICE_DEV_ID_E822L_SGMII:
557 status = ice_get_orom_ver_info(hw);
559 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
567 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
568 * @hw: pointer to the HW structure
569 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
570 * @words: (in) number of words to read; (out) number of words actually read
571 * @data: words read from the Shadow RAM
573 * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
574 * method. The buf read is preceded by the NVM ownership take
575 * and followed by the release.
578 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
580 enum ice_status status;
582 status = ice_acquire_nvm(hw, ICE_RES_READ);
584 status = ice_read_sr_buf_aq(hw, offset, words, data);
592 * ice_nvm_validate_checksum
593 * @hw: pointer to the HW struct
595 * Verify NVM PFA checksum validity (0x0706)
597 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
599 struct ice_aqc_nvm_checksum *cmd;
600 struct ice_aq_desc desc;
601 enum ice_status status;
603 status = ice_acquire_nvm(hw, ICE_RES_READ);
607 cmd = &desc.params.nvm_checksum;
609 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
610 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
612 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
616 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
617 status = ICE_ERR_NVM_CHECKSUM;
623 * ice_nvm_access_get_features - Return the NVM access features structure
624 * @cmd: NVM access command to process
625 * @data: storage for the driver NVM features
627 * Fill in the data section of the NVM access request with a copy of the NVM
628 * features structure.
631 ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
632 union ice_nvm_access_data *data)
634 /* The provided data_size must be at least as large as our NVM
635 * features structure. A larger size should not be treated as an
636 * error, to allow future extensions to to the features structure to
637 * work on older drivers.
639 if (cmd->data_size < sizeof(struct ice_nvm_features))
640 return ICE_ERR_NO_MEMORY;
642 /* Initialize the data buffer to zeros */
643 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
645 /* Fill in the features data */
646 data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
647 data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
648 data->drv_features.size = sizeof(struct ice_nvm_features);
649 data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
655 * ice_nvm_access_get_module - Helper function to read module value
656 * @cmd: NVM access command structure
658 * Reads the module value out of the NVM access config field.
660 u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)
662 return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
666 * ice_nvm_access_get_flags - Helper function to read flags value
667 * @cmd: NVM access command structure
669 * Reads the flags value out of the NVM access config field.
671 u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)
673 return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
677 * ice_nvm_access_get_adapter - Helper function to read adapter info
678 * @cmd: NVM access command structure
680 * Read the adapter info value out of the NVM access config field.
682 u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)
684 return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
685 ICE_NVM_CFG_ADAPTER_INFO_S);
689 * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
690 * @cmd: NVM access command structure
692 * Validates that an NVM access structure is request to read or write a valid
693 * register offset. First validates that the module and flags are correct, and
694 * then ensures that the register offset is one of the accepted registers.
696 static enum ice_status
697 ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
699 u32 module, flags, offset;
702 module = ice_nvm_access_get_module(cmd);
703 flags = ice_nvm_access_get_flags(cmd);
704 offset = cmd->offset;
706 /* Make sure the module and flags indicate a read/write request */
707 if (module != ICE_NVM_REG_RW_MODULE ||
708 flags != ICE_NVM_REG_RW_FLAGS ||
709 cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))
710 return ICE_ERR_PARAM;
714 case GL_HICR_EN: /* Note, this register is read only */
717 case GLGEN_CSR_DEBUG_C:
728 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
729 if (offset == (u32)GL_HIDA(i))
732 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
733 if (offset == (u32)GL_HIBA(i))
736 /* All other register offsets are not valid */
737 return ICE_ERR_OUT_OF_RANGE;
741 * ice_nvm_access_read - Handle an NVM read request
742 * @hw: pointer to the HW struct
743 * @cmd: NVM access command to process
744 * @data: storage for the register value read
746 * Process an NVM access request to read a register.
749 ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
750 union ice_nvm_access_data *data)
752 enum ice_status status;
754 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
756 /* Always initialize the output data, even on failure */
757 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
759 /* Make sure this is a valid read/write access request */
760 status = ice_validate_nvm_rw_reg(cmd);
764 ice_debug(hw, ICE_DBG_NVM, "NVM access: reading register %08x\n",
767 /* Read the register and store the contents in the data field */
768 data->regval = rd32(hw, cmd->offset);
774 * ice_nvm_access_write - Handle an NVM write request
775 * @hw: pointer to the HW struct
776 * @cmd: NVM access command to process
777 * @data: NVM access data to write
779 * Process an NVM access request to write a register.
782 ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
783 union ice_nvm_access_data *data)
785 enum ice_status status;
787 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
789 /* Make sure this is a valid read/write access request */
790 status = ice_validate_nvm_rw_reg(cmd);
794 /* Reject requests to write to read-only registers */
795 switch (cmd->offset) {
798 return ICE_ERR_OUT_OF_RANGE;
803 ice_debug(hw, ICE_DBG_NVM,
804 "NVM access: writing register %08x with value %08x\n",
805 cmd->offset, data->regval);
807 /* Write the data field to the specified register */
808 wr32(hw, cmd->offset, data->regval);
814 * ice_handle_nvm_access - Handle an NVM access request
815 * @hw: pointer to the HW struct
816 * @cmd: NVM access command info
817 * @data: pointer to read or return data
819 * Process an NVM access request. Read the command structure information and
820 * determine if it is valid. If not, report an error indicating the command
823 * For valid commands, perform the necessary function, copying the data into
824 * the provided data buffer.
827 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
828 union ice_nvm_access_data *data)
830 u32 module, flags, adapter_info;
832 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
834 /* Extended flags are currently reserved and must be zero */
835 if ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)
836 return ICE_ERR_PARAM;
838 /* Adapter info must match the HW device ID */
839 adapter_info = ice_nvm_access_get_adapter(cmd);
840 if (adapter_info != hw->device_id)
841 return ICE_ERR_PARAM;
843 switch (cmd->command) {
844 case ICE_NVM_CMD_READ:
845 module = ice_nvm_access_get_module(cmd);
846 flags = ice_nvm_access_get_flags(cmd);
848 /* Getting the driver's NVM features structure shares the same
849 * command type as reading a register. Read the config field
850 * to determine if this is a request to get features.
852 if (module == ICE_NVM_GET_FEATURES_MODULE &&
853 flags == ICE_NVM_GET_FEATURES_FLAGS &&
855 return ice_nvm_access_get_features(cmd, data);
857 return ice_nvm_access_read(hw, cmd, data);
858 case ICE_NVM_CMD_WRITE:
859 return ice_nvm_access_write(hw, cmd, data);
861 return ICE_ERR_PARAM;