1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
10 * @hw: pointer to the HW struct
11 * @module_typeid: module pointer location in words from the NVM beginning
12 * @offset: byte offset from the module beginning
13 * @length: length of the section to be read (in bytes from the offset)
14 * @data: command buffer (size [bytes] = length)
15 * @last_command: tells if this is the last command in a series
16 * @read_shadow_ram: tell if this is a shadow RAM read
17 * @cd: pointer to command details structure or NULL
19 * Read the NVM using the admin queue commands (0x0701)
21 static enum ice_status
22 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
23 void *data, bool last_command, bool read_shadow_ram,
26 struct ice_aq_desc desc;
27 struct ice_aqc_nvm *cmd;
29 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
31 cmd = &desc.params.nvm;
33 /* In offset the highest byte must be zeroed. */
34 if (offset & 0xFF000000)
37 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
39 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
40 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
42 /* If this is the last command in a series, set the proper flag. */
44 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
45 cmd->module_typeid = CPU_TO_LE16(module_typeid);
46 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
47 cmd->offset_high = (offset >> 16) & 0xFF;
48 cmd->length = CPU_TO_LE16(length);
50 return ice_aq_send_cmd(hw, &desc, data, length, cd);
54 * ice_check_sr_access_params - verify params for Shadow RAM R/W operations.
55 * @hw: pointer to the HW structure
56 * @offset: offset in words from module start
57 * @words: number of words to access
59 static enum ice_status
60 ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words)
62 if ((offset + words) > hw->nvm.sr_words) {
63 ice_debug(hw, ICE_DBG_NVM,
64 "NVM error: offset beyond SR lmt.\n");
68 if (words > ICE_SR_SECTOR_SIZE_IN_WORDS) {
69 /* We can access only up to 4KB (one sector), in one AQ write */
70 ice_debug(hw, ICE_DBG_NVM,
71 "NVM error: tried to access %d words, limit is %d.\n",
72 words, ICE_SR_SECTOR_SIZE_IN_WORDS);
76 if (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) !=
77 (offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) {
78 /* A single access cannot spread over two sectors */
79 ice_debug(hw, ICE_DBG_NVM,
80 "NVM error: cannot spread over two sectors.\n");
88 * ice_read_sr_aq - Read Shadow RAM.
89 * @hw: pointer to the HW structure
90 * @offset: offset in words from module start
91 * @words: number of words to read
92 * @data: buffer for words reads from Shadow RAM
93 * @last_command: tells the AdminQ that this is the last command
95 * Reads 16-bit word buffers from the Shadow RAM using the admin command.
97 static enum ice_status
98 ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,
101 enum ice_status status;
103 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
105 status = ice_check_sr_access_params(hw, offset, words);
107 /* values in "offset" and "words" parameters are sized as words
108 * (16 bits) but ice_aq_read_nvm expects these values in bytes.
109 * So do this conversion while calling ice_aq_read_nvm.
112 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
113 2 * offset, 2 * words, data,
114 last_command, true, NULL);
120 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
121 * @hw: pointer to the HW structure
122 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
123 * @data: word read from the Shadow RAM
125 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method.
127 static enum ice_status
128 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
130 enum ice_status status;
132 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
134 status = ice_read_sr_aq(hw, offset, 1, data, true);
136 *data = LE16_TO_CPU(*(_FORCE_ __le16 *)data);
143 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
144 * @hw: pointer to the HW structure
145 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
146 * @words: (in) number of words to read; (out) number of words actually read
147 * @data: words read from the Shadow RAM
149 * Reads 16 bit words (data buf) from the SR using the ice_read_sr_aq
150 * method. Ownership of the NVM is taken before reading the buffer and later
153 static enum ice_status
154 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
156 enum ice_status status;
157 bool last_cmd = false;
161 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
164 u16 read_size, off_w;
166 /* Calculate number of bytes we should read in this step.
167 * It's not allowed to read more than one page at a time or
168 * to cross page boundaries.
170 off_w = offset % ICE_SR_SECTOR_SIZE_IN_WORDS;
173 (ICE_SR_SECTOR_SIZE_IN_WORDS - off_w)) :
174 MIN_T(u16, (*words - words_read),
175 ICE_SR_SECTOR_SIZE_IN_WORDS);
177 /* Check if this is last command, if so set proper flag */
178 if ((words_read + read_size) >= *words)
181 status = ice_read_sr_aq(hw, offset, read_size,
182 data + words_read, last_cmd);
184 goto read_nvm_buf_aq_exit;
186 /* Increment counter for words already read and move offset to
189 words_read += read_size;
191 } while (words_read < *words);
193 for (i = 0; i < *words; i++)
194 data[i] = LE16_TO_CPU(((_FORCE_ __le16 *)data)[i]);
196 read_nvm_buf_aq_exit:
202 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
203 * @hw: pointer to the HW structure
204 * @access: NVM access type (read or write)
206 * This function will request NVM ownership.
208 static enum ice_status
209 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
211 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
213 if (hw->nvm.blank_nvm_mode)
216 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
220 * ice_release_nvm - Generic request for releasing the NVM ownership
221 * @hw: pointer to the HW structure
223 * This function will release NVM ownership.
225 static void ice_release_nvm(struct ice_hw *hw)
227 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
229 if (hw->nvm.blank_nvm_mode)
232 ice_release_res(hw, ICE_NVM_RES_ID);
236 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
237 * @hw: pointer to the HW structure
238 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
239 * @data: word read from the Shadow RAM
241 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
243 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
245 enum ice_status status;
247 status = ice_acquire_nvm(hw, ICE_RES_READ);
249 status = ice_read_sr_word_aq(hw, offset, data);
257 * ice_init_nvm - initializes NVM setting
258 * @hw: pointer to the HW struct
260 * This function reads and populates NVM settings such as Shadow RAM size,
261 * max_timeout, and blank_nvm_mode
263 enum ice_status ice_init_nvm(struct ice_hw *hw)
265 struct ice_nvm_info *nvm = &hw->nvm;
266 u16 oem_hi, oem_lo, cfg_ptr;
267 u16 eetrack_lo, eetrack_hi;
268 enum ice_status status = ICE_SUCCESS;
272 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
274 /* The SR size is stored regardless of the NVM programming mode
275 * as the blank mode may be used in the factory line.
277 gens_stat = rd32(hw, GLNVM_GENS);
278 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
280 /* Switching to words (sr_size contains power of 2) */
281 nvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
283 /* Check if we are in the normal or blank NVM programming mode */
284 fla = rd32(hw, GLNVM_FLA);
285 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
286 nvm->blank_nvm_mode = false;
287 } else { /* Blank programming mode */
288 nvm->blank_nvm_mode = true;
289 status = ICE_ERR_NVM_BLANK_MODE;
290 ice_debug(hw, ICE_DBG_NVM,
291 "NVM init error: unsupported blank mode.\n");
295 status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &nvm->ver);
297 ice_debug(hw, ICE_DBG_INIT,
298 "Failed to read DEV starter version.\n");
302 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
304 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK lo.\n");
307 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
309 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK hi.\n");
313 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
315 status = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);
317 ice_debug(hw, ICE_DBG_INIT, "Failed to read BOOT_CONFIG_PTR.\n");
321 status = ice_read_sr_word(hw, (cfg_ptr + ICE_NVM_OEM_VER_OFF), &oem_hi);
323 ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER hi.\n");
327 status = ice_read_sr_word(hw, (cfg_ptr + (ICE_NVM_OEM_VER_OFF + 1)),
330 ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER lo.\n");
334 nvm->oem_ver = ((u32)oem_hi << 16) | oem_lo;
340 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
341 * @hw: pointer to the HW structure
342 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
343 * @words: (in) number of words to read; (out) number of words actually read
344 * @data: words read from the Shadow RAM
346 * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
347 * method. The buf read is preceded by the NVM ownership take
348 * and followed by the release.
351 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
353 enum ice_status status;
355 status = ice_acquire_nvm(hw, ICE_RES_READ);
357 status = ice_read_sr_buf_aq(hw, offset, words, data);
366 * ice_nvm_validate_checksum
367 * @hw: pointer to the HW struct
369 * Verify NVM PFA checksum validity (0x0706)
371 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
373 struct ice_aqc_nvm_checksum *cmd;
374 struct ice_aq_desc desc;
375 enum ice_status status;
377 status = ice_acquire_nvm(hw, ICE_RES_READ);
381 cmd = &desc.params.nvm_checksum;
383 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
384 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
386 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
390 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
391 status = ICE_ERR_NVM_CHECKSUM;