1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
9 * @hw: pointer to the HW struct
10 * @module_typeid: module pointer location in words from the NVM beginning
11 * @offset: byte offset from the module beginning
12 * @length: length of the section to be read (in bytes from the offset)
13 * @data: command buffer (size [bytes] = length)
14 * @last_command: tells if this is the last command in a series
15 * @read_shadow_ram: tell if this is a shadow RAM read
16 * @cd: pointer to command details structure or NULL
18 * Read the NVM using the admin queue commands (0x0701)
20 static enum ice_status
21 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
22 void *data, bool last_command, bool read_shadow_ram,
25 struct ice_aq_desc desc;
26 struct ice_aqc_nvm *cmd;
28 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
30 cmd = &desc.params.nvm;
32 /* In offset the highest byte must be zeroed. */
33 if (offset & 0xFF000000)
36 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
38 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
39 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
41 /* If this is the last command in a series, set the proper flag. */
43 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
44 cmd->module_typeid = CPU_TO_LE16(module_typeid);
45 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
46 cmd->offset_high = (offset >> 16) & 0xFF;
47 cmd->length = CPU_TO_LE16(length);
49 return ice_aq_send_cmd(hw, &desc, data, length, cd);
53 * ice_check_sr_access_params - verify params for Shadow RAM R/W operations.
54 * @hw: pointer to the HW structure
55 * @offset: offset in words from module start
56 * @words: number of words to access
58 static enum ice_status
59 ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words)
61 if ((offset + words) > hw->nvm.sr_words) {
62 ice_debug(hw, ICE_DBG_NVM,
63 "NVM error: offset beyond SR lmt.\n");
67 if (words > ICE_SR_SECTOR_SIZE_IN_WORDS) {
68 /* We can access only up to 4KB (one sector), in one AQ write */
69 ice_debug(hw, ICE_DBG_NVM,
70 "NVM error: tried to access %d words, limit is %d.\n",
71 words, ICE_SR_SECTOR_SIZE_IN_WORDS);
75 if (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) !=
76 (offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) {
77 /* A single access cannot spread over two sectors */
78 ice_debug(hw, ICE_DBG_NVM,
79 "NVM error: cannot spread over two sectors.\n");
87 * ice_read_sr_aq - Read Shadow RAM.
88 * @hw: pointer to the HW structure
89 * @offset: offset in words from module start
90 * @words: number of words to read
91 * @data: buffer for words reads from Shadow RAM
92 * @last_command: tells the AdminQ that this is the last command
94 * Reads 16-bit word buffers from the Shadow RAM using the admin command.
96 static enum ice_status
97 ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,
100 enum ice_status status;
102 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
104 status = ice_check_sr_access_params(hw, offset, words);
106 /* values in "offset" and "words" parameters are sized as words
107 * (16 bits) but ice_aq_read_nvm expects these values in bytes.
108 * So do this conversion while calling ice_aq_read_nvm.
111 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
112 2 * offset, 2 * words, data,
113 last_command, true, NULL);
119 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
120 * @hw: pointer to the HW structure
121 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
122 * @data: word read from the Shadow RAM
124 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method.
126 static enum ice_status
127 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
129 enum ice_status status;
131 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
133 status = ice_read_sr_aq(hw, offset, 1, data, true);
135 *data = LE16_TO_CPU(*(_FORCE_ __le16 *)data);
141 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
142 * @hw: pointer to the HW structure
143 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
144 * @words: (in) number of words to read; (out) number of words actually read
145 * @data: words read from the Shadow RAM
147 * Reads 16 bit words (data buf) from the SR using the ice_read_sr_aq
148 * method. Ownership of the NVM is taken before reading the buffer and later
151 static enum ice_status
152 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
154 enum ice_status status;
155 bool last_cmd = false;
159 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
162 u16 read_size, off_w;
164 /* Calculate number of bytes we should read in this step.
165 * It's not allowed to read more than one page at a time or
166 * to cross page boundaries.
168 off_w = offset % ICE_SR_SECTOR_SIZE_IN_WORDS;
171 (ICE_SR_SECTOR_SIZE_IN_WORDS - off_w)) :
172 MIN_T(u16, (*words - words_read),
173 ICE_SR_SECTOR_SIZE_IN_WORDS);
175 /* Check if this is last command, if so set proper flag */
176 if ((words_read + read_size) >= *words)
179 status = ice_read_sr_aq(hw, offset, read_size,
180 data + words_read, last_cmd);
182 goto read_nvm_buf_aq_exit;
184 /* Increment counter for words already read and move offset to
187 words_read += read_size;
189 } while (words_read < *words);
191 for (i = 0; i < *words; i++)
192 data[i] = LE16_TO_CPU(((_FORCE_ __le16 *)data)[i]);
194 read_nvm_buf_aq_exit:
200 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
201 * @hw: pointer to the HW structure
202 * @access: NVM access type (read or write)
204 * This function will request NVM ownership.
206 static enum ice_status
207 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
209 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
211 if (hw->nvm.blank_nvm_mode)
214 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
218 * ice_release_nvm - Generic request for releasing the NVM ownership
219 * @hw: pointer to the HW structure
221 * This function will release NVM ownership.
223 static void ice_release_nvm(struct ice_hw *hw)
225 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
227 if (hw->nvm.blank_nvm_mode)
230 ice_release_res(hw, ICE_NVM_RES_ID);
234 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
235 * @hw: pointer to the HW structure
236 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
237 * @data: word read from the Shadow RAM
239 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
241 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
243 enum ice_status status;
245 status = ice_acquire_nvm(hw, ICE_RES_READ);
247 status = ice_read_sr_word_aq(hw, offset, data);
255 * ice_init_nvm - initializes NVM setting
256 * @hw: pointer to the HW struct
258 * This function reads and populates NVM settings such as Shadow RAM size,
259 * max_timeout, and blank_nvm_mode
261 enum ice_status ice_init_nvm(struct ice_hw *hw)
263 struct ice_nvm_info *nvm = &hw->nvm;
264 u16 oem_hi, oem_lo, boot_cfg_tlv, boot_cfg_tlv_len;
265 u16 eetrack_lo, eetrack_hi;
266 enum ice_status status;
270 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
272 /* The SR size is stored regardless of the NVM programming mode
273 * as the blank mode may be used in the factory line.
275 gens_stat = rd32(hw, GLNVM_GENS);
276 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
278 /* Switching to words (sr_size contains power of 2) */
279 nvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
281 /* Check if we are in the normal or blank NVM programming mode */
282 fla = rd32(hw, GLNVM_FLA);
283 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
284 nvm->blank_nvm_mode = false;
286 /* Blank programming mode */
287 nvm->blank_nvm_mode = true;
288 ice_debug(hw, ICE_DBG_NVM,
289 "NVM init error: unsupported blank mode.\n");
290 return ICE_ERR_NVM_BLANK_MODE;
293 status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &nvm->ver);
295 ice_debug(hw, ICE_DBG_INIT,
296 "Failed to read DEV starter version.\n");
300 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
302 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK lo.\n");
305 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
307 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK hi.\n");
311 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
313 /* the following devices do not have boot_cfg_tlv yet */
314 if (hw->device_id == ICE_DEV_ID_C822N_BACKPLANE ||
315 hw->device_id == ICE_DEV_ID_C822N_QSFP ||
316 hw->device_id == ICE_DEV_ID_C822N_SFP)
319 status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len,
320 ICE_SR_BOOT_CFG_PTR);
322 ice_debug(hw, ICE_DBG_INIT,
323 "Failed to read Boot Configuration Block TLV.\n");
327 /* Boot Configuration Block must have length at least 2 words
328 * (Combo Image Version High and Combo Image Version Low)
330 if (boot_cfg_tlv_len < 2) {
331 ice_debug(hw, ICE_DBG_INIT,
332 "Invalid Boot Configuration Block TLV size.\n");
333 return ICE_ERR_INVAL_SIZE;
336 status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OEM_VER_OFF),
339 ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER hi.\n");
343 status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OEM_VER_OFF + 1),
346 ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER lo.\n");
350 nvm->oem_ver = ((u32)oem_hi << 16) | oem_lo;
356 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
357 * @hw: pointer to the HW structure
358 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
359 * @words: (in) number of words to read; (out) number of words actually read
360 * @data: words read from the Shadow RAM
362 * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
363 * method. The buf read is preceded by the NVM ownership take
364 * and followed by the release.
367 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
369 enum ice_status status;
371 status = ice_acquire_nvm(hw, ICE_RES_READ);
373 status = ice_read_sr_buf_aq(hw, offset, words, data);
381 * ice_nvm_validate_checksum
382 * @hw: pointer to the HW struct
384 * Verify NVM PFA checksum validity (0x0706)
386 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
388 struct ice_aqc_nvm_checksum *cmd;
389 struct ice_aq_desc desc;
390 enum ice_status status;
392 status = ice_acquire_nvm(hw, ICE_RES_READ);
396 cmd = &desc.params.nvm_checksum;
398 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
399 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
401 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
405 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
406 status = ICE_ERR_NVM_CHECKSUM;
412 * ice_nvm_access_get_features - Return the NVM access features structure
413 * @cmd: NVM access command to process
414 * @data: storage for the driver NVM features
416 * Fill in the data section of the NVM access request with a copy of the NVM
417 * features structure.
420 ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
421 union ice_nvm_access_data *data)
423 /* The provided data_size must be at least as large as our NVM
424 * features structure. A larger size should not be treated as an
425 * error, to allow future extensions to to the features structure to
426 * work on older drivers.
428 if (cmd->data_size < sizeof(struct ice_nvm_features))
429 return ICE_ERR_NO_MEMORY;
431 /* Initialize the data buffer to zeros */
432 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
434 /* Fill in the features data */
435 data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
436 data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
437 data->drv_features.size = sizeof(struct ice_nvm_features);
438 data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
444 * ice_nvm_access_get_module - Helper function to read module value
445 * @cmd: NVM access command structure
447 * Reads the module value out of the NVM access config field.
449 u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)
451 return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
455 * ice_nvm_access_get_flags - Helper function to read flags value
456 * @cmd: NVM access command structure
458 * Reads the flags value out of the NVM access config field.
460 u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)
462 return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
466 * ice_nvm_access_get_adapter - Helper function to read adapter info
467 * @cmd: NVM access command structure
469 * Read the adapter info value out of the NVM access config field.
471 u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)
473 return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
474 ICE_NVM_CFG_ADAPTER_INFO_S);
478 * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
479 * @cmd: NVM access command structure
481 * Validates that an NVM access structure is request to read or write a valid
482 * register offset. First validates that the module and flags are correct, and
483 * then ensures that the register offset is one of the accepted registers.
485 static enum ice_status
486 ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
488 u32 module, flags, offset;
491 module = ice_nvm_access_get_module(cmd);
492 flags = ice_nvm_access_get_flags(cmd);
493 offset = cmd->offset;
495 /* Make sure the module and flags indicate a read/write request */
496 if (module != ICE_NVM_REG_RW_MODULE ||
497 flags != ICE_NVM_REG_RW_FLAGS ||
498 cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))
499 return ICE_ERR_PARAM;
503 case GL_HICR_EN: /* Note, this register is read only */
506 case GLGEN_CSR_DEBUG_C:
516 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
517 if (offset == (u32)GL_HIDA(i))
520 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
521 if (offset == (u32)GL_HIBA(i))
524 /* All other register offsets are not valid */
525 return ICE_ERR_OUT_OF_RANGE;
529 * ice_nvm_access_read - Handle an NVM read request
530 * @hw: pointer to the HW struct
531 * @cmd: NVM access command to process
532 * @data: storage for the register value read
534 * Process an NVM access request to read a register.
537 ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
538 union ice_nvm_access_data *data)
540 enum ice_status status;
542 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
544 /* Always initialize the output data, even on failure */
545 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
547 /* Make sure this is a valid read/write access request */
548 status = ice_validate_nvm_rw_reg(cmd);
552 ice_debug(hw, ICE_DBG_NVM, "NVM access: reading register %08x\n",
555 /* Read the register and store the contents in the data field */
556 data->regval = rd32(hw, cmd->offset);
562 * ice_nvm_access_write - Handle an NVM write request
563 * @hw: pointer to the HW struct
564 * @cmd: NVM access command to process
565 * @data: NVM access data to write
567 * Process an NVM access request to write a register.
570 ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
571 union ice_nvm_access_data *data)
573 enum ice_status status;
575 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
577 /* Make sure this is a valid read/write access request */
578 status = ice_validate_nvm_rw_reg(cmd);
582 /* The HICR_EN register is read-only */
583 if (cmd->offset == GL_HICR_EN)
584 return ICE_ERR_OUT_OF_RANGE;
586 ice_debug(hw, ICE_DBG_NVM,
587 "NVM access: writing register %08x with value %08x\n",
588 cmd->offset, data->regval);
590 /* Write the data field to the specified register */
591 wr32(hw, cmd->offset, data->regval);
597 * ice_handle_nvm_access - Handle an NVM access request
598 * @hw: pointer to the HW struct
599 * @cmd: NVM access command info
600 * @data: pointer to read or return data
602 * Process an NVM access request. Read the command structure information and
603 * determine if it is valid. If not, report an error indicating the command
606 * For valid commands, perform the necessary function, copying the data into
607 * the provided data buffer.
610 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
611 union ice_nvm_access_data *data)
613 u32 module, flags, adapter_info;
615 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
617 /* Extended flags are currently reserved and must be zero */
618 if ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)
619 return ICE_ERR_PARAM;
621 /* Adapter info must match the HW device ID */
622 adapter_info = ice_nvm_access_get_adapter(cmd);
623 if (adapter_info != hw->device_id)
624 return ICE_ERR_PARAM;
626 switch (cmd->command) {
627 case ICE_NVM_CMD_READ:
628 module = ice_nvm_access_get_module(cmd);
629 flags = ice_nvm_access_get_flags(cmd);
631 /* Getting the driver's NVM features structure shares the same
632 * command type as reading a register. Read the config field
633 * to determine if this is a request to get features.
635 if (module == ICE_NVM_GET_FEATURES_MODULE &&
636 flags == ICE_NVM_GET_FEATURES_FLAGS &&
638 return ice_nvm_access_get_features(cmd, data);
640 return ice_nvm_access_read(hw, cmd, data);
641 case ICE_NVM_CMD_WRITE:
642 return ice_nvm_access_write(hw, cmd, data);
644 return ICE_ERR_PARAM;