1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
9 * @hw: pointer to the HW struct
10 * @module_typeid: module pointer location in words from the NVM beginning
11 * @offset: byte offset from the module beginning
12 * @length: length of the section to be read (in bytes from the offset)
13 * @data: command buffer (size [bytes] = length)
14 * @last_command: tells if this is the last command in a series
15 * @read_shadow_ram: tell if this is a shadow RAM read
16 * @cd: pointer to command details structure or NULL
18 * Read the NVM using the admin queue commands (0x0701)
21 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
22 void *data, bool last_command, bool read_shadow_ram,
25 struct ice_aq_desc desc;
26 struct ice_aqc_nvm *cmd;
28 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
30 cmd = &desc.params.nvm;
32 if (offset > ICE_AQC_NVM_MAX_OFFSET)
35 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
37 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
38 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
40 /* If this is the last command in a series, set the proper flag. */
42 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
43 cmd->module_typeid = CPU_TO_LE16(module_typeid);
44 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
45 cmd->offset_high = (offset >> 16) & 0xFF;
46 cmd->length = CPU_TO_LE16(length);
48 return ice_aq_send_cmd(hw, &desc, data, length, cd);
52 * ice_read_flat_nvm - Read portion of NVM by flat offset
53 * @hw: pointer to the HW struct
54 * @offset: offset from beginning of NVM
55 * @length: (in) number of bytes to read; (out) number of bytes actually read
56 * @data: buffer to return data in (sized to fit the specified length)
57 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
59 * Reads a portion of the NVM, as a flat memory space. This function correctly
60 * breaks read requests across Shadow RAM sectors and ensures that no single
61 * read request exceeds the maximum 4KB read for a single AdminQ command.
63 * Returns a status code on failure. Note that the data pointer may be
64 * partially updated if some reads succeed before a failure.
67 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
70 enum ice_status status;
75 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
79 /* Verify the length of the read if this is for the Shadow RAM */
80 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) {
81 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested data is beyond Shadow RAM limit\n");
86 u32 read_size, sector_offset;
88 /* ice_aq_read_nvm cannot read more than 4KB at a time.
89 * Additionally, a read from the Shadow RAM may not cross over
90 * a sector boundary. Conveniently, the sector size is also
93 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
94 read_size = MIN_T(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
97 last_cmd = !(bytes_read + read_size < inlen);
99 /* ice_aq_read_nvm takes the length as a u16. Our read_size is
100 * calculated using a u32, but the ICE_AQ_MAX_BUF_LEN maximum
101 * size guarantees that it will fit within the 2 bytes.
103 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
104 offset, (u16)read_size,
105 data + bytes_read, last_cmd,
106 read_shadow_ram, NULL);
110 bytes_read += read_size;
114 *length = bytes_read;
119 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
120 * @hw: pointer to the HW structure
121 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
122 * @data: word read from the Shadow RAM
124 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
126 static enum ice_status
127 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
129 u32 bytes = sizeof(u16);
130 enum ice_status status;
133 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
135 /* Note that ice_read_flat_nvm checks if the read is past the Shadow
136 * RAM size, and ensures we don't read across a Shadow RAM sector
139 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
140 (_FORCE_ u8 *)&data_local, true);
144 *data = LE16_TO_CPU(data_local);
149 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
150 * @hw: pointer to the HW structure
151 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
152 * @words: (in) number of words to read; (out) number of words actually read
153 * @data: words read from the Shadow RAM
155 * Reads 16 bit words (data buf) from the Shadow RAM. Ownership of the NVM is
156 * taken before reading the buffer and later released.
158 static enum ice_status
159 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
161 u32 bytes = *words * 2, i;
162 enum ice_status status;
164 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
166 /* ice_read_flat_nvm takes into account the 4KB AdminQ and Shadow RAM
167 * sector restrictions necessary when reading from the NVM.
169 status = ice_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true);
171 /* Report the number of words successfully read */
174 /* Byte swap the words up to the amount we actually read */
175 for (i = 0; i < *words; i++)
176 data[i] = LE16_TO_CPU(((_FORCE_ __le16 *)data)[i]);
182 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
183 * @hw: pointer to the HW structure
184 * @access: NVM access type (read or write)
186 * This function will request NVM ownership.
189 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
191 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
193 if (hw->flash.blank_nvm_mode)
196 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
200 * ice_release_nvm - Generic request for releasing the NVM ownership
201 * @hw: pointer to the HW structure
203 * This function will release NVM ownership.
205 void ice_release_nvm(struct ice_hw *hw)
207 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
209 if (hw->flash.blank_nvm_mode)
212 ice_release_res(hw, ICE_NVM_RES_ID);
216 * ice_get_flash_bank_offset - Get offset into requested flash bank
217 * @hw: pointer to the HW structure
218 * @bank: whether to read from the active or inactive flash bank
219 * @module: the module to read from
221 * Based on the module, lookup the module offset from the beginning of the
224 * Returns the flash offset. Note that a value of zero is invalid and must be
225 * treated as an error.
227 static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
229 struct ice_bank_info *banks = &hw->flash.banks;
230 enum ice_flash_bank active_bank;
231 bool second_bank_active;
235 case ICE_SR_1ST_NVM_BANK_PTR:
236 offset = banks->nvm_ptr;
237 size = banks->nvm_size;
238 active_bank = banks->nvm_bank;
240 case ICE_SR_1ST_OROM_BANK_PTR:
241 offset = banks->orom_ptr;
242 size = banks->orom_size;
243 active_bank = banks->orom_bank;
245 case ICE_SR_NETLIST_BANK_PTR:
246 offset = banks->netlist_ptr;
247 size = banks->netlist_size;
248 active_bank = banks->netlist_bank;
251 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module);
255 switch (active_bank) {
256 case ICE_1ST_FLASH_BANK:
257 second_bank_active = false;
259 case ICE_2ND_FLASH_BANK:
260 second_bank_active = true;
263 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n",
268 /* The second flash bank is stored immediately following the first
269 * bank. Based on whether the 1st or 2nd bank is active, and whether
270 * we want the active or inactive bank, calculate the desired offset.
273 case ICE_ACTIVE_FLASH_BANK:
274 return offset + (second_bank_active ? size : 0);
275 case ICE_INACTIVE_FLASH_BANK:
276 return offset + (second_bank_active ? 0 : size);
279 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);
284 * ice_read_flash_module - Read a word from one of the main NVM modules
285 * @hw: pointer to the HW structure
286 * @bank: which bank of the module to read
287 * @module: the module to read
288 * @offset: the offset into the module in bytes
289 * @data: storage for the word read from the flash
290 * @length: bytes of data to read
292 * Read data from the specified flash module. The bank parameter indicates
293 * whether or not to read from the active bank or the inactive bank of that
296 * The word will be read using flat NVM access, and relies on the
297 * hw->flash.banks data being setup by ice_determine_active_flash_banks()
298 * during initialization.
300 static enum ice_status
301 ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,
302 u32 offset, u8 *data, u32 length)
304 enum ice_status status;
307 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
309 start = ice_get_flash_bank_offset(hw, bank, module);
311 ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n",
313 return ICE_ERR_PARAM;
316 status = ice_acquire_nvm(hw, ICE_RES_READ);
320 status = ice_read_flat_nvm(hw, start + offset, &length, data, false);
328 * ice_read_nvm_module - Read from the active main NVM module
329 * @hw: pointer to the HW structure
330 * @bank: whether to read from active or inactive NVM module
331 * @offset: offset into the NVM module to read, in words
332 * @data: storage for returned word value
334 * Read the specified word from the active NVM module. This includes the CSS
335 * header at the start of the NVM module.
337 static enum ice_status
338 ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
340 enum ice_status status;
343 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16),
344 (_FORCE_ u8 *)&data_local, sizeof(u16));
346 *data = LE16_TO_CPU(data_local);
352 * ice_read_orom_module - Read from the active Option ROM module
353 * @hw: pointer to the HW structure
354 * @bank: whether to read from active or inactive OROM module
355 * @offset: offset into the OROM module to read, in words
356 * @data: storage for returned word value
358 * Read the specified word from the active Option ROM module of the flash.
359 * Note that unlike the NVM module, the CSS data is stored at the end of the
360 * module instead of at the beginning.
362 static enum ice_status
363 ice_read_orom_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
365 enum ice_status status;
368 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, offset * sizeof(u16),
369 (_FORCE_ u8 *)&data_local, sizeof(u16));
371 *data = LE16_TO_CPU(data_local);
377 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
378 * @hw: pointer to the HW structure
379 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
380 * @data: word read from the Shadow RAM
382 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
384 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
386 enum ice_status status;
388 status = ice_acquire_nvm(hw, ICE_RES_READ);
390 status = ice_read_sr_word_aq(hw, offset, data);
398 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
399 * @hw: pointer to hardware structure
400 * @module_tlv: pointer to module TLV to return
401 * @module_tlv_len: pointer to module TLV length to return
402 * @module_type: module type requested
404 * Finds the requested sub module TLV type from the Preserved Field
405 * Area (PFA) and returns the TLV pointer and length. The caller can
406 * use these to read the variable length TLV value.
409 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
412 enum ice_status status;
413 u16 pfa_len, pfa_ptr;
416 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
417 if (status != ICE_SUCCESS) {
418 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
421 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
422 if (status != ICE_SUCCESS) {
423 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
426 /* Starting with first TLV after PFA length, iterate through the list
427 * of TLVs to find the requested one.
429 next_tlv = pfa_ptr + 1;
430 while (next_tlv < pfa_ptr + pfa_len) {
431 u16 tlv_sub_module_type;
435 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
436 if (status != ICE_SUCCESS) {
437 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
440 /* Read TLV length */
441 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
442 if (status != ICE_SUCCESS) {
443 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
446 if (tlv_sub_module_type == module_type) {
448 *module_tlv = next_tlv;
449 *module_tlv_len = tlv_len;
452 return ICE_ERR_INVAL_SIZE;
454 /* Check next TLV, i.e. current TLV pointer + length + 2 words
455 * (for current TLV's type and length)
457 next_tlv = next_tlv + tlv_len + 2;
459 /* Module does not exist */
460 return ICE_ERR_DOES_NOT_EXIST;
464 * ice_read_pba_string - Reads part number string from NVM
465 * @hw: pointer to hardware structure
466 * @pba_num: stores the part number string from the NVM
467 * @pba_num_size: part number string buffer length
469 * Reads the part number string from the NVM.
472 ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
474 u16 pba_tlv, pba_tlv_len;
475 enum ice_status status;
476 u16 pba_word, pba_size;
479 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
480 ICE_SR_PBA_BLOCK_PTR);
481 if (status != ICE_SUCCESS) {
482 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
486 /* pba_size is the next word */
487 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
488 if (status != ICE_SUCCESS) {
489 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
493 if (pba_tlv_len < pba_size) {
494 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
495 return ICE_ERR_INVAL_SIZE;
498 /* Subtract one to get PBA word count (PBA Size word is included in
502 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
503 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
504 return ICE_ERR_PARAM;
507 for (i = 0; i < pba_size; i++) {
508 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
509 if (status != ICE_SUCCESS) {
510 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
514 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
515 pba_num[(i * 2) + 1] = pba_word & 0xFF;
517 pba_num[(pba_size * 2)] = '\0';
523 * ice_get_nvm_srev - Read the security revision from the NVM CSS header
524 * @hw: pointer to the HW struct
525 * @bank: whether to read from the active or inactive flash bank
526 * @srev: storage for security revision
528 * Read the security revision out of the CSS header of the active NVM module
531 static enum ice_status ice_get_nvm_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)
533 enum ice_status status;
536 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_L, &srev_l);
540 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_H, &srev_h);
544 *srev = srev_h << 16 | srev_l;
550 * ice_get_nvm_ver_info - Read NVM version information
551 * @hw: pointer to the HW struct
552 * @nvm: pointer to NVM info structure
554 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling
555 * in the nvm info structure.
557 static enum ice_status
558 ice_get_nvm_ver_info(struct ice_hw *hw, struct ice_nvm_info *nvm)
560 u16 eetrack_lo, eetrack_hi, ver;
561 enum ice_status status;
563 status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &ver);
565 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
568 nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
569 nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
571 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
573 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
576 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
578 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
582 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
584 status = ice_get_nvm_srev(hw, ICE_ACTIVE_FLASH_BANK, &nvm->srev);
586 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM security revision.\n");
592 * ice_get_orom_srev - Read the security revision from the OROM CSS header
593 * @hw: pointer to the HW struct
594 * @bank: whether to read from active or inactive flash module
595 * @srev: storage for security revision
597 * Read the security revision out of the CSS header of the active OROM module
600 static enum ice_status ice_get_orom_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)
602 enum ice_status status;
606 if (hw->flash.banks.orom_size < ICE_NVM_OROM_TRAILER_LENGTH) {
607 ice_debug(hw, ICE_DBG_NVM, "Unexpected Option ROM Size of %u\n",
608 hw->flash.banks.orom_size);
612 /* calculate how far into the Option ROM the CSS header starts. Note
613 * that ice_read_orom_module takes a word offset so we need to
616 css_start = (hw->flash.banks.orom_size - ICE_NVM_OROM_TRAILER_LENGTH) / 2;
618 status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_L, &srev_l);
622 status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_H, &srev_h);
626 *srev = srev_h << 16 | srev_l;
632 * ice_get_orom_civd_data - Get the combo version information from Option ROM
633 * @hw: pointer to the HW struct
634 * @bank: whether to read from the active or inactive flash module
635 * @civd: storage for the Option ROM CIVD data.
637 * Searches through the Option ROM flash contents to locate the CIVD data for
640 static enum ice_status
641 ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank,
642 struct ice_orom_civd_info *civd)
644 struct ice_orom_civd_info tmp;
645 enum ice_status status;
648 /* The CIVD section is located in the Option ROM aligned to 512 bytes.
649 * The first 4 bytes must contain the ASCII characters "$CIV".
650 * A simple modulo 256 sum of all of the bytes of the structure must
653 for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) {
656 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR,
657 offset, (u8 *)&tmp, sizeof(tmp));
659 ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM CIVD data\n");
663 /* Skip forward until we find a matching signature */
664 if (memcmp("$CIV", tmp.signature, sizeof(tmp.signature)) != 0)
667 /* Verify that the simple checksum is zero */
668 for (i = 0; i < sizeof(tmp); i++)
669 sum += ((u8 *)&tmp)[i];
672 ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n",
685 * ice_get_orom_ver_info - Read Option ROM version information
686 * @hw: pointer to the HW struct
687 * @bank: whether to read from the active or inactive flash module
688 * @orom: pointer to Option ROM info structure
690 * Read Option ROM version and security revision from the Option ROM flash
693 static enum ice_status
694 ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom)
696 struct ice_orom_civd_info civd;
697 enum ice_status status;
700 status = ice_get_orom_civd_data(hw, bank, &civd);
702 ice_debug(hw, ICE_DBG_NVM, "Failed to locate valid Option ROM CIVD data\n");
706 combo_ver = LE32_TO_CPU(civd.combo_ver);
708 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >> ICE_OROM_VER_SHIFT);
709 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK);
710 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >> ICE_OROM_VER_BUILD_SHIFT);
712 status = ice_get_orom_srev(hw, bank, &orom->srev);
714 ice_debug(hw, ICE_DBG_NVM, "Failed to read Option ROM security revision.\n");
722 * ice_get_inactive_orom_ver - Read Option ROM version from the inactive bank
723 * @hw: pointer to the HW structure
724 * @orom: storage for Option ROM version information
726 * Reads the Option ROM version and security revision data for the inactive
727 * section of flash. Used to access version data for a pending update that has
728 * not yet been activated.
730 enum ice_status ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom)
732 return ice_get_orom_ver_info(hw, ICE_INACTIVE_FLASH_BANK, orom);
736 * ice_discover_flash_size - Discover the available flash size.
737 * @hw: pointer to the HW struct
739 * The device flash could be up to 16MB in size. However, it is possible that
740 * the actual size is smaller. Use bisection to determine the accessible size
743 static enum ice_status ice_discover_flash_size(struct ice_hw *hw)
745 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
746 enum ice_status status;
748 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
750 status = ice_acquire_nvm(hw, ICE_RES_READ);
754 while ((max_size - min_size) > 1) {
755 u32 offset = (max_size + min_size) / 2;
759 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
760 if (status == ICE_ERR_AQ_ERROR &&
761 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
762 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
764 status = ICE_SUCCESS;
766 } else if (!status) {
767 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
771 /* an unexpected error occurred */
772 goto err_read_flat_nvm;
776 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
778 hw->flash.flash_size = max_size;
787 * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word
788 * @hw: pointer to the HW structure
789 * @offset: the word offset of the Shadow RAM word to read
790 * @pointer: pointer value read from Shadow RAM
792 * Read the given Shadow RAM word, and convert it to a pointer value specified
793 * in bytes. This function assumes the specified offset is a valid pointer
796 * Each pointer word specifies whether it is stored in word size or 4KB
797 * sector size by using the highest bit. The reported pointer value will be in
798 * bytes, intended for flat NVM reads.
800 static enum ice_status
801 ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
803 enum ice_status status;
806 status = ice_read_sr_word(hw, offset, &value);
810 /* Determine if the pointer is in 4KB or word units */
811 if (value & ICE_SR_NVM_PTR_4KB_UNITS)
812 *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;
814 *pointer = value * 2;
820 * ice_read_sr_area_size - Read an area size from a Shadow RAM word
821 * @hw: pointer to the HW structure
822 * @offset: the word offset of the Shadow RAM to read
823 * @size: size value read from the Shadow RAM
825 * Read the given Shadow RAM word, and convert it to an area size value
826 * specified in bytes. This function assumes the specified offset is a valid
829 * Each area size word is specified in 4KB sector units. This function reports
830 * the size in bytes, intended for flat NVM reads.
832 static enum ice_status
833 ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
835 enum ice_status status;
838 status = ice_read_sr_word(hw, offset, &value);
842 /* Area sizes are always specified in 4KB units */
843 *size = value * 4 * 1024;
849 * ice_determine_active_flash_banks - Discover active bank for each module
850 * @hw: pointer to the HW struct
852 * Read the Shadow RAM control word and determine which banks are active for
853 * the NVM, OROM, and Netlist modules. Also read and calculate the associated
854 * pointer and size. These values are then cached into the ice_flash_info
855 * structure for later use in order to calculate the correct offset to read
856 * from the active module.
858 static enum ice_status
859 ice_determine_active_flash_banks(struct ice_hw *hw)
861 struct ice_bank_info *banks = &hw->flash.banks;
862 enum ice_status status;
865 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
867 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
871 /* Check that the control word indicates validity */
872 if ((ctrl_word & ICE_SR_CTRL_WORD_1_M) >> ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) {
873 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
877 if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))
878 banks->nvm_bank = ICE_1ST_FLASH_BANK;
880 banks->nvm_bank = ICE_2ND_FLASH_BANK;
882 if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))
883 banks->orom_bank = ICE_1ST_FLASH_BANK;
885 banks->orom_bank = ICE_2ND_FLASH_BANK;
887 if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))
888 banks->netlist_bank = ICE_1ST_FLASH_BANK;
890 banks->netlist_bank = ICE_2ND_FLASH_BANK;
892 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
894 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
898 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
900 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
904 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
906 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
910 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
912 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
916 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
918 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
922 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
924 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
932 * ice_init_nvm - initializes NVM setting
933 * @hw: pointer to the HW struct
935 * This function reads and populates NVM settings such as Shadow RAM size,
936 * max_timeout, and blank_nvm_mode
938 enum ice_status ice_init_nvm(struct ice_hw *hw)
940 struct ice_flash_info *flash = &hw->flash;
941 enum ice_status status;
945 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
947 /* The SR size is stored regardless of the NVM programming mode
948 * as the blank mode may be used in the factory line.
950 gens_stat = rd32(hw, GLNVM_GENS);
951 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
953 /* Switching to words (sr_size contains power of 2) */
954 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
956 /* Check if we are in the normal or blank NVM programming mode */
957 fla = rd32(hw, GLNVM_FLA);
958 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
959 flash->blank_nvm_mode = false;
961 /* Blank programming mode */
962 flash->blank_nvm_mode = true;
963 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
964 return ICE_ERR_NVM_BLANK_MODE;
967 status = ice_discover_flash_size(hw);
969 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");
973 status = ice_determine_active_flash_banks(hw);
975 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
979 status = ice_get_nvm_ver_info(hw, &flash->nvm);
981 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
985 status = ice_get_orom_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->orom);
987 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
993 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
994 * @hw: pointer to the HW structure
995 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
996 * @words: (in) number of words to read; (out) number of words actually read
997 * @data: words read from the Shadow RAM
999 * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
1000 * method. The buf read is preceded by the NVM ownership take
1001 * and followed by the release.
1004 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
1006 enum ice_status status;
1008 status = ice_acquire_nvm(hw, ICE_RES_READ);
1010 status = ice_read_sr_buf_aq(hw, offset, words, data);
1011 ice_release_nvm(hw);
1018 * ice_nvm_validate_checksum
1019 * @hw: pointer to the HW struct
1021 * Verify NVM PFA checksum validity (0x0706)
1023 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
1025 struct ice_aqc_nvm_checksum *cmd;
1026 struct ice_aq_desc desc;
1027 enum ice_status status;
1029 status = ice_acquire_nvm(hw, ICE_RES_READ);
1033 cmd = &desc.params.nvm_checksum;
1035 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
1036 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
1038 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1039 ice_release_nvm(hw);
1042 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
1043 status = ICE_ERR_NVM_CHECKSUM;
1049 * ice_nvm_access_get_features - Return the NVM access features structure
1050 * @cmd: NVM access command to process
1051 * @data: storage for the driver NVM features
1053 * Fill in the data section of the NVM access request with a copy of the NVM
1054 * features structure.
1057 ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
1058 union ice_nvm_access_data *data)
1060 /* The provided data_size must be at least as large as our NVM
1061 * features structure. A larger size should not be treated as an
1062 * error, to allow future extensions to the features structure to
1063 * work on older drivers.
1065 if (cmd->data_size < sizeof(struct ice_nvm_features))
1066 return ICE_ERR_NO_MEMORY;
1068 /* Initialize the data buffer to zeros */
1069 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
1071 /* Fill in the features data */
1072 data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
1073 data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
1074 data->drv_features.size = sizeof(struct ice_nvm_features);
1075 data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
1081 * ice_nvm_access_get_module - Helper function to read module value
1082 * @cmd: NVM access command structure
1084 * Reads the module value out of the NVM access config field.
1086 u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)
1088 return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
1092 * ice_nvm_access_get_flags - Helper function to read flags value
1093 * @cmd: NVM access command structure
1095 * Reads the flags value out of the NVM access config field.
1097 u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)
1099 return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
1103 * ice_nvm_access_get_adapter - Helper function to read adapter info
1104 * @cmd: NVM access command structure
1106 * Read the adapter info value out of the NVM access config field.
1108 u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)
1110 return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
1111 ICE_NVM_CFG_ADAPTER_INFO_S);
1115 * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
1116 * @cmd: NVM access command structure
1118 * Validates that an NVM access structure is request to read or write a valid
1119 * register offset. First validates that the module and flags are correct, and
1120 * then ensures that the register offset is one of the accepted registers.
1122 static enum ice_status
1123 ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
1125 u32 module, flags, offset;
1128 module = ice_nvm_access_get_module(cmd);
1129 flags = ice_nvm_access_get_flags(cmd);
1130 offset = cmd->offset;
1132 /* Make sure the module and flags indicate a read/write request */
1133 if (module != ICE_NVM_REG_RW_MODULE ||
1134 flags != ICE_NVM_REG_RW_FLAGS ||
1135 cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))
1136 return ICE_ERR_PARAM;
1140 case GL_HICR_EN: /* Note, this register is read only */
1143 case GLGEN_CSR_DEBUG_C:
1145 case GLPCI_LBARCTRL:
1154 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
1155 if (offset == (u32)GL_HIDA(i))
1158 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
1159 if (offset == (u32)GL_HIBA(i))
1162 /* All other register offsets are not valid */
1163 return ICE_ERR_OUT_OF_RANGE;
1167 * ice_nvm_access_read - Handle an NVM read request
1168 * @hw: pointer to the HW struct
1169 * @cmd: NVM access command to process
1170 * @data: storage for the register value read
1172 * Process an NVM access request to read a register.
1175 ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1176 union ice_nvm_access_data *data)
1178 enum ice_status status;
1180 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1182 /* Always initialize the output data, even on failure */
1183 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
1185 /* Make sure this is a valid read/write access request */
1186 status = ice_validate_nvm_rw_reg(cmd);
1190 ice_debug(hw, ICE_DBG_NVM, "NVM access: reading register %08x\n",
1193 /* Read the register and store the contents in the data field */
1194 data->regval = rd32(hw, cmd->offset);
1200 * ice_nvm_access_write - Handle an NVM write request
1201 * @hw: pointer to the HW struct
1202 * @cmd: NVM access command to process
1203 * @data: NVM access data to write
1205 * Process an NVM access request to write a register.
1208 ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1209 union ice_nvm_access_data *data)
1211 enum ice_status status;
1213 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1215 /* Make sure this is a valid read/write access request */
1216 status = ice_validate_nvm_rw_reg(cmd);
1220 /* Reject requests to write to read-only registers */
1221 switch (cmd->offset) {
1224 return ICE_ERR_OUT_OF_RANGE;
1229 ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n",
1230 cmd->offset, data->regval);
1232 /* Write the data field to the specified register */
1233 wr32(hw, cmd->offset, data->regval);
1239 * ice_handle_nvm_access - Handle an NVM access request
1240 * @hw: pointer to the HW struct
1241 * @cmd: NVM access command info
1242 * @data: pointer to read or return data
1244 * Process an NVM access request. Read the command structure information and
1245 * determine if it is valid. If not, report an error indicating the command
1248 * For valid commands, perform the necessary function, copying the data into
1249 * the provided data buffer.
1252 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1253 union ice_nvm_access_data *data)
1255 u32 module, flags, adapter_info;
1257 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1259 /* Extended flags are currently reserved and must be zero */
1260 if ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)
1261 return ICE_ERR_PARAM;
1263 /* Adapter info must match the HW device ID */
1264 adapter_info = ice_nvm_access_get_adapter(cmd);
1265 if (adapter_info != hw->device_id)
1266 return ICE_ERR_PARAM;
1268 switch (cmd->command) {
1269 case ICE_NVM_CMD_READ:
1270 module = ice_nvm_access_get_module(cmd);
1271 flags = ice_nvm_access_get_flags(cmd);
1273 /* Getting the driver's NVM features structure shares the same
1274 * command type as reading a register. Read the config field
1275 * to determine if this is a request to get features.
1277 if (module == ICE_NVM_GET_FEATURES_MODULE &&
1278 flags == ICE_NVM_GET_FEATURES_FLAGS &&
1280 return ice_nvm_access_get_features(cmd, data);
1282 return ice_nvm_access_read(hw, cmd, data);
1283 case ICE_NVM_CMD_WRITE:
1284 return ice_nvm_access_write(hw, cmd, data);
1286 return ICE_ERR_PARAM;