1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Intel Corporation
13 #include <sys/queue.h>
16 #include <rte_common.h>
17 #include <rte_memcpy.h>
18 #include <rte_malloc.h>
19 #include <rte_memzone.h>
20 #include <rte_byteorder.h>
21 #include <rte_cycles.h>
22 #include <rte_spinlock.h>
26 #include "ice_alloc.h"
28 #include "../ice_logs.h"
30 #ifndef __INTEL_NET_BASE_OSDEP__
31 #define __INTEL_NET_BASE_OSDEP__
46 #define __le16 uint16_t
49 #define __le32 uint32_t
52 #define __le64 uint64_t
55 #define __be16 uint16_t
58 #define __be32 uint32_t
61 #define __be64 uint64_t
64 /* Avoid macro redefinition warning on Windows */
65 #ifdef RTE_EXEC_ENV_WINDOWS
73 #define min(a, b) RTE_MIN(a, b)
74 #define max(a, b) RTE_MAX(a, b)
76 #define FIELD_SIZEOF(t, f) RTE_SIZEOF_FIELD(t, f)
77 #define ARRAY_SIZE(arr) RTE_DIM(arr)
79 #define CPU_TO_LE16(o) rte_cpu_to_le_16(o)
80 #define CPU_TO_LE32(s) rte_cpu_to_le_32(s)
81 #define CPU_TO_LE64(h) rte_cpu_to_le_64(h)
82 #define LE16_TO_CPU(a) rte_le_to_cpu_16(a)
83 #define LE32_TO_CPU(c) rte_le_to_cpu_32(c)
84 #define LE64_TO_CPU(k) rte_le_to_cpu_64(k)
86 #define CPU_TO_BE16(o) rte_cpu_to_be_16(o)
87 #define CPU_TO_BE32(o) rte_cpu_to_be_32(o)
88 #define CPU_TO_BE64(o) rte_cpu_to_be_64(o)
89 #define BE16_TO_CPU(o) rte_be_to_cpu_16(o)
91 #define NTOHS(a) rte_be_to_cpu_16(a)
92 #define NTOHL(a) rte_be_to_cpu_32(a)
93 #define HTONS(a) rte_cpu_to_be_16(a)
94 #define HTONL(a) rte_cpu_to_be_32(a)
96 static __rte_always_inline uint32_t
97 readl(volatile void *addr)
99 return rte_le_to_cpu_32(rte_read32(addr));
102 static __rte_always_inline void
103 writel(uint32_t value, volatile void *addr)
105 rte_write32(rte_cpu_to_le_32(value), addr);
108 static __rte_always_inline void
109 writel_relaxed(uint32_t value, volatile void *addr)
111 rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
114 static __rte_always_inline uint64_t
115 readq(volatile void *addr)
117 return rte_le_to_cpu_64(rte_read64(addr));
120 static __rte_always_inline void
121 writeq(uint64_t value, volatile void *addr)
123 rte_write64(rte_cpu_to_le_64(value), addr);
126 #define wr32(a, reg, value) writel((value), (a)->hw_addr + (reg))
127 #define rd32(a, reg) readl((a)->hw_addr + (reg))
128 #define wr64(a, reg, value) writeq((value), (a)->hw_addr + (reg))
129 #define rd64(a, reg) readq((a)->hw_addr + (reg))
131 #endif /* __INTEL_NET_BASE_OSDEP__ */
133 #ifndef __always_unused
134 #define __always_unused __rte_unused
136 #ifndef __maybe_unused
137 #define __maybe_unused __rte_unused
140 #define __packed __rte_packed
144 #define BIT_ULL(a) (1ULL << (a))
147 #define MAKEMASK(m, s) ((m) << (s))
149 #define ice_debug(h, m, s, ...) \
151 if (((m) & (h)->debug_mask)) \
152 PMD_DRV_LOG_RAW(DEBUG, "ice %02x.%x " s, \
153 (h)->bus.device, (h)->bus.func, \
157 #define ice_info(hw, fmt, args...) ice_debug(hw, ICE_DBG_ALL, fmt, ##args)
158 #define ice_warn(hw, fmt, args...) ice_debug(hw, ICE_DBG_ALL, fmt, ##args)
159 #define ice_debug_array(hw, type, rowsize, groupsize, buf, len) \
161 struct ice_hw *hw_l = hw; \
165 for (i = 0; i < len_l; i += 8) \
166 ice_debug(hw_l, type, \
167 "0x%04X 0x%016"PRIx64"\n", \
168 i, *((u64 *)((buf_l) + i))); \
170 #define ice_snprintf snprintf
172 #define SNPRINTF ice_snprintf
175 #define ICE_PCI_REG_WRITE(reg, value) writel(value, reg)
176 #define ICE_PCI_REG_WC_WRITE(reg, value) rte_write32_wc(value, reg)
178 #define ICE_READ_REG(hw, reg) rd32(hw, reg)
179 #define ICE_WRITE_REG(hw, reg, value) wr32(hw, reg, value)
181 #define ice_flush(a) ICE_READ_REG((a), GLGEN_STAT)
182 #define icevf_flush(a) ICE_READ_REG((a), VFGEN_RSTAT)
184 #define flush(a) ICE_READ_REG((a), GLGEN_STAT)
185 #define div64_long(n, d) ((n) / (d))
187 #define BITS_PER_BYTE 8
189 /* memory allocation tracking */
197 struct ice_virt_mem {
202 #define ice_malloc(h, s) rte_zmalloc(NULL, s, 0)
203 #define ice_calloc(h, c, s) rte_calloc(NULL, c, s, 0)
204 #define ice_free(h, m) rte_free(m)
206 #define ice_memset(a, b, c, d) memset((a), (b), (c))
207 #define ice_memcpy(a, b, c, d) rte_memcpy((a), (b), (c))
211 rte_spinlock_t spinlock;
215 ice_init_lock(struct ice_lock *sp)
217 rte_spinlock_init(&sp->spinlock);
221 ice_acquire_lock(struct ice_lock *sp)
223 rte_spinlock_lock(&sp->spinlock);
227 ice_release_lock(struct ice_lock *sp)
229 rte_spinlock_unlock(&sp->spinlock);
233 ice_destroy_lock(__rte_unused struct ice_lock *sp)
239 static __rte_always_inline void *
240 ice_memdup(__rte_unused struct ice_hw *hw, const void *src, size_t size,
241 __rte_unused enum ice_memcpy_type dir)
245 p = ice_malloc(hw, size);
247 rte_memcpy(p, src, size);
253 ice_alloc_dma_mem(__rte_unused struct ice_hw *hw,
254 struct ice_dma_mem *mem, u64 size)
256 static uint64_t ice_dma_memzone_id;
257 const struct rte_memzone *mz = NULL;
258 char z_name[RTE_MEMZONE_NAMESIZE];
263 snprintf(z_name, sizeof(z_name), "ice_dma_%" PRIu64,
264 __atomic_fetch_add(&ice_dma_memzone_id, 1, __ATOMIC_RELAXED));
265 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
273 mem->zone = (const void *)mz;
274 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
275 "%"PRIu64, mz->name, mem->pa);
281 ice_free_dma_mem(__rte_unused struct ice_hw *hw,
282 struct ice_dma_mem *mem)
284 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
285 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
287 rte_memzone_free((const struct rte_memzone *)mem->zone);
294 ice_hweight8(u32 num)
299 for (i = 0; i < 8; i++) {
300 bits += (u8)(num & 0x1);
308 ice_hweight32(u32 num)
313 for (i = 0; i < 32; i++) {
314 bits += (u8)(num & 0x1);
321 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
322 #define DELAY(x) rte_delay_us(x)
323 #define ice_usec_delay(x, y) rte_delay_us(x)
324 #define ice_msec_delay(x, y) rte_delay_us(1000 * (x))
325 #define udelay(x) DELAY(x)
326 #define msleep(x) DELAY(1000 * (x))
327 #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
329 struct ice_list_entry {
330 LIST_ENTRY(ice_list_entry) next;
333 LIST_HEAD(ice_list_head, ice_list_entry);
335 #define LIST_ENTRY_TYPE ice_list_entry
336 #define LIST_HEAD_TYPE ice_list_head
337 #define INIT_LIST_HEAD(list_head) LIST_INIT(list_head)
338 #define LIST_DEL(entry) LIST_REMOVE(entry, next)
339 /* LIST_EMPTY(list_head)) the same in sys/queue.h */
341 /*Note parameters are swapped*/
342 #define LIST_FIRST_ENTRY(head, type, field) (type *)((head)->lh_first)
343 #define LIST_NEXT_ENTRY(entry, type, field) \
344 ((type *)(entry)->field.next.le_next)
345 #define LIST_ADD(entry, list_head) LIST_INSERT_HEAD(list_head, entry, next)
346 #define LIST_ADD_AFTER(entry, list_entry) \
347 LIST_INSERT_AFTER(list_entry, entry, next)
349 static inline void list_add_tail(struct ice_list_entry *entry,
350 struct ice_list_head *head)
352 struct ice_list_entry *tail = head->lh_first;
355 LIST_INSERT_HEAD(head, entry, next);
358 while (tail->next.le_next != NULL)
359 tail = tail->next.le_next;
360 LIST_INSERT_AFTER(tail, entry, next);
363 #define LIST_ADD_TAIL(entry, head) list_add_tail(entry, head)
364 #define LIST_FOR_EACH_ENTRY(pos, head, type, member) \
365 for ((pos) = (head)->lh_first ? \
366 container_of((head)->lh_first, struct type, member) : \
369 (pos) = (pos)->member.next.le_next ? \
370 container_of((pos)->member.next.le_next, struct type, \
374 #define LIST_FOR_EACH_ENTRY_SAFE(pos, tmp, head, type, member) \
375 for ((pos) = (head)->lh_first ? \
376 container_of((head)->lh_first, struct type, member) : \
378 (tmp) = (pos) == 0 ? 0 : ((pos)->member.next.le_next ? \
379 container_of((pos)->member.next.le_next, struct type, \
384 (tmp) = (pos) == 0 ? 0 : ((tmp)->member.next.le_next ? \
385 container_of((pos)->member.next.le_next, struct type, \
389 #define LIST_REPLACE_INIT(list_head, head) do { \
390 (head)->lh_first = (list_head)->lh_first; \
391 INIT_LIST_HEAD(list_head); \
394 #define HLIST_NODE_TYPE LIST_ENTRY_TYPE
395 #define HLIST_HEAD_TYPE LIST_HEAD_TYPE
396 #define INIT_HLIST_HEAD(list_head) INIT_LIST_HEAD(list_head)
397 #define HLIST_ADD_HEAD(entry, list_head) LIST_ADD(entry, list_head)
398 #define HLIST_EMPTY(list_head) LIST_EMPTY(list_head)
399 #define HLIST_DEL(entry) LIST_DEL(entry)
400 #define HLIST_FOR_EACH_ENTRY(pos, head, type, member) \
401 LIST_FOR_EACH_ENTRY(pos, head, type, member)
403 #ifndef ICE_DBG_TRACE
404 #define ICE_DBG_TRACE BIT_ULL(0)
407 #ifndef DIVIDE_AND_ROUND_UP
408 #define DIVIDE_AND_ROUND_UP(a, b) (((a) + (b) - 1) / (b))
411 #ifndef ICE_INTEL_VENDOR_ID
412 #define ICE_INTEL_VENDOR_ID 0x8086
415 #ifndef IS_UNICAST_ETHER_ADDR
416 #define IS_UNICAST_ETHER_ADDR(addr) \
417 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0))
420 #ifndef IS_MULTICAST_ETHER_ADDR
421 #define IS_MULTICAST_ETHER_ADDR(addr) \
422 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1))
425 #ifndef IS_BROADCAST_ETHER_ADDR
426 /* Check whether an address is broadcast. */
427 #define IS_BROADCAST_ETHER_ADDR(addr) \
428 ((bool)((((u16 *)(addr))[0] == ((u16)0xffff))))
431 #ifndef IS_ZERO_ETHER_ADDR
432 #define IS_ZERO_ETHER_ADDR(addr) \
433 (((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \
434 ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \
435 ((bool)((((u16 *)(addr))[2] == ((u16)0x0)))))
438 #endif /* _ICE_OSDEP_H_ */