1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
5 #ifndef _ICE_PTP_CONSTS_H_
6 #define _ICE_PTP_CONSTS_H_
8 /* Constant definitions related to the hardware clock used for PTP 1588
9 * features and functionality.
11 /* Constants defined for the PTP 1588 clock hardware. */
14 * struct ice_time_ref_info_e822
16 * E822 hardware can use different sources as the reference for the PTP
17 * hardware clock. Each clock has different characteristics such as a slightly
18 * different frequency, etc.
20 * This lookup table defines several constants that depend on the current time
21 * reference. See the struct ice_time_ref_info_e822 for information about the
22 * meaning of each constant.
24 const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {
25 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
28 823437500, /* 823.4375 MHz PLL */
35 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
38 783360000, /* 783.36 MHz */
45 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
48 796875000, /* 796.875 MHz */
55 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
58 816000000, /* 816 MHz */
65 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
68 830078125, /* 830.78125 MHz */
75 /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
78 783360000, /* 783.36 MHz */
86 const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
87 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
99 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
111 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
123 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
135 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
147 /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
160 /* struct ice_vernier_info_e822
162 * E822 hardware calibrates the delay of the timestamp indication from the
163 * actual packet transmission or reception during the initialization of the
164 * PHY. To do this, the hardware mechanism uses some conversions between the
165 * various clocks within the PHY block. This table defines constants used to
166 * calculate the correct conversion ratios in the PHY registers.
168 * Many of the values relate to the PAR/PCS clock conversion registers. For
169 * these registers, a value of 0 means that the associated register is not
170 * used by this link speed, and that the register should be cleared by writing
171 * 0. Other values specify the clock frequency in Hz.
173 const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD] = {
174 /* ICE_PTP_LNK_SPD_1G */
177 31250000, /* 31.25 MHz */
179 31250000, /* 31.25 MHz */
181 125000000, /* 125 MHz */
183 125000000, /* 125 MHz */
184 /* tx_desk_rsgb_par */
186 /* rx_desk_rsgb_par */
188 /* tx_desk_rsgb_pcs */
190 /* rx_desk_rsgb_pcs */
194 /* pmd_adj_divisor */
199 /* ICE_PTP_LNK_SPD_10G */
202 257812500, /* 257.8125 MHz */
204 257812500, /* 257.8125 MHz */
206 156250000, /* 156.25 MHz */
208 156250000, /* 156.25 MHz */
209 /* tx_desk_rsgb_par */
211 /* rx_desk_rsgb_par */
213 /* tx_desk_rsgb_pcs */
215 /* rx_desk_rsgb_pcs */
219 /* pmd_adj_divisor */
224 /* ICE_PTP_LNK_SPD_25G */
227 644531250, /* 644.53125 MHZ */
229 644531250, /* 644.53125 MHz */
231 390625000, /* 390.625 MHz */
233 390625000, /* 390.625 MHz */
234 /* tx_desk_rsgb_par */
236 /* rx_desk_rsgb_par */
238 /* tx_desk_rsgb_pcs */
240 /* rx_desk_rsgb_pcs */
244 /* pmd_adj_divisor */
249 /* ICE_PTP_LNK_SPD_25G_RS */
259 /* tx_desk_rsgb_par */
260 161132812, /* 162.1328125 MHz Reed Solomon gearbox */
261 /* rx_desk_rsgb_par */
262 161132812, /* 162.1328125 MHz Reed Solomon gearbox */
263 /* tx_desk_rsgb_pcs */
264 97656250, /* 97.62625 MHz Reed Solomon gearbox */
265 /* rx_desk_rsgb_pcs */
266 97656250, /* 97.62625 MHz Reed Solomon gearbox */
269 /* pmd_adj_divisor */
274 /* ICE_PTP_LNK_SPD_40G */
281 156250000, /* 156.25 MHz */
283 156250000, /* 156.25 MHz */
284 /* tx_desk_rsgb_par */
286 /* rx_desk_rsgb_par */
287 156250000, /* 156.25 MHz deskew clock */
288 /* tx_desk_rsgb_pcs */
290 /* rx_desk_rsgb_pcs */
291 156250000, /* 156.25 MHz deskew clock */
294 /* pmd_adj_divisor */
299 /* ICE_PTP_LNK_SPD_50G */
302 644531250, /* 644.53125 MHZ */
304 644531250, /* 644.53125 MHZ */
306 390625000, /* 390.625 MHz */
308 390625000, /* 390.625 MHz */
309 /* tx_desk_rsgb_par */
311 /* rx_desk_rsgb_par */
312 195312500, /* 193.3125 MHz deskew clock */
313 /* tx_desk_rsgb_pcs */
315 /* rx_desk_rsgb_pcs */
316 195312500, /* 193.3125 MHz deskew clock */
319 /* pmd_adj_divisor */
324 /* ICE_PTP_LNK_SPD_50G_RS */
329 644531250, /* 644.53125 MHz */
333 644531250, /* 644.53125 MHz */
334 /* tx_desk_rsgb_par */
335 322265625, /* 322.265625 MHz Reed Solomon gearbox */
336 /* rx_desk_rsgb_par */
337 322265625, /* 322.265625 MHz Reed Solomon gearbox */
338 /* tx_desk_rsgb_pcs */
339 644531250, /* 644.53125 MHz Reed Solomon gearbox */
340 /* rx_desk_rsgb_pcs */
341 644531250, /* 644.53125 MHz Reed Solomon gearbox */
344 /* pmd_adj_divisor */
349 /* ICE_PTP_LNK_SPD_100G_RS */
354 644531250, /* 644.53125 MHz */
358 644531250, /* 644.53125 MHz */
359 /* tx_desk_rsgb_par */
360 644531250, /* 644.53125 MHz Reed Solomon gearbox */
361 /* rx_desk_rsgb_par */
362 644531250, /* 644.53125 MHz Reed Solomon gearbox */
363 /* tx_desk_rsgb_pcs */
364 644531250, /* 644.53125 MHz Reed Solomon gearbox */
365 /* rx_desk_rsgb_pcs */
366 644531250, /* 644.53125 MHz Reed Solomon gearbox */
369 /* pmd_adj_divisor */
376 #endif /* _ICE_PTP_CONSTS_H_ */