drivers/net/ice/base/ice_ptp_consts.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2021 Intel Corporation
   3  */
   4
   5 #ifndef _ICE_PTP_CONSTS_H_
   6 #define _ICE_PTP_CONSTS_H_
   7
   8 /* Constant definitions related to the hardware clock used for PTP 1588
   9  * features and functionality.
  10  */
  11 /* Constants defined for the PTP 1588 clock hardware. */
  12
  13 /*
  14  * struct ice_time_ref_info_e822
  15  *
  16  * E822 hardware can use different sources as the reference for the PTP
  17  * hardware clock. Each clock has different characteristics such as a slightly
  18  * different frequency, etc.
  19  *
  20  * This lookup table defines several constants that depend on the current time
  21  * reference. See the struct ice_time_ref_info_e822 for information about the
  22  * meaning of each constant.
  23  */
  24 const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {
  25         /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
  26         {
  27                 /* pll_freq */
  28                 823437500, /* 823.4375 MHz PLL */
  29                 /* nominal_incval */
  30                 0x136e44fabULL,
  31                 /* pps_delay */
  32                 11,
  33         },
  34
  35         /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
  36         {
  37                 /* pll_freq */
  38                 783360000, /* 783.36 MHz */
  39                 /* nominal_incval */
  40                 0x146cc2177ULL,
  41                 /* pps_delay */
  42                 12,
  43         },
  44
  45         /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
  46         {
  47                 /* pll_freq */
  48                 796875000, /* 796.875 MHz */
  49                 /* nominal_incval */
  50                 0x141414141ULL,
  51                 /* pps_delay */
  52                 12,
  53         },
  54
  55         /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
  56         {
  57                 /* pll_freq */
  58                 816000000, /* 816 MHz */
  59                 /* nominal_incval */
  60                 0x139b9b9baULL,
  61                 /* pps_delay */
  62                 12,
  63         },
  64
  65         /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
  66         {
  67                 /* pll_freq */
  68                 830078125, /* 830.78125 MHz */
  69                 /* nominal_incval */
  70                 0x134679aceULL,
  71                 /* pps_delay */
  72                 11,
  73         },
  74
  75         /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
  76         {
  77                 /* pll_freq */
  78                 783360000, /* 783.36 MHz */
  79                 /* nominal_incval */
  80                 0x146cc2177ULL,
  81                 /* pps_delay */
  82                 12,
  83         },
  84 };
  85
  86 const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
  87         /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
  88         {
  89                 /* refclk_pre_div */
  90                 1,
  91                 /* feedback_div */
  92                 197,
  93                 /* frac_n_div */
  94                 2621440,
  95                 /* post_pll_div */
  96                 6,
  97         },
  98
  99         /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
 100         {
 101                 /* refclk_pre_div */
 102                 5,
 103                 /* feedback_div */
 104                 223,
 105                 /* frac_n_div */
 106                 524288,
 107                 /* post_pll_div */
 108                 7,
 109         },
 110
 111         /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
 112         {
 113                 /* refclk_pre_div */
 114                 5,
 115                 /* feedback_div */
 116                 223,
 117                 /* frac_n_div */
 118                 524288,
 119                 /* post_pll_div */
 120                 7,
 121         },
 122
 123         /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
 124         {
 125                 /* refclk_pre_div */
 126                 5,
 127                 /* feedback_div */
 128                 159,
 129                 /* frac_n_div */
 130                 1572864,
 131                 /* post_pll_div */
 132                 6,
 133         },
 134
 135         /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
 136         {
 137                 /* refclk_pre_div */
 138                 5,
 139                 /* feedback_div */
 140                 159,
 141                 /* frac_n_div */
 142                 1572864,
 143                 /* post_pll_div */
 144                 6,
 145         },
 146
 147         /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
 148         {
 149                 /* refclk_pre_div */
 150                 10,
 151                 /* feedback_div */
 152                 223,
 153                 /* frac_n_div */
 154                 524288,
 155                 /* post_pll_div */
 156                 7,
 157         },
 158 };
 159
 160 #endif /* _ICE_PTP_CONSTS_H_ */