1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
6 #include "ice_common.h"
7 #include "ice_ptp_hw.h"
8 #include "ice_ptp_consts.h"
9 #include "ice_cgu_regs.h"
11 /* Low level functions for interacting with and managing the device clock used
12 * for the Precision Time Protocol.
14 * The ice hardware represents the current time using three registers:
16 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R
17 * +---------------+ +---------------+ +---------------+
18 * | 32 bits | | 32 bits | | 32 bits |
19 * +---------------+ +---------------+ +---------------+
21 * The registers are incremented every clock tick using a 40bit increment
22 * value defined over two registers:
24 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L
25 * +---------------+ +---------------+
26 * | 8 bit s | | 32 bits |
27 * +---------------+ +---------------+
29 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L
30 * registers every clock source tick. Depending on the specific device
31 * configuration, the clock source frequency could be one of a number of
34 * For E810 devices, the increment frequency is 812.5 MHz
36 * For E822 devices the clock can be derived from different sources, and the
37 * increment has an effective frequency of one of the following:
45 * The hardware captures timestamps in the PHY for incoming packets, and for
46 * outgoing packets on request. To support this, the PHY maintains a timer
47 * that matches the lower 64 bits of the global source timer.
49 * In order to ensure that the PHY timers and the source timer are equivalent,
50 * shadow registers are used to prepare the desired initial values. A special
51 * sync command is issued to trigger copying from the shadow registers into
52 * the appropriate source and PHY registers simultaneously.
54 * The driver supports devices which have different PHYs with subtly different
55 * mechanisms to program and control the timers. We divide the devices into
56 * families named after the first major device, E810 and similar devices, and
57 * E822 and similar devices.
59 * - E822 based devices have additional support for fine grained Vernier
60 * calibration which requires significant setup
61 * - The layout of timestamp data in the PHY register blocks is different
62 * - The way timer synchronization commands are issued is different.
64 * To support this, very low level functions have an e810 or e822 suffix
65 * indicating what type of device they work on. Higher level abstractions for
66 * tasks that can be done on both devices do not have the suffix and will
67 * correctly look up the appropriate low level function when running.
69 * Functions which only make sense on a single device family may not have
70 * a suitable generic implementation
74 * ice_get_ptp_src_clock_index - determine source clock index
75 * @hw: pointer to HW struct
77 * Determine the source clock index currently in use, based on device
78 * capabilities reported during initialization.
80 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw)
82 return hw->func_caps.ts_func_info.tmr_index_assoc;
86 * ice_ptp_read_src_incval - Read source timer increment value
87 * @hw: pointer to HW struct
89 * Read the increment value of the source timer and return it.
91 u64 ice_ptp_read_src_incval(struct ice_hw *hw)
96 tmr_idx = ice_get_ptp_src_clock_index(hw);
98 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
99 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
101 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
105 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
106 * @hw: pointer to HW struct
108 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the
109 * write immediately. This triggers the hardware to begin executing all of the
110 * source and PHY timer commands synchronously.
112 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
114 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD);
118 /* E822 family functions
120 * The following functions operate on the E822 family of devices.
124 * ice_fill_phy_msg_e822 - Fill message data for a PHY register access
125 * @msg: the PHY message buffer to fill in
126 * @port: the port to access
127 * @offset: the register offset
130 ice_fill_phy_msg_e822(struct ice_sbq_msg_input *msg, u8 port, u16 offset)
132 int phy_port, phy, quadtype;
134 phy_port = port % ICE_PORTS_PER_PHY;
135 phy = port / ICE_PORTS_PER_PHY;
136 quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_NUM_QUAD_TYPE;
139 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port);
140 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port);
142 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port);
143 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port);
147 msg->dest_dev = rmn_0;
149 msg->dest_dev = rmn_1;
151 msg->dest_dev = rmn_2;
155 * ice_is_64b_phy_reg_e822 - Check if this is a 64bit PHY register
156 * @low_addr: the low address to check
157 * @high_addr: on return, contains the high address of the 64bit register
159 * Checks if the provided low address is one of the known 64bit PHY values
160 * represented as two 32bit registers. If it is, return the appropriate high
161 * register offset to use.
163 static bool ice_is_64b_phy_reg_e822(u16 low_addr, u16 *high_addr)
166 case P_REG_PAR_PCS_TX_OFFSET_L:
167 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U;
169 case P_REG_PAR_PCS_RX_OFFSET_L:
170 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U;
172 case P_REG_PAR_TX_TIME_L:
173 *high_addr = P_REG_PAR_TX_TIME_U;
175 case P_REG_PAR_RX_TIME_L:
176 *high_addr = P_REG_PAR_RX_TIME_U;
178 case P_REG_TOTAL_TX_OFFSET_L:
179 *high_addr = P_REG_TOTAL_TX_OFFSET_U;
181 case P_REG_TOTAL_RX_OFFSET_L:
182 *high_addr = P_REG_TOTAL_RX_OFFSET_U;
184 case P_REG_UIX66_10G_40G_L:
185 *high_addr = P_REG_UIX66_10G_40G_U;
187 case P_REG_UIX66_25G_100G_L:
188 *high_addr = P_REG_UIX66_25G_100G_U;
190 case P_REG_TX_CAPTURE_L:
191 *high_addr = P_REG_TX_CAPTURE_U;
193 case P_REG_RX_CAPTURE_L:
194 *high_addr = P_REG_RX_CAPTURE_U;
196 case P_REG_TX_TIMER_INC_PRE_L:
197 *high_addr = P_REG_TX_TIMER_INC_PRE_U;
199 case P_REG_RX_TIMER_INC_PRE_L:
200 *high_addr = P_REG_RX_TIMER_INC_PRE_U;
208 * ice_is_40b_phy_reg_e822 - Check if this is a 40bit PHY register
209 * @low_addr: the low address to check
210 * @high_addr: on return, contains the high address of the 40bit value
212 * Checks if the provided low address is one of the known 40bit PHY values
213 * split into two registers with the lower 8 bits in the low register and the
214 * upper 32 bits in the high register. If it is, return the appropriate high
215 * register offset to use.
217 static bool ice_is_40b_phy_reg_e822(u16 low_addr, u16 *high_addr)
220 case P_REG_TIMETUS_L:
221 *high_addr = P_REG_TIMETUS_U;
223 case P_REG_PAR_RX_TUS_L:
224 *high_addr = P_REG_PAR_RX_TUS_U;
226 case P_REG_PAR_TX_TUS_L:
227 *high_addr = P_REG_PAR_TX_TUS_U;
229 case P_REG_PCS_RX_TUS_L:
230 *high_addr = P_REG_PCS_RX_TUS_U;
232 case P_REG_PCS_TX_TUS_L:
233 *high_addr = P_REG_PCS_TX_TUS_U;
235 case P_REG_DESK_PAR_RX_TUS_L:
236 *high_addr = P_REG_DESK_PAR_RX_TUS_U;
238 case P_REG_DESK_PAR_TX_TUS_L:
239 *high_addr = P_REG_DESK_PAR_TX_TUS_U;
241 case P_REG_DESK_PCS_RX_TUS_L:
242 *high_addr = P_REG_DESK_PCS_RX_TUS_U;
244 case P_REG_DESK_PCS_TX_TUS_L:
245 *high_addr = P_REG_DESK_PCS_TX_TUS_U;
253 * ice_read_phy_reg_e822_lp - Read a PHY register
254 * @hw: pointer to the HW struct
255 * @port: PHY port to read from
256 * @offset: PHY register offset to read
257 * @val: on return, the contents read from the PHY
258 * @lock_sbq: true if the sideband queue lock must be acquired
260 * Read a PHY register for the given port over the device sideband queue.
262 static enum ice_status
263 ice_read_phy_reg_e822_lp(struct ice_hw *hw, u8 port, u16 offset, u32 *val,
266 struct ice_sbq_msg_input msg = {0};
267 enum ice_status status;
269 ice_fill_phy_msg_e822(&msg, port, offset);
270 msg.opcode = ice_sbq_msg_rd;
272 status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
274 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
285 ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
287 return ice_read_phy_reg_e822_lp(hw, port, offset, val, true);
291 * ice_read_40b_phy_reg_e822 - Read a 40bit value from PHY registers
292 * @hw: pointer to the HW struct
293 * @port: PHY port to read from
294 * @low_addr: offset of the lower register to read from
295 * @val: on return, the contents of the 40bit value from the PHY registers
297 * Reads the two registers associated with a 40bit value and returns it in the
298 * val pointer. The offset always specifies the lower register offset to use.
299 * The high offset is looked up. This function only operates on registers
300 * known to be split into a lower 8 bit chunk and an upper 32 bit chunk.
302 static enum ice_status
303 ice_read_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
305 enum ice_status status;
309 /* Only operate on registers known to be split into two 32bit
312 if (!ice_is_40b_phy_reg_e822(low_addr, &high_addr)) {
313 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
315 return ICE_ERR_PARAM;
318 status = ice_read_phy_reg_e822(hw, port, low_addr, &low);
320 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, status %d",
325 status = ice_read_phy_reg_e822(hw, port, high_addr, &high);
327 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, status %d",
332 *val = (u64)high << P_REG_40B_HIGH_S | (low & P_REG_40B_LOW_M);
338 * ice_read_64b_phy_reg_e822 - Read a 64bit value from PHY registers
339 * @hw: pointer to the HW struct
340 * @port: PHY port to read from
341 * @low_addr: offset of the lower register to read from
342 * @val: on return, the contents of the 64bit value from the PHY registers
344 * Reads the two registers associated with a 64bit value and returns it in the
345 * val pointer. The offset always specifies the lower register offset to use.
346 * The high offset is looked up. This function only operates on registers
347 * known to be two parts of a 64bit value.
349 static enum ice_status
350 ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
352 enum ice_status status;
356 /* Only operate on registers known to be split into two 32bit
359 if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) {
360 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
362 return ICE_ERR_PARAM;
365 status = ice_read_phy_reg_e822(hw, port, low_addr, &low);
367 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, status %d",
372 status = ice_read_phy_reg_e822(hw, port, high_addr, &high);
374 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, status %d",
379 *val = (u64)high << 32 | low;
385 * ice_write_phy_reg_e822_lp - Write a PHY register
386 * @hw: pointer to the HW struct
387 * @port: PHY port to write to
388 * @offset: PHY register offset to write
389 * @val: The value to write to the register
390 * @lock_sbq: true if the sideband queue lock must be acquired
392 * Write a PHY register for the given port over the device sideband queue.
394 static enum ice_status
395 ice_write_phy_reg_e822_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val,
398 struct ice_sbq_msg_input msg = {0};
399 enum ice_status status;
401 ice_fill_phy_msg_e822(&msg, port, offset);
402 msg.opcode = ice_sbq_msg_wr;
405 status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
407 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
416 ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val)
418 return ice_write_phy_reg_e822_lp(hw, port, offset, val, true);
422 * ice_write_40b_phy_reg_e822 - Write a 40b value to the PHY
423 * @hw: pointer to the HW struct
424 * @port: port to write to
425 * @low_addr: offset of the low register
426 * @val: 40b value to write
428 * Write the provided 40b value to the two associated registers by splitting
429 * it up into two chunks, the lower 8 bits and the upper 32 bits.
431 static enum ice_status
432 ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
434 enum ice_status status;
438 /* Only operate on registers known to be split into a lower 8 bit
439 * register and an upper 32 bit register.
441 if (!ice_is_40b_phy_reg_e822(low_addr, &high_addr)) {
442 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n",
444 return ICE_ERR_PARAM;
447 low = (u32)(val & P_REG_40B_LOW_M);
448 high = (u32)(val >> P_REG_40B_HIGH_S);
450 status = ice_write_phy_reg_e822(hw, port, low_addr, low);
452 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
457 status = ice_write_phy_reg_e822(hw, port, high_addr, high);
459 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
468 * ice_write_64b_phy_reg_e822 - Write a 64bit value to PHY registers
469 * @hw: pointer to the HW struct
470 * @port: PHY port to read from
471 * @low_addr: offset of the lower register to read from
472 * @val: the contents of the 64bit value to write to PHY
474 * Write the 64bit value to the two associated 32bit PHY registers. The offset
475 * is always specified as the lower register, and the high address is looked
476 * up. This function only operates on registers known to be two parts of
479 static enum ice_status
480 ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
482 enum ice_status status;
486 /* Only operate on registers known to be split into two 32bit
489 if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) {
490 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
492 return ICE_ERR_PARAM;
495 low = ICE_LO_DWORD(val);
496 high = ICE_HI_DWORD(val);
498 status = ice_write_phy_reg_e822(hw, port, low_addr, low);
500 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
505 status = ice_write_phy_reg_e822(hw, port, high_addr, high);
507 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
516 * ice_fill_quad_msg_e822 - Fill message data for quad register access
517 * @msg: the PHY message buffer to fill in
518 * @quad: the quad to access
519 * @offset: the register offset
521 * Fill a message buffer for accessing a register in a quad shared between
525 ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)
529 msg->dest_dev = rmn_0;
531 if ((quad % ICE_NUM_QUAD_TYPE) == 0)
532 addr = Q_0_BASE + offset;
534 addr = Q_1_BASE + offset;
536 msg->msg_addr_low = ICE_LO_WORD(addr);
537 msg->msg_addr_high = ICE_HI_WORD(addr);
541 * ice_read_quad_reg_e822_lp - Read a PHY quad register
542 * @hw: pointer to the HW struct
543 * @quad: quad to read from
544 * @offset: quad register offset to read
545 * @val: on return, the contents read from the quad
546 * @lock_sbq: true if the sideband queue lock must be acquired
548 * Read a quad register over the device sideband queue. Quad registers are
549 * shared between multiple PHYs.
551 static enum ice_status
552 ice_read_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 *val,
555 struct ice_sbq_msg_input msg = {0};
556 enum ice_status status;
558 if (quad >= ICE_MAX_QUAD)
559 return ICE_ERR_PARAM;
561 ice_fill_quad_msg_e822(&msg, quad, offset);
562 msg.opcode = ice_sbq_msg_rd;
564 status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
566 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
577 ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)
579 return ice_read_quad_reg_e822_lp(hw, quad, offset, val, true);
583 * ice_write_quad_reg_e822_lp - Write a PHY quad register
584 * @hw: pointer to the HW struct
585 * @quad: quad to write to
586 * @offset: quad register offset to write
587 * @val: The value to write to the register
588 * @lock_sbq: true if the sideband queue lock must be acquired
590 * Write a quad register over the device sideband queue. Quad registers are
591 * shared between multiple PHYs.
593 static enum ice_status
594 ice_write_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 val,
597 struct ice_sbq_msg_input msg = {0};
598 enum ice_status status;
600 if (quad >= ICE_MAX_QUAD)
601 return ICE_ERR_PARAM;
603 ice_fill_quad_msg_e822(&msg, quad, offset);
604 msg.opcode = ice_sbq_msg_wr;
607 status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
609 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
618 ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val)
620 return ice_write_quad_reg_e822_lp(hw, quad, offset, val, true);
624 * ice_read_phy_tstamp_e822 - Read a PHY timestamp out of the quad block
625 * @hw: pointer to the HW struct
626 * @quad: the quad to read from
627 * @idx: the timestamp index to read
628 * @tstamp: on return, the 40bit timestamp value
630 * Read a 40bit timestamp value out of the two associated registers in the
631 * quad memory block that is shared between the internal PHYs of the E822
634 static enum ice_status
635 ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)
637 enum ice_status status;
638 u16 lo_addr, hi_addr;
641 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
642 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
644 status = ice_read_quad_reg_e822(hw, quad, lo_addr, &lo);
646 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n",
651 status = ice_read_quad_reg_e822(hw, quad, hi_addr, &hi);
653 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n",
658 /* For E822 based internal PHYs, the timestamp is reported with the
659 * lower 8 bits in the low register, and the upper 32 bits in the high
662 *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M);
668 * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block
669 * @hw: pointer to the HW struct
670 * @quad: the quad to read from
671 * @idx: the timestamp index to reset
673 * Clear a timestamp, resetting its valid bit, from the PHY quad block that is
674 * shared between the internal PHYs on the E822 devices.
676 static enum ice_status
677 ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)
679 enum ice_status status;
680 u16 lo_addr, hi_addr;
682 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
683 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
685 status = ice_write_quad_reg_e822(hw, quad, lo_addr, 0);
687 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n",
692 status = ice_write_quad_reg_e822(hw, quad, hi_addr, 0);
694 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n",
703 * ice_read_cgu_reg_e822 - Read a CGU register
704 * @hw: pointer to the HW struct
705 * @addr: Register address to read
706 * @val: storage for register value read
708 * Read the contents of a register of the Clock Generation Unit. Only
709 * applicable to E822 devices.
711 static enum ice_status
712 ice_read_cgu_reg_e822(struct ice_hw *hw, u16 addr, u32 *val)
714 struct ice_sbq_msg_input cgu_msg;
715 enum ice_status status;
717 cgu_msg.opcode = ice_sbq_msg_rd;
718 cgu_msg.dest_dev = cgu;
719 cgu_msg.msg_addr_low = addr;
720 cgu_msg.msg_addr_high = 0x0;
722 status = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
724 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, status %d\n",
735 * ice_write_cgu_reg_e822 - Write a CGU register
736 * @hw: pointer to the HW struct
737 * @addr: Register address to write
738 * @val: value to write into the register
740 * Write the specified value to a register of the Clock Generation Unit. Only
741 * applicable to E822 devices.
743 static enum ice_status
744 ice_write_cgu_reg_e822(struct ice_hw *hw, u16 addr, u32 val)
746 struct ice_sbq_msg_input cgu_msg;
747 enum ice_status status;
749 cgu_msg.opcode = ice_sbq_msg_wr;
750 cgu_msg.dest_dev = cgu;
751 cgu_msg.msg_addr_low = addr;
752 cgu_msg.msg_addr_high = 0x0;
755 status = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
757 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, status %d\n",
766 * ice_clk_freq_str - Convert time_ref_freq to string
767 * @clk_freq: Clock frequency
769 * Convert the specified TIME_REF clock frequency to a string.
771 static const char *ice_clk_freq_str(u8 clk_freq)
773 switch ((enum ice_time_ref_freq)clk_freq) {
774 case ICE_TIME_REF_FREQ_25_000:
776 case ICE_TIME_REF_FREQ_122_880:
778 case ICE_TIME_REF_FREQ_125_000:
780 case ICE_TIME_REF_FREQ_153_600:
782 case ICE_TIME_REF_FREQ_156_250:
784 case ICE_TIME_REF_FREQ_245_760:
792 * ice_clk_src_str - Convert time_ref_src to string
793 * @clk_src: Clock source
795 * Convert the specified clock source to its string name.
797 static const char *ice_clk_src_str(u8 clk_src)
799 switch ((enum ice_clk_src)clk_src) {
800 case ICE_CLK_SRC_TCX0:
802 case ICE_CLK_SRC_TIME_REF:
810 * ice_cfg_cgu_pll_e822 - Configure the Clock Generation Unit
811 * @hw: pointer to the HW struct
812 * @clk_freq: Clock frequency to program
813 * @clk_src: Clock source to select (TIME_REF, or TCX0)
815 * Configure the Clock Generation Unit with the desired clock frequency and
816 * time reference, enabling the PLL which drives the PTP hardware clock.
819 ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
820 enum ice_clk_src clk_src)
822 union tspll_ro_bwm_lf bwm_lf;
823 union nac_cgu_dword19 dw19;
824 union nac_cgu_dword22 dw22;
825 union nac_cgu_dword24 dw24;
826 union nac_cgu_dword9 dw9;
827 enum ice_status status;
829 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
830 ice_warn(hw, "Invalid TIME_REF frequency %u\n", clk_freq);
831 return ICE_ERR_PARAM;
834 if (clk_src >= NUM_ICE_CLK_SRC) {
835 ice_warn(hw, "Invalid clock source %u\n", clk_src);
836 return ICE_ERR_PARAM;
839 if (clk_src == ICE_CLK_SRC_TCX0 &&
840 clk_freq != ICE_TIME_REF_FREQ_25_000) {
841 ice_warn(hw, "TCX0 only supports 25 MHz frequency\n");
842 return ICE_ERR_PARAM;
845 status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD9, &dw9.val);
849 status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);
853 status = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
857 /* Log the current clock configuration */
858 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
859 dw24.field.ts_pll_enable ? "enabled" : "disabled",
860 ice_clk_src_str(dw24.field.time_ref_sel),
861 ice_clk_freq_str(dw9.field.time_ref_freq_sel),
862 bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
864 /* Disable the PLL before changing the clock source or frequency */
865 if (dw24.field.ts_pll_enable) {
866 dw24.field.ts_pll_enable = 0;
868 status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);
873 /* Set the frequency */
874 dw9.field.time_ref_freq_sel = clk_freq;
875 status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val);
879 /* Configure the TS PLL feedback divisor */
880 status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD19, &dw19.val);
884 dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
885 dw19.field.tspll_ndivratio = 1;
887 status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val);
891 /* Configure the TS PLL post divisor */
892 status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD22, &dw22.val);
896 dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
897 dw22.field.time1588clk_sel_div2 = 0;
899 status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val);
903 /* Configure the TS PLL pre divisor and clock source */
904 status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);
908 dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
909 dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
910 dw24.field.time_ref_sel = clk_src;
912 status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);
916 /* Finally, enable the PLL */
917 dw24.field.ts_pll_enable = 1;
919 status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);
923 /* Wait to verify if the PLL locks */
924 ice_msec_delay(1, true);
926 status = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
930 if (!bwm_lf.field.plllock_true_lock_cri) {
931 ice_warn(hw, "CGU PLL failed to lock\n");
932 return ICE_ERR_NOT_READY;
935 /* Log the current clock configuration */
936 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
937 dw24.field.ts_pll_enable ? "enabled" : "disabled",
938 ice_clk_src_str(dw24.field.time_ref_sel),
939 ice_clk_freq_str(dw9.field.time_ref_freq_sel),
940 bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
947 * ice_init_cgu_e822 - Initialize CGU with settings from firmware
948 * @hw: pointer to the HW structure
950 * Initialize the Clock Generation Unit of the E822 device.
952 static enum ice_status ice_init_cgu_e822(struct ice_hw *hw)
954 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
955 union tspll_cntr_bist_settings cntr_bist;
956 enum ice_status status;
958 status = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,
963 /* Disable sticky lock detection so lock status reported is accurate */
964 cntr_bist.field.i_plllock_sel_0 = 0;
965 cntr_bist.field.i_plllock_sel_1 = 0;
967 status = ice_write_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,
972 /* Configure the CGU PLL using the parameters from the function
975 status = ice_cfg_cgu_pll_e822(hw, ts_info->time_ref,
976 (enum ice_clk_src)ts_info->clk_src);
984 * ice_ptp_init_phc_e822 - Perform E822 specific PHC initialization
985 * @hw: pointer to HW struct
987 * Perform PHC initialization steps specific to E822 devices.
989 static enum ice_status ice_ptp_init_phc_e822(struct ice_hw *hw)
991 enum ice_status status;
994 /* Enable reading switch and PHY registers over the sideband queue */
995 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
996 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
997 regval = rd32(hw, PF_SB_REM_DEV_CTL);
998 regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ |
999 PF_SB_REM_DEV_CTL_PHY0);
1000 wr32(hw, PF_SB_REM_DEV_CTL, regval);
1002 /* Initialize the Clock Generation Unit */
1003 status = ice_init_cgu_e822(hw);
1007 /* Set window length for all the ports */
1008 return ice_ptp_set_vernier_wl(hw);
1012 * ice_ptp_prep_phy_time_e822 - Prepare PHY port with initial time
1013 * @hw: pointer to the HW struct
1014 * @time: Time to initialize the PHY port clocks to
1016 * Program the PHY port registers with a new initial time value. The port
1017 * clock will be initialized once the driver issues an INIT_TIME sync
1018 * command. The time value is the upper 32 bits of the PHY timer, usually in
1019 * units of nominal nanoseconds.
1021 static enum ice_status
1022 ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time)
1024 enum ice_status status;
1028 /* The time represents the upper 32 bits of the PHY timer, so we need
1029 * to shift to account for this when programming.
1031 phy_time = (u64)time << 32;
1033 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1036 status = ice_write_64b_phy_reg_e822(hw, port,
1037 P_REG_TX_TIMER_INC_PRE_L,
1043 status = ice_write_64b_phy_reg_e822(hw, port,
1044 P_REG_RX_TIMER_INC_PRE_L,
1053 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, status %d\n",
1060 * ice_ptp_prep_port_adj_e822 - Prepare a single port for time adjust
1061 * @hw: pointer to HW struct
1062 * @port: Port number to be programmed
1063 * @time: time in cycles to adjust the port Tx and Rx clocks
1064 * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
1065 * sq_lock has already been locked at a higher level
1067 * Program the port for an atomic adjustment by writing the Tx and Rx timer
1068 * registers. The atomic adjustment won't be completed until the driver issues
1069 * an ADJ_TIME command.
1071 * Note that time is not in units of nanoseconds. It is in clock time
1072 * including the lower sub-nanosecond portion of the port timer.
1074 * Negative adjustments are supported using 2s complement arithmetic.
1077 ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time,
1080 enum ice_status status;
1083 l_time = ICE_LO_DWORD(time);
1084 u_time = ICE_HI_DWORD(time);
1087 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TIMER_INC_PRE_L,
1092 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TIMER_INC_PRE_U,
1098 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TIMER_INC_PRE_L,
1103 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TIMER_INC_PRE_U,
1111 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, status %d\n",
1117 * ice_ptp_prep_phy_adj_e822 - Prep PHY ports for a time adjustment
1118 * @hw: pointer to HW struct
1119 * @adj: adjustment in nanoseconds
1120 * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
1121 * sq_lock has already been locked at a higher level
1123 * Prepare the PHY ports for an atomic time adjustment by programming the PHY
1124 * Tx and Rx port registers. The actual adjustment is completed by issuing an
1125 * ADJ_TIME or ADJ_TIME_AT_TIME sync command.
1127 static enum ice_status
1128 ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj, bool lock_sbq)
1133 /* The port clock supports adjustment of the sub-nanosecond portion of
1134 * the clock. We shift the provided adjustment in nanoseconds to
1135 * calculate the appropriate adjustment to program into the PHY ports.
1138 cycles = (s64)adj << 32;
1140 cycles = -(((s64)-adj) << 32);
1142 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1143 enum ice_status status;
1145 status = ice_ptp_prep_port_adj_e822(hw, port, cycles,
1155 * ice_ptp_prep_phy_incval_e822 - Prepare PHY ports for time adjustment
1156 * @hw: pointer to HW struct
1157 * @incval: new increment value to prepare
1159 * Prepare each of the PHY ports for a new increment value by programming the
1160 * port's TIMETUS registers. The new increment value will be updated after
1161 * issuing an INIT_INCVAL command.
1163 static enum ice_status
1164 ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval)
1166 enum ice_status status;
1169 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1170 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L,
1179 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, status %d\n",
1186 * ice_ptp_read_phy_incval_e822 - Read a PHY port's current incval
1187 * @hw: pointer to the HW struct
1188 * @port: the port to read
1189 * @incval: on return, the time_clk_cyc incval for this port
1191 * Read the time_clk_cyc increment value for a given PHY port.
1194 ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port, u64 *incval)
1196 enum ice_status status;
1198 status = ice_read_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval);
1200 ice_debug(hw, ICE_DBG_PTP, "Failed to read TIMETUS_L, status %d\n",
1205 ice_debug(hw, ICE_DBG_PTP, "read INCVAL = 0x%016llx\n",
1206 (unsigned long long)*incval);
1212 * ice_ptp_prep_phy_adj_target_e822 - Prepare PHY for adjust at target time
1213 * @hw: pointer to HW struct
1214 * @target_time: target time to program
1216 * Program the PHY port Tx and Rx TIMER_CNT_ADJ registers used for the
1217 * ADJ_TIME_AT_TIME command. This should be used in conjunction with
1218 * ice_ptp_prep_phy_adj_e822 to program an atomic adjustment that is
1219 * delayed until a specified target time.
1221 * Note that a target time adjustment is not currently supported on E810
1224 static enum ice_status
1225 ice_ptp_prep_phy_adj_target_e822(struct ice_hw *hw, u32 target_time)
1227 enum ice_status status;
1230 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1233 /* No sub-nanoseconds data */
1234 status = ice_write_phy_reg_e822_lp(hw, port,
1235 P_REG_TX_TIMER_CNT_ADJ_L,
1240 status = ice_write_phy_reg_e822_lp(hw, port,
1241 P_REG_TX_TIMER_CNT_ADJ_U,
1247 /* No sub-nanoseconds data */
1248 status = ice_write_phy_reg_e822_lp(hw, port,
1249 P_REG_RX_TIMER_CNT_ADJ_L,
1254 status = ice_write_phy_reg_e822_lp(hw, port,
1255 P_REG_RX_TIMER_CNT_ADJ_U,
1264 ice_debug(hw, ICE_DBG_PTP, "Failed to write target time for port %u, status %d\n",
1271 * ice_ptp_read_port_capture - Read a port's local time capture
1272 * @hw: pointer to HW struct
1273 * @port: Port number to read
1274 * @tx_ts: on return, the Tx port time capture
1275 * @rx_ts: on return, the Rx port time capture
1277 * Read the port's Tx and Rx local time capture values.
1279 * Note this has no equivalent for the E810 devices.
1282 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
1284 enum ice_status status;
1287 status = ice_read_64b_phy_reg_e822(hw, port, P_REG_TX_CAPTURE_L, tx_ts);
1289 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, status %d\n",
1294 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n",
1295 (unsigned long long)*tx_ts);
1298 status = ice_read_64b_phy_reg_e822(hw, port, P_REG_RX_CAPTURE_L, rx_ts);
1300 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, status %d\n",
1305 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n",
1306 (unsigned long long)*rx_ts);
1312 * ice_ptp_one_port_cmd - Prepare a single PHY port for a timer command
1313 * @hw: pointer to HW struct
1314 * @port: Port to which cmd has to be sent
1315 * @cmd: Command to be sent to the port
1316 * @lock_sbq: true if the sideband queue lock must be acquired
1318 * Prepare the requested port for an upcoming timer sync command.
1320 * Note there is no equivalent of this operation on E810, as that device
1321 * always handles all external PHYs internally.
1324 ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
1327 enum ice_status status;
1331 tmr_idx = ice_get_ptp_src_clock_index(hw);
1332 cmd_val = tmr_idx << SEL_PHY_SRC;
1335 cmd_val |= PHY_CMD_INIT_TIME;
1338 cmd_val |= PHY_CMD_INIT_INCVAL;
1341 cmd_val |= PHY_CMD_ADJ_TIME;
1343 case ADJ_TIME_AT_TIME:
1344 cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME;
1347 cmd_val |= PHY_CMD_READ_TIME;
1350 ice_warn(hw, "Unknown timer command %u\n", cmd);
1351 return ICE_ERR_PARAM;
1355 /* Read, modify, write */
1356 status = ice_read_phy_reg_e822_lp(hw, port, P_REG_TX_TMR_CMD, &val,
1359 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, status %d\n",
1364 /* Modify necessary bits only and perform write */
1365 val &= ~TS_CMD_MASK;
1368 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TMR_CMD, val,
1371 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, status %d\n",
1377 /* Read, modify, write */
1378 status = ice_read_phy_reg_e822_lp(hw, port, P_REG_RX_TMR_CMD, &val,
1381 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, status %d\n",
1386 /* Modify necessary bits only and perform write */
1387 val &= ~TS_CMD_MASK;
1390 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TMR_CMD, val,
1393 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, status %d\n",
1402 * ice_ptp_port_cmd_e822 - Prepare all ports for a timer command
1403 * @hw: pointer to the HW struct
1404 * @cmd: timer command to prepare
1405 * @lock_sbq: true if the sideband queue lock must be acquired
1407 * Prepare all ports connected to this device for an upcoming timer sync
1410 static enum ice_status
1411 ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
1416 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1417 enum ice_status status;
1419 status = ice_ptp_one_port_cmd(hw, port, cmd, lock_sbq);
1427 /* E822 Vernier calibration functions
1429 * The following functions are used as part of the vernier calibration of
1430 * a port. This calibration increases the precision of the timestamps on the
1435 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
1436 * @hw: pointer to the HW struct
1438 * Set the window length used for the vernier port calibration process.
1440 enum ice_status ice_ptp_set_vernier_wl(struct ice_hw *hw)
1444 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1445 enum ice_status status;
1447 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL,
1448 PTP_VERNIER_WL, true);
1450 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, status %d\n",
1460 * ice_phy_get_speed_and_fec_e822 - Get link speed and FEC based on serdes mode
1461 * @hw: pointer to HW struct
1462 * @port: the port to read from
1463 * @link_out: if non-NULL, holds link speed on success
1464 * @fec_out: if non-NULL, holds FEC algorithm on success
1466 * Read the serdes data for the PHY port and extract the link speed and FEC
1470 ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
1471 enum ice_ptp_link_spd *link_out,
1472 enum ice_ptp_fec_mode *fec_out)
1474 enum ice_ptp_link_spd link;
1475 enum ice_ptp_fec_mode fec;
1476 enum ice_status status;
1479 status = ice_read_phy_reg_e822(hw, port, P_REG_LINK_SPEED, &serdes);
1481 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n");
1485 /* Determine the FEC algorithm */
1486 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes);
1488 serdes &= P_REG_LINK_SPEED_SERDES_M;
1490 /* Determine the link speed */
1491 if (fec == ICE_PTP_FEC_MODE_RS_FEC) {
1493 case ICE_PTP_SERDES_25G:
1494 link = ICE_PTP_LNK_SPD_25G_RS;
1496 case ICE_PTP_SERDES_50G:
1497 link = ICE_PTP_LNK_SPD_50G_RS;
1499 case ICE_PTP_SERDES_100G:
1500 link = ICE_PTP_LNK_SPD_100G_RS;
1503 return ICE_ERR_OUT_OF_RANGE;
1507 case ICE_PTP_SERDES_1G:
1508 link = ICE_PTP_LNK_SPD_1G;
1510 case ICE_PTP_SERDES_10G:
1511 link = ICE_PTP_LNK_SPD_10G;
1513 case ICE_PTP_SERDES_25G:
1514 link = ICE_PTP_LNK_SPD_25G;
1516 case ICE_PTP_SERDES_40G:
1517 link = ICE_PTP_LNK_SPD_40G;
1519 case ICE_PTP_SERDES_50G:
1520 link = ICE_PTP_LNK_SPD_50G;
1523 return ICE_ERR_OUT_OF_RANGE;
1536 * ice_phy_cfg_lane_e822 - Configure PHY quad for single/multi-lane timestamp
1537 * @hw: pointer to HW struct
1538 * @port: to configure the quad for
1540 void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)
1542 enum ice_ptp_link_spd link_spd;
1543 enum ice_status status;
1547 status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, NULL);
1549 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, status %d\n",
1554 quad = port / ICE_PORTS_PER_QUAD;
1556 status = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
1558 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, status %d\n",
1563 if (link_spd >= ICE_PTP_LNK_SPD_40G)
1564 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
1566 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
1568 status = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
1570 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, status %d\n",
1577 * ice_phy_cfg_uix_e822 - Configure Serdes UI to TU conversion for E822
1578 * @hw: pointer to the HW structure
1579 * @port: the port to configure
1581 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC
1582 * hardware clock time units (TUs). That is, determine the number of TUs per
1583 * serdes unit interval, and program the UIX registers with this conversion.
1585 * This conversion is used as part of the calibration process when determining
1586 * the additional error of a timestamp vs the real time of transmission or
1587 * receipt of the packet.
1589 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers
1590 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks.
1592 * To calculate the conversion ratio, we use the following facts:
1594 * a) the clock frequency in Hz (cycles per second)
1595 * b) the number of TUs per cycle (the increment value of the clock)
1596 * c) 1 second per 1 billion nanoseconds
1597 * d) the duration of 66 UIs in nanoseconds
1599 * Given these facts, we can use the following table to work out what ratios
1600 * to multiply in order to get the number of TUs per 66 UIs:
1602 * cycles | 1 second | incval (TUs) | nanoseconds
1603 * -------+--------------+--------------+-------------
1604 * second | 1 billion ns | cycle | 66 UIs
1606 * To perform the multiplication using integers without too much loss of
1607 * precision, we can take use the following equation:
1609 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion)
1611 * We scale up to using 6600 UI instead of 66 in order to avoid fractional
1612 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns)
1614 * The increment value has a maximum expected range of about 34 bits, while
1615 * the frequency value is about 29 bits. Multiplying these values shouldn't
1616 * overflow the 64 bits. However, we must then further multiply them again by
1617 * the Serdes unit interval duration. To avoid overflow here, we split the
1618 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and
1619 * a divide by 390,625,000. This does lose some precision, but avoids
1620 * miscalculation due to arithmetic overflow.
1622 static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)
1624 u64 cur_freq, clk_incval, tu_per_sec, uix;
1625 enum ice_status status;
1627 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
1628 clk_incval = ice_ptp_read_src_incval(hw);
1630 /* Calculate TUs per second divided by 256 */
1631 tu_per_sec = (cur_freq * clk_incval) >> 8;
1633 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */
1634 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
1636 /* Program the 10Gb/40Gb conversion ratio */
1637 uix = DIV_64BIT(tu_per_sec * LINE_UI_10G_40G, 390625000);
1639 status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,
1642 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, status %d\n",
1647 /* Program the 25Gb/100Gb conversion ratio */
1648 uix = DIV_64BIT(tu_per_sec * LINE_UI_25G_100G, 390625000);
1650 status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,
1653 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, status %d\n",
1662 * ice_phy_cfg_parpcs_e822 - Configure TUs per PAR/PCS clock cycle
1663 * @hw: pointer to the HW struct
1664 * @port: port to configure
1666 * Configure the number of TUs for the PAR and PCS clocks used as part of the
1667 * timestamp calibration process. This depends on the link speed, as the PHY
1668 * uses different markers depending on the speed.
1671 * - Tx/Rx PAR/PCS markers
1674 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
1677 * - Tx/Rx PAR/PCS markers
1678 * - Rx Deskew PAR/PCS markers
1680 * 50G RS and 100GB RS:
1681 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
1682 * - Rx Deskew PAR/PCS markers
1683 * - Tx PAR/PCS markers
1685 * To calculate the conversion, we use the PHC clock frequency (cycles per
1686 * second), the increment value (TUs per cycle), and the related PHY clock
1687 * frequency to calculate the TUs per unit of the PHY link clock. The
1688 * following table shows how the units convert:
1690 * cycles | TUs | second
1691 * -------+-------+--------
1692 * second | cycle | cycles
1694 * For each conversion register, look up the appropriate frequency from the
1695 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program
1696 * this to the appropriate register, preparing hardware to perform timestamp
1697 * calibration to calculate the total Tx or Rx offset to adjust the timestamp
1698 * in order to calibrate for the internal PHY delays.
1700 * Note that the increment value ranges up to ~34 bits, and the clock
1701 * frequency is ~29 bits, so multiplying them together should fit within the
1702 * 64 bit arithmetic.
1704 static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
1706 u64 cur_freq, clk_incval, tu_per_sec, phy_tus;
1707 enum ice_ptp_link_spd link_spd;
1708 enum ice_ptp_fec_mode fec_mode;
1709 enum ice_status status;
1711 status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
1715 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
1716 clk_incval = ice_ptp_read_src_incval(hw);
1718 /* Calculate TUs per cycle of the PHC clock */
1719 tu_per_sec = cur_freq * clk_incval;
1721 /* For each PHY conversion register, look up the appropriate link
1722 * speed frequency and determine the TUs per that clock's cycle time.
1723 * Split this into a high and low value and then program the
1724 * appropriate register. If that link speed does not use the
1725 * associated register, write zeros to clear it instead.
1728 /* P_REG_PAR_TX_TUS */
1729 if (e822_vernier[link_spd].tx_par_clk)
1730 phy_tus = DIV_64BIT(tu_per_sec,
1731 e822_vernier[link_spd].tx_par_clk);
1735 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_TX_TUS_L,
1740 /* P_REG_PAR_RX_TUS */
1741 if (e822_vernier[link_spd].rx_par_clk)
1742 phy_tus = DIV_64BIT(tu_per_sec,
1743 e822_vernier[link_spd].rx_par_clk);
1747 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_RX_TUS_L,
1752 /* P_REG_PCS_TX_TUS */
1753 if (e822_vernier[link_spd].tx_pcs_clk)
1754 phy_tus = DIV_64BIT(tu_per_sec,
1755 e822_vernier[link_spd].tx_pcs_clk);
1759 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_TX_TUS_L,
1764 /* P_REG_PCS_RX_TUS */
1765 if (e822_vernier[link_spd].rx_pcs_clk)
1766 phy_tus = DIV_64BIT(tu_per_sec,
1767 e822_vernier[link_spd].rx_pcs_clk);
1771 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_RX_TUS_L,
1776 /* P_REG_DESK_PAR_TX_TUS */
1777 if (e822_vernier[link_spd].tx_desk_rsgb_par)
1778 phy_tus = DIV_64BIT(tu_per_sec,
1779 e822_vernier[link_spd].tx_desk_rsgb_par);
1783 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_TX_TUS_L,
1788 /* P_REG_DESK_PAR_RX_TUS */
1789 if (e822_vernier[link_spd].rx_desk_rsgb_par)
1790 phy_tus = DIV_64BIT(tu_per_sec,
1791 e822_vernier[link_spd].rx_desk_rsgb_par);
1795 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_RX_TUS_L,
1800 /* P_REG_DESK_PCS_TX_TUS */
1801 if (e822_vernier[link_spd].tx_desk_rsgb_pcs)
1802 phy_tus = DIV_64BIT(tu_per_sec,
1803 e822_vernier[link_spd].tx_desk_rsgb_pcs);
1807 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_TX_TUS_L,
1812 /* P_REG_DESK_PCS_RX_TUS */
1813 if (e822_vernier[link_spd].rx_desk_rsgb_pcs)
1814 phy_tus = DIV_64BIT(tu_per_sec,
1815 e822_vernier[link_spd].rx_desk_rsgb_pcs);
1819 return ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_RX_TUS_L,
1824 * ice_calc_fixed_tx_offset_e822 - Calculated Fixed Tx offset for a port
1825 * @hw: pointer to the HW struct
1826 * @link_spd: the Link speed to calculate for
1828 * Calculate the fixed offset due to known static latency data.
1831 ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
1833 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
1835 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
1836 clk_incval = ice_ptp_read_src_incval(hw);
1838 /* Calculate TUs per second */
1839 tu_per_sec = cur_freq * clk_incval;
1841 /* Calculate number of TUs to add for the fixed Tx latency. Since the
1842 * latency measurement is in 1/100th of a nanosecond, we need to
1843 * multiply by tu_per_sec and then divide by 1e11. This calculation
1844 * overflows 64 bit integer arithmetic, so break it up into two
1845 * divisions by 1e4 first then by 1e7.
1847 fixed_offset = DIV_64BIT(tu_per_sec, 10000);
1848 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay;
1849 fixed_offset = DIV_64BIT(fixed_offset, 10000000);
1851 return fixed_offset;
1855 * ice_phy_cfg_tx_offset_e822 - Configure total Tx timestamp offset
1856 * @hw: pointer to the HW struct
1857 * @port: the PHY port to configure
1859 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to
1860 * adjust Tx timestamps by. This is calculated by combining some known static
1861 * latency along with the Vernier offset computations done by hardware.
1863 * This function must be called only after the offset registers are valid,
1864 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
1865 * has measured the offset.
1867 * To avoid overflow, when calculating the offset based on the known static
1868 * latency values, we use measurements in 1/100th of a nanosecond, and divide
1869 * the TUs per second up front. This avoids overflow while allowing
1870 * calculation of the adjustment using integer arithmetic.
1872 enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)
1874 enum ice_ptp_link_spd link_spd;
1875 enum ice_ptp_fec_mode fec_mode;
1876 enum ice_status status;
1877 u64 total_offset, val;
1879 status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
1883 total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
1885 /* Read the first Vernier offset from the PHY register and add it to
1888 if (link_spd == ICE_PTP_LNK_SPD_1G ||
1889 link_spd == ICE_PTP_LNK_SPD_10G ||
1890 link_spd == ICE_PTP_LNK_SPD_25G ||
1891 link_spd == ICE_PTP_LNK_SPD_25G_RS ||
1892 link_spd == ICE_PTP_LNK_SPD_40G ||
1893 link_spd == ICE_PTP_LNK_SPD_50G) {
1894 status = ice_read_64b_phy_reg_e822(hw, port,
1895 P_REG_PAR_PCS_TX_OFFSET_L,
1900 total_offset += val;
1903 /* For Tx, we only need to use the second Vernier offset for
1904 * multi-lane link speeds with RS-FEC. The lanes will always be
1907 if (link_spd == ICE_PTP_LNK_SPD_50G_RS ||
1908 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
1909 status = ice_read_64b_phy_reg_e822(hw, port,
1910 P_REG_PAR_TX_TIME_L,
1915 total_offset += val;
1918 /* Now that the total offset has been calculated, program it to the
1919 * PHY and indicate that the Tx offset is ready. After this,
1920 * timestamps will be enabled.
1922 status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
1927 status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
1935 * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode
1936 * @hw: pointer to the HW struct
1937 * @port: the PHY port to configure
1939 * Calculate and program the fixed Tx offset, and indicate that the offset is
1940 * ready. This can be used when operating in bypass mode.
1942 static enum ice_status
1943 ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port)
1945 enum ice_ptp_link_spd link_spd;
1946 enum ice_ptp_fec_mode fec_mode;
1947 enum ice_status status;
1950 status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
1954 total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
1956 /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L
1957 * register, then indicate that the Tx offset is ready. After this,
1958 * timestamps will be enabled.
1960 * Note that this skips including the more precise offsets generated
1961 * by the Vernier calibration.
1963 status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
1968 status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
1976 * ice_phy_calc_pmd_adj_e822 - Calculate PMD adjustment for Rx
1977 * @hw: pointer to the HW struct
1978 * @port: the PHY port to adjust for
1979 * @link_spd: the current link speed of the PHY
1980 * @fec_mode: the current FEC mode of the PHY
1981 * @pmd_adj: on return, the amount to adjust the Rx total offset by
1983 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY.
1984 * This varies by link speed and FEC mode. The value calculated accounts for
1985 * various delays caused when receiving a packet.
1987 static enum ice_status
1988 ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
1989 enum ice_ptp_link_spd link_spd,
1990 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)
1992 u64 cur_freq, clk_incval, tu_per_sec, mult, adj;
1993 u32 pmd_adj_divisor, val;
1994 enum ice_status status;
1997 status = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &val);
1999 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, status %d\n",
2004 pmd_align = (u8)val;
2006 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
2007 clk_incval = ice_ptp_read_src_incval(hw);
2009 /* Calculate TUs per second */
2010 tu_per_sec = cur_freq * clk_incval;
2012 /* Get the link speed dependent PMD adjustment divisor */
2013 pmd_adj_divisor = e822_vernier[link_spd].pmd_adj_divisor;
2015 /* The PMD alignment adjustment measurement depends on the link speed,
2016 * and whether FEC is enabled. For each link speed, the alignment
2017 * adjustment is calculated by dividing a value by the length of
2018 * a Time Unit in nanoseconds.
2020 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8
2021 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33)
2022 * 10G w/FEC: align * 0.1 * 32/33
2023 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33)
2024 * 25G w/FEC: align * 0.4 * 32/33
2025 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33)
2026 * 40G w/FEC: align * 0.1 * 32/33
2027 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33)
2028 * 50G w/FEC: align * 0.8 * 32/33
2030 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33.
2032 * To allow for calculating this value using integer arithmetic, we
2033 * instead start with the number of TUs per second, (inverse of the
2034 * length of a Time Unit in nanoseconds), multiply by a value based
2035 * on the PMD alignment register, and then divide by the right value
2036 * calculated based on the table above. To avoid integer overflow this
2037 * division is broken up into a step of dividing by 125 first.
2039 if (link_spd == ICE_PTP_LNK_SPD_1G) {
2043 mult = (pmd_align + 6) % 10;
2044 } else if (link_spd == ICE_PTP_LNK_SPD_10G ||
2045 link_spd == ICE_PTP_LNK_SPD_25G ||
2046 link_spd == ICE_PTP_LNK_SPD_40G ||
2047 link_spd == ICE_PTP_LNK_SPD_50G) {
2048 /* If Clause 74 FEC, always calculate PMD adjust */
2049 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74)
2053 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS ||
2054 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
2055 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
2057 mult = pmd_align + 40;
2061 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n",
2066 /* In some cases, there's no need to adjust for the PMD alignment */
2072 /* Calculate the adjustment by multiplying TUs per second by the
2073 * appropriate multiplier and divisor. To avoid overflow, we first
2074 * divide by 125, and then handle remaining divisor based on the link
2075 * speed pmd_adj_divisor value.
2077 adj = DIV_64BIT(tu_per_sec, 125);
2079 adj = DIV_64BIT(adj, pmd_adj_divisor);
2081 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx
2082 * cycle count is necessary.
2084 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) {
2088 status = ice_read_phy_reg_e822(hw, port, P_REG_RX_40_TO_160_CNT,
2091 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, status %d\n",
2096 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M;
2098 mult = (4 - rx_cycle) * 40;
2100 cycle_adj = DIV_64BIT(tu_per_sec, 125);
2102 cycle_adj = DIV_64BIT(cycle_adj, pmd_adj_divisor);
2106 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) {
2110 status = ice_read_phy_reg_e822(hw, port, P_REG_RX_80_TO_160_CNT,
2113 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, status %d\n",
2118 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M;
2120 mult = rx_cycle * 40;
2122 cycle_adj = DIV_64BIT(tu_per_sec, 125);
2124 cycle_adj = DIV_64BIT(cycle_adj, pmd_adj_divisor);
2130 /* Return the calculated adjustment */
2137 * ice_calc_fixed_rx_offset_e822 - Calculated the fixed Rx offset for a port
2138 * @hw: pointer to HW struct
2139 * @link_spd: The Link speed to calculate for
2141 * Determine the fixed Rx latency for a given link speed.
2144 ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
2146 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
2148 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
2149 clk_incval = ice_ptp_read_src_incval(hw);
2151 /* Calculate TUs per second */
2152 tu_per_sec = cur_freq * clk_incval;
2154 /* Calculate number of TUs to add for the fixed Rx latency. Since the
2155 * latency measurement is in 1/100th of a nanosecond, we need to
2156 * multiply by tu_per_sec and then divide by 1e11. This calculation
2157 * overflows 64 bit integer arithmetic, so break it up into two
2158 * divisions by 1e4 first then by 1e7.
2160 fixed_offset = DIV_64BIT(tu_per_sec, 10000);
2161 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay;
2162 fixed_offset = DIV_64BIT(fixed_offset, 10000000);
2164 return fixed_offset;
2168 * ice_phy_cfg_rx_offset_e822 - Configure total Rx timestamp offset
2169 * @hw: pointer to the HW struct
2170 * @port: the PHY port to configure
2172 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to
2173 * adjust Rx timestamps by. This combines calculations from the Vernier offset
2174 * measurements taken in hardware with some data about known fixed delay as
2175 * well as adjusting for multi-lane alignment delay.
2177 * This function must be called only after the offset registers are valid,
2178 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
2179 * has measured the offset.
2181 * To avoid overflow, when calculating the offset based on the known static
2182 * latency values, we use measurements in 1/100th of a nanosecond, and divide
2183 * the TUs per second up front. This avoids overflow while allowing
2184 * calculation of the adjustment using integer arithmetic.
2186 enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)
2188 enum ice_ptp_link_spd link_spd;
2189 enum ice_ptp_fec_mode fec_mode;
2190 u64 total_offset, pmd, val;
2191 enum ice_status status;
2193 status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
2197 total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
2199 /* Read the first Vernier offset from the PHY register and add it to
2202 status = ice_read_64b_phy_reg_e822(hw, port,
2203 P_REG_PAR_PCS_RX_OFFSET_L,
2208 total_offset += val;
2210 /* For Rx, all multi-lane link speeds include a second Vernier
2211 * calibration, because the lanes might not be aligned.
2213 if (link_spd == ICE_PTP_LNK_SPD_40G ||
2214 link_spd == ICE_PTP_LNK_SPD_50G ||
2215 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
2216 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
2217 status = ice_read_64b_phy_reg_e822(hw, port,
2218 P_REG_PAR_RX_TIME_L,
2223 total_offset += val;
2226 /* In addition, Rx must account for the PMD alignment */
2227 status = ice_phy_calc_pmd_adj_e822(hw, port, link_spd, fec_mode, &pmd);
2231 /* For RS-FEC, this adjustment adds delay, but for other modes, it
2234 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC)
2235 total_offset += pmd;
2237 total_offset -= pmd;
2239 /* Now that the total offset has been calculated, program it to the
2240 * PHY and indicate that the Rx offset is ready. After this,
2241 * timestamps will be enabled.
2243 status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
2248 status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
2256 * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode
2257 * @hw: pointer to the HW struct
2258 * @port: the PHY port to configure
2260 * Calculate and program the fixed Rx offset, and indicate that the offset is
2261 * ready. This can be used when operating in bypass mode.
2263 static enum ice_status
2264 ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port)
2266 enum ice_ptp_link_spd link_spd;
2267 enum ice_ptp_fec_mode fec_mode;
2268 enum ice_status status;
2271 status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
2275 total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
2277 /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L
2278 * register, then indicate that the Rx offset is ready. After this,
2279 * timestamps will be enabled.
2281 * Note that this skips including the more precise offsets generated
2282 * by Vernier calibration.
2284 status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
2289 status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
2297 * ice_read_phy_and_phc_time_e822 - Simultaneously capture PHC and PHY time
2298 * @hw: pointer to the HW struct
2299 * @port: the PHY port to read
2300 * @phy_time: on return, the 64bit PHY timer value
2301 * @phc_time: on return, the lower 64bits of PHC time
2303 * Issue a READ_TIME timer command to simultaneously capture the PHY and PHC
2306 static enum ice_status
2307 ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,
2310 enum ice_status status;
2311 u64 tx_time, rx_time;
2315 tmr_idx = ice_get_ptp_src_clock_index(hw);
2317 /* Prepare the PHC timer for a READ_TIME capture command */
2318 ice_ptp_src_cmd(hw, READ_TIME);
2320 /* Prepare the PHY timer for a READ_TIME capture command */
2321 status = ice_ptp_one_port_cmd(hw, port, READ_TIME, true);
2325 /* Issue the sync to start the READ_TIME capture */
2326 ice_ptp_exec_tmr_cmd(hw);
2328 /* Read the captured PHC time from the shadow time registers */
2329 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
2330 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
2331 *phc_time = (u64)lo << 32 | zo;
2333 /* Read the captured PHY time from the PHY shadow registers */
2334 status = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time);
2338 /* If the PHY Tx and Rx timers don't match, log a warning message.
2339 * Note that this should not happen in normal circumstances since the
2340 * driver always programs them together.
2342 if (tx_time != rx_time)
2343 ice_warn(hw, "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
2344 port, (unsigned long long)tx_time,
2345 (unsigned long long)rx_time);
2347 *phy_time = tx_time;
2353 * ice_sync_phy_timer_e822 - Synchronize the PHY timer with PHC timer
2354 * @hw: pointer to the HW struct
2355 * @port: the PHY port to synchronize
2357 * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
2358 * This is done by issuing a READ_TIME command which triggers a simultaneous
2359 * read of the PHY timer and PHC timer. Then we use the difference to
2360 * calculate an appropriate 2s complement addition to add to the PHY timer in
2361 * order to ensure it reads the same value as the primary PHC timer.
2363 static enum ice_status ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
2365 u64 phc_time, phy_time, difference;
2366 enum ice_status status;
2368 if (!ice_ptp_lock(hw)) {
2369 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
2370 return ICE_ERR_NOT_READY;
2373 status = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);
2377 /* Calculate the amount required to add to the port time in order for
2378 * it to match the PHC time.
2380 * Note that the port adjustment is done using 2s complement
2381 * arithmetic. This is convenient since it means that we can simply
2382 * calculate the difference between the PHC time and the port time,
2383 * and it will be interpreted correctly.
2385 difference = phc_time - phy_time;
2387 status = ice_ptp_prep_port_adj_e822(hw, port, (s64)difference, true);
2391 status = ice_ptp_one_port_cmd(hw, port, ADJ_TIME, true);
2395 /* Issue the sync to activate the time adjustment */
2396 ice_ptp_exec_tmr_cmd(hw);
2398 /* Re-capture the timer values to flush the command registers and
2399 * verify that the time was properly adjusted.
2401 status = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);
2405 ice_info(hw, "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
2406 port, (unsigned long long)phy_time,
2407 (unsigned long long)phc_time);
2419 * ice_stop_phy_timer_e822 - Stop the PHY clock timer
2420 * @hw: pointer to the HW struct
2421 * @port: the PHY port to stop
2422 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS
2424 * Stop the clock of a PHY port. This must be done as part of the flow to
2425 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2426 * initialized or when link speed changes.
2429 ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)
2431 enum ice_status status;
2434 status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0);
2438 status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0);
2442 status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
2446 val &= ~P_REG_PS_START_M;
2447 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2451 val &= ~P_REG_PS_ENA_CLK_M;
2452 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2457 val |= P_REG_PS_SFT_RESET_M;
2458 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2463 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
2469 * ice_start_phy_timer_e822 - Start the PHY clock timer
2470 * @hw: pointer to the HW struct
2471 * @port: the PHY port to start
2472 * @bypass: if true, start the PHY in bypass mode
2474 * Start the clock of a PHY port. This must be done as part of the flow to
2475 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2476 * initialized or when link speed changes.
2478 * Bypass mode enables timestamps immediately without waiting for Vernier
2479 * calibration to complete. Hardware will still continue taking Vernier
2480 * measurements on Tx or Rx of packets, but they will not be applied to
2481 * timestamps. Use ice_phy_exit_bypass_e822 to exit bypass mode once hardware
2482 * has completed offset calculation.
2485 ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
2487 enum ice_status status;
2492 tmr_idx = ice_get_ptp_src_clock_index(hw);
2494 status = ice_stop_phy_timer_e822(hw, port, false);
2498 ice_phy_cfg_lane_e822(hw, port);
2500 status = ice_phy_cfg_uix_e822(hw, port);
2504 status = ice_phy_cfg_parpcs_e822(hw, port);
2508 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
2509 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
2510 incval = (u64)hi << 32 | lo;
2512 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval);
2516 status = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL, true);
2520 ice_ptp_exec_tmr_cmd(hw);
2522 status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
2526 val |= P_REG_PS_SFT_RESET_M;
2527 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2531 val |= P_REG_PS_START_M;
2532 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2536 val &= ~P_REG_PS_SFT_RESET_M;
2537 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2541 status = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL, true);
2545 ice_ptp_exec_tmr_cmd(hw);
2547 val |= P_REG_PS_ENA_CLK_M;
2548 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2552 val |= P_REG_PS_LOAD_OFFSET_M;
2553 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2557 ice_ptp_exec_tmr_cmd(hw);
2559 status = ice_sync_phy_timer_e822(hw, port);
2564 val |= P_REG_PS_BYPASS_MODE_M;
2565 /* Enter BYPASS mode, enabling timestamps immediately. */
2566 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2570 /* Program the fixed Tx offset */
2571 status = ice_phy_cfg_fixed_tx_offset_e822(hw, port);
2575 /* Program the fixed Rx offset */
2576 status = ice_phy_cfg_fixed_rx_offset_e822(hw, port);
2581 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
2587 * ice_phy_exit_bypass_e822 - Exit bypass mode, after vernier calculations
2588 * @hw: pointer to the HW struct
2589 * @port: the PHY port to configure
2591 * After hardware finishes vernier calculations for the Tx and Rx offset, this
2592 * function can be used to exit bypass mode by updating the total Tx and Rx
2593 * offsets, and then disabling bypass. This will enable hardware to include
2594 * the more precise offset calibrations, increasing precision of the generated
2597 * This cannot be done until hardware has measured the offsets, which requires
2598 * waiting until at least one packet has been sent and received by the device.
2600 enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port)
2602 enum ice_status status;
2605 status = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, &val);
2607 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, status %d\n",
2612 if (!(val & P_REG_TX_OV_STATUS_OV_M)) {
2613 ice_debug(hw, ICE_DBG_PTP, "Tx offset is not yet valid for port %u\n",
2615 return ICE_ERR_NOT_READY;
2618 status = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, &val);
2620 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, status %d\n",
2625 if (!(val & P_REG_TX_OV_STATUS_OV_M)) {
2626 ice_debug(hw, ICE_DBG_PTP, "Rx offset is not yet valid for port %u\n",
2628 return ICE_ERR_NOT_READY;
2631 status = ice_phy_cfg_tx_offset_e822(hw, port);
2633 ice_debug(hw, ICE_DBG_PTP, "Failed to program total Tx offset for port %u, status %d\n",
2638 status = ice_phy_cfg_rx_offset_e822(hw, port);
2640 ice_debug(hw, ICE_DBG_PTP, "Failed to program total Rx offset for port %u, status %d\n",
2645 /* Exit bypass mode now that the offset has been updated */
2646 status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
2648 ice_debug(hw, ICE_DBG_PTP, "Failed to read P_REG_PS for port %u, status %d\n",
2653 if (!(val & P_REG_PS_BYPASS_MODE_M))
2654 ice_debug(hw, ICE_DBG_PTP, "Port %u not in bypass mode\n",
2657 val &= ~P_REG_PS_BYPASS_MODE_M;
2658 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2660 ice_debug(hw, ICE_DBG_PTP, "Failed to disable bypass for port %u, status %d\n",
2665 ice_info(hw, "Exiting bypass mode on PHY port %u\n", port);
2672 * The following functions operate on the E810 series devices which use
2673 * a separate external PHY.
2677 * ice_read_phy_reg_e810_lp - Read register from external PHY on E810
2678 * @hw: pointer to the HW struct
2679 * @addr: the address to read from
2680 * @val: On return, the value read from the PHY
2681 * @lock_sbq: true if the sideband queue lock must be acquired
2683 * Read a register from the external PHY on the E810 device.
2685 static enum ice_status
2686 ice_read_phy_reg_e810_lp(struct ice_hw *hw, u32 addr, u32 *val, bool lock_sbq)
2688 struct ice_sbq_msg_input msg = {0};
2689 enum ice_status status;
2691 msg.msg_addr_low = ICE_LO_WORD(addr);
2692 msg.msg_addr_high = ICE_HI_WORD(addr);
2693 msg.opcode = ice_sbq_msg_rd;
2694 msg.dest_dev = rmn_0;
2696 status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
2698 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
2708 static enum ice_status
2709 ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)
2711 return ice_read_phy_reg_e810_lp(hw, addr, val, true);
2715 * ice_write_phy_reg_e810_lp - Write register on external PHY on E810
2716 * @hw: pointer to the HW struct
2717 * @addr: the address to writem to
2718 * @val: the value to write to the PHY
2719 * @lock_sbq: true if the sideband queue lock must be acquired
2721 * Write a value to a register of the external PHY on the E810 device.
2723 static enum ice_status
2724 ice_write_phy_reg_e810_lp(struct ice_hw *hw, u32 addr, u32 val, bool lock_sbq)
2726 struct ice_sbq_msg_input msg = {0};
2727 enum ice_status status;
2729 msg.msg_addr_low = ICE_LO_WORD(addr);
2730 msg.msg_addr_high = ICE_HI_WORD(addr);
2731 msg.opcode = ice_sbq_msg_wr;
2732 msg.dest_dev = rmn_0;
2735 status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
2737 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
2745 static enum ice_status
2746 ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val)
2748 return ice_write_phy_reg_e810_lp(hw, addr, val, true);
2752 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY
2753 * @hw: pointer to the HW struct
2754 * @lport: the lport to read from
2755 * @idx: the timestamp index to read
2756 * @tstamp: on return, the 40bit timestamp value
2758 * Read a 40bit timestamp value out of the timestamp block of the external PHY
2759 * on the E810 device.
2761 static enum ice_status
2762 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
2764 enum ice_status status;
2765 u32 lo_addr, hi_addr, lo, hi;
2767 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
2768 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
2770 status = ice_read_phy_reg_e810(hw, lo_addr, &lo);
2772 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n",
2777 status = ice_read_phy_reg_e810(hw, hi_addr, &hi);
2779 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n",
2784 /* For E810 devices, the timestamp is reported with the lower 32 bits
2785 * in the low register, and the upper 8 bits in the high register.
2787 *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M);
2793 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY
2794 * @hw: pointer to the HW struct
2795 * @lport: the lport to read from
2796 * @idx: the timestamp index to reset
2798 * Clear a timestamp, resetting its valid bit, from the timestamp block of the
2799 * external PHY on the E810 device.
2801 static enum ice_status
2802 ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx)
2804 enum ice_status status;
2805 u32 lo_addr, hi_addr;
2807 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
2808 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
2810 status = ice_write_phy_reg_e810(hw, lo_addr, 0);
2812 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n",
2817 status = ice_write_phy_reg_e810(hw, hi_addr, 0);
2819 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n",
2828 * ice_ptp_init_phy_e810 - Enable PTP function on the external PHY
2829 * @hw: pointer to HW struct
2831 * Enable the timesync PTP functionality for the external PHY connected to
2834 * Note there is no equivalent function needed on E822 based devices.
2836 enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw)
2838 enum ice_status status;
2841 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2842 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx),
2843 GLTSYN_ENA_TSYN_ENA_M);
2845 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n",
2852 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
2853 * @hw: pointer to HW struct
2855 * Perform E810-specific PTP hardware clock initialization steps.
2857 static enum ice_status ice_ptp_init_phc_e810(struct ice_hw *hw)
2859 /* Ensure synchronization delay is zero */
2860 wr32(hw, GLTSYN_SYNC_DLAY, 0);
2862 /* Initialize the PHY */
2863 return ice_ptp_init_phy_e810(hw);
2867 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
2868 * @hw: Board private structure
2869 * @time: Time to initialize the PHY port clock to
2871 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the
2872 * initial clock time. The time will not actually be programmed until the
2873 * driver issues an INIT_TIME command.
2875 * The time value is the upper 32 bits of the PHY timer, usually in units of
2876 * nominal nanoseconds.
2878 static enum ice_status ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time)
2880 enum ice_status status;
2883 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2884 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
2886 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, status %d\n",
2891 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time);
2893 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, status %d\n",
2902 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment
2903 * @hw: pointer to HW struct
2904 * @adj: adjustment value to program
2905 * @lock_sbq: true if the sideband queue luck must be acquired
2907 * Prepare the PHY port for an atomic adjustment by programming the PHY
2908 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment
2909 * is completed by issuing an ADJ_TIME sync command.
2911 * The adjustment value only contains the portion used for the upper 32bits of
2912 * the PHY timer, usually in units of nominal nanoseconds. Negative
2913 * adjustments are supported using 2s complement arithmetic.
2915 static enum ice_status
2916 ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj, bool lock_sbq)
2918 enum ice_status status;
2921 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2923 /* Adjustments are represented as signed 2's complement values in
2924 * nanoseconds. Sub-nanosecond adjustment is not supported.
2926 status = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_SHADJ_L(tmr_idx),
2929 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, status %d\n",
2934 status = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_SHADJ_H(tmr_idx),
2937 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, status %d\n",
2946 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change
2947 * @hw: pointer to HW struct
2948 * @incval: The new 40bit increment value to prepare
2950 * Prepare the PHY port for a new increment value by programming the PHY
2951 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is
2952 * completed by issuing an INIT_INCVAL command.
2954 static enum ice_status
2955 ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
2957 enum ice_status status;
2961 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2962 low = ICE_LO_DWORD(incval);
2963 high = ICE_HI_DWORD(incval);
2965 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low);
2967 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, status %d\n",
2972 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high);
2974 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, status %d\n",
2983 * ice_ptp_prep_phy_adj_target_e810 - Prepare PHY port with adjust target
2984 * @hw: Board private structure
2985 * @target_time: Time to trigger the clock adjustment at
2987 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation for
2988 * a target time adjust, which will trigger an adjustment of the clock in the
2989 * future. The actual adjustment will occur the next time the PHY port timer
2990 * crosses over the provided value after the driver issues an ADJ_TIME_AT_TIME
2993 * The time value is the upper 32 bits of the PHY timer, usually in units of
2994 * nominal nanoseconds.
2996 static enum ice_status
2997 ice_ptp_prep_phy_adj_target_e810(struct ice_hw *hw, u32 target_time)
2999 enum ice_status status;
3002 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3003 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
3005 ice_debug(hw, ICE_DBG_PTP, "Failed to write target time to SHTIME_0, status %d\n",
3010 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx),
3013 ice_debug(hw, ICE_DBG_PTP, "Failed to write target time to SHTIME_L, status %d\n",
3022 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command
3023 * @hw: pointer to HW struct
3024 * @cmd: Command to be sent to the port
3025 * @lock_sbq: true if the sideband queue lock must be acquired
3027 * Prepare the external PHYs connected to this device for a timer sync
3030 static enum ice_status
3031 ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
3034 enum ice_status status;
3039 cmd_val = GLTSYN_CMD_INIT_TIME;
3042 cmd_val = GLTSYN_CMD_INIT_INCVAL;
3045 cmd_val = GLTSYN_CMD_ADJ_TIME;
3047 case ADJ_TIME_AT_TIME:
3048 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
3051 cmd_val = GLTSYN_CMD_READ_TIME;
3054 ice_warn(hw, "Unknown timer command %u\n", cmd);
3055 return ICE_ERR_PARAM;
3058 /* Read, modify, write */
3059 status = ice_read_phy_reg_e810_lp(hw, ETH_GLTSYN_CMD, &val, lock_sbq);
3061 ice_debug(hw, ICE_DBG_PTP, "Failed to read GLTSYN_CMD, status %d\n",
3066 /* Modify necessary bits only and perform write */
3067 val &= ~TS_CMD_MASK_E810;
3070 status = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_CMD, val, lock_sbq);
3072 ice_debug(hw, ICE_DBG_PTP, "Failed to write back GLTSYN_CMD, status %d\n",
3080 /* E810T SMA functions
3082 * The following functions operate specifically on E810T hardware and are used
3083 * to access the extended GPIOs available.
3087 * ice_get_pca9575_handle
3088 * @hw: pointer to the hw struct
3089 * @pca9575_handle: GPIO controller's handle
3091 * Find and return the GPIO controller's handle in the netlist.
3092 * When found - the value will be cached in the hw structure and following calls
3093 * will return cached value
3095 static enum ice_status
3096 ice_get_pca9575_handle(struct ice_hw *hw, __le16 *pca9575_handle)
3098 struct ice_aqc_get_link_topo *cmd;
3099 struct ice_aq_desc desc;
3100 enum ice_status status;
3103 if (!hw || !pca9575_handle)
3104 return ICE_ERR_PARAM;
3106 /* If handle was read previously return cached value */
3107 if (hw->io_expander_handle) {
3108 *pca9575_handle = hw->io_expander_handle;
3112 /* If handle was not detected read it from the netlist */
3113 cmd = &desc.params.get_link_topo;
3114 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
3116 /* Set node type to GPIO controller */
3117 cmd->addr.topo_params.node_type_ctx =
3118 (ICE_AQC_LINK_TOPO_NODE_TYPE_M &
3119 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL);
3121 #define SW_PCA9575_SFP_TOPO_IDX 2
3122 #define SW_PCA9575_QSFP_TOPO_IDX 1
3124 /* Check if the SW IO expander controlling SMA exists in the netlist. */
3125 if (hw->device_id == ICE_DEV_ID_E810C_SFP)
3126 idx = SW_PCA9575_SFP_TOPO_IDX;
3127 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP)
3128 idx = SW_PCA9575_QSFP_TOPO_IDX;
3130 return ICE_ERR_NOT_SUPPORTED;
3132 cmd->addr.topo_params.index = idx;
3134 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
3136 return ICE_ERR_NOT_SUPPORTED;
3138 /* Verify if we found the right IO expander type */
3139 if (desc.params.get_link_topo.node_part_num !=
3140 ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575)
3141 return ICE_ERR_NOT_SUPPORTED;
3143 /* If present save the handle and return it */
3144 hw->io_expander_handle = desc.params.get_link_topo.addr.handle;
3145 *pca9575_handle = hw->io_expander_handle;
3151 * ice_read_e810t_pca9575_reg
3152 * @hw: pointer to the hw struct
3153 * @offset: GPIO controller register offset
3154 * @data: pointer to data to be read from the GPIO controller
3156 * Read the register from the GPIO controller
3159 ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data)
3161 struct ice_aqc_link_topo_addr link_topo;
3162 enum ice_status status;
3165 memset(&link_topo, 0, sizeof(link_topo));
3167 status = ice_get_pca9575_handle(hw, &link_topo.handle);
3171 link_topo.topo_params.node_type_ctx =
3172 (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<
3173 ICE_AQC_LINK_TOPO_NODE_CTX_S);
3175 addr = CPU_TO_LE16((u16)offset);
3177 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL);
3181 * ice_write_e810t_pca9575_reg
3182 * @hw: pointer to the hw struct
3183 * @offset: GPIO controller register offset
3184 * @data: data to be written to the GPIO controller
3186 * Write the data to the GPIO controller register
3189 ice_write_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 data)
3191 struct ice_aqc_link_topo_addr link_topo;
3192 enum ice_status status;
3195 memset(&link_topo, 0, sizeof(link_topo));
3197 status = ice_get_pca9575_handle(hw, &link_topo.handle);
3201 link_topo.topo_params.node_type_ctx =
3202 (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<
3203 ICE_AQC_LINK_TOPO_NODE_CTX_S);
3205 addr = CPU_TO_LE16((u16)offset);
3207 return ice_aq_write_i2c(hw, link_topo, 0, addr, 1, &data, NULL);
3211 * ice_read_sma_ctrl_e810t
3212 * @hw: pointer to the hw struct
3213 * @data: pointer to data to be read from the GPIO controller
3215 * Read the SMA controller state. Only bits 3-7 in data are valid.
3217 enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data)
3219 enum ice_status status;
3223 status = ice_get_pca9575_handle(hw, &handle);
3229 for (i = ICE_E810T_SMA_MIN_BIT; i <= ICE_E810T_SMA_MAX_BIT; i++) {
3232 status = ice_aq_get_gpio(hw, handle, i + ICE_E810T_P1_OFFSET,
3236 *data |= (u8)(!pin) << i;
3243 * ice_write_sma_ctrl_e810t
3244 * @hw: pointer to the hw struct
3245 * @data: data to be written to the GPIO controller
3247 * Write the data to the SMA controller. Only bits 3-7 in data are valid.
3249 enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data)
3251 enum ice_status status;
3255 status = ice_get_pca9575_handle(hw, &handle);
3259 for (i = ICE_E810T_SMA_MIN_BIT; i <= ICE_E810T_SMA_MAX_BIT; i++) {
3262 pin = !(data & (1 << i));
3263 status = ice_aq_set_gpio(hw, handle, i + ICE_E810T_P1_OFFSET,
3273 * ice_e810t_is_pca9575_present
3274 * @hw: pointer to the hw struct
3276 * Check if the SW IO expander is present in the netlist
3278 bool ice_e810t_is_pca9575_present(struct ice_hw *hw)
3280 enum ice_status status;
3283 if (!ice_is_e810t(hw))
3286 status = ice_get_pca9575_handle(hw, &handle);
3287 if (!status && handle)
3293 /* Device agnostic functions
3295 * The following functions implement shared behavior common to both E822 and
3296 * E810 devices, possibly calling a device specific implementation where
3301 * ice_ptp_lock - Acquire PTP global semaphore register lock
3302 * @hw: pointer to the HW struct
3304 * Acquire the global PTP hardware semaphore lock. Returns true if the lock
3305 * was acquired, false otherwise.
3307 * The PFTSYN_SEM register sets the busy bit on read, returning the previous
3308 * value. If software sees the busy bit cleared, this means that this function
3309 * acquired the lock (and the busy bit is now set). If software sees the busy
3310 * bit set, it means that another function acquired the lock.
3312 * Software must clear the busy bit with a write to release the lock for other
3313 * functions when done.
3315 bool ice_ptp_lock(struct ice_hw *hw)
3322 for (i = 0; i < MAX_TRIES; i++) {
3323 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
3324 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M;
3326 /* Somebody is holding the lock */
3327 ice_msec_delay(10, true);
3338 * ice_ptp_unlock - Release PTP global semaphore register lock
3339 * @hw: pointer to the HW struct
3341 * Release the global PTP hardware semaphore lock. This is done by writing to
3342 * the PFTSYN_SEM register.
3344 void ice_ptp_unlock(struct ice_hw *hw)
3346 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);
3350 * ice_ptp_src_cmd - Prepare source timer for a timer command
3351 * @hw: pointer to HW structure
3352 * @cmd: Timer command
3354 * Prepare the source timer for an upcoming timer sync command.
3356 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
3361 tmr_idx = ice_get_ptp_src_clock_index(hw);
3362 cmd_val = tmr_idx << SEL_CPK_SRC;
3366 cmd_val |= GLTSYN_CMD_INIT_TIME;
3369 cmd_val |= GLTSYN_CMD_INIT_INCVAL;
3372 cmd_val |= GLTSYN_CMD_ADJ_TIME;
3374 case ADJ_TIME_AT_TIME:
3375 cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME;
3378 cmd_val |= GLTSYN_CMD_READ_TIME;
3381 ice_warn(hw, "Unknown timer command %u\n", cmd);
3385 wr32(hw, GLTSYN_CMD, cmd_val);
3389 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
3390 * @hw: pointer to HW struct
3391 * @cmd: the command to issue
3392 * @lock_sbq: true if the sideband queue lock must be acquired
3394 * Prepare the source timer and PHY timers and then trigger the requested
3395 * command. This causes the shadow registers previously written in preparation
3396 * for the command to be synchronously applied to both the source and PHY
3399 static enum ice_status
3400 ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
3402 enum ice_status status;
3404 /* First, prepare the source timer */
3405 ice_ptp_src_cmd(hw, cmd);
3407 /* Next, prepare the ports */
3408 if (ice_is_e810(hw))
3409 status = ice_ptp_port_cmd_e810(hw, cmd, lock_sbq);
3411 status = ice_ptp_port_cmd_e822(hw, cmd, lock_sbq);
3413 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, status %d\n",
3418 /* Write the sync command register to drive both source and PHY timer
3419 * commands synchronously
3421 ice_ptp_exec_tmr_cmd(hw);
3427 * ice_ptp_init_time - Initialize device time to provided value
3428 * @hw: pointer to HW struct
3429 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H)
3431 * Initialize the device to the specified time provided. This requires a three
3434 * 1) write the new init time to the source timer shadow registers
3435 * 2) write the new init time to the phy timer shadow registers
3436 * 3) issue an init_time timer command to synchronously switch both the source
3437 * and port timers to the new init time value at the next clock cycle.
3439 enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)
3441 enum ice_status status;
3444 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3447 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time));
3448 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time));
3449 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
3452 /* Fill Rx and Tx ports and send msg to PHY */
3453 if (ice_is_e810(hw))
3454 status = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
3456 status = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF);
3460 return ice_ptp_tmr_cmd(hw, INIT_TIME, true);
3464 * ice_ptp_write_incval - Program PHC with new increment value
3465 * @hw: pointer to HW struct
3466 * @incval: Source timer increment value per clock cycle
3468 * Program the PHC with a new increment value. This requires a three-step
3471 * 1) Write the increment value to the source timer shadow registers
3472 * 2) Write the increment value to the PHY timer shadow registers
3473 * 3) Issue an INIT_INCVAL timer command to synchronously switch both the
3474 * source and port timers to the new increment value at the next clock
3477 enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
3479 enum ice_status status;
3482 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3485 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval));
3486 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval));
3488 if (ice_is_e810(hw))
3489 status = ice_ptp_prep_phy_incval_e810(hw, incval);
3491 status = ice_ptp_prep_phy_incval_e822(hw, incval);
3495 return ice_ptp_tmr_cmd(hw, INIT_INCVAL, true);
3499 * ice_ptp_write_incval_locked - Program new incval while holding semaphore
3500 * @hw: pointer to HW struct
3501 * @incval: Source timer increment value per clock cycle
3503 * Program a new PHC incval while holding the PTP semaphore.
3505 enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)
3507 enum ice_status status;
3509 if (!ice_ptp_lock(hw))
3510 return ICE_ERR_NOT_READY;
3512 status = ice_ptp_write_incval(hw, incval);
3520 * ice_ptp_adj_clock - Adjust PHC clock time atomically
3521 * @hw: pointer to HW struct
3522 * @adj: Adjustment in nanoseconds
3523 * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
3524 * sq_lock has already been locked at a higher level
3526 * Perform an atomic adjustment of the PHC time by the specified number of
3527 * nanoseconds. This requires a three-step process:
3529 * 1) Write the adjustment to the source timer shadow registers
3530 * 2) Write the adjustment to the PHY timer shadow registers
3531 * 3) Issue an ADJ_TIME timer command to synchronously apply the adjustment to
3532 * both the source and port timers at the next clock cycle.
3534 enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)
3536 enum ice_status status;
3539 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3541 /* Write the desired clock adjustment into the GLTSYN_SHADJ register.
3542 * For an ADJ_TIME command, this set of registers represents the value
3543 * to add to the clock time. It supports subtraction by interpreting
3544 * the value as a 2's complement integer.
3546 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
3547 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
3549 if (ice_is_e810(hw))
3550 status = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq);
3552 status = ice_ptp_prep_phy_adj_e822(hw, adj, lock_sbq);
3556 return ice_ptp_tmr_cmd(hw, ADJ_TIME, lock_sbq);
3560 * ice_ptp_adj_clock_at_time - Adjust PHC atomically at specified time
3561 * @hw: pointer to HW struct
3562 * @at_time: Time in nanoseconds at which to perform the adjustment
3563 * @adj: Adjustment in nanoseconds
3565 * Perform an atomic adjustment to the PHC clock at the specified time. This
3566 * requires a five-step process:
3568 * 1) Write the adjustment to the source timer shadow adjust registers
3569 * 2) Write the target time to the source timer shadow time registers
3570 * 3) Write the adjustment to the PHY timers shadow adjust registers
3571 * 4) Write the target time to the PHY timers shadow adjust registers
3572 * 5) Issue an ADJ_TIME_AT_TIME command to initiate the atomic adjustment.
3575 ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)
3577 enum ice_status status;
3578 u32 time_lo, time_hi;
3581 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3582 time_lo = ICE_LO_DWORD(at_time);
3583 time_hi = ICE_HI_DWORD(at_time);
3585 /* Write the desired clock adjustment into the GLTSYN_SHADJ register.
3586 * For an ADJ_TIME_AT_TIME command, this set of registers represents
3587 * the value to add to the clock time. It supports subtraction by
3588 * interpreting the value as a 2's complement integer.
3590 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
3591 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
3593 /* Write the target time to trigger the adjustment for source clock */
3594 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
3595 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), time_lo);
3596 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), time_hi);
3598 /* Prepare PHY port adjustments */
3599 if (ice_is_e810(hw))
3600 status = ice_ptp_prep_phy_adj_e810(hw, adj, true);
3602 status = ice_ptp_prep_phy_adj_e822(hw, adj, true);
3606 /* Set target time for each PHY port */
3607 if (ice_is_e810(hw))
3608 status = ice_ptp_prep_phy_adj_target_e810(hw, time_lo);
3610 status = ice_ptp_prep_phy_adj_target_e822(hw, time_lo);
3614 return ice_ptp_tmr_cmd(hw, ADJ_TIME_AT_TIME, true);
3618 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block
3619 * @hw: pointer to the HW struct
3620 * @block: the block to read from
3621 * @idx: the timestamp index to read
3622 * @tstamp: on return, the 40bit timestamp value
3624 * Read a 40bit timestamp value out of the timestamp block. For E822 devices,
3625 * the block is the quad to read from. For E810 devices, the block is the
3626 * logical port to read from.
3629 ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
3631 if (ice_is_e810(hw))
3632 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
3634 return ice_read_phy_tstamp_e822(hw, block, idx, tstamp);
3638 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block
3639 * @hw: pointer to the HW struct
3640 * @block: the block to read from
3641 * @idx: the timestamp index to reset
3643 * Clear a timestamp, resetting its valid bit, from the timestamp block. For
3644 * E822 devices, the block is the quad to clear from. For E810 devices, the
3645 * block is the logical port to clear from.
3648 ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
3650 if (ice_is_e810(hw))
3651 return ice_clear_phy_tstamp_e810(hw, block, idx);
3653 return ice_clear_phy_tstamp_e822(hw, block, idx);
3657 * ice_ptp_init_phc - Initialize PTP hardware clock
3658 * @hw: pointer to the HW struct
3660 * Perform the steps required to initialize the PTP hardware clock.
3662 enum ice_status ice_ptp_init_phc(struct ice_hw *hw)
3664 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3666 /* Enable source clocks */
3667 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);
3669 /* Clear event status indications for auxiliary pins */
3670 (void)rd32(hw, GLTSYN_STAT(src_idx));
3672 if (ice_is_e810(hw))
3673 return ice_ptp_init_phc_e810(hw);
3675 return ice_ptp_init_phc_e822(hw);