1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
6 #include "ice_common.h"
7 #include "ice_ptp_hw.h"
8 #include "ice_ptp_consts.h"
9 #include "ice_cgu_regs.h"
11 /* Low level functions for interacting with and managing the device clock used
12 * for the Precision Time Protocol.
14 * The ice hardware represents the current time using three registers:
16 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R
17 * +---------------+ +---------------+ +---------------+
18 * | 32 bits | | 32 bits | | 32 bits |
19 * +---------------+ +---------------+ +---------------+
21 * The registers are incremented every clock tick using a 40bit increment
22 * value defined over two registers:
24 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L
25 * +---------------+ +---------------+
26 * | 8 bit s | | 32 bits |
27 * +---------------+ +---------------+
29 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L
30 * registers every clock source tick. Depending on the specific device
31 * configuration, the clock source frequency could be one of a number of
34 * For E810 devices, the increment frequency is 812.5 MHz
36 * For E822 devices the clock can be derived from different sources, and the
37 * increment has an effective frequency of one of the following:
45 * The hardware captures timestamps in the PHY for incoming packets, and for
46 * outgoing packets on request. To support this, the PHY maintains a timer
47 * that matches the lower 64 bits of the global source timer.
49 * In order to ensure that the PHY timers and the source timer are equivalent,
50 * shadow registers are used to prepare the desired initial values. A special
51 * sync command is issued to trigger copying from the shadow registers into
52 * the appropriate source and PHY registers simultaneously.
54 * The driver supports devices which have different PHYs with subtly different
55 * mechanisms to program and control the timers. We divide the devices into
56 * families named after the first major device, E810 and similar devices, and
57 * E822 and similar devices.
59 * - E822 based devices have additional support for fine grained Vernier
60 * calibration which requires significant setup
61 * - The layout of timestamp data in the PHY register blocks is different
62 * - The way timer synchronization commands are issued is different.
64 * To support this, very low level functions have an e810 or e822 suffix
65 * indicating what type of device they work on. Higher level abstractions for
66 * tasks that can be done on both devices do not have the suffix and will
67 * correctly look up the appropriate low level function when running.
69 * Functions which only make sense on a single device family may not have
70 * a suitable generic implementation
74 * ice_get_ptp_src_clock_index - determine source clock index
75 * @hw: pointer to HW struct
77 * Determine the source clock index currently in use, based on device
78 * capabilities reported during initialization.
80 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw)
82 return hw->func_caps.ts_func_info.tmr_index_assoc;
86 * ice_ptp_read_src_incval - Read source timer increment value
87 * @hw: pointer to HW struct
89 * Read the increment value of the source timer and return it.
91 u64 ice_ptp_read_src_incval(struct ice_hw *hw)
96 tmr_idx = ice_get_ptp_src_clock_index(hw);
98 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
99 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
101 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
105 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
106 * @hw: pointer to HW struct
108 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the
109 * write immediately. This triggers the hardware to begin executing all of the
110 * source and PHY timer commands synchronously.
112 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
114 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD);
118 /* E822 family functions
120 * The following functions operate on the E822 family of devices.
124 * ice_fill_phy_msg_e822 - Fill message data for a PHY register access
125 * @msg: the PHY message buffer to fill in
126 * @port: the port to access
127 * @offset: the register offset
130 ice_fill_phy_msg_e822(struct ice_sbq_msg_input *msg, u8 port, u16 offset)
132 int phy_port, phy, quadtype;
134 phy_port = port % ICE_PORTS_PER_PHY;
135 phy = port / ICE_PORTS_PER_PHY;
136 quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_NUM_QUAD_TYPE;
139 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port);
140 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port);
142 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port);
143 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port);
147 msg->dest_dev = rmn_0;
149 msg->dest_dev = rmn_1;
151 msg->dest_dev = rmn_2;
155 * ice_is_64b_phy_reg_e822 - Check if this is a 64bit PHY register
156 * @low_addr: the low address to check
157 * @high_addr: on return, contains the high address of the 64bit register
159 * Checks if the provided low address is one of the known 64bit PHY values
160 * represented as two 32bit registers. If it is, return the appropriate high
161 * register offset to use.
163 static bool ice_is_64b_phy_reg_e822(u16 low_addr, u16 *high_addr)
166 case P_REG_PAR_PCS_TX_OFFSET_L:
167 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U;
169 case P_REG_PAR_PCS_RX_OFFSET_L:
170 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U;
172 case P_REG_PAR_TX_TIME_L:
173 *high_addr = P_REG_PAR_TX_TIME_U;
175 case P_REG_PAR_RX_TIME_L:
176 *high_addr = P_REG_PAR_RX_TIME_U;
178 case P_REG_TOTAL_TX_OFFSET_L:
179 *high_addr = P_REG_TOTAL_TX_OFFSET_U;
181 case P_REG_TOTAL_RX_OFFSET_L:
182 *high_addr = P_REG_TOTAL_RX_OFFSET_U;
184 case P_REG_UIX66_10G_40G_L:
185 *high_addr = P_REG_UIX66_10G_40G_U;
187 case P_REG_UIX66_25G_100G_L:
188 *high_addr = P_REG_UIX66_25G_100G_U;
190 case P_REG_TX_CAPTURE_L:
191 *high_addr = P_REG_TX_CAPTURE_U;
193 case P_REG_RX_CAPTURE_L:
194 *high_addr = P_REG_RX_CAPTURE_U;
196 case P_REG_TX_TIMER_INC_PRE_L:
197 *high_addr = P_REG_TX_TIMER_INC_PRE_U;
199 case P_REG_RX_TIMER_INC_PRE_L:
200 *high_addr = P_REG_RX_TIMER_INC_PRE_U;
208 * ice_is_40b_phy_reg_e822 - Check if this is a 40bit PHY register
209 * @low_addr: the low address to check
210 * @high_addr: on return, contains the high address of the 40bit value
212 * Checks if the provided low address is one of the known 40bit PHY values
213 * split into two registers with the lower 8 bits in the low register and the
214 * upper 32 bits in the high register. If it is, return the appropriate high
215 * register offset to use.
217 static bool ice_is_40b_phy_reg_e822(u16 low_addr, u16 *high_addr)
220 case P_REG_TIMETUS_L:
221 *high_addr = P_REG_TIMETUS_U;
223 case P_REG_PAR_RX_TUS_L:
224 *high_addr = P_REG_PAR_RX_TUS_U;
226 case P_REG_PAR_TX_TUS_L:
227 *high_addr = P_REG_PAR_TX_TUS_U;
229 case P_REG_PCS_RX_TUS_L:
230 *high_addr = P_REG_PCS_RX_TUS_U;
232 case P_REG_PCS_TX_TUS_L:
233 *high_addr = P_REG_PCS_TX_TUS_U;
235 case P_REG_DESK_PAR_RX_TUS_L:
236 *high_addr = P_REG_DESK_PAR_RX_TUS_U;
238 case P_REG_DESK_PAR_TX_TUS_L:
239 *high_addr = P_REG_DESK_PAR_TX_TUS_U;
241 case P_REG_DESK_PCS_RX_TUS_L:
242 *high_addr = P_REG_DESK_PCS_RX_TUS_U;
244 case P_REG_DESK_PCS_TX_TUS_L:
245 *high_addr = P_REG_DESK_PCS_TX_TUS_U;
253 * ice_read_phy_reg_e822_lp - Read a PHY register
254 * @hw: pointer to the HW struct
255 * @port: PHY port to read from
256 * @offset: PHY register offset to read
257 * @val: on return, the contents read from the PHY
258 * @lock_sbq: true if the sideband queue lock must be acquired
260 * Read a PHY register for the given port over the device sideband queue.
262 static enum ice_status
263 ice_read_phy_reg_e822_lp(struct ice_hw *hw, u8 port, u16 offset, u32 *val,
266 struct ice_sbq_msg_input msg = {0};
267 enum ice_status status;
269 ice_fill_phy_msg_e822(&msg, port, offset);
270 msg.opcode = ice_sbq_msg_rd;
272 status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
274 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
285 ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
287 return ice_read_phy_reg_e822_lp(hw, port, offset, val, true);
291 * ice_read_40b_phy_reg_e822 - Read a 40bit value from PHY registers
292 * @hw: pointer to the HW struct
293 * @port: PHY port to read from
294 * @low_addr: offset of the lower register to read from
295 * @val: on return, the contents of the 40bit value from the PHY registers
297 * Reads the two registers associated with a 40bit value and returns it in the
298 * val pointer. The offset always specifies the lower register offset to use.
299 * The high offset is looked up. This function only operates on registers
300 * known to be split into a lower 8 bit chunk and an upper 32 bit chunk.
302 static enum ice_status
303 ice_read_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
305 enum ice_status status;
309 /* Only operate on registers known to be split into two 32bit
312 if (!ice_is_40b_phy_reg_e822(low_addr, &high_addr)) {
313 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
315 return ICE_ERR_PARAM;
318 status = ice_read_phy_reg_e822(hw, port, low_addr, &low);
320 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, status %d",
325 status = ice_read_phy_reg_e822(hw, port, high_addr, &high);
327 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, status %d",
332 *val = (u64)high << P_REG_40B_HIGH_S | (low & P_REG_40B_LOW_M);
338 * ice_read_64b_phy_reg_e822 - Read a 64bit value from PHY registers
339 * @hw: pointer to the HW struct
340 * @port: PHY port to read from
341 * @low_addr: offset of the lower register to read from
342 * @val: on return, the contents of the 64bit value from the PHY registers
344 * Reads the two registers associated with a 64bit value and returns it in the
345 * val pointer. The offset always specifies the lower register offset to use.
346 * The high offset is looked up. This function only operates on registers
347 * known to be two parts of a 64bit value.
349 static enum ice_status
350 ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
352 enum ice_status status;
356 /* Only operate on registers known to be split into two 32bit
359 if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) {
360 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
362 return ICE_ERR_PARAM;
365 status = ice_read_phy_reg_e822(hw, port, low_addr, &low);
367 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, status %d",
372 status = ice_read_phy_reg_e822(hw, port, high_addr, &high);
374 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, status %d",
379 *val = (u64)high << 32 | low;
385 * ice_write_phy_reg_e822_lp - Write a PHY register
386 * @hw: pointer to the HW struct
387 * @port: PHY port to write to
388 * @offset: PHY register offset to write
389 * @val: The value to write to the register
390 * @lock_sbq: true if the sideband queue lock must be acquired
392 * Write a PHY register for the given port over the device sideband queue.
394 static enum ice_status
395 ice_write_phy_reg_e822_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val,
398 struct ice_sbq_msg_input msg = {0};
399 enum ice_status status;
401 ice_fill_phy_msg_e822(&msg, port, offset);
402 msg.opcode = ice_sbq_msg_wr;
405 status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
407 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
416 ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val)
418 return ice_write_phy_reg_e822_lp(hw, port, offset, val, true);
422 * ice_write_40b_phy_reg_e822 - Write a 40b value to the PHY
423 * @hw: pointer to the HW struct
424 * @port: port to write to
425 * @low_addr: offset of the low register
426 * @val: 40b value to write
428 * Write the provided 40b value to the two associated registers by splitting
429 * it up into two chunks, the lower 8 bits and the upper 32 bits.
431 static enum ice_status
432 ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
434 enum ice_status status;
438 /* Only operate on registers known to be split into a lower 8 bit
439 * register and an upper 32 bit register.
441 if (!ice_is_40b_phy_reg_e822(low_addr, &high_addr)) {
442 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n",
444 return ICE_ERR_PARAM;
447 low = (u32)(val & P_REG_40B_LOW_M);
448 high = (u32)(val >> P_REG_40B_HIGH_S);
450 status = ice_write_phy_reg_e822(hw, port, low_addr, low);
452 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
457 status = ice_write_phy_reg_e822(hw, port, high_addr, high);
459 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
468 * ice_write_64b_phy_reg_e822 - Write a 64bit value to PHY registers
469 * @hw: pointer to the HW struct
470 * @port: PHY port to read from
471 * @low_addr: offset of the lower register to read from
472 * @val: the contents of the 64bit value to write to PHY
474 * Write the 64bit value to the two associated 32bit PHY registers. The offset
475 * is always specified as the lower register, and the high address is looked
476 * up. This function only operates on registers known to be two parts of
479 static enum ice_status
480 ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
482 enum ice_status status;
486 /* Only operate on registers known to be split into two 32bit
489 if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) {
490 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
492 return ICE_ERR_PARAM;
495 low = ICE_LO_DWORD(val);
496 high = ICE_HI_DWORD(val);
498 status = ice_write_phy_reg_e822(hw, port, low_addr, low);
500 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
505 status = ice_write_phy_reg_e822(hw, port, high_addr, high);
507 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
516 * ice_fill_quad_msg_e822 - Fill message data for quad register access
517 * @msg: the PHY message buffer to fill in
518 * @quad: the quad to access
519 * @offset: the register offset
521 * Fill a message buffer for accessing a register in a quad shared between
525 ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)
529 msg->dest_dev = rmn_0;
531 if ((quad % ICE_NUM_QUAD_TYPE) == 0)
532 addr = Q_0_BASE + offset;
534 addr = Q_1_BASE + offset;
536 msg->msg_addr_low = ICE_LO_WORD(addr);
537 msg->msg_addr_high = ICE_HI_WORD(addr);
541 * ice_read_quad_reg_e822_lp - Read a PHY quad register
542 * @hw: pointer to the HW struct
543 * @quad: quad to read from
544 * @offset: quad register offset to read
545 * @val: on return, the contents read from the quad
546 * @lock_sbq: true if the sideband queue lock must be acquired
548 * Read a quad register over the device sideband queue. Quad registers are
549 * shared between multiple PHYs.
551 static enum ice_status
552 ice_read_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 *val,
555 struct ice_sbq_msg_input msg = {0};
556 enum ice_status status;
558 if (quad >= ICE_MAX_QUAD)
559 return ICE_ERR_PARAM;
561 ice_fill_quad_msg_e822(&msg, quad, offset);
562 msg.opcode = ice_sbq_msg_rd;
564 status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
566 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
577 ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)
579 return ice_read_quad_reg_e822_lp(hw, quad, offset, val, true);
583 * ice_write_quad_reg_e822_lp - Write a PHY quad register
584 * @hw: pointer to the HW struct
585 * @quad: quad to write to
586 * @offset: quad register offset to write
587 * @val: The value to write to the register
588 * @lock_sbq: true if the sideband queue lock must be acquired
590 * Write a quad register over the device sideband queue. Quad registers are
591 * shared between multiple PHYs.
593 static enum ice_status
594 ice_write_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 val,
597 struct ice_sbq_msg_input msg = {0};
598 enum ice_status status;
600 if (quad >= ICE_MAX_QUAD)
601 return ICE_ERR_PARAM;
603 ice_fill_quad_msg_e822(&msg, quad, offset);
604 msg.opcode = ice_sbq_msg_wr;
607 status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
609 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
618 ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val)
620 return ice_write_quad_reg_e822_lp(hw, quad, offset, val, true);
624 * ice_read_phy_tstamp_e822 - Read a PHY timestamp out of the quad block
625 * @hw: pointer to the HW struct
626 * @quad: the quad to read from
627 * @idx: the timestamp index to read
628 * @tstamp: on return, the 40bit timestamp value
630 * Read a 40bit timestamp value out of the two associated registers in the
631 * quad memory block that is shared between the internal PHYs of the E822
634 static enum ice_status
635 ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)
637 enum ice_status status;
638 u16 lo_addr, hi_addr;
641 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
642 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
644 status = ice_read_quad_reg_e822(hw, quad, lo_addr, &lo);
646 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n",
651 status = ice_read_quad_reg_e822(hw, quad, hi_addr, &hi);
653 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n",
658 /* For E822 based internal PHYs, the timestamp is reported with the
659 * lower 8 bits in the low register, and the upper 32 bits in the high
662 *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M);
668 * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block
669 * @hw: pointer to the HW struct
670 * @quad: the quad to read from
671 * @idx: the timestamp index to reset
673 * Clear a timestamp, resetting its valid bit, from the PHY quad block that is
674 * shared between the internal PHYs on the E822 devices.
676 static enum ice_status
677 ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)
679 enum ice_status status;
680 u16 lo_addr, hi_addr;
682 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
683 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
685 status = ice_write_quad_reg_e822(hw, quad, lo_addr, 0);
687 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n",
692 status = ice_write_quad_reg_e822(hw, quad, hi_addr, 0);
694 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n",
703 * ice_read_cgu_reg_e822 - Read a CGU register
704 * @hw: pointer to the HW struct
705 * @addr: Register address to read
706 * @val: storage for register value read
708 * Read the contents of a register of the Clock Generation Unit. Only
709 * applicable to E822 devices.
711 static enum ice_status
712 ice_read_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 *val)
714 struct ice_sbq_msg_input cgu_msg;
715 enum ice_status status;
717 cgu_msg.opcode = ice_sbq_msg_rd;
718 cgu_msg.dest_dev = cgu;
719 cgu_msg.msg_addr_low = addr;
720 cgu_msg.msg_addr_high = 0x0;
722 status = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
724 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, status %d\n",
735 * ice_write_cgu_reg_e822 - Write a CGU register
736 * @hw: pointer to the HW struct
737 * @addr: Register address to write
738 * @val: value to write into the register
740 * Write the specified value to a register of the Clock Generation Unit. Only
741 * applicable to E822 devices.
743 static enum ice_status
744 ice_write_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 val)
746 struct ice_sbq_msg_input cgu_msg;
747 enum ice_status status;
749 cgu_msg.opcode = ice_sbq_msg_wr;
750 cgu_msg.dest_dev = cgu;
751 cgu_msg.msg_addr_low = addr;
752 cgu_msg.msg_addr_high = 0x0;
755 status = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
757 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, status %d\n",
766 * ice_clk_freq_str - Convert time_ref_freq to string
767 * @clk_freq: Clock frequency
769 * Convert the specified TIME_REF clock frequency to a string.
771 static const char *ice_clk_freq_str(u8 clk_freq)
773 switch ((enum ice_time_ref_freq)clk_freq) {
774 case ICE_TIME_REF_FREQ_25_000:
776 case ICE_TIME_REF_FREQ_122_880:
778 case ICE_TIME_REF_FREQ_125_000:
780 case ICE_TIME_REF_FREQ_153_600:
782 case ICE_TIME_REF_FREQ_156_250:
784 case ICE_TIME_REF_FREQ_245_760:
792 * ice_clk_src_str - Convert time_ref_src to string
793 * @clk_src: Clock source
795 * Convert the specified clock source to its string name.
797 static const char *ice_clk_src_str(u8 clk_src)
799 switch ((enum ice_clk_src)clk_src) {
800 case ICE_CLK_SRC_TCX0:
802 case ICE_CLK_SRC_TIME_REF:
810 * ice_cfg_cgu_pll_e822 - Configure the Clock Generation Unit
811 * @hw: pointer to the HW struct
812 * @clk_freq: Clock frequency to program
813 * @clk_src: Clock source to select (TIME_REF, or TCX0)
815 * Configure the Clock Generation Unit with the desired clock frequency and
816 * time reference, enabling the PLL which drives the PTP hardware clock.
819 ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
820 enum ice_clk_src clk_src)
822 union tspll_ro_bwm_lf bwm_lf;
823 union nac_cgu_dword19 dw19;
824 union nac_cgu_dword22 dw22;
825 union nac_cgu_dword24 dw24;
826 union nac_cgu_dword9 dw9;
827 enum ice_status status;
829 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
830 ice_warn(hw, "Invalid TIME_REF frequency %u\n", clk_freq);
831 return ICE_ERR_PARAM;
834 if (clk_src >= NUM_ICE_CLK_SRC) {
835 ice_warn(hw, "Invalid clock source %u\n", clk_src);
836 return ICE_ERR_PARAM;
839 if (clk_src == ICE_CLK_SRC_TCX0 &&
840 clk_freq != ICE_TIME_REF_FREQ_25_000) {
841 ice_warn(hw, "TCX0 only supports 25 MHz frequency\n");
842 return ICE_ERR_PARAM;
845 status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD9, &dw9.val);
849 status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);
853 status = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
857 /* Log the current clock configuration */
858 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
859 dw24.field.ts_pll_enable ? "enabled" : "disabled",
860 ice_clk_src_str(dw24.field.time_ref_sel),
861 ice_clk_freq_str(dw9.field.time_ref_freq_sel),
862 bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
864 /* Disable the PLL before changing the clock source or frequency */
865 if (dw24.field.ts_pll_enable) {
866 dw24.field.ts_pll_enable = 0;
868 status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);
873 /* Set the frequency */
874 dw9.field.time_ref_freq_sel = clk_freq;
875 status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val);
879 /* Configure the TS PLL feedback divisor */
880 status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD19, &dw19.val);
884 dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
885 dw19.field.tspll_ndivratio = 1;
887 status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val);
891 /* Configure the TS PLL post divisor */
892 status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD22, &dw22.val);
896 dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
897 dw22.field.time1588clk_sel_div2 = 0;
899 status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val);
903 /* Configure the TS PLL pre divisor and clock source */
904 status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);
908 dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
909 dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
910 dw24.field.time_ref_sel = clk_src;
912 status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);
916 /* Finally, enable the PLL */
917 dw24.field.ts_pll_enable = 1;
919 status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);
923 /* Wait to verify if the PLL locks */
924 ice_msec_delay(1, true);
926 status = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
930 if (!bwm_lf.field.plllock_true_lock_cri) {
931 ice_warn(hw, "CGU PLL failed to lock\n");
932 return ICE_ERR_NOT_READY;
935 /* Log the current clock configuration */
936 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
937 dw24.field.ts_pll_enable ? "enabled" : "disabled",
938 ice_clk_src_str(dw24.field.time_ref_sel),
939 ice_clk_freq_str(dw9.field.time_ref_freq_sel),
940 bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
947 * ice_init_cgu_e822 - Initialize CGU with settings from firmware
948 * @hw: pointer to the HW structure
950 * Initialize the Clock Generation Unit of the E822 device.
952 static enum ice_status ice_init_cgu_e822(struct ice_hw *hw)
954 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
955 union tspll_cntr_bist_settings cntr_bist;
956 enum ice_status status;
958 status = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,
963 /* Disable sticky lock detection so lock status reported is accurate */
964 cntr_bist.field.i_plllock_sel_0 = 0;
965 cntr_bist.field.i_plllock_sel_1 = 0;
967 status = ice_write_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,
972 /* Configure the CGU PLL using the parameters from the function
975 status = ice_cfg_cgu_pll_e822(hw, ts_info->time_ref,
976 (enum ice_clk_src)ts_info->clk_src);
984 * ice_ptp_init_phc_e822 - Perform E822 specific PHC initialization
985 * @hw: pointer to HW struct
987 * Perform PHC initialization steps specific to E822 devices.
989 static enum ice_status ice_ptp_init_phc_e822(struct ice_hw *hw)
991 enum ice_status status;
994 /* Enable reading switch and PHY registers over the sideband queue */
995 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
996 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
997 regval = rd32(hw, PF_SB_REM_DEV_CTL);
998 regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ |
999 PF_SB_REM_DEV_CTL_PHY0);
1000 wr32(hw, PF_SB_REM_DEV_CTL, regval);
1002 /* Initialize the Clock Generation Unit */
1003 status = ice_init_cgu_e822(hw);
1007 /* Set window length for all the ports */
1008 return ice_ptp_set_vernier_wl(hw);
1012 * ice_ptp_prep_phy_time_e822 - Prepare PHY port with initial time
1013 * @hw: pointer to the HW struct
1014 * @time: Time to initialize the PHY port clocks to
1016 * Program the PHY port registers with a new initial time value. The port
1017 * clock will be initialized once the driver issues an INIT_TIME sync
1018 * command. The time value is the upper 32 bits of the PHY timer, usually in
1019 * units of nominal nanoseconds.
1021 static enum ice_status
1022 ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time)
1024 enum ice_status status;
1028 /* The time represents the upper 32 bits of the PHY timer, so we need
1029 * to shift to account for this when programming.
1031 phy_time = (u64)time << 32;
1033 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1036 status = ice_write_64b_phy_reg_e822(hw, port,
1037 P_REG_TX_TIMER_INC_PRE_L,
1043 status = ice_write_64b_phy_reg_e822(hw, port,
1044 P_REG_RX_TIMER_INC_PRE_L,
1053 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, status %d\n",
1060 * ice_ptp_prep_port_adj_e822 - Prepare a single port for time adjust
1061 * @hw: pointer to HW struct
1062 * @port: Port number to be programmed
1063 * @time: time in cycles to adjust the port Tx and Rx clocks
1064 * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
1065 * sq_lock has already been locked at a higher level
1067 * Program the port for an atomic adjustment by writing the Tx and Rx timer
1068 * registers. The atomic adjustment won't be completed until the driver issues
1069 * an ADJ_TIME command.
1071 * Note that time is not in units of nanoseconds. It is in clock time
1072 * including the lower sub-nanosecond portion of the port timer.
1074 * Negative adjustments are supported using 2s complement arithmetic.
1077 ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time,
1080 enum ice_status status;
1083 l_time = ICE_LO_DWORD(time);
1084 u_time = ICE_HI_DWORD(time);
1087 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TIMER_INC_PRE_L,
1092 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TIMER_INC_PRE_U,
1098 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TIMER_INC_PRE_L,
1103 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TIMER_INC_PRE_U,
1111 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, status %d\n",
1117 * ice_ptp_prep_phy_adj_e822 - Prep PHY ports for a time adjustment
1118 * @hw: pointer to HW struct
1119 * @adj: adjustment in nanoseconds
1120 * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
1121 * sq_lock has already been locked at a higher level
1123 * Prepare the PHY ports for an atomic time adjustment by programming the PHY
1124 * Tx and Rx port registers. The actual adjustment is completed by issuing an
1125 * ADJ_TIME or ADJ_TIME_AT_TIME sync command.
1127 static enum ice_status
1128 ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj, bool lock_sbq)
1133 /* The port clock supports adjustment of the sub-nanosecond portion of
1134 * the clock. We shift the provided adjustment in nanoseconds to
1135 * calculate the appropriate adjustment to program into the PHY ports.
1138 cycles = (s64)adj << 32;
1140 cycles = -(((s64)-adj) << 32);
1142 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1143 enum ice_status status;
1145 status = ice_ptp_prep_port_adj_e822(hw, port, cycles,
1155 * ice_ptp_prep_phy_incval_e822 - Prepare PHY ports for time adjustment
1156 * @hw: pointer to HW struct
1157 * @incval: new increment value to prepare
1159 * Prepare each of the PHY ports for a new increment value by programming the
1160 * port's TIMETUS registers. The new increment value will be updated after
1161 * issuing an INIT_INCVAL command.
1163 static enum ice_status
1164 ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval)
1166 enum ice_status status;
1169 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1170 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L,
1179 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, status %d\n",
1186 * ice_ptp_read_phy_incval_e822 - Read a PHY port's current incval
1187 * @hw: pointer to the HW struct
1188 * @port: the port to read
1189 * @incval: on return, the time_clk_cyc incval for this port
1191 * Read the time_clk_cyc increment value for a given PHY port.
1194 ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port, u64 *incval)
1196 enum ice_status status;
1198 status = ice_read_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval);
1200 ice_debug(hw, ICE_DBG_PTP, "Failed to read TIMETUS_L, status %d\n",
1205 ice_debug(hw, ICE_DBG_PTP, "read INCVAL = 0x%016llx\n",
1206 (unsigned long long)*incval);
1212 * ice_ptp_prep_phy_adj_target_e822 - Prepare PHY for adjust at target time
1213 * @hw: pointer to HW struct
1214 * @target_time: target time to program
1216 * Program the PHY port Tx and Rx TIMER_CNT_ADJ registers used for the
1217 * ADJ_TIME_AT_TIME command. This should be used in conjunction with
1218 * ice_ptp_prep_phy_adj_e822 to program an atomic adjustment that is
1219 * delayed until a specified target time.
1221 * Note that a target time adjustment is not currently supported on E810
1224 static enum ice_status
1225 ice_ptp_prep_phy_adj_target_e822(struct ice_hw *hw, u32 target_time)
1227 enum ice_status status;
1230 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1233 /* No sub-nanoseconds data */
1234 status = ice_write_phy_reg_e822_lp(hw, port,
1235 P_REG_TX_TIMER_CNT_ADJ_L,
1240 status = ice_write_phy_reg_e822_lp(hw, port,
1241 P_REG_TX_TIMER_CNT_ADJ_U,
1247 /* No sub-nanoseconds data */
1248 status = ice_write_phy_reg_e822_lp(hw, port,
1249 P_REG_RX_TIMER_CNT_ADJ_L,
1254 status = ice_write_phy_reg_e822_lp(hw, port,
1255 P_REG_RX_TIMER_CNT_ADJ_U,
1264 ice_debug(hw, ICE_DBG_PTP, "Failed to write target time for port %u, status %d\n",
1271 * ice_ptp_read_port_capture - Read a port's local time capture
1272 * @hw: pointer to HW struct
1273 * @port: Port number to read
1274 * @tx_ts: on return, the Tx port time capture
1275 * @rx_ts: on return, the Rx port time capture
1277 * Read the port's Tx and Rx local time capture values.
1279 * Note this has no equivalent for the E810 devices.
1282 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
1284 enum ice_status status;
1287 status = ice_read_64b_phy_reg_e822(hw, port, P_REG_TX_CAPTURE_L, tx_ts);
1289 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, status %d\n",
1294 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n",
1295 (unsigned long long)*tx_ts);
1298 status = ice_read_64b_phy_reg_e822(hw, port, P_REG_RX_CAPTURE_L, rx_ts);
1300 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, status %d\n",
1305 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n",
1306 (unsigned long long)*rx_ts);
1312 * ice_ptp_one_port_cmd - Prepare a single PHY port for a timer command
1313 * @hw: pointer to HW struct
1314 * @port: Port to which cmd has to be sent
1315 * @cmd: Command to be sent to the port
1316 * @lock_sbq: true if the sideband queue lock must be acquired
1318 * Prepare the requested port for an upcoming timer sync command.
1320 * Note there is no equivalent of this operation on E810, as that device
1321 * always handles all external PHYs internally.
1324 ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
1327 enum ice_status status;
1331 tmr_idx = ice_get_ptp_src_clock_index(hw);
1332 cmd_val = tmr_idx << SEL_PHY_SRC;
1335 cmd_val |= PHY_CMD_INIT_TIME;
1338 cmd_val |= PHY_CMD_INIT_INCVAL;
1341 cmd_val |= PHY_CMD_ADJ_TIME;
1343 case ADJ_TIME_AT_TIME:
1344 cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME;
1347 cmd_val |= PHY_CMD_READ_TIME;
1350 ice_warn(hw, "Unknown timer command %u\n", cmd);
1351 return ICE_ERR_PARAM;
1355 /* Read, modify, write */
1356 status = ice_read_phy_reg_e822_lp(hw, port, P_REG_TX_TMR_CMD, &val,
1359 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, status %d\n",
1364 /* Modify necessary bits only and perform write */
1365 val &= ~TS_CMD_MASK;
1368 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TMR_CMD, val,
1371 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, status %d\n",
1377 /* Read, modify, write */
1378 status = ice_read_phy_reg_e822_lp(hw, port, P_REG_RX_TMR_CMD, &val,
1381 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, status %d\n",
1386 /* Modify necessary bits only and perform write */
1387 val &= ~TS_CMD_MASK;
1390 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TMR_CMD, val,
1393 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, status %d\n",
1402 * ice_ptp_port_cmd_e822 - Prepare all ports for a timer command
1403 * @hw: pointer to the HW struct
1404 * @cmd: timer command to prepare
1405 * @lock_sbq: true if the sideband queue lock must be acquired
1407 * Prepare all ports connected to this device for an upcoming timer sync
1410 static enum ice_status
1411 ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
1416 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1417 enum ice_status status;
1419 status = ice_ptp_one_port_cmd(hw, port, cmd, lock_sbq);
1427 /* E822 Vernier calibration functions
1429 * The following functions are used as part of the vernier calibration of
1430 * a port. This calibration increases the precision of the timestamps on the
1435 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
1436 * @hw: pointer to the HW struct
1438 * Set the window length used for the vernier port calibration process.
1440 enum ice_status ice_ptp_set_vernier_wl(struct ice_hw *hw)
1444 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1445 enum ice_status status;
1447 status = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL,
1448 PTP_VERNIER_WL, true);
1450 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, status %d\n",
1460 * ice_phy_get_speed_and_fec_e822 - Get link speed and FEC based on serdes mode
1461 * @hw: pointer to HW struct
1462 * @port: the port to read from
1463 * @link_out: if non-NULL, holds link speed on success
1464 * @fec_out: if non-NULL, holds FEC algorithm on success
1466 * Read the serdes data for the PHY port and extract the link speed and FEC
1470 ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
1471 enum ice_ptp_link_spd *link_out,
1472 enum ice_ptp_fec_mode *fec_out)
1474 enum ice_ptp_link_spd link;
1475 enum ice_ptp_fec_mode fec;
1476 enum ice_status status;
1479 status = ice_read_phy_reg_e822(hw, port, P_REG_LINK_SPEED, &serdes);
1481 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n");
1485 /* Determine the FEC algorithm */
1486 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes);
1488 serdes &= P_REG_LINK_SPEED_SERDES_M;
1490 /* Determine the link speed */
1491 if (fec == ICE_PTP_FEC_MODE_RS_FEC) {
1493 case ICE_PTP_SERDES_25G:
1494 link = ICE_PTP_LNK_SPD_25G_RS;
1496 case ICE_PTP_SERDES_50G:
1497 link = ICE_PTP_LNK_SPD_50G_RS;
1499 case ICE_PTP_SERDES_100G:
1500 link = ICE_PTP_LNK_SPD_100G_RS;
1503 return ICE_ERR_OUT_OF_RANGE;
1507 case ICE_PTP_SERDES_1G:
1508 link = ICE_PTP_LNK_SPD_1G;
1510 case ICE_PTP_SERDES_10G:
1511 link = ICE_PTP_LNK_SPD_10G;
1513 case ICE_PTP_SERDES_25G:
1514 link = ICE_PTP_LNK_SPD_25G;
1516 case ICE_PTP_SERDES_40G:
1517 link = ICE_PTP_LNK_SPD_40G;
1519 case ICE_PTP_SERDES_50G:
1520 link = ICE_PTP_LNK_SPD_50G;
1523 return ICE_ERR_OUT_OF_RANGE;
1536 * ice_phy_cfg_lane_e822 - Configure PHY quad for single/multi-lane timestamp
1537 * @hw: pointer to HW struct
1538 * @port: to configure the quad for
1540 void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)
1542 enum ice_ptp_link_spd link_spd;
1543 enum ice_status status;
1547 status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, NULL);
1549 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, status %d\n",
1554 quad = port / ICE_PORTS_PER_QUAD;
1556 status = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
1558 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, status %d\n",
1563 if (link_spd >= ICE_PTP_LNK_SPD_40G)
1564 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
1566 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
1568 status = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
1570 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, status %d\n",
1577 * ice_phy_cfg_uix_e822 - Configure Serdes UI to TU conversion for E822
1578 * @hw: pointer to the HW structure
1579 * @port: the port to configure
1581 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC
1582 * hardware clock time units (TUs). That is, determine the number of TUs per
1583 * serdes unit interval, and program the UIX registers with this conversion.
1585 * This conversion is used as part of the calibration process when determining
1586 * the additional error of a timestamp vs the real time of transmission or
1587 * receipt of the packet.
1589 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers
1590 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks.
1592 * To calculate the conversion ratio, we use the following facts:
1594 * a) the clock frequency in Hz (cycles per second)
1595 * b) the number of TUs per cycle (the increment value of the clock)
1596 * c) 1 second per 1 billion nanoseconds
1597 * d) the duration of 66 UIs in nanoseconds
1599 * Given these facts, we can use the following table to work out what ratios
1600 * to multiply in order to get the number of TUs per 66 UIs:
1602 * cycles | 1 second | incval (TUs) | nanoseconds
1603 * -------+--------------+--------------+-------------
1604 * second | 1 billion ns | cycle | 66 UIs
1606 * To perform the multiplication using integers without too much loss of
1607 * precision, we can take use the following equation:
1609 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion)
1611 * We scale up to using 6600 UI instead of 66 in order to avoid fractional
1612 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns)
1614 * The increment value has a maximum expected range of about 34 bits, while
1615 * the frequency value is about 29 bits. Multiplying these values shouldn't
1616 * overflow the 64 bits. However, we must then further multiply them again by
1617 * the Serdes unit interval duration. To avoid overflow here, we split the
1618 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and
1619 * a divide by 390,625,000. This does lose some precision, but avoids
1620 * miscalculation due to arithmetic overflow.
1622 static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)
1624 u64 cur_freq, clk_incval, tu_per_sec, uix;
1625 enum ice_status status;
1627 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
1628 clk_incval = ice_ptp_read_src_incval(hw);
1630 /* Calculate TUs per second divided by 256 */
1631 tu_per_sec = (cur_freq * clk_incval) >> 8;
1633 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */
1634 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
1636 /* Program the 10Gb/40Gb conversion ratio */
1637 uix = (tu_per_sec * LINE_UI_10G_40G) / 390625000;
1639 status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,
1642 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, status %d\n",
1647 /* Program the 25Gb/100Gb conversion ratio */
1648 uix = (tu_per_sec * LINE_UI_25G_100G) / 390625000;
1650 status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,
1653 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, status %d\n",
1662 * ice_phy_cfg_parpcs_e822 - Configure TUs per PAR/PCS clock cycle
1663 * @hw: pointer to the HW struct
1664 * @port: port to configure
1666 * Configure the number of TUs for the PAR and PCS clocks used as part of the
1667 * timestamp calibration process. This depends on the link speed, as the PHY
1668 * uses different markers depending on the speed.
1671 * - Tx/Rx PAR/PCS markers
1674 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
1677 * - Tx/Rx PAR/PCS markers
1678 * - Rx Deskew PAR/PCS markers
1680 * 50G RS and 100GB RS:
1681 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
1682 * - Rx Deskew PAR/PCS markers
1683 * - Tx PAR/PCS markers
1685 * To calculate the conversion, we use the PHC clock frequency (cycles per
1686 * second), the increment value (TUs per cycle), and the related PHY clock
1687 * frequency to calculate the TUs per unit of the PHY link clock. The
1688 * following table shows how the units convert:
1690 * cycles | TUs | second
1691 * -------+-------+--------
1692 * second | cycle | cycles
1694 * For each conversion register, look up the appropriate frequency from the
1695 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program
1696 * this to the appropriate register, preparing hardware to perform timestamp
1697 * calibration to calculate the total Tx or Rx offset to adjust the timestamp
1698 * in order to calibrate for the internal PHY delays.
1700 * Note that the increment value ranges up to ~34 bits, and the clock
1701 * frequency is ~29 bits, so multiplying them together should fit within the
1702 * 64 bit arithmetic.
1704 static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
1706 u64 cur_freq, clk_incval, tu_per_sec, phy_tus;
1707 enum ice_ptp_link_spd link_spd;
1708 enum ice_ptp_fec_mode fec_mode;
1709 enum ice_status status;
1711 status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
1715 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
1716 clk_incval = ice_ptp_read_src_incval(hw);
1718 /* Calculate TUs per cycle of the PHC clock */
1719 tu_per_sec = cur_freq * clk_incval;
1721 /* For each PHY conversion register, look up the appropriate link
1722 * speed frequency and determine the TUs per that clock's cycle time.
1723 * Split this into a high and low value and then program the
1724 * appropriate register. If that link speed does not use the
1725 * associated register, write zeros to clear it instead.
1728 /* P_REG_PAR_TX_TUS */
1729 if (e822_vernier[link_spd].tx_par_clk)
1730 phy_tus = tu_per_sec / e822_vernier[link_spd].tx_par_clk;
1734 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_TX_TUS_L,
1739 /* P_REG_PAR_RX_TUS */
1740 if (e822_vernier[link_spd].rx_par_clk)
1741 phy_tus = tu_per_sec / e822_vernier[link_spd].rx_par_clk;
1745 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_RX_TUS_L,
1750 /* P_REG_PCS_TX_TUS */
1751 if (e822_vernier[link_spd].tx_pcs_clk)
1752 phy_tus = tu_per_sec / e822_vernier[link_spd].tx_pcs_clk;
1756 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_TX_TUS_L,
1761 /* P_REG_PCS_RX_TUS */
1762 if (e822_vernier[link_spd].rx_pcs_clk)
1763 phy_tus = tu_per_sec / e822_vernier[link_spd].rx_pcs_clk;
1767 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_RX_TUS_L,
1772 /* P_REG_DESK_PAR_TX_TUS */
1773 if (e822_vernier[link_spd].tx_desk_rsgb_par)
1774 phy_tus = tu_per_sec / e822_vernier[link_spd].tx_desk_rsgb_par;
1778 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_TX_TUS_L,
1783 /* P_REG_DESK_PAR_RX_TUS */
1784 if (e822_vernier[link_spd].rx_desk_rsgb_par)
1785 phy_tus = tu_per_sec / e822_vernier[link_spd].rx_desk_rsgb_par;
1789 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_RX_TUS_L,
1794 /* P_REG_DESK_PCS_TX_TUS */
1795 if (e822_vernier[link_spd].tx_desk_rsgb_pcs)
1796 phy_tus = tu_per_sec / e822_vernier[link_spd].tx_desk_rsgb_pcs;
1800 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_TX_TUS_L,
1805 /* P_REG_DESK_PCS_RX_TUS */
1806 if (e822_vernier[link_spd].rx_desk_rsgb_pcs)
1807 phy_tus = tu_per_sec / e822_vernier[link_spd].rx_desk_rsgb_pcs;
1811 return ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_RX_TUS_L,
1816 * ice_calc_fixed_tx_offset_e822 - Calculated Fixed Tx offset for a port
1817 * @hw: pointer to the HW struct
1818 * @link_spd: the Link speed to calculate for
1820 * Calculate the fixed offset due to known static latency data.
1823 ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
1825 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
1827 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
1828 clk_incval = ice_ptp_read_src_incval(hw);
1830 /* Calculate TUs per second */
1831 tu_per_sec = cur_freq * clk_incval;
1833 /* Calculate number of TUs to add for the fixed Tx latency. Since the
1834 * latency measurement is in 1/100th of a nanosecond, we need to
1835 * multiply by tu_per_sec and then divide by 1e11. This calculation
1836 * overflows 64 bit integer arithmetic, so break it up into two
1837 * divisions by 1e4 first then by 1e7.
1839 fixed_offset = tu_per_sec / 10000;
1840 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay;
1841 fixed_offset /= 10000000;
1843 return fixed_offset;
1847 * ice_phy_cfg_tx_offset_e822 - Configure total Tx timestamp offset
1848 * @hw: pointer to the HW struct
1849 * @port: the PHY port to configure
1851 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to
1852 * adjust Tx timestamps by. This is calculated by combining some known static
1853 * latency along with the Vernier offset computations done by hardware.
1855 * This function must be called only after the offset registers are valid,
1856 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
1857 * has measured the offset.
1859 * To avoid overflow, when calculating the offset based on the known static
1860 * latency values, we use measurements in 1/100th of a nanosecond, and divide
1861 * the TUs per second up front. This avoids overflow while allowing
1862 * calculation of the adjustment using integer arithmetic.
1864 enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)
1866 enum ice_ptp_link_spd link_spd;
1867 enum ice_ptp_fec_mode fec_mode;
1868 enum ice_status status;
1869 u64 total_offset, val;
1871 status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
1875 total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
1877 /* Read the first Vernier offset from the PHY register and add it to
1880 if (link_spd == ICE_PTP_LNK_SPD_1G ||
1881 link_spd == ICE_PTP_LNK_SPD_10G ||
1882 link_spd == ICE_PTP_LNK_SPD_25G ||
1883 link_spd == ICE_PTP_LNK_SPD_25G_RS ||
1884 link_spd == ICE_PTP_LNK_SPD_40G ||
1885 link_spd == ICE_PTP_LNK_SPD_50G) {
1886 status = ice_read_64b_phy_reg_e822(hw, port,
1887 P_REG_PAR_PCS_TX_OFFSET_L,
1892 total_offset += val;
1895 /* For Tx, we only need to use the second Vernier offset for
1896 * multi-lane link speeds with RS-FEC. The lanes will always be
1899 if (link_spd == ICE_PTP_LNK_SPD_50G_RS ||
1900 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
1901 status = ice_read_64b_phy_reg_e822(hw, port,
1902 P_REG_PAR_TX_TIME_L,
1907 total_offset += val;
1910 /* Now that the total offset has been calculated, program it to the
1911 * PHY and indicate that the Tx offset is ready. After this,
1912 * timestamps will be enabled.
1914 status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
1919 status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
1927 * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode
1928 * @hw: pointer to the HW struct
1929 * @port: the PHY port to configure
1931 * Calculate and program the fixed Tx offset, and indicate that the offset is
1932 * ready. This can be used when operating in bypass mode.
1934 static enum ice_status
1935 ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port)
1937 enum ice_ptp_link_spd link_spd;
1938 enum ice_ptp_fec_mode fec_mode;
1939 enum ice_status status;
1942 status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
1946 total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
1948 /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L
1949 * register, then indicate that the Tx offset is ready. After this,
1950 * timestamps will be enabled.
1952 * Note that this skips including the more precise offsets generated
1953 * by the Vernier calibration.
1955 status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
1960 status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
1968 * ice_phy_calc_pmd_adj_e822 - Calculate PMD adjustment for Rx
1969 * @hw: pointer to the HW struct
1970 * @port: the PHY port to adjust for
1971 * @link_spd: the current link speed of the PHY
1972 * @fec_mode: the current FEC mode of the PHY
1973 * @pmd_adj: on return, the amount to adjust the Rx total offset by
1975 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY.
1976 * This varies by link speed and FEC mode. The value calculated accounts for
1977 * various delays caused when receiving a packet.
1979 static enum ice_status
1980 ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
1981 enum ice_ptp_link_spd link_spd,
1982 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)
1984 u64 cur_freq, clk_incval, tu_per_sec, mult, adj;
1985 enum ice_status status;
1989 status = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &val);
1991 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, status %d\n",
1996 pmd_align = (u8)val;
1998 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
1999 clk_incval = ice_ptp_read_src_incval(hw);
2001 /* Calculate TUs per second */
2002 tu_per_sec = cur_freq * clk_incval;
2004 /* The PMD alignment adjustment measurement depends on the link speed,
2005 * and whether FEC is enabled. For each link speed, the alignment
2006 * adjustment is calculated by dividing a value by the length of
2007 * a Time Unit in nanoseconds.
2009 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8
2010 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33)
2011 * 10G w/FEC: align * 0.1 * 32/33
2012 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33)
2013 * 25G w/FEC: align * 0.4 * 32/33
2014 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33)
2015 * 40G w/FEC: align * 0.1 * 32/33
2016 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33)
2017 * 50G w/FEC: align * 0.8 * 32/33
2019 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33.
2021 * To allow for calculating this value using integer arithmetic, we
2022 * instead start with the number of TUs per second, (inverse of the
2023 * length of a Time Unit in nanoseconds), multiply by a value based
2024 * on the PMD alignment register, and then divide by the right value
2025 * calculated based on the table above. To avoid integer overflow this
2026 * division is broken up into a step of dividing by 125 first.
2028 if (link_spd == ICE_PTP_LNK_SPD_1G) {
2032 mult = (pmd_align + 6) % 10;
2033 } else if (link_spd == ICE_PTP_LNK_SPD_10G ||
2034 link_spd == ICE_PTP_LNK_SPD_25G ||
2035 link_spd == ICE_PTP_LNK_SPD_40G ||
2036 link_spd == ICE_PTP_LNK_SPD_50G) {
2037 /* If Clause 74 FEC, always calculate PMD adjust */
2038 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74)
2042 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS ||
2043 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
2044 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
2046 mult = pmd_align + 40;
2050 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n",
2055 /* In some cases, there's no need to adjust for the PMD alignment */
2061 /* Calculate the adjustment by multiplying TUs per second by the
2062 * appropriate multiplier and divisor. To avoid overflow, we first
2063 * divide by 125, and then handle remaining divisor based on the link
2064 * speed pmd_adj_divisor value.
2066 adj = tu_per_sec / 125;
2068 adj /= e822_vernier[link_spd].pmd_adj_divisor;
2070 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx
2071 * cycle count is necessary.
2073 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) {
2077 status = ice_read_phy_reg_e822(hw, port, P_REG_RX_40_TO_160_CNT,
2080 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, status %d\n",
2085 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M;
2087 mult = (4 - rx_cycle) * 40;
2089 cycle_adj = tu_per_sec / 125;
2091 cycle_adj /= e822_vernier[link_spd].pmd_adj_divisor;
2095 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) {
2099 status = ice_read_phy_reg_e822(hw, port, P_REG_RX_80_TO_160_CNT,
2102 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, status %d\n",
2107 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M;
2109 mult = rx_cycle * 40;
2111 cycle_adj = tu_per_sec / 125;
2113 cycle_adj /= e822_vernier[link_spd].pmd_adj_divisor;
2119 /* Return the calculated adjustment */
2126 * ice_calc_fixed_rx_offset_e822 - Calculated the fixed Rx offset for a port
2127 * @hw: pointer to HW struct
2128 * @link_spd: The Link speed to calculate for
2130 * Determine the fixed Rx latency for a given link speed.
2133 ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
2135 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
2137 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
2138 clk_incval = ice_ptp_read_src_incval(hw);
2140 /* Calculate TUs per second */
2141 tu_per_sec = cur_freq * clk_incval;
2143 /* Calculate number of TUs to add for the fixed Rx latency. Since the
2144 * latency measurement is in 1/100th of a nanosecond, we need to
2145 * multiply by tu_per_sec and then divide by 1e11. This calculation
2146 * overflows 64 bit integer arithmetic, so break it up into two
2147 * divisions by 1e4 first then by 1e7.
2149 fixed_offset = tu_per_sec / 10000;
2150 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay;
2151 fixed_offset /= 10000000;
2153 return fixed_offset;
2157 * ice_phy_cfg_rx_offset_e822 - Configure total Rx timestamp offset
2158 * @hw: pointer to the HW struct
2159 * @port: the PHY port to configure
2161 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to
2162 * adjust Rx timestamps by. This combines calculations from the Vernier offset
2163 * measurements taken in hardware with some data about known fixed delay as
2164 * well as adjusting for multi-lane alignment delay.
2166 * This function must be called only after the offset registers are valid,
2167 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
2168 * has measured the offset.
2170 * To avoid overflow, when calculating the offset based on the known static
2171 * latency values, we use measurements in 1/100th of a nanosecond, and divide
2172 * the TUs per second up front. This avoids overflow while allowing
2173 * calculation of the adjustment using integer arithmetic.
2175 enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)
2177 enum ice_ptp_link_spd link_spd;
2178 enum ice_ptp_fec_mode fec_mode;
2179 u64 total_offset, pmd, val;
2180 enum ice_status status;
2182 status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
2186 total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
2188 /* Read the first Vernier offset from the PHY register and add it to
2191 status = ice_read_64b_phy_reg_e822(hw, port,
2192 P_REG_PAR_PCS_RX_OFFSET_L,
2197 total_offset += val;
2199 /* For Rx, all multi-lane link speeds include a second Vernier
2200 * calibration, because the lanes might not be aligned.
2202 if (link_spd == ICE_PTP_LNK_SPD_40G ||
2203 link_spd == ICE_PTP_LNK_SPD_50G ||
2204 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
2205 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
2206 status = ice_read_64b_phy_reg_e822(hw, port,
2207 P_REG_PAR_RX_TIME_L,
2212 total_offset += val;
2215 /* In addition, Rx must account for the PMD alignment */
2216 status = ice_phy_calc_pmd_adj_e822(hw, port, link_spd, fec_mode, &pmd);
2220 /* For RS-FEC, this adjustment adds delay, but for other modes, it
2223 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC)
2224 total_offset += pmd;
2226 total_offset -= pmd;
2228 /* Now that the total offset has been calculated, program it to the
2229 * PHY and indicate that the Rx offset is ready. After this,
2230 * timestamps will be enabled.
2232 status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
2237 status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
2245 * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode
2246 * @hw: pointer to the HW struct
2247 * @port: the PHY port to configure
2249 * Calculate and program the fixed Rx offset, and indicate that the offset is
2250 * ready. This can be used when operating in bypass mode.
2252 static enum ice_status
2253 ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port)
2255 enum ice_ptp_link_spd link_spd;
2256 enum ice_ptp_fec_mode fec_mode;
2257 enum ice_status status;
2260 status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
2264 total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
2266 /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L
2267 * register, then indicate that the Rx offset is ready. After this,
2268 * timestamps will be enabled.
2270 * Note that this skips including the more precise offsets generated
2271 * by Vernier calibration.
2273 status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
2278 status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
2286 * ice_read_phy_and_phc_time_e822 - Simultaneously capture PHC and PHY time
2287 * @hw: pointer to the HW struct
2288 * @port: the PHY port to read
2289 * @phy_time: on return, the 64bit PHY timer value
2290 * @phc_time: on return, the lower 64bits of PHC time
2292 * Issue a READ_TIME timer command to simultaneously capture the PHY and PHC
2295 static enum ice_status
2296 ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,
2299 enum ice_status status;
2300 u64 tx_time, rx_time;
2304 tmr_idx = ice_get_ptp_src_clock_index(hw);
2306 /* Prepare the PHC timer for a READ_TIME capture command */
2307 ice_ptp_src_cmd(hw, READ_TIME);
2309 /* Prepare the PHY timer for a READ_TIME capture command */
2310 status = ice_ptp_one_port_cmd(hw, port, READ_TIME, true);
2314 /* Issue the sync to start the READ_TIME capture */
2315 ice_ptp_exec_tmr_cmd(hw);
2317 /* Read the captured PHC time from the shadow time registers */
2318 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
2319 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
2320 *phc_time = (u64)lo << 32 | zo;
2322 /* Read the captured PHY time from the PHY shadow registers */
2323 status = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time);
2327 /* If the PHY Tx and Rx timers don't match, log a warning message.
2328 * Note that this should not happen in normal circumstances since the
2329 * driver always programs them together.
2331 if (tx_time != rx_time)
2332 ice_warn(hw, "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
2333 port, (unsigned long long)tx_time,
2334 (unsigned long long)rx_time);
2336 *phy_time = tx_time;
2342 * ice_sync_phy_timer_e822 - Synchronize the PHY timer with PHC timer
2343 * @hw: pointer to the HW struct
2344 * @port: the PHY port to synchronize
2346 * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
2347 * This is done by issuing a READ_TIME command which triggers a simultaneous
2348 * read of the PHY timer and PHC timer. Then we use the difference to
2349 * calculate an appropriate 2s complement addition to add to the PHY timer in
2350 * order to ensure it reads the same value as the primary PHC timer.
2352 static enum ice_status ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
2354 u64 phc_time, phy_time, difference;
2355 enum ice_status status;
2357 if (!ice_ptp_lock(hw)) {
2358 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
2359 return ICE_ERR_NOT_READY;
2362 status = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);
2366 /* Calculate the amount required to add to the port time in order for
2367 * it to match the PHC time.
2369 * Note that the port adjustment is done using 2s complement
2370 * arithmetic. This is convenient since it means that we can simply
2371 * calculate the difference between the PHC time and the port time,
2372 * and it will be interpreted correctly.
2374 difference = phc_time - phy_time;
2376 status = ice_ptp_prep_port_adj_e822(hw, port, (s64)difference, true);
2380 status = ice_ptp_one_port_cmd(hw, port, ADJ_TIME, true);
2384 /* Issue the sync to activate the time adjustment */
2385 ice_ptp_exec_tmr_cmd(hw);
2387 /* Re-capture the timer values to flush the command registers and
2388 * verify that the time was properly adjusted.
2390 status = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);
2394 ice_info(hw, "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
2395 port, (unsigned long long)phy_time,
2396 (unsigned long long)phc_time);
2408 * ice_stop_phy_timer_e822 - Stop the PHY clock timer
2409 * @hw: pointer to the HW struct
2410 * @port: the PHY port to stop
2411 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS
2413 * Stop the clock of a PHY port. This must be done as part of the flow to
2414 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2415 * initialized or when link speed changes.
2418 ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)
2420 enum ice_status status;
2423 status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0);
2427 status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0);
2431 status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
2435 val &= ~P_REG_PS_START_M;
2436 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2440 val &= ~P_REG_PS_ENA_CLK_M;
2441 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2446 val |= P_REG_PS_SFT_RESET_M;
2447 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2452 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
2458 * ice_start_phy_timer_e822 - Start the PHY clock timer
2459 * @hw: pointer to the HW struct
2460 * @port: the PHY port to start
2461 * @bypass: if true, start the PHY in bypass mode
2463 * Start the clock of a PHY port. This must be done as part of the flow to
2464 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2465 * initialized or when link speed changes.
2467 * Bypass mode enables timestamps immediately without waiting for Vernier
2468 * calibration to complete. Hardware will still continue taking Vernier
2469 * measurements on Tx or Rx of packets, but they will not be applied to
2470 * timestamps. Use ice_phy_exit_bypass_e822 to exit bypass mode once hardware
2471 * has completed offset calculation.
2474 ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
2476 enum ice_status status;
2481 tmr_idx = ice_get_ptp_src_clock_index(hw);
2483 status = ice_stop_phy_timer_e822(hw, port, false);
2487 ice_phy_cfg_lane_e822(hw, port);
2489 status = ice_phy_cfg_uix_e822(hw, port);
2493 status = ice_phy_cfg_parpcs_e822(hw, port);
2497 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
2498 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
2499 incval = (u64)hi << 32 | lo;
2501 status = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval);
2505 status = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL, true);
2509 ice_ptp_exec_tmr_cmd(hw);
2511 status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
2515 val |= P_REG_PS_SFT_RESET_M;
2516 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2520 val |= P_REG_PS_START_M;
2521 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2525 val &= ~P_REG_PS_SFT_RESET_M;
2526 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2530 status = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL, true);
2534 ice_ptp_exec_tmr_cmd(hw);
2536 val |= P_REG_PS_ENA_CLK_M;
2537 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2541 val |= P_REG_PS_LOAD_OFFSET_M;
2542 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2546 ice_ptp_exec_tmr_cmd(hw);
2548 status = ice_sync_phy_timer_e822(hw, port);
2553 val |= P_REG_PS_BYPASS_MODE_M;
2554 /* Enter BYPASS mode, enabling timestamps immediately. */
2555 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2559 /* Program the fixed Tx offset */
2560 status = ice_phy_cfg_fixed_tx_offset_e822(hw, port);
2564 /* Program the fixed Rx offset */
2565 status = ice_phy_cfg_fixed_rx_offset_e822(hw, port);
2570 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
2576 * ice_phy_exit_bypass_e822 - Exit bypass mode, after vernier calculations
2577 * @hw: pointer to the HW struct
2578 * @port: the PHY port to configure
2580 * After hardware finishes vernier calculations for the Tx and Rx offset, this
2581 * function can be used to exit bypass mode by updating the total Tx and Rx
2582 * offsets, and then disabling bypass. This will enable hardware to include
2583 * the more precise offset calibrations, increasing precision of the generated
2586 * This cannot be done until hardware has measured the offsets, which requires
2587 * waiting until at least one packet has been sent and received by the device.
2589 enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port)
2591 enum ice_status status;
2594 status = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, &val);
2596 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, status %d\n",
2601 if (!(val & P_REG_TX_OV_STATUS_OV_M)) {
2602 ice_debug(hw, ICE_DBG_PTP, "Tx offset is not yet valid for port %u\n",
2604 return ICE_ERR_NOT_READY;
2607 status = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, &val);
2609 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, status %d\n",
2614 if (!(val & P_REG_TX_OV_STATUS_OV_M)) {
2615 ice_debug(hw, ICE_DBG_PTP, "Rx offset is not yet valid for port %u\n",
2617 return ICE_ERR_NOT_READY;
2620 status = ice_phy_cfg_tx_offset_e822(hw, port);
2622 ice_debug(hw, ICE_DBG_PTP, "Failed to program total Tx offset for port %u, status %d\n",
2627 status = ice_phy_cfg_rx_offset_e822(hw, port);
2629 ice_debug(hw, ICE_DBG_PTP, "Failed to program total Rx offset for port %u, status %d\n",
2634 /* Exit bypass mode now that the offset has been updated */
2635 status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
2637 ice_debug(hw, ICE_DBG_PTP, "Failed to read P_REG_PS for port %u, status %d\n",
2642 if (!(val & P_REG_PS_BYPASS_MODE_M))
2643 ice_debug(hw, ICE_DBG_PTP, "Port %u not in bypass mode\n",
2646 val &= ~P_REG_PS_BYPASS_MODE_M;
2647 status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2649 ice_debug(hw, ICE_DBG_PTP, "Failed to disable bypass for port %u, status %d\n",
2654 ice_info(hw, "Exiting bypass mode on PHY port %u\n", port);
2661 * The following functions operate on the E810 series devices which use
2662 * a separate external PHY.
2666 * ice_read_phy_reg_e810_lp - Read register from external PHY on E810
2667 * @hw: pointer to the HW struct
2668 * @addr: the address to read from
2669 * @val: On return, the value read from the PHY
2670 * @lock_sbq: true if the sideband queue lock must be acquired
2672 * Read a register from the external PHY on the E810 device.
2674 static enum ice_status
2675 ice_read_phy_reg_e810_lp(struct ice_hw *hw, u32 addr, u32 *val, bool lock_sbq)
2677 struct ice_sbq_msg_input msg = {0};
2678 enum ice_status status;
2680 msg.msg_addr_low = ICE_LO_WORD(addr);
2681 msg.msg_addr_high = ICE_HI_WORD(addr);
2682 msg.opcode = ice_sbq_msg_rd;
2683 msg.dest_dev = rmn_0;
2685 status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
2687 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
2697 static enum ice_status
2698 ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)
2700 return ice_read_phy_reg_e810_lp(hw, addr, val, true);
2704 * ice_write_phy_reg_e810_lp - Write register on external PHY on E810
2705 * @hw: pointer to the HW struct
2706 * @addr: the address to writem to
2707 * @val: the value to write to the PHY
2708 * @lock_sbq: true if the sideband queue lock must be acquired
2710 * Write a value to a register of the external PHY on the E810 device.
2712 static enum ice_status
2713 ice_write_phy_reg_e810_lp(struct ice_hw *hw, u32 addr, u32 val, bool lock_sbq)
2715 struct ice_sbq_msg_input msg = {0};
2716 enum ice_status status;
2718 msg.msg_addr_low = ICE_LO_WORD(addr);
2719 msg.msg_addr_high = ICE_HI_WORD(addr);
2720 msg.opcode = ice_sbq_msg_wr;
2721 msg.dest_dev = rmn_0;
2724 status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
2726 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
2734 static enum ice_status
2735 ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val)
2737 return ice_write_phy_reg_e810_lp(hw, addr, val, true);
2741 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY
2742 * @hw: pointer to the HW struct
2743 * @lport: the lport to read from
2744 * @idx: the timestamp index to read
2745 * @tstamp: on return, the 40bit timestamp value
2747 * Read a 40bit timestamp value out of the timestamp block of the external PHY
2748 * on the E810 device.
2750 static enum ice_status
2751 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
2753 enum ice_status status;
2754 u32 lo_addr, hi_addr, lo, hi;
2756 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
2757 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
2759 status = ice_read_phy_reg_e810(hw, lo_addr, &lo);
2761 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n",
2766 status = ice_read_phy_reg_e810(hw, hi_addr, &hi);
2768 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n",
2773 /* For E810 devices, the timestamp is reported with the lower 32 bits
2774 * in the low register, and the upper 8 bits in the high register.
2776 *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M);
2782 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY
2783 * @hw: pointer to the HW struct
2784 * @lport: the lport to read from
2785 * @idx: the timestamp index to reset
2787 * Clear a timestamp, resetting its valid bit, from the timestamp block of the
2788 * external PHY on the E810 device.
2790 static enum ice_status
2791 ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx)
2793 enum ice_status status;
2794 u32 lo_addr, hi_addr;
2796 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
2797 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
2799 status = ice_write_phy_reg_e810(hw, lo_addr, 0);
2801 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n",
2806 status = ice_write_phy_reg_e810(hw, hi_addr, 0);
2808 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n",
2817 * ice_ptp_init_phy_e810 - Enable PTP function on the external PHY
2818 * @hw: pointer to HW struct
2820 * Enable the timesync PTP functionality for the external PHY connected to
2823 * Note there is no equivalent function needed on E822 based devices.
2825 enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw)
2827 enum ice_status status;
2830 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2831 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx),
2832 GLTSYN_ENA_TSYN_ENA_M);
2834 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n",
2841 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
2842 * @hw: pointer to HW struct
2844 * Perform E810-specific PTP hardware clock initialization steps.
2846 static enum ice_status ice_ptp_init_phc_e810(struct ice_hw *hw)
2848 /* Ensure synchronization delay is zero */
2849 wr32(hw, GLTSYN_SYNC_DLAY, 0);
2851 /* Initialize the PHY */
2852 return ice_ptp_init_phy_e810(hw);
2856 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
2857 * @hw: Board private structure
2858 * @time: Time to initialize the PHY port clock to
2860 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the
2861 * initial clock time. The time will not actually be programmed until the
2862 * driver issues an INIT_TIME command.
2864 * The time value is the upper 32 bits of the PHY timer, usually in units of
2865 * nominal nanoseconds.
2867 static enum ice_status ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time)
2869 enum ice_status status;
2872 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2873 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
2875 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, status %d\n",
2880 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time);
2882 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, status %d\n",
2891 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment
2892 * @hw: pointer to HW struct
2893 * @adj: adjustment value to program
2894 * @lock_sbq: true if the sideband queue luck must be acquired
2896 * Prepare the PHY port for an atomic adjustment by programming the PHY
2897 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment
2898 * is completed by issuing an ADJ_TIME sync command.
2900 * The adjustment value only contains the portion used for the upper 32bits of
2901 * the PHY timer, usually in units of nominal nanoseconds. Negative
2902 * adjustments are supported using 2s complement arithmetic.
2904 static enum ice_status
2905 ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj, bool lock_sbq)
2907 enum ice_status status;
2910 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2912 /* Adjustments are represented as signed 2's complement values in
2913 * nanoseconds. Sub-nanosecond adjustment is not supported.
2915 status = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_SHADJ_L(tmr_idx),
2918 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, status %d\n",
2923 status = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_SHADJ_H(tmr_idx),
2926 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, status %d\n",
2935 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change
2936 * @hw: pointer to HW struct
2937 * @incval: The new 40bit increment value to prepare
2939 * Prepare the PHY port for a new increment value by programming the PHY
2940 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is
2941 * completed by issuing an INIT_INCVAL command.
2943 static enum ice_status
2944 ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
2946 enum ice_status status;
2950 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2951 low = ICE_LO_DWORD(incval);
2952 high = ICE_HI_DWORD(incval);
2954 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low);
2956 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, status %d\n",
2961 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high);
2963 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, status %d\n",
2972 * ice_ptp_prep_phy_adj_target_e810 - Prepare PHY port with adjust target
2973 * @hw: Board private structure
2974 * @target_time: Time to trigger the clock adjustment at
2976 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation for
2977 * a target time adjust, which will trigger an adjustment of the clock in the
2978 * future. The actual adjustment will occur the next time the PHY port timer
2979 * crosses over the provided value after the driver issues an ADJ_TIME_AT_TIME
2982 * The time value is the upper 32 bits of the PHY timer, usually in units of
2983 * nominal nanoseconds.
2985 static enum ice_status
2986 ice_ptp_prep_phy_adj_target_e810(struct ice_hw *hw, u32 target_time)
2988 enum ice_status status;
2991 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2992 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
2994 ice_debug(hw, ICE_DBG_PTP, "Failed to write target time to SHTIME_0, status %d\n",
2999 status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx),
3002 ice_debug(hw, ICE_DBG_PTP, "Failed to write target time to SHTIME_L, status %d\n",
3011 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command
3012 * @hw: pointer to HW struct
3013 * @cmd: Command to be sent to the port
3014 * @lock_sbq: true if the sideband queue lock must be acquired
3016 * Prepare the external PHYs connected to this device for a timer sync
3019 static enum ice_status
3020 ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
3023 enum ice_status status;
3028 cmd_val = GLTSYN_CMD_INIT_TIME;
3031 cmd_val = GLTSYN_CMD_INIT_INCVAL;
3034 cmd_val = GLTSYN_CMD_ADJ_TIME;
3036 case ADJ_TIME_AT_TIME:
3037 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
3040 cmd_val = GLTSYN_CMD_READ_TIME;
3043 ice_warn(hw, "Unknown timer command %u\n", cmd);
3044 return ICE_ERR_PARAM;
3047 /* Read, modify, write */
3048 status = ice_read_phy_reg_e810_lp(hw, ETH_GLTSYN_CMD, &val, lock_sbq);
3050 ice_debug(hw, ICE_DBG_PTP, "Failed to read GLTSYN_CMD, status %d\n",
3055 /* Modify necessary bits only and perform write */
3056 val &= ~TS_CMD_MASK_E810;
3059 status = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_CMD, val, lock_sbq);
3061 ice_debug(hw, ICE_DBG_PTP, "Failed to write back GLTSYN_CMD, status %d\n",
3069 /* Device agnostic functions
3071 * The following functions implement shared behavior common to both E822 and
3072 * E810 devices, possibly calling a device specific implementation where
3077 * ice_ptp_lock - Acquire PTP global semaphore register lock
3078 * @hw: pointer to the HW struct
3080 * Acquire the global PTP hardware semaphore lock. Returns true if the lock
3081 * was acquired, false otherwise.
3083 * The PFTSYN_SEM register sets the busy bit on read, returning the previous
3084 * value. If software sees the busy bit cleared, this means that this function
3085 * acquired the lock (and the busy bit is now set). If software sees the busy
3086 * bit set, it means that another function acquired the lock.
3088 * Software must clear the busy bit with a write to release the lock for other
3089 * functions when done.
3091 bool ice_ptp_lock(struct ice_hw *hw)
3098 for (i = 0; i < MAX_TRIES; i++) {
3099 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
3100 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M;
3102 /* Somebody is holding the lock */
3103 ice_msec_delay(10, true);
3114 * ice_ptp_unlock - Release PTP global semaphore register lock
3115 * @hw: pointer to the HW struct
3117 * Release the global PTP hardware semaphore lock. This is done by writing to
3118 * the PFTSYN_SEM register.
3120 void ice_ptp_unlock(struct ice_hw *hw)
3122 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);
3126 * ice_ptp_src_cmd - Prepare source timer for a timer command
3127 * @hw: pointer to HW structure
3128 * @cmd: Timer command
3130 * Prepare the source timer for an upcoming timer sync command.
3132 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
3137 tmr_idx = ice_get_ptp_src_clock_index(hw);
3138 cmd_val = tmr_idx << SEL_CPK_SRC;
3142 cmd_val |= GLTSYN_CMD_INIT_TIME;
3145 cmd_val |= GLTSYN_CMD_INIT_INCVAL;
3148 cmd_val |= GLTSYN_CMD_ADJ_TIME;
3150 case ADJ_TIME_AT_TIME:
3151 cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME;
3154 cmd_val |= GLTSYN_CMD_READ_TIME;
3157 ice_warn(hw, "Unknown timer command %u\n", cmd);
3161 wr32(hw, GLTSYN_CMD, cmd_val);
3165 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
3166 * @hw: pointer to HW struct
3167 * @cmd: the command to issue
3168 * @lock_sbq: true if the sideband queue lock must be acquired
3170 * Prepare the source timer and PHY timers and then trigger the requested
3171 * command. This causes the shadow registers previously written in preparation
3172 * for the command to be synchronously applied to both the source and PHY
3175 static enum ice_status
3176 ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
3178 enum ice_status status;
3180 /* First, prepare the source timer */
3181 ice_ptp_src_cmd(hw, cmd);
3183 /* Next, prepare the ports */
3184 if (ice_is_e810(hw))
3185 status = ice_ptp_port_cmd_e810(hw, cmd, lock_sbq);
3187 status = ice_ptp_port_cmd_e822(hw, cmd, lock_sbq);
3189 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, status %d\n",
3194 /* Write the sync command register to drive both source and PHY timer
3195 * commands synchronously
3197 ice_ptp_exec_tmr_cmd(hw);
3203 * ice_ptp_init_time - Initialize device time to provided value
3204 * @hw: pointer to HW struct
3205 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H)
3207 * Initialize the device to the specified time provided. This requires a three
3210 * 1) write the new init time to the source timer shadow registers
3211 * 2) write the new init time to the phy timer shadow registers
3212 * 3) issue an init_time timer command to synchronously switch both the source
3213 * and port timers to the new init time value at the next clock cycle.
3215 enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)
3217 enum ice_status status;
3220 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3223 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time));
3224 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time));
3225 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
3228 /* Fill Rx and Tx ports and send msg to PHY */
3229 if (ice_is_e810(hw))
3230 status = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
3232 status = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF);
3236 return ice_ptp_tmr_cmd(hw, INIT_TIME, true);
3240 * ice_ptp_write_incval - Program PHC with new increment value
3241 * @hw: pointer to HW struct
3242 * @incval: Source timer increment value per clock cycle
3244 * Program the PHC with a new increment value. This requires a three-step
3247 * 1) Write the increment value to the source timer shadow registers
3248 * 2) Write the increment value to the PHY timer shadow registers
3249 * 3) Issue an INIT_INCVAL timer command to synchronously switch both the
3250 * source and port timers to the new increment value at the next clock
3253 enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
3255 enum ice_status status;
3258 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3261 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval));
3262 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval));
3264 if (ice_is_e810(hw))
3265 status = ice_ptp_prep_phy_incval_e810(hw, incval);
3267 status = ice_ptp_prep_phy_incval_e822(hw, incval);
3271 return ice_ptp_tmr_cmd(hw, INIT_INCVAL, true);
3275 * ice_ptp_write_incval_locked - Program new incval while holding semaphore
3276 * @hw: pointer to HW struct
3277 * @incval: Source timer increment value per clock cycle
3279 * Program a new PHC incval while holding the PTP semaphore.
3281 enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)
3283 enum ice_status status;
3285 if (!ice_ptp_lock(hw))
3286 return ICE_ERR_NOT_READY;
3288 status = ice_ptp_write_incval(hw, incval);
3296 * ice_ptp_adj_clock - Adjust PHC clock time atomically
3297 * @hw: pointer to HW struct
3298 * @adj: Adjustment in nanoseconds
3299 * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
3300 * sq_lock has already been locked at a higher level
3302 * Perform an atomic adjustment of the PHC time by the specified number of
3303 * nanoseconds. This requires a three-step process:
3305 * 1) Write the adjustment to the source timer shadow registers
3306 * 2) Write the adjustment to the PHY timer shadow registers
3307 * 3) Issue an ADJ_TIME timer command to synchronously apply the adjustment to
3308 * both the source and port timers at the next clock cycle.
3310 enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)
3312 enum ice_status status;
3315 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3317 /* Write the desired clock adjustment into the GLTSYN_SHADJ register.
3318 * For an ADJ_TIME command, this set of registers represents the value
3319 * to add to the clock time. It supports subtraction by interpreting
3320 * the value as a 2's complement integer.
3322 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
3323 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
3325 if (ice_is_e810(hw))
3326 status = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq);
3328 status = ice_ptp_prep_phy_adj_e822(hw, adj, lock_sbq);
3332 return ice_ptp_tmr_cmd(hw, ADJ_TIME, lock_sbq);
3336 * ice_ptp_adj_clock_at_time - Adjust PHC atomically at specified time
3337 * @hw: pointer to HW struct
3338 * @at_time: Time in nanoseconds at which to perform the adjustment
3339 * @adj: Adjustment in nanoseconds
3341 * Perform an atomic adjustment to the PHC clock at the specified time. This
3342 * requires a five-step process:
3344 * 1) Write the adjustment to the source timer shadow adjust registers
3345 * 2) Write the target time to the source timer shadow time registers
3346 * 3) Write the adjustment to the PHY timers shadow adjust registers
3347 * 4) Write the target time to the PHY timers shadow adjust registers
3348 * 5) Issue an ADJ_TIME_AT_TIME command to initiate the atomic adjustment.
3351 ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)
3353 enum ice_status status;
3354 u32 time_lo, time_hi;
3357 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3358 time_lo = ICE_LO_DWORD(at_time);
3359 time_hi = ICE_HI_DWORD(at_time);
3361 /* Write the desired clock adjustment into the GLTSYN_SHADJ register.
3362 * For an ADJ_TIME_AT_TIME command, this set of registers represents
3363 * the value to add to the clock time. It supports subtraction by
3364 * interpreting the value as a 2's complement integer.
3366 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
3367 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
3369 /* Write the target time to trigger the adjustment for source clock */
3370 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
3371 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), time_lo);
3372 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), time_hi);
3374 /* Prepare PHY port adjustments */
3375 if (ice_is_e810(hw))
3376 status = ice_ptp_prep_phy_adj_e810(hw, adj, true);
3378 status = ice_ptp_prep_phy_adj_e822(hw, adj, true);
3382 /* Set target time for each PHY port */
3383 if (ice_is_e810(hw))
3384 status = ice_ptp_prep_phy_adj_target_e810(hw, time_lo);
3386 status = ice_ptp_prep_phy_adj_target_e822(hw, time_lo);
3390 return ice_ptp_tmr_cmd(hw, ADJ_TIME_AT_TIME, true);
3394 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block
3395 * @hw: pointer to the HW struct
3396 * @block: the block to read from
3397 * @idx: the timestamp index to read
3398 * @tstamp: on return, the 40bit timestamp value
3400 * Read a 40bit timestamp value out of the timestamp block. For E822 devices,
3401 * the block is the quad to read from. For E810 devices, the block is the
3402 * logical port to read from.
3405 ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
3407 if (ice_is_e810(hw))
3408 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
3410 return ice_read_phy_tstamp_e822(hw, block, idx, tstamp);
3414 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block
3415 * @hw: pointer to the HW struct
3416 * @block: the block to read from
3417 * @idx: the timestamp index to reset
3419 * Clear a timestamp, resetting its valid bit, from the timestamp block. For
3420 * E822 devices, the block is the quad to clear from. For E810 devices, the
3421 * block is the logical port to clear from.
3424 ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
3426 if (ice_is_e810(hw))
3427 return ice_clear_phy_tstamp_e810(hw, block, idx);
3429 return ice_clear_phy_tstamp_e822(hw, block, idx);
3433 * ice_ptp_init_phc - Initialize PTP hardware clock
3434 * @hw: pointer to the HW struct
3436 * Perform the steps required to initialize the PTP hardware clock.
3438 enum ice_status ice_ptp_init_phc(struct ice_hw *hw)
3440 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3442 /* Enable source clocks */
3443 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);
3445 /* Clear event status indications for auxiliary pins */
3446 (void)rd32(hw, GLTSYN_STAT(src_idx));
3448 if (ice_is_e810(hw))
3449 return ice_ptp_init_phc_e810(hw);
3451 return ice_ptp_init_phc_e822(hw);