1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
25 enum ice_ptp_link_spd {
29 ICE_PTP_LNK_SPD_25G_RS,
32 ICE_PTP_LNK_SPD_50G_RS,
33 ICE_PTP_LNK_SPD_100G_RS,
34 NUM_ICE_PTP_LNK_SPD /* Must be last */
37 enum ice_ptp_fec_mode {
38 ICE_PTP_FEC_MODE_NONE,
39 ICE_PTP_FEC_MODE_CLAUSE74,
40 ICE_PTP_FEC_MODE_RS_FEC
44 * struct ice_time_ref_info_e822
45 * @pll_freq: Frequency of PLL that drives timer ticks in Hz
46 * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
47 * @pps_delay: propagation delay of the PPS output signal
49 * Characteristic information for the various TIME_REF sources possible in the
52 struct ice_time_ref_info_e822 {
59 * struct ice_vernier_info_e822
60 * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
61 * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
62 * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
63 * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
64 * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
65 * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
66 * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
67 * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
68 * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
69 * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
70 * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
72 * Table of constants used during as part of the Vernier calibration of the Tx
73 * and Rx timestamps. This includes frequency values used to compute TUs per
74 * PAR/PCS clock cycle, and static delay values measured during hardware
77 * Note that some values are not used for all link speeds, and the
78 * P_REG_DESK_PAR* registers may represent different clock markers at
79 * different link speeds, either the deskew marker for multi-lane link speeds
80 * or the Reed Solomon gearbox marker for RS-FEC.
82 struct ice_vernier_info_e822 {
97 * struct ice_cgu_pll_params_e822
98 * @refclk_pre_div: Reference clock pre-divisor
99 * @feedback_div: Feedback divisor
100 * @frac_n_div: Fractional divisor
101 * @post_pll_div: Post PLL divisor
103 * Clock Generation Unit parameters used to program the PLL based on the
104 * selected TIME_REF frequency.
106 struct ice_cgu_pll_params_e822 {
114 ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
116 /* Table of constants related to possible TIME_REF sources */
117 extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];
119 /* Table of constants for Vernier calibration on E822 */
120 extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD];
122 /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
123 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
125 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
127 /* Device agnostic functions */
128 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
129 u64 ice_ptp_read_src_incval(struct ice_hw *hw);
130 bool ice_ptp_lock(struct ice_hw *hw);
131 void ice_ptp_unlock(struct ice_hw *hw);
132 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);
133 enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time);
134 enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
135 enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
136 enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq);
138 ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj);
140 ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
142 ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
143 enum ice_status ice_ptp_init_phc(struct ice_hw *hw);
145 /* E822 family functions */
147 ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val);
149 ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val);
151 ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
153 ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
155 ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time,
158 ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port, u64 *incval);
160 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts);
162 ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
165 ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
166 enum ice_clk_src clk_src);
169 * ice_e822_time_ref - Get the current TIME_REF from capabilities
170 * @hw: pointer to the HW structure
172 * Returns the current TIME_REF from the capabilities structure.
174 static inline enum ice_time_ref_freq ice_e822_time_ref(struct ice_hw *hw)
176 return hw->func_caps.ts_func_info.time_ref;
180 * ice_set_e822_time_ref - Set new TIME_REF
181 * @hw: pointer to the HW structure
182 * @time_ref: new TIME_REF to set
184 * Update the TIME_REF in the capabilities structure in response to some
185 * change, such as an update to the CGU registers.
188 ice_set_e822_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
190 hw->func_caps.ts_func_info.time_ref = time_ref;
193 static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref)
195 return e822_time_ref[time_ref].pll_freq;
198 static inline u64 ice_e822_nominal_incval(enum ice_time_ref_freq time_ref)
200 return e822_time_ref[time_ref].nominal_incval;
203 static inline u64 ice_e822_pps_delay(enum ice_time_ref_freq time_ref)
205 return e822_time_ref[time_ref].pps_delay;
208 /* E822 Vernier calibration functions */
209 enum ice_status ice_ptp_set_vernier_wl(struct ice_hw *hw);
211 ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
212 enum ice_ptp_link_spd *link_out,
213 enum ice_ptp_fec_mode *fec_out);
214 void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port);
216 ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);
218 ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass);
219 enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);
220 enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);
221 enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port);
223 /* E810 family functions */
224 enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw);
226 ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
228 ice_write_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 data);
229 enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
230 enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
231 bool ice_e810t_is_pca9575_present(struct ice_hw *hw);
233 #define PFTSYN_SEM_BYTES 4
235 #define ICE_PTP_CLOCK_INDEX_0 0x00
236 #define ICE_PTP_CLOCK_INDEX_1 0x01
238 /* PHY timer commands */
239 #define SEL_CPK_SRC 8
240 #define SEL_PHY_SRC 3
242 /* Time Sync command Definitions */
243 #define GLTSYN_CMD_INIT_TIME BIT(0)
244 #define GLTSYN_CMD_INIT_INCVAL BIT(1)
245 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
246 #define GLTSYN_CMD_ADJ_TIME BIT(2)
247 #define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))
248 #define GLTSYN_CMD_READ_TIME BIT(7)
250 /* PHY port Time Sync command definitions */
251 #define PHY_CMD_INIT_TIME BIT(0)
252 #define PHY_CMD_INIT_INCVAL BIT(1)
253 #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
254 #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
255 #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
257 #define TS_CMD_MASK_E810 0xFF
258 #define TS_CMD_MASK 0xF
259 #define SYNC_EXEC_CMD 0x3
261 /* Macros to derive port low and high addresses on both quads */
262 #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
263 #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
264 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
265 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
267 /* PHY QUAD register base addresses */
268 #define Q_0_BASE 0x94000
269 #define Q_1_BASE 0x114000
271 /* Timestamp memory reset registers */
272 #define Q_REG_TS_CTRL 0x618
273 #define Q_REG_TS_CTRL_S 0
274 #define Q_REG_TS_CTRL_M BIT(0)
276 /* Timestamp availability status registers */
277 #define Q_REG_TX_MEMORY_STATUS_L 0xCF0
278 #define Q_REG_TX_MEMORY_STATUS_U 0xCF4
280 /* Tx FIFO status registers */
281 #define Q_REG_FIFO23_STATUS 0xCF8
282 #define Q_REG_FIFO01_STATUS 0xCFC
283 #define Q_REG_FIFO02_S 0
284 #define Q_REG_FIFO02_M MAKEMASK(0x3FF, 0)
285 #define Q_REG_FIFO13_S 10
286 #define Q_REG_FIFO13_M MAKEMASK(0x3FF, 10)
288 /* Interrupt control Config registers */
289 #define Q_REG_TX_MEM_GBL_CFG 0xC08
290 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
291 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
292 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S 1
293 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M MAKEMASK(0xFF, 1)
294 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S 9
295 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M MAKEMASK(0x3F, 9)
296 #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S 15
297 #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
299 /* Tx Timestamp data registers */
300 #define Q_REG_TX_MEMORY_BANK_START 0xA00
302 /* PHY port register base addresses */
303 #define P_0_BASE 0x80000
304 #define P_4_BASE 0x106000
306 /* Timestamp init registers */
307 #define P_REG_RX_TIMER_INC_PRE_L 0x46C
308 #define P_REG_RX_TIMER_INC_PRE_U 0x470
309 #define P_REG_TX_TIMER_INC_PRE_L 0x44C
310 #define P_REG_TX_TIMER_INC_PRE_U 0x450
312 /* Timestamp match and adjust target registers */
313 #define P_REG_RX_TIMER_CNT_ADJ_L 0x474
314 #define P_REG_RX_TIMER_CNT_ADJ_U 0x478
315 #define P_REG_TX_TIMER_CNT_ADJ_L 0x454
316 #define P_REG_TX_TIMER_CNT_ADJ_U 0x458
318 /* Timestamp capture registers */
319 #define P_REG_RX_CAPTURE_L 0x4D8
320 #define P_REG_RX_CAPTURE_U 0x4DC
321 #define P_REG_TX_CAPTURE_L 0x4B4
322 #define P_REG_TX_CAPTURE_U 0x4B8
324 /* Timestamp PHY incval registers */
325 #define P_REG_TIMETUS_L 0x410
326 #define P_REG_TIMETUS_U 0x414
328 #define P_REG_40B_LOW_M 0xFF
329 #define P_REG_40B_HIGH_S 8
331 /* PHY window length registers */
332 #define P_REG_WL 0x40C
334 #define PTP_VERNIER_WL 0x111ed
336 /* PHY start registers */
337 #define P_REG_PS 0x408
338 #define P_REG_PS_START_S 0
339 #define P_REG_PS_START_M BIT(0)
340 #define P_REG_PS_BYPASS_MODE_S 1
341 #define P_REG_PS_BYPASS_MODE_M BIT(1)
342 #define P_REG_PS_ENA_CLK_S 2
343 #define P_REG_PS_ENA_CLK_M BIT(2)
344 #define P_REG_PS_LOAD_OFFSET_S 3
345 #define P_REG_PS_LOAD_OFFSET_M BIT(3)
346 #define P_REG_PS_SFT_RESET_S 11
347 #define P_REG_PS_SFT_RESET_M BIT(11)
349 /* PHY offset valid registers */
350 #define P_REG_TX_OV_STATUS 0x4D4
351 #define P_REG_TX_OV_STATUS_OV_S 0
352 #define P_REG_TX_OV_STATUS_OV_M BIT(0)
353 #define P_REG_RX_OV_STATUS 0x4F8
354 #define P_REG_RX_OV_STATUS_OV_S 0
355 #define P_REG_RX_OV_STATUS_OV_M BIT(0)
357 /* PHY offset ready registers */
358 #define P_REG_TX_OR 0x45C
359 #define P_REG_RX_OR 0x47C
361 /* PHY total offset registers */
362 #define P_REG_TOTAL_RX_OFFSET_L 0x460
363 #define P_REG_TOTAL_RX_OFFSET_U 0x464
364 #define P_REG_TOTAL_TX_OFFSET_L 0x440
365 #define P_REG_TOTAL_TX_OFFSET_U 0x444
367 /* Timestamp PAR/PCS registers */
368 #define P_REG_UIX66_10G_40G_L 0x480
369 #define P_REG_UIX66_10G_40G_U 0x484
370 #define P_REG_UIX66_25G_100G_L 0x488
371 #define P_REG_UIX66_25G_100G_U 0x48C
372 #define P_REG_DESK_PAR_RX_TUS_L 0x490
373 #define P_REG_DESK_PAR_RX_TUS_U 0x494
374 #define P_REG_DESK_PAR_TX_TUS_L 0x498
375 #define P_REG_DESK_PAR_TX_TUS_U 0x49C
376 #define P_REG_DESK_PCS_RX_TUS_L 0x4A0
377 #define P_REG_DESK_PCS_RX_TUS_U 0x4A4
378 #define P_REG_DESK_PCS_TX_TUS_L 0x4A8
379 #define P_REG_DESK_PCS_TX_TUS_U 0x4AC
380 #define P_REG_PAR_RX_TUS_L 0x420
381 #define P_REG_PAR_RX_TUS_U 0x424
382 #define P_REG_PAR_TX_TUS_L 0x428
383 #define P_REG_PAR_TX_TUS_U 0x42C
384 #define P_REG_PCS_RX_TUS_L 0x430
385 #define P_REG_PCS_RX_TUS_U 0x434
386 #define P_REG_PCS_TX_TUS_L 0x438
387 #define P_REG_PCS_TX_TUS_U 0x43C
388 #define P_REG_PAR_RX_TIME_L 0x4F0
389 #define P_REG_PAR_RX_TIME_U 0x4F4
390 #define P_REG_PAR_TX_TIME_L 0x4CC
391 #define P_REG_PAR_TX_TIME_U 0x4D0
392 #define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
393 #define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
394 #define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
395 #define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
396 #define P_REG_LINK_SPEED 0x4FC
397 #define P_REG_LINK_SPEED_SERDES_S 0
398 #define P_REG_LINK_SPEED_SERDES_M MAKEMASK(0x7, 0)
399 #define P_REG_LINK_SPEED_FEC_MODE_S 3
400 #define P_REG_LINK_SPEED_FEC_MODE_M MAKEMASK(0x3, 3)
401 #define P_REG_LINK_SPEED_FEC_MODE(reg) \
402 (((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >> \
403 P_REG_LINK_SPEED_FEC_MODE_S)
405 /* PHY timestamp related registers */
406 #define P_REG_PMD_ALIGNMENT 0x0FC
407 #define P_REG_RX_80_TO_160_CNT 0x6FC
408 #define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
409 #define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
410 #define P_REG_RX_40_TO_160_CNT 0x8FC
411 #define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
412 #define P_REG_RX_40_TO_160_CNT_RXCYC_M MAKEMASK(0x3, 0)
414 /* Rx FIFO status registers */
415 #define P_REG_RX_OV_FS 0x4F8
416 #define P_REG_RX_OV_FS_FIFO_STATUS_S 2
417 #define P_REG_RX_OV_FS_FIFO_STATUS_M MAKEMASK(0x3FF, 2)
419 /* Timestamp command registers */
420 #define P_REG_TX_TMR_CMD 0x448
421 #define P_REG_RX_TMR_CMD 0x468
423 /* E810 timesync enable register */
424 #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
426 /* E810 shadow init time registers */
427 #define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
428 #define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
430 /* E810 shadow time adjust registers */
431 #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
432 #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
434 /* E810 timer command register */
435 #define ETH_GLTSYN_CMD 0x03000344
437 /* Source timer incval macros */
438 #define INCVAL_HIGH_M 0xFF
440 /* Timestamp block macros */
441 #define TS_LOW_M 0xFFFFFFFF
442 #define TS_HIGH_M 0xFF
445 #define TS_PHY_LOW_M 0xFF
446 #define TS_PHY_HIGH_M 0xFFFFFFFF
447 #define TS_PHY_HIGH_S 8
449 #define BYTES_PER_IDX_ADDR_L_U 8
450 #define BYTES_PER_IDX_ADDR_L 4
452 /* Internal PHY timestamp address */
453 #define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
454 #define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U + \
455 BYTES_PER_IDX_ADDR_L))
457 /* External PHY timestamp address */
458 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
459 ((idx) * BYTES_PER_IDX_ADDR_L_U))
461 #define LOW_TX_MEMORY_BANK_START 0x03090000
462 #define HIGH_TX_MEMORY_BANK_START 0x03090004
464 /* E810T PCA9575 IO controller registers */
465 #define ICE_PCA9575_P0_IN 0x0
466 #define ICE_PCA9575_P1_IN 0x1
467 #define ICE_PCA9575_P0_CFG 0x8
468 #define ICE_PCA9575_P1_CFG 0x9
469 #define ICE_PCA9575_P0_OUT 0xA
470 #define ICE_PCA9575_P1_OUT 0xB
472 /* E810T PCA9575 IO controller pin control */
473 #define ICE_E810T_P0_GNSS_PRSNT_N BIT(4)
474 #define ICE_E810T_P1_SMA1_DIR_EN BIT(4)
475 #define ICE_E810T_P1_SMA1_TX_EN BIT(5)
476 #define ICE_E810T_P1_SMA2_UFL2_RX_DIS BIT(3)
477 #define ICE_E810T_P1_SMA2_DIR_EN BIT(6)
478 #define ICE_E810T_P1_SMA2_TX_EN BIT(7)
480 #define ICE_E810T_SMA_MIN_BIT 3
481 #define ICE_E810T_SMA_MAX_BIT 7
482 #define ICE_E810T_P1_OFFSET 8
484 #endif /* _ICE_PTP_HW_H_ */