1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
8 #include "ice_common.h"
10 #define ICE_QGRP_LAYER_OFFSET 2
11 #define ICE_VSI_LAYER_OFFSET 4
12 #define ICE_AGG_LAYER_OFFSET 6
13 #define ICE_SCHED_INVAL_LAYER_NUM 0xFF
14 /* Burst size is a 12 bits register that is configured while creating the RL
15 * profile(s). MSB is a granularity bit and tells the granularity type
16 * 0 - LSB bits are in 64 bytes granularity
17 * 1 - LSB bits are in 1K bytes granularity
19 #define ICE_64_BYTE_GRANULARITY 0
20 #define ICE_KBYTE_GRANULARITY BIT(11)
21 #define ICE_MIN_BURST_SIZE_ALLOWED 64 /* In Bytes */
22 #define ICE_MAX_BURST_SIZE_ALLOWED \
23 ((BIT(11) - 1) * 1024) /* In Bytes */
24 #define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \
25 ((BIT(11) - 1) * 64) /* In Bytes */
26 #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY ICE_MAX_BURST_SIZE_ALLOWED
28 #define ICE_RL_PROF_ACCURACY_BYTES 128
29 #define ICE_RL_PROF_MULTIPLIER 10000
30 #define ICE_RL_PROF_TS_MULTIPLIER 32
31 #define ICE_RL_PROF_FRACTION 512
33 #define ICE_PSM_CLK_367MHZ_IN_HZ 367647059
34 #define ICE_PSM_CLK_416MHZ_IN_HZ 416666667
35 #define ICE_PSM_CLK_446MHZ_IN_HZ 446428571
36 #define ICE_PSM_CLK_390MHZ_IN_HZ 390625000
38 struct rl_profile_params {
45 /* BW rate limit profile parameters list entry along
46 * with bandwidth maintained per layer in port info
48 struct ice_aqc_rl_profile_info {
49 struct ice_aqc_rl_profile_elem profile;
50 struct LIST_ENTRY_TYPE list_entry;
51 u32 bw; /* requested */
52 u16 prof_id_ref; /* profile ID to node association ref count */
55 struct ice_sched_agg_vsi_info {
56 struct LIST_ENTRY_TYPE list_entry;
57 ice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
59 /* save aggregator VSI TC bitmap */
60 ice_declare_bitmap(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
63 struct ice_sched_agg_info {
64 struct LIST_HEAD_TYPE agg_vsi_list;
65 struct LIST_ENTRY_TYPE list_entry;
66 ice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
68 enum ice_agg_type agg_type;
69 /* bw_t_info saves aggregator BW information */
70 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
71 /* save aggregator TC bitmap */
72 ice_declare_bitmap(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
75 /* FW AQ command calls */
77 ice_aq_query_rl_profile(struct ice_hw *hw, u16 num_profiles,
78 struct ice_aqc_rl_profile_elem *buf, u16 buf_size,
79 struct ice_sq_cd *cd);
81 ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_nodes,
82 struct ice_aqc_cfg_l2_node_cgd_elem *buf, u16 buf_size,
83 struct ice_sq_cd *cd);
85 ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,
86 struct ice_aqc_txsched_elem_data *buf, u16 buf_size,
87 u16 *elems_ret, struct ice_sq_cd *cd);
88 enum ice_status ice_sched_init_port(struct ice_port_info *pi);
89 enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw);
90 void ice_sched_get_psm_clk_freq(struct ice_hw *hw);
92 /* Functions to cleanup scheduler SW DB */
93 void ice_sched_clear_port(struct ice_port_info *pi);
94 void ice_sched_cleanup_all(struct ice_hw *hw);
95 void ice_sched_clear_agg(struct ice_hw *hw);
97 /* Get a scheduling node from SW DB for given TEID */
98 struct ice_sched_node *ice_sched_get_node(struct ice_port_info *pi, u32 teid);
99 struct ice_sched_node *
100 ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid);
101 /* Add a scheduling node into SW DB for given info */
103 ice_sched_add_node(struct ice_port_info *pi, u8 layer,
104 struct ice_aqc_txsched_elem_data *info);
105 void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node);
106 struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc);
107 struct ice_sched_node *
108 ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
111 ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs,
112 u8 owner, bool enable);
113 enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle);
114 struct ice_sched_node *
115 ice_sched_get_vsi_node(struct ice_port_info *pi, struct ice_sched_node *tc_node,
117 bool ice_sched_is_tree_balanced(struct ice_hw *hw, struct ice_sched_node *node);
119 ice_aq_query_node_to_root(struct ice_hw *hw, u32 node_teid,
120 struct ice_aqc_txsched_elem_data *buf, u16 buf_size,
121 struct ice_sq_cd *cd);
123 /* Tx scheduler rate limiter functions */
125 ice_cfg_agg(struct ice_port_info *pi, u32 agg_id,
126 enum ice_agg_type agg_type, u8 tc_bitmap);
128 ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle,
130 enum ice_status ice_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id);
132 ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
133 u16 q_handle, enum ice_rl_type rl_type, u32 bw);
135 ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
136 u16 q_handle, enum ice_rl_type rl_type);
138 ice_cfg_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc,
139 enum ice_rl_type rl_type, u32 bw);
141 ice_cfg_tc_node_bw_dflt_lmt(struct ice_port_info *pi, u8 tc,
142 enum ice_rl_type rl_type);
144 ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
145 enum ice_rl_type rl_type, u32 bw);
147 ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
148 enum ice_rl_type rl_type);
150 ice_cfg_agg_bw_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,
151 enum ice_rl_type rl_type, u32 bw);
153 ice_cfg_agg_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,
154 enum ice_rl_type rl_type);
156 ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 min_bw,
157 u32 max_bw, u32 shared_bw);
159 ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle);
161 ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 min_bw,
162 u32 max_bw, u32 shared_bw);
164 ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id);
166 ice_cfg_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,
167 u32 min_bw, u32 max_bw, u32 shared_bw);
169 ice_cfg_agg_bw_no_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id,
172 ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,
175 ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap,
176 enum ice_rl_type rl_type, u8 *bw_alloc);
178 ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id,
179 u16 num_vsis, u16 *vsi_handle_arr,
180 u8 *node_prio, u8 tc);
182 ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap,
183 enum ice_rl_type rl_type, u8 *bw_alloc);
185 ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base,
186 struct ice_sched_node *node);
188 ice_sched_set_agg_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle);
190 ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id,
191 enum ice_agg_type agg_type, u8 tc,
192 enum ice_rl_type rl_type, u32 bw);
194 ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle,
195 u32 min_bw, u32 max_bw, u32 shared_bw);
197 ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 min_bw,
198 u32 max_bw, u32 shared_bw);
200 ice_sched_set_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id,
201 u8 tc, u32 min_bw, u32 max_bw,
204 ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi,
205 struct ice_sched_node *node, u8 priority);
207 ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
208 enum ice_rl_type rl_type, u8 bw_alloc);
209 enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
210 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw);
211 void ice_sched_replay_agg(struct ice_hw *hw);
212 enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi);
213 enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);
214 enum ice_status ice_sched_replay_root_node_bw(struct ice_port_info *pi);
216 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
218 #endif /* _ICE_SCHED_H_ */