1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
17 #define ICE_BYTES_PER_WORD 2
18 #define ICE_BYTES_PER_DWORD 4
19 #define ICE_MAX_TRAFFIC_CLASS 8
22 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
25 #include "ice_status.h"
26 #include "ice_hw_autogen.h"
27 #include "ice_devids.h"
28 #include "ice_osdep.h"
29 #include "ice_controlq.h"
30 #include "ice_lan_tx_rx.h"
31 #include "ice_flex_type.h"
32 #include "ice_protocol_type.h"
34 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
36 return ice_is_bit_set(&bitmap, tc);
40 #define DIV_64BIT(n, d) ((n) / (d))
41 #endif /* DIV_64BIT */
43 static inline u64 round_up_64bit(u64 a, u32 b)
45 return DIV_64BIT(((a) + (b) / 2), (b));
48 static inline u32 ice_round_to_num(u32 N, u32 R)
50 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
51 ((((N) + (R) - 1) / (R)) * (R)));
54 /* Driver always calls main vsi_handle first */
55 #define ICE_MAIN_VSI_HANDLE 0
57 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
58 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
60 /* Data type manipulation macros. */
61 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
62 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
63 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
65 /* debug masks - set these bits in hw->debug_mask to control output */
66 #define ICE_DBG_INIT BIT_ULL(1)
67 #define ICE_DBG_RELEASE BIT_ULL(2)
69 #define ICE_DBG_LINK BIT_ULL(4)
70 #define ICE_DBG_PHY BIT_ULL(5)
71 #define ICE_DBG_QCTX BIT_ULL(6)
72 #define ICE_DBG_NVM BIT_ULL(7)
73 #define ICE_DBG_LAN BIT_ULL(8)
74 #define ICE_DBG_FLOW BIT_ULL(9)
75 #define ICE_DBG_DCB BIT_ULL(10)
76 #define ICE_DBG_DIAG BIT_ULL(11)
77 #define ICE_DBG_FD BIT_ULL(12)
78 #define ICE_DBG_SW BIT_ULL(13)
79 #define ICE_DBG_SCHED BIT_ULL(14)
81 #define ICE_DBG_PKG BIT_ULL(16)
82 #define ICE_DBG_RES BIT_ULL(17)
83 #define ICE_DBG_AQ_MSG BIT_ULL(24)
84 #define ICE_DBG_AQ_DESC BIT_ULL(25)
85 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
86 #define ICE_DBG_AQ_CMD BIT_ULL(27)
87 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
89 ICE_DBG_AQ_DESC_BUF | \
92 #define ICE_DBG_USER BIT_ULL(31)
93 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
100 enum ice_aq_res_ids {
103 ICE_CHANGE_LOCK_RES_ID,
104 ICE_GLOBAL_CFG_LOCK_RES_ID
107 /* FW update timeout definitions are in milliseconds */
108 #define ICE_NVM_TIMEOUT 180000
109 #define ICE_CHANGE_LOCK_TIMEOUT 1000
110 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
112 enum ice_aq_res_access_type {
117 struct ice_driver_ver {
122 u8 driver_string[32];
141 enum ice_set_fc_aq_failures {
142 ICE_SET_FC_AQ_FAIL_NONE = 0,
143 ICE_SET_FC_AQ_FAIL_GET,
144 ICE_SET_FC_AQ_FAIL_SET,
145 ICE_SET_FC_AQ_FAIL_UPDATE
148 /* These are structs for managing the hardware information and the operations */
156 enum ice_media_type {
157 ICE_MEDIA_UNKNOWN = 0,
164 /* Software VSI types. */
169 #endif /* ADQ_SUPPORT */
172 struct ice_link_status {
173 /* Refer to ice_aq_phy_type for bits definition */
176 u8 topo_media_conflict;
180 u8 lse_ena; /* Link Status Event notification */
186 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
187 * ice_aqc_get_phy_caps structure
189 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
192 /* Different data queue types: These are mainly for SW consumption. */
201 /* Different reset sources for which a disable queue AQ call has to be made in
202 * order to clean the Tx scheduler as a part of the reset
204 enum ice_disq_rst_src {
209 /* PHY info such as phy_type, etc... */
210 struct ice_phy_info {
211 struct ice_link_status link_info;
212 struct ice_link_status link_info_old;
215 enum ice_media_type media_type;
219 #define ICE_MAX_NUM_MIRROR_RULES 64
221 /* Common HW capabilities for SW use */
222 struct ice_hw_common_caps {
223 /* Write CSR protection */
226 /* switching mode supported - EVB switching (including cloud) */
227 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
229 /* Manageablity mode & supported protocols over MCTP */
231 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
232 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
233 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
235 u32 mgmt_protocols_mctp;
236 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
237 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
238 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
239 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
243 /* DCB capabilities */
244 u32 active_tc_bitmap;
247 /* RSS related capabilities */
248 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
249 u32 rss_table_entry_width; /* RSS Entry width in bits */
252 u32 num_rxq; /* Number/Total Rx queues */
253 u32 rxq_first_id; /* First queue ID for Rx queues */
254 u32 num_txq; /* Number/Total Tx queues */
255 u32 txq_first_id; /* First queue ID for Tx queues */
258 u32 num_msix_vectors;
259 u32 msix_vector_first_id;
261 /* Max MTU for function or device */
265 u32 num_wol_proxy_fltr;
266 u32 wol_proxy_vsi_seid;
268 /* LED/SDP pin count */
272 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
273 #define ICE_MAX_SUPPORTED_GPIO_LED 12
274 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
275 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
276 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
278 /* EVB capabilities */
279 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
280 u8 evb_802_1_qbh; /* Bridge Port Extension */
286 /* WoL and APM support */
287 #define ICE_WOL_SUPPORT_M BIT(0)
288 #define ICE_ACPI_PROG_MTHD_M BIT(1)
289 #define ICE_PROXY_SUPPORT_M BIT(2)
296 /* Function specific capabilities */
297 struct ice_hw_func_caps {
298 struct ice_hw_common_caps common_cap;
302 /* Device wide capabilities */
303 struct ice_hw_dev_caps {
304 struct ice_hw_common_caps common_cap;
305 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
309 /* Information about MAC such as address, etc... */
310 struct ice_mac_info {
311 u8 lan_addr[ETH_ALEN];
312 u8 perm_addr[ETH_ALEN];
313 u8 port_addr[ETH_ALEN];
314 u8 wol_addr[ETH_ALEN];
321 ice_bus_embedded, /* Is device Embedded versus card */
326 enum ice_pcie_bus_speed {
327 ice_pcie_speed_unknown = 0xff,
328 ice_pcie_speed_2_5GT = 0x14,
329 ice_pcie_speed_5_0GT = 0x15,
330 ice_pcie_speed_8_0GT = 0x16,
331 ice_pcie_speed_16_0GT = 0x17
335 enum ice_pcie_link_width {
336 ice_pcie_lnk_width_resrv = 0x00,
337 ice_pcie_lnk_x1 = 0x01,
338 ice_pcie_lnk_x2 = 0x02,
339 ice_pcie_lnk_x4 = 0x04,
340 ice_pcie_lnk_x8 = 0x08,
341 ice_pcie_lnk_x12 = 0x0C,
342 ice_pcie_lnk_x16 = 0x10,
343 ice_pcie_lnk_x32 = 0x20,
344 ice_pcie_lnk_width_unknown = 0xff,
347 /* Reset types used to determine which kind of reset was requested. These
348 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
349 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
350 * because its reset source is different than the other types listed.
362 struct ice_bus_info {
363 enum ice_pcie_bus_speed speed;
364 enum ice_pcie_link_width width;
365 enum ice_bus_type type;
372 /* Flow control (FC) parameters */
374 enum ice_fc_mode current_mode; /* FC mode in effect */
375 enum ice_fc_mode req_mode; /* FC mode requested by caller */
378 /* NVM Information */
379 struct ice_nvm_info {
380 u32 eetrack; /* NVM data version */
381 u32 oem_ver; /* OEM version info */
382 u16 sr_words; /* Shadow RAM size in words */
383 u16 ver; /* NVM package version */
384 u8 blank_nvm_mode; /* is NVM empty (no FW present)*/
387 /* Max number of port to queue branches w.r.t topology */
388 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
390 #define ice_for_each_traffic_class(_i) \
391 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
393 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
394 * to driver defined policy for default aggregator
396 #define ICE_INVAL_TEID 0xFFFFFFFF
397 #define ICE_DFLT_AGG_ID 0
399 struct ice_sched_node {
400 struct ice_sched_node *parent;
401 struct ice_sched_node *sibling; /* next sibling in the same layer */
402 struct ice_sched_node **children;
403 struct ice_aqc_txsched_elem_data info;
404 u32 agg_id; /* aggregator group ID */
406 u8 in_use; /* suspended or in use */
407 u8 tx_sched_layer; /* Logical Layer (1-9) */
411 #define ICE_SCHED_NODE_OWNER_LAN 0
412 #define ICE_SCHED_NODE_OWNER_AE 1
413 #define ICE_SCHED_NODE_OWNER_RDMA 2
416 /* Access Macros for Tx Sched Elements data */
417 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
418 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
419 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
420 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
421 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
422 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
423 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
424 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
425 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
426 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
427 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
429 struct ice_sched_rl_profle {
430 u32 rate; /* In Kbps */
431 struct ice_aqc_rl_profile_elem info;
434 /* The aggregator type determines if identifier is for a VSI group,
435 * aggregator group, aggregator of queues, or queue group.
438 ICE_AGG_TYPE_UNKNOWN = 0,
440 ICE_AGG_TYPE_AGG, /* aggregator */
446 /* Rate limit types */
449 ICE_MIN_BW, /* for CIR profile */
450 ICE_MAX_BW, /* for EIR profile */
451 ICE_SHARED_BW /* for shared profile */
454 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
455 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
456 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
457 #define ICE_SCHED_NO_PRIORITY 0
458 #define ICE_SCHED_NO_BW_WT 0
459 #define ICE_SCHED_DFLT_RL_PROF_ID 0
460 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
461 #define ICE_SCHED_DFLT_BW_WT 1
462 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
463 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
465 /* Access Macros for Tx Sched RL Profile data */
466 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
467 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
468 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
469 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
470 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
473 /* The following tree example shows the naming conventions followed under
474 * ice_port_info struct for default scheduler tree topology.
478 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
482 * / |-> num_elements (range:1 - 9)
483 * * | implies num_of_layers
487 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
488 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
489 * need TEID of (a) to add queues.
492 * -> has 8 branches (one for each TC)
493 * -> First branch (TC0) has 4 elements
495 * -> (a) is the topmost layer node created by firmware on branch 0
497 * Note: Above asterisk tree covers only basic terminology and scenario.
498 * Refer to the documentation for more info.
501 /* Data structure for saving BW information */
509 ICE_BW_TYPE_CNT /* This must be last */
517 struct ice_bw_type_info {
518 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
520 struct ice_bw cir_bw;
521 struct ice_bw eir_bw;
525 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
526 struct ice_sched_vsi_info {
527 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
528 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
529 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
530 /* bw_t_info saves VSI BW information */
531 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
534 /* CEE or IEEE 802.1Qaz ETS Configuration data */
535 struct ice_dcb_ets_cfg {
539 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
540 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
541 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
544 /* CEE or IEEE 802.1Qaz PFC Configuration data */
545 struct ice_dcb_pfc_cfg {
552 /* CEE or IEEE 802.1Qaz Application Priority data */
553 struct ice_dcb_app_priority_table {
559 #define ICE_MAX_USER_PRIORITY 8
560 #define ICE_DCBX_MAX_APPS 32
561 #define ICE_LLDPDU_SIZE 1500
562 #define ICE_TLV_STATUS_OPER 0x1
563 #define ICE_TLV_STATUS_SYNC 0x2
564 #define ICE_TLV_STATUS_ERR 0x4
565 #define ICE_APP_PROT_ID_FCOE 0x8906
566 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
567 #define ICE_APP_PROT_ID_FIP 0x8914
568 #define ICE_APP_SEL_ETHTYPE 0x1
569 #define ICE_APP_SEL_TCPIP 0x2
570 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
571 #define ICE_CEE_APP_SEL_TCPIP 0x1
573 struct ice_dcbx_cfg {
575 u32 tlv_status; /* CEE mode TLV status */
576 struct ice_dcb_ets_cfg etscfg;
577 struct ice_dcb_ets_cfg etsrec;
578 struct ice_dcb_pfc_cfg pfc;
579 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
581 #define ICE_DCBX_MODE_CEE 0x1
582 #define ICE_DCBX_MODE_IEEE 0x2
584 #define ICE_DCBX_APPS_NON_WILLING 0x1
587 struct ice_port_info {
588 struct ice_sched_node *root; /* Root Node per Port */
589 struct ice_hw *hw; /* back pointer to HW instance */
590 u32 last_node_teid; /* scheduler last node info */
591 u16 sw_id; /* Initial switch ID belongs to port */
594 #define ICE_SCHED_PORT_STATE_INIT 0x0
595 #define ICE_SCHED_PORT_STATE_READY 0x1
596 u16 dflt_tx_vsi_rule_id;
598 u16 dflt_rx_vsi_rule_id;
600 struct ice_fc_info fc;
601 struct ice_mac_info mac;
602 struct ice_phy_info phy;
603 struct ice_lock sched_lock; /* protect access to TXSched tree */
604 /* List contain profile ID(s) and other params per layer */
605 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
606 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
608 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
609 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
610 /* LLDP/DCBX Status */
614 #define ICE_LPORT_MASK 0xff
618 struct ice_switch_info {
619 struct LIST_HEAD_TYPE vsi_list_map_head;
620 struct ice_sw_recipe *recp_list;
623 /* FW logging configuration */
624 struct ice_fw_log_evnt {
625 u8 cfg : 4; /* New event enables to configure */
626 u8 cur : 4; /* Current/active event enables */
629 struct ice_fw_log_cfg {
630 u8 cq_en : 1; /* FW logging is enabled via the control queue */
631 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
632 u8 actv_evnts; /* Cumulation of currently enabled log events */
634 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
635 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
636 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
637 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
638 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
641 /* Port hardware description */
645 struct ice_aqc_layer_props *layer_info;
646 struct ice_port_info *port_info;
647 /* 2D Array for each Tx Sched RL Profile type */
648 struct ice_sched_rl_profile **cir_profiles;
649 struct ice_sched_rl_profile **eir_profiles;
650 struct ice_sched_rl_profile **srl_profiles;
651 u64 debug_mask; /* BITMAP for debug mask */
652 enum ice_mac_type mac_type;
657 u16 subsystem_device_id;
658 u16 subsystem_vendor_id;
661 u8 pf_id; /* device profile info */
663 u16 max_burst_size; /* driver sets this value */
664 /* Tx Scheduler values */
665 u16 num_tx_sched_layers;
666 u16 num_tx_sched_phys_layers;
669 u8 sw_entry_point_layer;
670 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
671 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
672 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
673 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
674 u8 evb_veb; /* true for VEB, false for VEPA */
675 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
676 struct ice_bus_info bus;
677 struct ice_nvm_info nvm;
678 struct ice_hw_dev_caps dev_caps; /* device capabilities */
679 struct ice_hw_func_caps func_caps; /* function capabilities */
681 struct ice_switch_info *switch_info; /* switch filter lists */
683 /* Control Queue info */
684 struct ice_ctl_q_info adminq;
685 struct ice_ctl_q_info mailboxq;
687 u8 api_branch; /* API branch version */
688 u8 api_maj_ver; /* API major version */
689 u8 api_min_ver; /* API minor version */
690 u8 api_patch; /* API patch version */
691 u8 fw_branch; /* firmware branch version */
692 u8 fw_maj_ver; /* firmware major version */
693 u8 fw_min_ver; /* firmware minor version */
694 u8 fw_patch; /* firmware patch version */
695 u32 fw_build; /* firmware build number */
697 struct ice_fw_log_cfg fw_log;
699 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
700 * register. Used for determining the itr/intrl granularity during
703 #define ICE_MAX_AGG_BW_200G 0x0
704 #define ICE_MAX_AGG_BW_100G 0X1
705 #define ICE_MAX_AGG_BW_50G 0x2
706 #define ICE_MAX_AGG_BW_25G 0x3
707 /* ITR granularity for different speeds */
708 #define ICE_ITR_GRAN_ABOVE_25 2
709 #define ICE_ITR_GRAN_MAX_25 4
710 /* ITR granularity in 1 us */
712 /* INTRL granularity for different speeds */
713 #define ICE_INTRL_GRAN_ABOVE_25 4
714 #define ICE_INTRL_GRAN_MAX_25 8
715 /* INTRL granularity in 1 us */
718 u8 ucast_shared; /* true if VSIs can share unicast addr */
720 /* Active package version (currently active) */
721 struct ice_pkg_ver active_pkg_ver;
722 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
724 /* Driver's package ver - (from the Metadata seg) */
725 struct ice_pkg_ver pkg_ver;
726 u8 pkg_name[ICE_PKG_NAME_SIZE];
728 /* Driver's Ice package version (from the Ice seg) */
729 struct ice_pkg_ver ice_pkg_ver;
730 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
732 /* Pointer to the ice segment */
735 /* Pointer to allocated copy of pkg memory */
740 struct ice_tunnel_table tnl;
742 #define ICE_PKG_FILENAME "package_file"
743 #define ICE_PKG_FILENAME_EXT "pkg"
744 #define ICE_PKG_FILE_MAJ_VER 1
745 #define ICE_PKG_FILE_MIN_VER 0
747 /* HW block tables */
748 struct ice_blk_info blk[ICE_BLK_COUNT];
749 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
750 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
753 /* Statistics collected by each port, VSI, VEB, and S-channel */
754 struct ice_eth_stats {
755 u64 rx_bytes; /* gorc */
756 u64 rx_unicast; /* uprc */
757 u64 rx_multicast; /* mprc */
758 u64 rx_broadcast; /* bprc */
759 u64 rx_discards; /* rdpc */
760 u64 rx_unknown_protocol; /* rupp */
761 u64 tx_bytes; /* gotc */
762 u64 tx_unicast; /* uptc */
763 u64 tx_multicast; /* mptc */
764 u64 tx_broadcast; /* bptc */
765 u64 tx_discards; /* tdpc */
766 u64 tx_errors; /* tepc */
771 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
772 struct ice_veb_up_stats {
773 u64 up_rx_pkts[ICE_MAX_UP];
774 u64 up_rx_bytes[ICE_MAX_UP];
775 u64 up_tx_pkts[ICE_MAX_UP];
776 u64 up_tx_bytes[ICE_MAX_UP];
779 /* Statistics collected by the MAC */
780 struct ice_hw_port_stats {
781 /* eth stats collected by the port */
782 struct ice_eth_stats eth;
783 /* additional port specific stats */
784 u64 tx_dropped_link_down; /* tdold */
785 u64 crc_errors; /* crcerrs */
786 u64 illegal_bytes; /* illerrc */
787 u64 error_bytes; /* errbc */
788 u64 mac_local_faults; /* mlfc */
789 u64 mac_remote_faults; /* mrfc */
790 u64 rx_len_errors; /* rlec */
791 u64 link_xon_rx; /* lxonrxc */
792 u64 link_xoff_rx; /* lxoffrxc */
793 u64 link_xon_tx; /* lxontxc */
794 u64 link_xoff_tx; /* lxofftxc */
795 u64 rx_size_64; /* prc64 */
796 u64 rx_size_127; /* prc127 */
797 u64 rx_size_255; /* prc255 */
798 u64 rx_size_511; /* prc511 */
799 u64 rx_size_1023; /* prc1023 */
800 u64 rx_size_1522; /* prc1522 */
801 u64 rx_size_big; /* prc9522 */
802 u64 rx_undersize; /* ruc */
803 u64 rx_fragments; /* rfc */
804 u64 rx_oversize; /* roc */
805 u64 rx_jabber; /* rjc */
806 u64 tx_size_64; /* ptc64 */
807 u64 tx_size_127; /* ptc127 */
808 u64 tx_size_255; /* ptc255 */
809 u64 tx_size_511; /* ptc511 */
810 u64 tx_size_1023; /* ptc1023 */
811 u64 tx_size_1522; /* ptc1522 */
812 u64 tx_size_big; /* ptc9522 */
813 u64 mac_short_pkt_dropped; /* mspdc */
816 enum ice_sw_fwd_act_type {
818 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
825 /* Checksum and Shadow RAM pointers */
826 #define ICE_SR_NVM_CTRL_WORD 0x00
827 #define ICE_SR_PHY_ANALOG_PTR 0x04
828 #define ICE_SR_OPTION_ROM_PTR 0x05
829 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
830 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
831 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
832 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
833 #define ICE_SR_EMP_IMAGE_PTR 0x0B
834 #define ICE_SR_PE_IMAGE_PTR 0x0C
835 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
836 #define ICE_SR_MNG_CFG_PTR 0x0E
837 #define ICE_SR_EMP_MODULE_PTR 0x0F
838 #define ICE_SR_PBA_FLAGS 0x15
839 #define ICE_SR_PBA_BLOCK_PTR 0x16
840 #define ICE_SR_BOOT_CFG_PTR 0x17
841 #define ICE_SR_NVM_WOL_CFG 0x19
842 #define ICE_NVM_OEM_VER_OFF 0x83
843 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
844 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
845 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
846 #define ICE_SR_NVM_MAP_VER 0x29
847 #define ICE_SR_NVM_IMAGE_VER 0x2A
848 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
849 #define ICE_SR_NVM_EETRACK_LO 0x2D
850 #define ICE_SR_NVM_EETRACK_HI 0x2E
851 #define ICE_NVM_VER_LO_SHIFT 0
852 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
853 #define ICE_NVM_VER_HI_SHIFT 12
854 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
855 #define ICE_OEM_EETRACK_ID 0xffffffff
856 #define ICE_OEM_VER_PATCH_SHIFT 0
857 #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT)
858 #define ICE_OEM_VER_BUILD_SHIFT 8
859 #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT)
860 #define ICE_OEM_VER_SHIFT 24
861 #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT)
862 #define ICE_SR_VPD_PTR 0x2F
863 #define ICE_SR_PXE_SETUP_PTR 0x30
864 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
865 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
866 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
867 #define ICE_SR_VLAN_CFG_PTR 0x37
868 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
869 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
870 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
871 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
872 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
873 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
874 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
875 #define ICE_SR_PFA_PTR 0x40
876 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
877 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
878 #define ICE_SR_NVM_BANK_SIZE 0x43
879 #define ICE_SR_1ND_OROM_BANK_PTR 0x44
880 #define ICE_SR_OROM_BANK_SIZE 0x45
881 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
882 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
883 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
885 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
886 #define ICE_SR_VPD_SIZE_WORDS 512
887 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
888 #define ICE_SR_CTRL_WORD_1_S 0x06
889 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
891 /* Shadow RAM related */
892 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
893 #define ICE_SR_BUF_ALIGNMENT 4096
894 #define ICE_SR_WORDS_IN_1KB 512
895 /* Checksum should be calculated such that after adding all the words,
896 * including the checksum word itself, the sum should be 0xBABA.
898 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
900 #define ICE_PBA_FLAG_DFLT 0xFAFA
901 /* Hash redirection LUT for VSI - maximum array size */
902 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
905 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
906 * This is needed to determine the BAR0 space for the VFs
908 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
909 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
910 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
912 #endif /* _ICE_TYPE_H_ */