1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
21 #define ICE_BYTES_PER_WORD 2
22 #define ICE_BYTES_PER_DWORD 4
23 #define ICE_MAX_TRAFFIC_CLASS 8
26 * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
27 * @a: value to round up
28 * @b: arbitrary multiple
30 * Round up to the next multiple of the arbitrary b.
31 * Note, when b is a power of 2 use ICE_ALIGN() instead.
33 #define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
35 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
37 #define IS_ASCII(_ch) ((_ch) < 0x80)
39 #include "ice_status.h"
40 #include "ice_hw_autogen.h"
41 #include "ice_devids.h"
42 #include "ice_osdep.h"
43 #include "ice_bitops.h" /* Must come before ice_controlq.h */
44 #include "ice_controlq.h"
45 #include "ice_lan_tx_rx.h"
46 #include "ice_flex_type.h"
47 #include "ice_protocol_type.h"
50 * ice_is_pow2 - check if integer value is a power of 2
51 * @val: unsigned integer to be validated
53 static inline bool ice_is_pow2(u64 val)
55 return (val && !(val & (val - 1)));
59 * ice_ilog2 - Calculates integer log base 2 of a number
60 * @n: number on which to perform operation
62 static inline int ice_ilog2(u64 n)
66 for (i = 63; i >= 0; i--)
67 if (((u64)1 << i) & n)
73 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
75 return ice_is_bit_set(&bitmap, tc);
78 #define DIV_64BIT(n, d) ((n) / (d))
80 static inline u64 round_up_64bit(u64 a, u32 b)
82 return DIV_64BIT(((a) + (b) / 2), (b));
85 static inline u32 ice_round_to_num(u32 N, u32 R)
87 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
88 ((((N) + (R) - 1) / (R)) * (R)));
91 /* Driver always calls main vsi_handle first */
92 #define ICE_MAIN_VSI_HANDLE 0
94 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
95 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
97 /* Data type manipulation macros. */
98 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
99 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
100 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
102 /* debug masks - set these bits in hw->debug_mask to control output */
103 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
104 #define ICE_DBG_INIT BIT_ULL(1)
105 #define ICE_DBG_RELEASE BIT_ULL(2)
106 #define ICE_DBG_FW_LOG BIT_ULL(3)
107 #define ICE_DBG_LINK BIT_ULL(4)
108 #define ICE_DBG_PHY BIT_ULL(5)
109 #define ICE_DBG_QCTX BIT_ULL(6)
110 #define ICE_DBG_NVM BIT_ULL(7)
111 #define ICE_DBG_LAN BIT_ULL(8)
112 #define ICE_DBG_FLOW BIT_ULL(9)
113 #define ICE_DBG_DCB BIT_ULL(10)
114 #define ICE_DBG_DIAG BIT_ULL(11)
115 #define ICE_DBG_FD BIT_ULL(12)
116 #define ICE_DBG_SW BIT_ULL(13)
117 #define ICE_DBG_SCHED BIT_ULL(14)
119 #define ICE_DBG_PKG BIT_ULL(16)
120 #define ICE_DBG_RES BIT_ULL(17)
121 #define ICE_DBG_AQ_MSG BIT_ULL(24)
122 #define ICE_DBG_AQ_DESC BIT_ULL(25)
123 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
124 #define ICE_DBG_AQ_CMD BIT_ULL(27)
125 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
127 ICE_DBG_AQ_DESC_BUF | \
130 #define ICE_DBG_USER BIT_ULL(31)
131 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
133 #ifndef __ALWAYS_UNUSED
134 #define __ALWAYS_UNUSED
137 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
138 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
139 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
140 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
142 enum ice_aq_res_ids {
145 ICE_CHANGE_LOCK_RES_ID,
146 ICE_GLOBAL_CFG_LOCK_RES_ID
149 /* FW update timeout definitions are in milliseconds */
150 #define ICE_NVM_TIMEOUT 180000
151 #define ICE_CHANGE_LOCK_TIMEOUT 1000
152 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
154 enum ice_aq_res_access_type {
159 struct ice_driver_ver {
164 u8 driver_string[32];
176 enum ice_phy_cache_mode {
189 struct ice_phy_cache_mode_data {
191 enum ice_fec_mode curr_user_fec_req;
192 enum ice_fc_mode curr_user_fc_req;
193 u16 curr_user_speed_req;
197 enum ice_set_fc_aq_failures {
198 ICE_SET_FC_AQ_FAIL_NONE = 0,
199 ICE_SET_FC_AQ_FAIL_GET,
200 ICE_SET_FC_AQ_FAIL_SET,
201 ICE_SET_FC_AQ_FAIL_UPDATE
204 /* These are structs for managing the hardware information and the operations */
212 enum ice_media_type {
213 ICE_MEDIA_UNKNOWN = 0,
220 /* Software VSI types. */
223 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
227 struct ice_link_status {
228 /* Refer to ice_aq_phy_type for bits definition */
231 u8 topo_media_conflict;
235 u8 lse_ena; /* Link Status Event notification */
241 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
242 * ice_aqc_get_phy_caps structure
244 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
247 /* Different data queue types: These are mainly for SW consumption. */
256 /* Different reset sources for which a disable queue AQ call has to be made in
257 * order to clean the Tx scheduler as a part of the reset
259 enum ice_disq_rst_src {
264 /* PHY info such as phy_type, etc... */
265 struct ice_phy_info {
266 struct ice_link_status link_info;
267 struct ice_link_status link_info_old;
270 enum ice_media_type media_type;
272 /* Please refer to struct ice_aqc_get_link_status_data to get
273 * detail of enable bit in curr_user_speed_req
275 u16 curr_user_speed_req;
276 enum ice_fec_mode curr_user_fec_req;
277 enum ice_fc_mode curr_user_fc_req;
278 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
281 #define ICE_MAX_NUM_MIRROR_RULES 64
283 /* protocol enumeration for filters */
284 enum ice_fltr_ptype {
285 /* NONE - used for undef/error */
286 ICE_FLTR_PTYPE_NONF_NONE = 0,
287 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
288 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
289 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
290 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
291 ICE_FLTR_PTYPE_FRAG_IPV4,
292 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
293 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
294 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
295 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
300 ICE_FD_HW_SEG_NON_TUN = 0,
305 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
306 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
308 struct ice_fd_hw_prof {
309 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
311 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
312 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
315 /* Common HW capabilities for SW use */
316 struct ice_hw_common_caps {
317 /* Write CSR protection */
320 /* switching mode supported - EVB switching (including cloud) */
321 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
323 /* Manageablity mode & supported protocols over MCTP */
325 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
326 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
327 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
329 u32 mgmt_protocols_mctp;
330 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
331 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
332 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
333 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
337 /* DCB capabilities */
338 u32 active_tc_bitmap;
341 /* RSS related capabilities */
342 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
343 u32 rss_table_entry_width; /* RSS Entry width in bits */
346 u32 num_rxq; /* Number/Total Rx queues */
347 u32 rxq_first_id; /* First queue ID for Rx queues */
348 u32 num_txq; /* Number/Total Tx queues */
349 u32 txq_first_id; /* First queue ID for Tx queues */
352 u32 num_msix_vectors;
353 u32 msix_vector_first_id;
355 /* Max MTU for function or device */
359 u32 num_wol_proxy_fltr;
360 u32 wol_proxy_vsi_seid;
362 /* LED/SDP pin count */
366 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
367 #define ICE_MAX_SUPPORTED_GPIO_LED 12
368 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
369 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
370 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
372 /* EVB capabilities */
373 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
374 u8 evb_802_1_qbh; /* Bridge Port Extension */
380 /* WoL and APM support */
381 #define ICE_WOL_SUPPORT_M BIT(0)
382 #define ICE_ACPI_PROG_MTHD_M BIT(1)
383 #define ICE_PROXY_SUPPORT_M BIT(2)
389 /* Function specific capabilities */
390 struct ice_hw_func_caps {
391 struct ice_hw_common_caps common_cap;
393 u32 fd_fltr_guar; /* Number of filters guaranteed */
394 u32 fd_fltr_best_effort; /* Number of best effort filters */
397 /* Device wide capabilities */
398 struct ice_hw_dev_caps {
399 struct ice_hw_common_caps common_cap;
400 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
401 u32 num_flow_director_fltr; /* Number of FD filters available */
405 /* Information about MAC such as address, etc... */
406 struct ice_mac_info {
407 u8 lan_addr[ETH_ALEN];
408 u8 perm_addr[ETH_ALEN];
409 u8 port_addr[ETH_ALEN];
410 u8 wol_addr[ETH_ALEN];
417 ice_bus_embedded, /* Is device Embedded versus card */
422 enum ice_pcie_bus_speed {
423 ice_pcie_speed_unknown = 0xff,
424 ice_pcie_speed_2_5GT = 0x14,
425 ice_pcie_speed_5_0GT = 0x15,
426 ice_pcie_speed_8_0GT = 0x16,
427 ice_pcie_speed_16_0GT = 0x17
431 enum ice_pcie_link_width {
432 ice_pcie_lnk_width_resrv = 0x00,
433 ice_pcie_lnk_x1 = 0x01,
434 ice_pcie_lnk_x2 = 0x02,
435 ice_pcie_lnk_x4 = 0x04,
436 ice_pcie_lnk_x8 = 0x08,
437 ice_pcie_lnk_x12 = 0x0C,
438 ice_pcie_lnk_x16 = 0x10,
439 ice_pcie_lnk_x32 = 0x20,
440 ice_pcie_lnk_width_unknown = 0xff,
443 /* Reset types used to determine which kind of reset was requested. These
444 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
445 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
446 * because its reset source is different than the other types listed.
458 struct ice_bus_info {
459 enum ice_pcie_bus_speed speed;
460 enum ice_pcie_link_width width;
461 enum ice_bus_type type;
468 /* Flow control (FC) parameters */
470 enum ice_fc_mode current_mode; /* FC mode in effect */
471 enum ice_fc_mode req_mode; /* FC mode requested by caller */
474 /* NVM Information */
475 struct ice_nvm_info {
476 u32 eetrack; /* NVM data version */
477 u32 oem_ver; /* OEM version info */
478 u16 sr_words; /* Shadow RAM size in words */
479 u16 ver; /* dev starter version */
480 u8 blank_nvm_mode; /* is NVM empty (no FW present)*/
483 #define ICE_NVM_VER_LEN 32
485 /* Max number of port to queue branches w.r.t topology */
486 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
488 #define ice_for_each_traffic_class(_i) \
489 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
491 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
492 * to driver defined policy for default aggregator
494 #define ICE_INVAL_TEID 0xFFFFFFFF
495 #define ICE_DFLT_AGG_ID 0
497 struct ice_sched_node {
498 struct ice_sched_node *parent;
499 struct ice_sched_node *sibling; /* next sibling in the same layer */
500 struct ice_sched_node **children;
501 struct ice_aqc_txsched_elem_data info;
502 u32 agg_id; /* aggregator group ID */
504 u8 in_use; /* suspended or in use */
505 u8 tx_sched_layer; /* Logical Layer (1-9) */
509 #define ICE_SCHED_NODE_OWNER_LAN 0
510 #define ICE_SCHED_NODE_OWNER_AE 1
511 #define ICE_SCHED_NODE_OWNER_RDMA 2
514 /* Access Macros for Tx Sched Elements data */
515 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
516 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
517 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
518 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
519 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
520 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
521 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
522 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
523 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
524 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
525 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
527 struct ice_sched_rl_profle {
528 u32 rate; /* In Kbps */
529 struct ice_aqc_rl_profile_elem info;
532 /* The aggregator type determines if identifier is for a VSI group,
533 * aggregator group, aggregator of queues, or queue group.
536 ICE_AGG_TYPE_UNKNOWN = 0,
538 ICE_AGG_TYPE_AGG, /* aggregator */
544 /* Rate limit types */
547 ICE_MIN_BW, /* for CIR profile */
548 ICE_MAX_BW, /* for EIR profile */
549 ICE_SHARED_BW /* for shared profile */
552 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
553 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
554 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
555 #define ICE_SCHED_NO_PRIORITY 0
556 #define ICE_SCHED_NO_BW_WT 0
557 #define ICE_SCHED_DFLT_RL_PROF_ID 0
558 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
559 #define ICE_SCHED_DFLT_BW_WT 1
560 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
561 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
563 /* Access Macros for Tx Sched RL Profile data */
564 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
565 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
566 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
567 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
568 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
570 /* The following tree example shows the naming conventions followed under
571 * ice_port_info struct for default scheduler tree topology.
575 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
579 * / |-> num_elements (range:1 - 9)
580 * * | implies num_of_layers
584 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
585 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
586 * need TEID of (a) to add queues.
589 * -> has 8 branches (one for each TC)
590 * -> First branch (TC0) has 4 elements
592 * -> (a) is the topmost layer node created by firmware on branch 0
594 * Note: Above asterisk tree covers only basic terminology and scenario.
595 * Refer to the documentation for more info.
598 /* Data structure for saving BW information */
606 ICE_BW_TYPE_CNT /* This must be last */
614 struct ice_bw_type_info {
615 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
617 struct ice_bw cir_bw;
618 struct ice_bw eir_bw;
622 /* VSI queue context structure for given TC */
626 /* bw_t_info saves queue BW information */
627 struct ice_bw_type_info bw_t_info;
630 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
631 struct ice_sched_vsi_info {
632 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
633 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
634 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
635 /* bw_t_info saves VSI BW information */
636 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
639 /* CEE or IEEE 802.1Qaz ETS Configuration data */
640 struct ice_dcb_ets_cfg {
644 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
645 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
646 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
649 /* CEE or IEEE 802.1Qaz PFC Configuration data */
650 struct ice_dcb_pfc_cfg {
657 /* CEE or IEEE 802.1Qaz Application Priority data */
658 struct ice_dcb_app_priority_table {
664 #define ICE_MAX_USER_PRIORITY 8
665 #define ICE_DCBX_MAX_APPS 32
666 #define ICE_LLDPDU_SIZE 1500
667 #define ICE_TLV_STATUS_OPER 0x1
668 #define ICE_TLV_STATUS_SYNC 0x2
669 #define ICE_TLV_STATUS_ERR 0x4
670 #define ICE_APP_PROT_ID_FCOE 0x8906
671 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
672 #define ICE_APP_PROT_ID_FIP 0x8914
673 #define ICE_APP_SEL_ETHTYPE 0x1
674 #define ICE_APP_SEL_TCPIP 0x2
675 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
676 #define ICE_CEE_APP_SEL_TCPIP 0x1
678 struct ice_dcbx_cfg {
680 u32 tlv_status; /* CEE mode TLV status */
681 struct ice_dcb_ets_cfg etscfg;
682 struct ice_dcb_ets_cfg etsrec;
683 struct ice_dcb_pfc_cfg pfc;
684 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
686 #define ICE_DCBX_MODE_CEE 0x1
687 #define ICE_DCBX_MODE_IEEE 0x2
689 #define ICE_DCBX_APPS_NON_WILLING 0x1
692 struct ice_port_info {
693 struct ice_sched_node *root; /* Root Node per Port */
694 struct ice_hw *hw; /* back pointer to HW instance */
695 u32 last_node_teid; /* scheduler last node info */
696 u16 sw_id; /* Initial switch ID belongs to port */
699 #define ICE_SCHED_PORT_STATE_INIT 0x0
700 #define ICE_SCHED_PORT_STATE_READY 0x1
702 #define ICE_LPORT_MASK 0xff
703 u16 dflt_tx_vsi_rule_id;
705 u16 dflt_rx_vsi_rule_id;
707 struct ice_fc_info fc;
708 struct ice_mac_info mac;
709 struct ice_phy_info phy;
710 struct ice_lock sched_lock; /* protect access to TXSched tree */
711 struct ice_sched_node *
712 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
713 /* List contain profile ID(s) and other params per layer */
714 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
715 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
716 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
718 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
719 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
720 /* LLDP/DCBX Status */
721 u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */
726 struct ice_switch_info {
727 struct LIST_HEAD_TYPE vsi_list_map_head;
728 struct ice_sw_recipe *recp_list;
731 /* Port hardware description */
735 struct ice_aqc_layer_props *layer_info;
736 struct ice_port_info *port_info;
737 /* 2D Array for each Tx Sched RL Profile type */
738 struct ice_sched_rl_profile **cir_profiles;
739 struct ice_sched_rl_profile **eir_profiles;
740 struct ice_sched_rl_profile **srl_profiles;
741 u64 debug_mask; /* BITMAP for debug mask */
742 enum ice_mac_type mac_type;
744 u16 fd_ctr_base; /* FD counter base index */
748 u16 subsystem_device_id;
749 u16 subsystem_vendor_id;
752 u8 pf_id; /* device profile info */
754 u16 max_burst_size; /* driver sets this value */
756 /* Tx Scheduler values */
757 u16 num_tx_sched_layers;
758 u16 num_tx_sched_phys_layers;
761 u8 sw_entry_point_layer;
762 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
763 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
764 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
765 u8 evb_veb; /* true for VEB, false for VEPA */
766 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
767 struct ice_bus_info bus;
768 struct ice_nvm_info nvm;
769 struct ice_hw_dev_caps dev_caps; /* device capabilities */
770 struct ice_hw_func_caps func_caps; /* function capabilities */
772 struct ice_switch_info *switch_info; /* switch filter lists */
774 /* Control Queue info */
775 struct ice_ctl_q_info adminq;
776 struct ice_ctl_q_info mailboxq;
778 u8 api_branch; /* API branch version */
779 u8 api_maj_ver; /* API major version */
780 u8 api_min_ver; /* API minor version */
781 u8 api_patch; /* API patch version */
782 u8 fw_branch; /* firmware branch version */
783 u8 fw_maj_ver; /* firmware major version */
784 u8 fw_min_ver; /* firmware minor version */
785 u8 fw_patch; /* firmware patch version */
786 u32 fw_build; /* firmware build number */
788 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
789 * register. Used for determining the ITR/INTRL granularity during
792 #define ICE_MAX_AGG_BW_200G 0x0
793 #define ICE_MAX_AGG_BW_100G 0X1
794 #define ICE_MAX_AGG_BW_50G 0x2
795 #define ICE_MAX_AGG_BW_25G 0x3
796 /* ITR granularity for different speeds */
797 #define ICE_ITR_GRAN_ABOVE_25 2
798 #define ICE_ITR_GRAN_MAX_25 4
799 /* ITR granularity in 1 us */
801 /* INTRL granularity for different speeds */
802 #define ICE_INTRL_GRAN_ABOVE_25 4
803 #define ICE_INTRL_GRAN_MAX_25 8
804 /* INTRL granularity in 1 us */
807 u8 ucast_shared; /* true if VSIs can share unicast addr */
809 /* Active package version (currently active) */
810 struct ice_pkg_ver active_pkg_ver;
811 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
812 u8 active_pkg_in_nvm;
814 enum ice_aq_err pkg_dwnld_status;
816 /* Driver's package ver - (from the Metadata seg) */
817 struct ice_pkg_ver pkg_ver;
818 u8 pkg_name[ICE_PKG_NAME_SIZE];
820 /* Driver's Ice package version (from the Ice seg) */
821 struct ice_pkg_ver ice_pkg_ver;
822 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
824 /* Pointer to the ice segment */
827 /* Pointer to allocated copy of pkg memory */
832 struct ice_tunnel_table tnl;
834 #define ICE_PKG_FILENAME "package_file"
835 #define ICE_PKG_FILENAME_EXT "pkg"
836 #define ICE_PKG_FILE_MAJ_VER 1
837 #define ICE_PKG_FILE_MIN_VER 0
839 /* HW block tables */
840 struct ice_blk_info blk[ICE_BLK_COUNT];
841 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
842 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
843 /* Flow Director filter info */
844 int fdir_active_fltr;
846 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
847 struct LIST_HEAD_TYPE fdir_list_head;
849 /* Book-keeping of side-band filter count per flow-type.
850 * This is used to detect and handle input set changes for
851 * respective flow-type.
853 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
855 struct ice_fd_hw_prof **fdir_prof;
856 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
857 struct ice_lock rss_locks; /* protect RSS configuration */
858 struct LIST_HEAD_TYPE rss_list_head;
861 /* Statistics collected by each port, VSI, VEB, and S-channel */
862 struct ice_eth_stats {
863 u64 rx_bytes; /* gorc */
864 u64 rx_unicast; /* uprc */
865 u64 rx_multicast; /* mprc */
866 u64 rx_broadcast; /* bprc */
867 u64 rx_discards; /* rdpc */
868 u64 rx_unknown_protocol; /* rupp */
869 u64 tx_bytes; /* gotc */
870 u64 tx_unicast; /* uptc */
871 u64 tx_multicast; /* mptc */
872 u64 tx_broadcast; /* bptc */
873 u64 tx_discards; /* tdpc */
874 u64 tx_errors; /* tepc */
875 u64 rx_no_desc; /* repc */
876 u64 rx_errors; /* repc */
881 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
882 struct ice_veb_up_stats {
883 u64 up_rx_pkts[ICE_MAX_UP];
884 u64 up_rx_bytes[ICE_MAX_UP];
885 u64 up_tx_pkts[ICE_MAX_UP];
886 u64 up_tx_bytes[ICE_MAX_UP];
889 /* Statistics collected by the MAC */
890 struct ice_hw_port_stats {
891 /* eth stats collected by the port */
892 struct ice_eth_stats eth;
893 /* additional port specific stats */
894 u64 tx_dropped_link_down; /* tdold */
895 u64 crc_errors; /* crcerrs */
896 u64 illegal_bytes; /* illerrc */
897 u64 error_bytes; /* errbc */
898 u64 mac_local_faults; /* mlfc */
899 u64 mac_remote_faults; /* mrfc */
900 u64 rx_len_errors; /* rlec */
901 u64 link_xon_rx; /* lxonrxc */
902 u64 link_xoff_rx; /* lxoffrxc */
903 u64 link_xon_tx; /* lxontxc */
904 u64 link_xoff_tx; /* lxofftxc */
905 u64 priority_xon_rx[8]; /* pxonrxc[8] */
906 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
907 u64 priority_xon_tx[8]; /* pxontxc[8] */
908 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
909 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
910 u64 rx_size_64; /* prc64 */
911 u64 rx_size_127; /* prc127 */
912 u64 rx_size_255; /* prc255 */
913 u64 rx_size_511; /* prc511 */
914 u64 rx_size_1023; /* prc1023 */
915 u64 rx_size_1522; /* prc1522 */
916 u64 rx_size_big; /* prc9522 */
917 u64 rx_undersize; /* ruc */
918 u64 rx_fragments; /* rfc */
919 u64 rx_oversize; /* roc */
920 u64 rx_jabber; /* rjc */
921 u64 tx_size_64; /* ptc64 */
922 u64 tx_size_127; /* ptc127 */
923 u64 tx_size_255; /* ptc255 */
924 u64 tx_size_511; /* ptc511 */
925 u64 tx_size_1023; /* ptc1023 */
926 u64 tx_size_1522; /* ptc1522 */
927 u64 tx_size_big; /* ptc9522 */
928 u64 mac_short_pkt_dropped; /* mspdc */
929 /* flow director stats */
934 enum ice_sw_fwd_act_type {
936 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
943 /* Checksum and Shadow RAM pointers */
944 #define ICE_SR_NVM_CTRL_WORD 0x00
945 #define ICE_SR_PHY_ANALOG_PTR 0x04
946 #define ICE_SR_OPTION_ROM_PTR 0x05
947 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
948 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
949 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
950 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
951 #define ICE_SR_EMP_IMAGE_PTR 0x0B
952 #define ICE_SR_PE_IMAGE_PTR 0x0C
953 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
954 #define ICE_SR_MNG_CFG_PTR 0x0E
955 #define ICE_SR_EMP_MODULE_PTR 0x0F
956 #define ICE_SR_PBA_BLOCK_PTR 0x16
957 #define ICE_SR_BOOT_CFG_PTR 0x132
958 #define ICE_SR_NVM_WOL_CFG 0x19
959 #define ICE_NVM_OEM_VER_OFF 0x02
960 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
961 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
962 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
963 #define ICE_SR_NVM_MAP_VER 0x29
964 #define ICE_SR_NVM_IMAGE_VER 0x2A
965 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
966 #define ICE_SR_NVM_EETRACK_LO 0x2D
967 #define ICE_SR_NVM_EETRACK_HI 0x2E
968 #define ICE_NVM_VER_LO_SHIFT 0
969 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
970 #define ICE_NVM_VER_HI_SHIFT 12
971 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
972 #define ICE_OEM_EETRACK_ID 0xffffffff
973 #define ICE_OEM_VER_PATCH_SHIFT 0
974 #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT)
975 #define ICE_OEM_VER_BUILD_SHIFT 8
976 #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT)
977 #define ICE_OEM_VER_SHIFT 24
978 #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT)
979 #define ICE_SR_VPD_PTR 0x2F
980 #define ICE_SR_PXE_SETUP_PTR 0x30
981 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
982 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
983 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
984 #define ICE_SR_VLAN_CFG_PTR 0x37
985 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
986 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
987 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
988 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
989 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
990 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
991 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
992 #define ICE_SR_PFA_PTR 0x40
993 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
994 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
995 #define ICE_SR_NVM_BANK_SIZE 0x43
996 #define ICE_SR_1ND_OROM_BANK_PTR 0x44
997 #define ICE_SR_OROM_BANK_SIZE 0x45
998 #define ICE_SR_NETLIST_BANK_PTR 0x46
999 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1000 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1001 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1002 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1003 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1005 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1006 #define ICE_SR_VPD_SIZE_WORDS 512
1007 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1008 #define ICE_SR_CTRL_WORD_1_S 0x06
1009 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1011 /* Shadow RAM related */
1012 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1013 #define ICE_SR_BUF_ALIGNMENT 4096
1014 #define ICE_SR_WORDS_IN_1KB 512
1015 /* Checksum should be calculated such that after adding all the words,
1016 * including the checksum word itself, the sum should be 0xBABA.
1018 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1020 #define ICE_PBA_FLAG_DFLT 0xFAFA
1021 /* Hash redirection LUT for VSI - maximum array size */
1022 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1025 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1026 * This is needed to determine the BAR0 space for the VFs
1028 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1029 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1030 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1032 #endif /* _ICE_TYPE_H_ */