1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
19 #define ICE_BYTES_PER_WORD 2
20 #define ICE_BYTES_PER_DWORD 4
21 #define ICE_MAX_TRAFFIC_CLASS 8
24 * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
25 * @a: value to round up
26 * @b: arbitrary multiple
28 * Round up to the next multiple of the arbitrary b.
29 * Note, when b is a power of 2 use ICE_ALIGN() instead.
31 #define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
33 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
35 #define IS_ASCII(_ch) ((_ch) < 0x80)
37 #define ice_struct_size(ptr, field, num) \
38 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
40 #include "ice_status.h"
41 #include "ice_hw_autogen.h"
42 #include "ice_devids.h"
43 #include "ice_osdep.h"
44 #include "ice_bitops.h" /* Must come before ice_controlq.h */
45 #include "ice_controlq.h"
46 #include "ice_lan_tx_rx.h"
47 #include "ice_flex_type.h"
48 #include "ice_protocol_type.h"
51 * ice_is_pow2 - check if integer value is a power of 2
52 * @val: unsigned integer to be validated
54 static inline bool ice_is_pow2(u64 val)
56 return (val && !(val & (val - 1)));
60 * ice_ilog2 - Calculates integer log base 2 of a number
61 * @n: number on which to perform operation
63 static inline int ice_ilog2(u64 n)
67 for (i = 63; i >= 0; i--)
68 if (((u64)1 << i) & n)
74 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
76 return ice_is_bit_set(&bitmap, tc);
79 #define DIV_64BIT(n, d) ((n) / (d))
81 static inline u64 round_up_64bit(u64 a, u32 b)
83 return DIV_64BIT(((a) + (b) / 2), (b));
86 static inline u32 ice_round_to_num(u32 N, u32 R)
88 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
89 ((((N) + (R) - 1) / (R)) * (R)));
92 /* Driver always calls main vsi_handle first */
93 #define ICE_MAIN_VSI_HANDLE 0
95 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
96 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
98 /* Data type manipulation macros. */
99 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
100 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
101 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
103 /* debug masks - set these bits in hw->debug_mask to control output */
104 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
105 #define ICE_DBG_INIT BIT_ULL(1)
106 #define ICE_DBG_RELEASE BIT_ULL(2)
107 #define ICE_DBG_FW_LOG BIT_ULL(3)
108 #define ICE_DBG_LINK BIT_ULL(4)
109 #define ICE_DBG_PHY BIT_ULL(5)
110 #define ICE_DBG_QCTX BIT_ULL(6)
111 #define ICE_DBG_NVM BIT_ULL(7)
112 #define ICE_DBG_LAN BIT_ULL(8)
113 #define ICE_DBG_FLOW BIT_ULL(9)
114 #define ICE_DBG_DCB BIT_ULL(10)
115 #define ICE_DBG_DIAG BIT_ULL(11)
116 #define ICE_DBG_FD BIT_ULL(12)
117 #define ICE_DBG_SW BIT_ULL(13)
118 #define ICE_DBG_SCHED BIT_ULL(14)
120 #define ICE_DBG_PKG BIT_ULL(16)
121 #define ICE_DBG_RES BIT_ULL(17)
122 #define ICE_DBG_AQ_MSG BIT_ULL(24)
123 #define ICE_DBG_AQ_DESC BIT_ULL(25)
124 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
125 #define ICE_DBG_AQ_CMD BIT_ULL(27)
126 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
128 ICE_DBG_AQ_DESC_BUF | \
131 #define ICE_DBG_USER BIT_ULL(31)
132 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
134 #define __ALWAYS_UNUSED
136 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
137 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
138 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
139 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
141 enum ice_aq_res_ids {
144 ICE_CHANGE_LOCK_RES_ID,
145 ICE_GLOBAL_CFG_LOCK_RES_ID
148 /* FW update timeout definitions are in milliseconds */
149 #define ICE_NVM_TIMEOUT 180000
150 #define ICE_CHANGE_LOCK_TIMEOUT 1000
151 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
153 enum ice_aq_res_access_type {
158 struct ice_driver_ver {
163 u8 driver_string[32];
176 enum ice_phy_cache_mode {
189 struct ice_phy_cache_mode_data {
191 enum ice_fec_mode curr_user_fec_req;
192 enum ice_fc_mode curr_user_fc_req;
193 u16 curr_user_speed_req;
197 enum ice_set_fc_aq_failures {
198 ICE_SET_FC_AQ_FAIL_NONE = 0,
199 ICE_SET_FC_AQ_FAIL_GET,
200 ICE_SET_FC_AQ_FAIL_SET,
201 ICE_SET_FC_AQ_FAIL_UPDATE
204 /* These are structs for managing the hardware information and the operations */
213 enum ice_media_type {
214 ICE_MEDIA_UNKNOWN = 0,
221 /* Software VSI types. */
224 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
228 struct ice_link_status {
229 /* Refer to ice_aq_phy_type for bits definition */
232 u8 topo_media_conflict;
236 u8 lse_ena; /* Link Status Event notification */
242 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
243 * ice_aqc_get_phy_caps structure
245 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
248 /* Different data queue types: These are mainly for SW consumption. */
257 /* Different reset sources for which a disable queue AQ call has to be made in
258 * order to clean the Tx scheduler as a part of the reset
260 enum ice_disq_rst_src {
265 /* PHY info such as phy_type, etc... */
266 struct ice_phy_info {
267 struct ice_link_status link_info;
268 struct ice_link_status link_info_old;
271 enum ice_media_type media_type;
273 /* Please refer to struct ice_aqc_get_link_status_data to get
274 * detail of enable bit in curr_user_speed_req
276 u16 curr_user_speed_req;
277 enum ice_fec_mode curr_user_fec_req;
278 enum ice_fc_mode curr_user_fc_req;
279 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
282 #define ICE_MAX_NUM_MIRROR_RULES 64
284 /* protocol enumeration for filters */
285 enum ice_fltr_ptype {
286 /* NONE - used for undef/error */
287 ICE_FLTR_PTYPE_NONF_NONE = 0,
288 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
289 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
290 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
291 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
292 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
293 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
294 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
295 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
296 ICE_FLTR_PTYPE_FRAG_IPV4,
297 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
298 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
299 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
300 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
305 ICE_FD_HW_SEG_NON_TUN = 0,
310 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
311 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
313 struct ice_fd_hw_prof {
314 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
316 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
317 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
320 /* Common HW capabilities for SW use */
321 struct ice_hw_common_caps {
322 /* Write CSR protection */
325 /* switching mode supported - EVB switching (including cloud) */
326 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
328 /* Manageablity mode & supported protocols over MCTP */
330 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
331 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
332 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
334 u32 mgmt_protocols_mctp;
335 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
336 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
337 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
338 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
342 /* DCB capabilities */
343 u32 active_tc_bitmap;
346 /* RSS related capabilities */
347 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
348 u32 rss_table_entry_width; /* RSS Entry width in bits */
351 u32 num_rxq; /* Number/Total Rx queues */
352 u32 rxq_first_id; /* First queue ID for Rx queues */
353 u32 num_txq; /* Number/Total Tx queues */
354 u32 txq_first_id; /* First queue ID for Tx queues */
357 u32 num_msix_vectors;
358 u32 msix_vector_first_id;
360 /* Max MTU for function or device */
364 u32 num_wol_proxy_fltr;
365 u32 wol_proxy_vsi_seid;
367 /* LED/SDP pin count */
371 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
372 #define ICE_MAX_SUPPORTED_GPIO_LED 12
373 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
374 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
375 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
377 /* EVB capabilities */
378 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
379 u8 evb_802_1_qbh; /* Bridge Port Extension */
385 /* WoL and APM support */
386 #define ICE_WOL_SUPPORT_M BIT(0)
387 #define ICE_ACPI_PROG_MTHD_M BIT(1)
388 #define ICE_PROXY_SUPPORT_M BIT(2)
394 /* Function specific capabilities */
395 struct ice_hw_func_caps {
396 struct ice_hw_common_caps common_cap;
398 u32 fd_fltr_guar; /* Number of filters guaranteed */
399 u32 fd_fltr_best_effort; /* Number of best effort filters */
402 /* Device wide capabilities */
403 struct ice_hw_dev_caps {
404 struct ice_hw_common_caps common_cap;
405 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
406 u32 num_flow_director_fltr; /* Number of FD filters available */
410 /* Information about MAC such as address, etc... */
411 struct ice_mac_info {
412 u8 lan_addr[ETH_ALEN];
413 u8 perm_addr[ETH_ALEN];
414 u8 port_addr[ETH_ALEN];
415 u8 wol_addr[ETH_ALEN];
422 ice_bus_embedded, /* Is device Embedded versus card */
427 enum ice_pcie_bus_speed {
428 ice_pcie_speed_unknown = 0xff,
429 ice_pcie_speed_2_5GT = 0x14,
430 ice_pcie_speed_5_0GT = 0x15,
431 ice_pcie_speed_8_0GT = 0x16,
432 ice_pcie_speed_16_0GT = 0x17
436 enum ice_pcie_link_width {
437 ice_pcie_lnk_width_resrv = 0x00,
438 ice_pcie_lnk_x1 = 0x01,
439 ice_pcie_lnk_x2 = 0x02,
440 ice_pcie_lnk_x4 = 0x04,
441 ice_pcie_lnk_x8 = 0x08,
442 ice_pcie_lnk_x12 = 0x0C,
443 ice_pcie_lnk_x16 = 0x10,
444 ice_pcie_lnk_x32 = 0x20,
445 ice_pcie_lnk_width_unknown = 0xff,
448 /* Reset types used to determine which kind of reset was requested. These
449 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
450 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
451 * because its reset source is different than the other types listed.
463 struct ice_bus_info {
464 enum ice_pcie_bus_speed speed;
465 enum ice_pcie_link_width width;
466 enum ice_bus_type type;
473 /* Flow control (FC) parameters */
475 enum ice_fc_mode current_mode; /* FC mode in effect */
476 enum ice_fc_mode req_mode; /* FC mode requested by caller */
479 /* Option ROM version information */
480 struct ice_orom_info {
481 u8 major; /* Major version of OROM */
482 u8 patch; /* Patch version of OROM */
483 u16 build; /* Build version of OROM */
486 /* NVM Information */
487 struct ice_nvm_info {
488 struct ice_orom_info orom; /* Option ROM version info */
489 u32 eetrack; /* NVM data version */
490 u16 sr_words; /* Shadow RAM size in words */
491 u8 major_ver; /* major version of dev starter */
492 u8 minor_ver; /* minor version of dev starter */
493 u8 blank_nvm_mode; /* is NVM empty (no FW present)*/
496 struct ice_link_default_override_tlv {
498 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
499 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
500 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
501 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
502 #define ICE_LINK_OVERRIDE_EN BIT(3)
503 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
504 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
506 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
507 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
508 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
509 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
510 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
512 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
518 #define ICE_NVM_VER_LEN 32
520 /* Max number of port to queue branches w.r.t topology */
521 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
523 #define ice_for_each_traffic_class(_i) \
524 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
526 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
527 * to driver defined policy for default aggregator
529 #define ICE_INVAL_TEID 0xFFFFFFFF
530 #define ICE_DFLT_AGG_ID 0
532 struct ice_sched_node {
533 struct ice_sched_node *parent;
534 struct ice_sched_node *sibling; /* next sibling in the same layer */
535 struct ice_sched_node **children;
536 struct ice_aqc_txsched_elem_data info;
537 u32 agg_id; /* aggregator group ID */
539 u8 in_use; /* suspended or in use */
540 u8 tx_sched_layer; /* Logical Layer (1-9) */
544 #define ICE_SCHED_NODE_OWNER_LAN 0
545 #define ICE_SCHED_NODE_OWNER_AE 1
546 #define ICE_SCHED_NODE_OWNER_RDMA 2
549 /* Access Macros for Tx Sched Elements data */
550 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
551 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
552 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
553 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
554 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
555 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
556 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
557 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
558 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
559 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
560 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
562 struct ice_sched_rl_profile {
563 u32 rate; /* In Kbps */
564 struct ice_aqc_rl_profile_elem info;
567 /* The aggregator type determines if identifier is for a VSI group,
568 * aggregator group, aggregator of queues, or queue group.
571 ICE_AGG_TYPE_UNKNOWN = 0,
573 ICE_AGG_TYPE_AGG, /* aggregator */
579 /* Rate limit types */
582 ICE_MIN_BW, /* for CIR profile */
583 ICE_MAX_BW, /* for EIR profile */
584 ICE_SHARED_BW /* for shared profile */
587 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
588 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
589 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
590 #define ICE_SCHED_NO_PRIORITY 0
591 #define ICE_SCHED_NO_BW_WT 0
592 #define ICE_SCHED_DFLT_RL_PROF_ID 0
593 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
594 #define ICE_SCHED_DFLT_BW_WT 1
595 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
596 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
598 /* Access Macros for Tx Sched RL Profile data */
599 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
600 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
601 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
602 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
603 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
605 /* The following tree example shows the naming conventions followed under
606 * ice_port_info struct for default scheduler tree topology.
610 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
614 * / |-> num_elements (range:1 - 9)
615 * * | implies num_of_layers
619 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
620 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
621 * need TEID of (a) to add queues.
624 * -> has 8 branches (one for each TC)
625 * -> First branch (TC0) has 4 elements
627 * -> (a) is the topmost layer node created by firmware on branch 0
629 * Note: Above asterisk tree covers only basic terminology and scenario.
630 * Refer to the documentation for more info.
633 /* Data structure for saving BW information */
641 ICE_BW_TYPE_CNT /* This must be last */
649 struct ice_bw_type_info {
650 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
652 struct ice_bw cir_bw;
653 struct ice_bw eir_bw;
657 /* VSI queue context structure for given TC */
661 /* bw_t_info saves queue BW information */
662 struct ice_bw_type_info bw_t_info;
665 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
666 struct ice_sched_vsi_info {
667 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
668 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
669 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
670 /* bw_t_info saves VSI BW information */
671 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
674 /* CEE or IEEE 802.1Qaz ETS Configuration data */
675 struct ice_dcb_ets_cfg {
679 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
680 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
681 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
684 /* CEE or IEEE 802.1Qaz PFC Configuration data */
685 struct ice_dcb_pfc_cfg {
692 /* CEE or IEEE 802.1Qaz Application Priority data */
693 struct ice_dcb_app_priority_table {
699 #define ICE_MAX_USER_PRIORITY 8
700 #define ICE_DCBX_MAX_APPS 32
701 #define ICE_LLDPDU_SIZE 1500
702 #define ICE_TLV_STATUS_OPER 0x1
703 #define ICE_TLV_STATUS_SYNC 0x2
704 #define ICE_TLV_STATUS_ERR 0x4
705 #define ICE_APP_PROT_ID_FCOE 0x8906
706 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
707 #define ICE_APP_PROT_ID_FIP 0x8914
708 #define ICE_APP_SEL_ETHTYPE 0x1
709 #define ICE_APP_SEL_TCPIP 0x2
710 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
711 #define ICE_CEE_APP_SEL_TCPIP 0x1
713 struct ice_dcbx_cfg {
715 u32 tlv_status; /* CEE mode TLV status */
716 struct ice_dcb_ets_cfg etscfg;
717 struct ice_dcb_ets_cfg etsrec;
718 struct ice_dcb_pfc_cfg pfc;
719 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
721 #define ICE_DCBX_MODE_CEE 0x1
722 #define ICE_DCBX_MODE_IEEE 0x2
724 #define ICE_DCBX_APPS_NON_WILLING 0x1
727 struct ice_port_info {
728 struct ice_sched_node *root; /* Root Node per Port */
729 struct ice_hw *hw; /* back pointer to HW instance */
730 u32 last_node_teid; /* scheduler last node info */
731 u16 sw_id; /* Initial switch ID belongs to port */
734 #define ICE_SCHED_PORT_STATE_INIT 0x0
735 #define ICE_SCHED_PORT_STATE_READY 0x1
737 #define ICE_LPORT_MASK 0xff
738 u16 dflt_tx_vsi_rule_id;
740 u16 dflt_rx_vsi_rule_id;
742 struct ice_fc_info fc;
743 struct ice_mac_info mac;
744 struct ice_phy_info phy;
745 struct ice_lock sched_lock; /* protect access to TXSched tree */
746 struct ice_sched_node *
747 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
748 /* List contain profile ID(s) and other params per layer */
749 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
750 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
751 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
753 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
754 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
755 /* LLDP/DCBX Status */
756 u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */
761 struct ice_switch_info {
762 struct LIST_HEAD_TYPE vsi_list_map_head;
763 struct ice_sw_recipe *recp_list;
764 u16 prof_res_bm_init;
766 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
769 /* Port hardware description */
773 struct ice_aqc_layer_props *layer_info;
774 struct ice_port_info *port_info;
775 /* 2D Array for each Tx Sched RL Profile type */
776 struct ice_sched_rl_profile **cir_profiles;
777 struct ice_sched_rl_profile **eir_profiles;
778 struct ice_sched_rl_profile **srl_profiles;
779 /* PSM clock frequency for calculating RL profile params */
781 u64 debug_mask; /* BITMAP for debug mask */
782 enum ice_mac_type mac_type;
784 u16 fd_ctr_base; /* FD counter base index */
788 u16 subsystem_device_id;
789 u16 subsystem_vendor_id;
792 u8 pf_id; /* device profile info */
794 u16 max_burst_size; /* driver sets this value */
796 /* Tx Scheduler values */
797 u8 num_tx_sched_layers;
798 u8 num_tx_sched_phys_layers;
801 u8 sw_entry_point_layer;
802 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
803 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
804 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
805 u8 evb_veb; /* true for VEB, false for VEPA */
806 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
807 struct ice_bus_info bus;
808 struct ice_nvm_info nvm;
809 struct ice_hw_dev_caps dev_caps; /* device capabilities */
810 struct ice_hw_func_caps func_caps; /* function capabilities */
812 struct ice_switch_info *switch_info; /* switch filter lists */
814 /* Control Queue info */
815 struct ice_ctl_q_info adminq;
816 struct ice_ctl_q_info mailboxq;
818 u8 api_branch; /* API branch version */
819 u8 api_maj_ver; /* API major version */
820 u8 api_min_ver; /* API minor version */
821 u8 api_patch; /* API patch version */
822 u8 fw_branch; /* firmware branch version */
823 u8 fw_maj_ver; /* firmware major version */
824 u8 fw_min_ver; /* firmware minor version */
825 u8 fw_patch; /* firmware patch version */
826 u32 fw_build; /* firmware build number */
828 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
829 * register. Used for determining the ITR/INTRL granularity during
832 #define ICE_MAX_AGG_BW_200G 0x0
833 #define ICE_MAX_AGG_BW_100G 0X1
834 #define ICE_MAX_AGG_BW_50G 0x2
835 #define ICE_MAX_AGG_BW_25G 0x3
836 /* ITR granularity for different speeds */
837 #define ICE_ITR_GRAN_ABOVE_25 2
838 #define ICE_ITR_GRAN_MAX_25 4
839 /* ITR granularity in 1 us */
841 /* INTRL granularity for different speeds */
842 #define ICE_INTRL_GRAN_ABOVE_25 4
843 #define ICE_INTRL_GRAN_MAX_25 8
844 /* INTRL granularity in 1 us */
847 u8 ucast_shared; /* true if VSIs can share unicast addr */
849 #define ICE_PHY_PER_NAC 1
850 #define ICE_MAX_QUAD 2
851 #define ICE_NUM_QUAD_TYPE 2
852 #define ICE_PORTS_PER_QUAD 4
853 #define ICE_PHY_0_LAST_QUAD 1
854 #define ICE_PORTS_PER_PHY 8
855 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
857 /* Active package version (currently active) */
858 struct ice_pkg_ver active_pkg_ver;
859 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
860 u8 active_pkg_in_nvm;
862 enum ice_aq_err pkg_dwnld_status;
864 /* Driver's package ver - (from the Metadata seg) */
865 struct ice_pkg_ver pkg_ver;
866 u8 pkg_name[ICE_PKG_NAME_SIZE];
868 /* Driver's Ice package version (from the Ice seg) */
869 struct ice_pkg_ver ice_pkg_ver;
870 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
872 /* Pointer to the ice segment */
875 /* Pointer to allocated copy of pkg memory */
880 struct ice_tunnel_table tnl;
882 /* HW block tables */
883 struct ice_blk_info blk[ICE_BLK_COUNT];
884 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
885 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
886 /* Flow Director filter info */
887 int fdir_active_fltr;
889 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
890 struct LIST_HEAD_TYPE fdir_list_head;
892 /* Book-keeping of side-band filter count per flow-type.
893 * This is used to detect and handle input set changes for
894 * respective flow-type.
896 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
898 struct ice_fd_hw_prof **fdir_prof;
899 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
900 struct ice_lock rss_locks; /* protect RSS configuration */
901 struct LIST_HEAD_TYPE rss_list_head;
904 /* Statistics collected by each port, VSI, VEB, and S-channel */
905 struct ice_eth_stats {
906 u64 rx_bytes; /* gorc */
907 u64 rx_unicast; /* uprc */
908 u64 rx_multicast; /* mprc */
909 u64 rx_broadcast; /* bprc */
910 u64 rx_discards; /* rdpc */
911 u64 rx_unknown_protocol; /* rupp */
912 u64 tx_bytes; /* gotc */
913 u64 tx_unicast; /* uptc */
914 u64 tx_multicast; /* mptc */
915 u64 tx_broadcast; /* bptc */
916 u64 tx_discards; /* tdpc */
917 u64 tx_errors; /* tepc */
918 u64 rx_no_desc; /* repc */
919 u64 rx_errors; /* repc */
924 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
925 struct ice_veb_up_stats {
926 u64 up_rx_pkts[ICE_MAX_UP];
927 u64 up_rx_bytes[ICE_MAX_UP];
928 u64 up_tx_pkts[ICE_MAX_UP];
929 u64 up_tx_bytes[ICE_MAX_UP];
932 /* Statistics collected by the MAC */
933 struct ice_hw_port_stats {
934 /* eth stats collected by the port */
935 struct ice_eth_stats eth;
936 /* additional port specific stats */
937 u64 tx_dropped_link_down; /* tdold */
938 u64 crc_errors; /* crcerrs */
939 u64 illegal_bytes; /* illerrc */
940 u64 error_bytes; /* errbc */
941 u64 mac_local_faults; /* mlfc */
942 u64 mac_remote_faults; /* mrfc */
943 u64 rx_len_errors; /* rlec */
944 u64 link_xon_rx; /* lxonrxc */
945 u64 link_xoff_rx; /* lxoffrxc */
946 u64 link_xon_tx; /* lxontxc */
947 u64 link_xoff_tx; /* lxofftxc */
948 u64 priority_xon_rx[8]; /* pxonrxc[8] */
949 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
950 u64 priority_xon_tx[8]; /* pxontxc[8] */
951 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
952 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
953 u64 rx_size_64; /* prc64 */
954 u64 rx_size_127; /* prc127 */
955 u64 rx_size_255; /* prc255 */
956 u64 rx_size_511; /* prc511 */
957 u64 rx_size_1023; /* prc1023 */
958 u64 rx_size_1522; /* prc1522 */
959 u64 rx_size_big; /* prc9522 */
960 u64 rx_undersize; /* ruc */
961 u64 rx_fragments; /* rfc */
962 u64 rx_oversize; /* roc */
963 u64 rx_jabber; /* rjc */
964 u64 tx_size_64; /* ptc64 */
965 u64 tx_size_127; /* ptc127 */
966 u64 tx_size_255; /* ptc255 */
967 u64 tx_size_511; /* ptc511 */
968 u64 tx_size_1023; /* ptc1023 */
969 u64 tx_size_1522; /* ptc1522 */
970 u64 tx_size_big; /* ptc9522 */
971 u64 mac_short_pkt_dropped; /* mspdc */
972 /* flow director stats */
977 enum ice_sw_fwd_act_type {
979 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
986 /* Checksum and Shadow RAM pointers */
987 #define ICE_SR_NVM_CTRL_WORD 0x00
988 #define ICE_SR_PHY_ANALOG_PTR 0x04
989 #define ICE_SR_OPTION_ROM_PTR 0x05
990 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
991 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
992 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
993 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
994 #define ICE_SR_EMP_IMAGE_PTR 0x0B
995 #define ICE_SR_PE_IMAGE_PTR 0x0C
996 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
997 #define ICE_SR_MNG_CFG_PTR 0x0E
998 #define ICE_SR_EMP_MODULE_PTR 0x0F
999 #define ICE_SR_PBA_BLOCK_PTR 0x16
1000 #define ICE_SR_BOOT_CFG_PTR 0x132
1001 #define ICE_SR_NVM_WOL_CFG 0x19
1002 #define ICE_NVM_OROM_VER_OFF 0x02
1003 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1004 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
1005 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
1006 #define ICE_SR_NVM_MAP_VER 0x29
1007 #define ICE_SR_NVM_IMAGE_VER 0x2A
1008 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
1009 #define ICE_SR_NVM_EETRACK_LO 0x2D
1010 #define ICE_SR_NVM_EETRACK_HI 0x2E
1011 #define ICE_NVM_VER_LO_SHIFT 0
1012 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1013 #define ICE_NVM_VER_HI_SHIFT 12
1014 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1015 #define ICE_OEM_EETRACK_ID 0xffffffff
1016 #define ICE_OROM_VER_PATCH_SHIFT 0
1017 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1018 #define ICE_OROM_VER_BUILD_SHIFT 8
1019 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1020 #define ICE_OROM_VER_SHIFT 24
1021 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1022 #define ICE_SR_VPD_PTR 0x2F
1023 #define ICE_SR_PXE_SETUP_PTR 0x30
1024 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
1025 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1026 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1027 #define ICE_SR_VLAN_CFG_PTR 0x37
1028 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1029 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1030 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1031 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1032 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
1033 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1034 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
1035 #define ICE_SR_PFA_PTR 0x40
1036 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
1037 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1038 #define ICE_SR_NVM_BANK_SIZE 0x43
1039 #define ICE_SR_1ND_OROM_BANK_PTR 0x44
1040 #define ICE_SR_OROM_BANK_SIZE 0x45
1041 #define ICE_SR_NETLIST_BANK_PTR 0x46
1042 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1043 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1044 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1045 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1046 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
1047 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1049 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1050 #define ICE_SR_VPD_SIZE_WORDS 512
1051 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1052 #define ICE_SR_CTRL_WORD_1_S 0x06
1053 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1055 /* Shadow RAM related */
1056 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1057 #define ICE_SR_BUF_ALIGNMENT 4096
1058 #define ICE_SR_WORDS_IN_1KB 512
1059 /* Checksum should be calculated such that after adding all the words,
1060 * including the checksum word itself, the sum should be 0xBABA.
1062 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1064 /* Link override related */
1065 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1066 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1067 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1068 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1069 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1070 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1071 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1072 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1074 #define ICE_PBA_FLAG_DFLT 0xFAFA
1075 /* Hash redirection LUT for VSI - maximum array size */
1076 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1079 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1080 * This is needed to determine the BAR0 space for the VFs
1082 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1083 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1084 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1086 #endif /* _ICE_TYPE_H_ */