1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
19 #define ICE_BYTES_PER_WORD 2
20 #define ICE_BYTES_PER_DWORD 4
21 #define ICE_MAX_TRAFFIC_CLASS 8
24 * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
25 * @a: value to round up
26 * @b: arbitrary multiple
28 * Round up to the next multiple of the arbitrary b.
29 * Note, when b is a power of 2 use ICE_ALIGN() instead.
31 #define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
33 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
35 #define IS_ASCII(_ch) ((_ch) < 0x80)
37 #define STRUCT_HACK_VAR_LEN
39 * ice_struct_size - size of struct with C99 flexible array member
40 * @ptr: pointer to structure
41 * @field: flexible array member (last member of the structure)
42 * @num: number of elements of that flexible array member
44 #define ice_struct_size(ptr, field, num) \
45 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
47 #include "ice_status.h"
48 #include "ice_hw_autogen.h"
49 #include "ice_devids.h"
50 #include "ice_osdep.h"
51 #include "ice_bitops.h" /* Must come before ice_controlq.h */
52 #include "ice_controlq.h"
53 #include "ice_lan_tx_rx.h"
54 #include "ice_flex_type.h"
55 #include "ice_protocol_type.h"
58 * ice_is_pow2 - check if integer value is a power of 2
59 * @val: unsigned integer to be validated
61 static inline bool ice_is_pow2(u64 val)
63 return (val && !(val & (val - 1)));
67 * ice_ilog2 - Calculates integer log base 2 of a number
68 * @n: number on which to perform operation
70 static inline int ice_ilog2(u64 n)
74 for (i = 63; i >= 0; i--)
75 if (((u64)1 << i) & n)
81 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
83 return ice_is_bit_set(&bitmap, tc);
86 #define DIV_64BIT(n, d) ((n) / (d))
88 static inline u64 round_up_64bit(u64 a, u32 b)
90 return DIV_64BIT(((a) + (b) / 2), (b));
93 static inline u32 ice_round_to_num(u32 N, u32 R)
95 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
96 ((((N) + (R) - 1) / (R)) * (R)));
99 /* Driver always calls main vsi_handle first */
100 #define ICE_MAIN_VSI_HANDLE 0
102 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
103 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
105 /* Data type manipulation macros. */
106 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
107 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
108 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
109 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF))
111 /* debug masks - set these bits in hw->debug_mask to control output */
112 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
113 #define ICE_DBG_INIT BIT_ULL(1)
114 #define ICE_DBG_RELEASE BIT_ULL(2)
115 #define ICE_DBG_FW_LOG BIT_ULL(3)
116 #define ICE_DBG_LINK BIT_ULL(4)
117 #define ICE_DBG_PHY BIT_ULL(5)
118 #define ICE_DBG_QCTX BIT_ULL(6)
119 #define ICE_DBG_NVM BIT_ULL(7)
120 #define ICE_DBG_LAN BIT_ULL(8)
121 #define ICE_DBG_FLOW BIT_ULL(9)
122 #define ICE_DBG_DCB BIT_ULL(10)
123 #define ICE_DBG_DIAG BIT_ULL(11)
124 #define ICE_DBG_FD BIT_ULL(12)
125 #define ICE_DBG_SW BIT_ULL(13)
126 #define ICE_DBG_SCHED BIT_ULL(14)
128 #define ICE_DBG_PKG BIT_ULL(16)
129 #define ICE_DBG_RES BIT_ULL(17)
130 #define ICE_DBG_ACL BIT_ULL(18)
131 #define ICE_DBG_AQ_MSG BIT_ULL(24)
132 #define ICE_DBG_AQ_DESC BIT_ULL(25)
133 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
134 #define ICE_DBG_AQ_CMD BIT_ULL(27)
135 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
137 ICE_DBG_AQ_DESC_BUF | \
140 #define ICE_DBG_USER BIT_ULL(31)
141 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
143 #define __ALWAYS_UNUSED
145 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
146 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
147 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
148 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
150 enum ice_aq_res_ids {
153 ICE_CHANGE_LOCK_RES_ID,
154 ICE_GLOBAL_CFG_LOCK_RES_ID
157 /* FW update timeout definitions are in milliseconds */
158 #define ICE_NVM_TIMEOUT 180000
159 #define ICE_CHANGE_LOCK_TIMEOUT 1000
160 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
162 enum ice_aq_res_access_type {
167 struct ice_driver_ver {
172 u8 driver_string[32];
185 enum ice_phy_cache_mode {
198 struct ice_phy_cache_mode_data {
200 enum ice_fec_mode curr_user_fec_req;
201 enum ice_fc_mode curr_user_fc_req;
202 u16 curr_user_speed_req;
206 enum ice_set_fc_aq_failures {
207 ICE_SET_FC_AQ_FAIL_NONE = 0,
208 ICE_SET_FC_AQ_FAIL_GET,
209 ICE_SET_FC_AQ_FAIL_SET,
210 ICE_SET_FC_AQ_FAIL_UPDATE
213 /* These are structs for managing the hardware information and the operations */
222 enum ice_media_type {
223 ICE_MEDIA_UNKNOWN = 0,
231 /* Software VSI types. */
234 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
238 struct ice_link_status {
239 /* Refer to ice_aq_phy_type for bits definition */
242 u8 topo_media_conflict;
246 u8 lse_ena; /* Link Status Event notification */
252 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
253 * ice_aqc_get_phy_caps structure
255 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
258 /* Different data queue types: These are mainly for SW consumption. */
267 /* Different reset sources for which a disable queue AQ call has to be made in
268 * order to clean the Tx scheduler as a part of the reset
270 enum ice_disq_rst_src {
275 /* PHY info such as phy_type, etc... */
276 struct ice_phy_info {
277 struct ice_link_status link_info;
278 struct ice_link_status link_info_old;
281 enum ice_media_type media_type;
283 /* Please refer to struct ice_aqc_get_link_status_data to get
284 * detail of enable bit in curr_user_speed_req
286 u16 curr_user_speed_req;
287 enum ice_fec_mode curr_user_fec_req;
288 enum ice_fc_mode curr_user_fc_req;
289 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
292 #define ICE_MAX_NUM_MIRROR_RULES 64
294 /* protocol enumeration for filters */
295 enum ice_fltr_ptype {
296 /* NONE - used for undef/error */
297 ICE_FLTR_PTYPE_NONF_NONE = 0,
298 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
299 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
300 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
301 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
302 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
303 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
304 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
305 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
306 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
307 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_OTHER,
308 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_IPV6_OTHER,
309 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
310 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
311 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
312 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
313 ICE_FLTR_PTYPE_NONF_IPV4_AH,
314 ICE_FLTR_PTYPE_NONF_IPV6_AH,
315 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
316 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
317 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
318 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
319 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
320 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
321 ICE_FLTR_PTYPE_NON_IP_L2,
322 ICE_FLTR_PTYPE_FRAG_IPV4,
323 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
324 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
325 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
326 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
331 ICE_FD_HW_SEG_NON_TUN = 0,
336 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
337 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
339 struct ice_fd_hw_prof {
340 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
342 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
343 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
346 /* Common HW capabilities for SW use */
347 struct ice_hw_common_caps {
348 /* Write CSR protection */
351 /* switching mode supported - EVB switching (including cloud) */
352 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
354 /* Manageablity mode & supported protocols over MCTP */
356 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
357 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
358 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
360 u32 mgmt_protocols_mctp;
361 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
362 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
363 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
364 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
368 /* DCB capabilities */
369 u32 active_tc_bitmap;
372 /* RSS related capabilities */
373 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
374 u32 rss_table_entry_width; /* RSS Entry width in bits */
377 u32 num_rxq; /* Number/Total Rx queues */
378 u32 rxq_first_id; /* First queue ID for Rx queues */
379 u32 num_txq; /* Number/Total Tx queues */
380 u32 txq_first_id; /* First queue ID for Tx queues */
383 u32 num_msix_vectors;
384 u32 msix_vector_first_id;
386 /* Max MTU for function or device */
390 u32 num_wol_proxy_fltr;
391 u32 wol_proxy_vsi_seid;
393 /* LED/SDP pin count */
397 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
398 #define ICE_MAX_SUPPORTED_GPIO_LED 12
399 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
400 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
401 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
403 /* EVB capabilities */
404 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
405 u8 evb_802_1_qbh; /* Bridge Port Extension */
411 /* WoL and APM support */
412 #define ICE_WOL_SUPPORT_M BIT(0)
413 #define ICE_ACPI_PROG_MTHD_M BIT(1)
414 #define ICE_PROXY_SUPPORT_M BIT(2)
418 bool nvm_unified_update;
419 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
422 /* Function specific capabilities */
423 struct ice_hw_func_caps {
424 struct ice_hw_common_caps common_cap;
426 u32 fd_fltr_guar; /* Number of filters guaranteed */
427 u32 fd_fltr_best_effort; /* Number of best effort filters */
430 /* Device wide capabilities */
431 struct ice_hw_dev_caps {
432 struct ice_hw_common_caps common_cap;
433 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
434 u32 num_flow_director_fltr; /* Number of FD filters available */
438 /* Information about MAC such as address, etc... */
439 struct ice_mac_info {
440 u8 lan_addr[ETH_ALEN];
441 u8 perm_addr[ETH_ALEN];
442 u8 port_addr[ETH_ALEN];
443 u8 wol_addr[ETH_ALEN];
450 ice_bus_embedded, /* Is device Embedded versus card */
455 enum ice_pcie_bus_speed {
456 ice_pcie_speed_unknown = 0xff,
457 ice_pcie_speed_2_5GT = 0x14,
458 ice_pcie_speed_5_0GT = 0x15,
459 ice_pcie_speed_8_0GT = 0x16,
460 ice_pcie_speed_16_0GT = 0x17
464 enum ice_pcie_link_width {
465 ice_pcie_lnk_width_resrv = 0x00,
466 ice_pcie_lnk_x1 = 0x01,
467 ice_pcie_lnk_x2 = 0x02,
468 ice_pcie_lnk_x4 = 0x04,
469 ice_pcie_lnk_x8 = 0x08,
470 ice_pcie_lnk_x12 = 0x0C,
471 ice_pcie_lnk_x16 = 0x10,
472 ice_pcie_lnk_x32 = 0x20,
473 ice_pcie_lnk_width_unknown = 0xff,
476 /* Reset types used to determine which kind of reset was requested. These
477 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
478 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
479 * because its reset source is different than the other types listed.
491 struct ice_bus_info {
492 enum ice_pcie_bus_speed speed;
493 enum ice_pcie_link_width width;
494 enum ice_bus_type type;
501 /* Flow control (FC) parameters */
503 enum ice_fc_mode current_mode; /* FC mode in effect */
504 enum ice_fc_mode req_mode; /* FC mode requested by caller */
507 /* Option ROM version information */
508 struct ice_orom_info {
509 u8 major; /* Major version of OROM */
510 u8 patch; /* Patch version of OROM */
511 u16 build; /* Build version of OROM */
514 /* NVM Information */
515 struct ice_nvm_info {
516 struct ice_orom_info orom; /* Option ROM version info */
517 u32 eetrack; /* NVM data version */
518 u16 sr_words; /* Shadow RAM size in words */
519 u32 flash_size; /* Size of available flash in bytes */
520 u8 major_ver; /* major version of dev starter */
521 u8 minor_ver; /* minor version of dev starter */
522 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
525 struct ice_link_default_override_tlv {
527 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
528 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
529 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
530 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
531 #define ICE_LINK_OVERRIDE_EN BIT(3)
532 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
533 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
535 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
536 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
537 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
538 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
539 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
541 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
547 #define ICE_NVM_VER_LEN 32
549 /* Max number of port to queue branches w.r.t topology */
550 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
552 #define ice_for_each_traffic_class(_i) \
553 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
555 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
556 * to driver defined policy for default aggregator
558 #define ICE_INVAL_TEID 0xFFFFFFFF
559 #define ICE_DFLT_AGG_ID 0
561 struct ice_sched_node {
562 struct ice_sched_node *parent;
563 struct ice_sched_node *sibling; /* next sibling in the same layer */
564 struct ice_sched_node **children;
565 struct ice_aqc_txsched_elem_data info;
566 u32 agg_id; /* aggregator group ID */
568 u8 in_use; /* suspended or in use */
569 u8 tx_sched_layer; /* Logical Layer (1-9) */
573 #define ICE_SCHED_NODE_OWNER_LAN 0
574 #define ICE_SCHED_NODE_OWNER_AE 1
575 #define ICE_SCHED_NODE_OWNER_RDMA 2
578 /* Access Macros for Tx Sched Elements data */
579 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
580 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
581 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
582 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
583 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
584 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
585 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
586 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
587 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
588 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
589 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
591 struct ice_sched_rl_profile {
592 u32 rate; /* In Kbps */
593 struct ice_aqc_rl_profile_elem info;
596 /* The aggregator type determines if identifier is for a VSI group,
597 * aggregator group, aggregator of queues, or queue group.
600 ICE_AGG_TYPE_UNKNOWN = 0,
602 ICE_AGG_TYPE_AGG, /* aggregator */
608 /* Rate limit types */
611 ICE_MIN_BW, /* for CIR profile */
612 ICE_MAX_BW, /* for EIR profile */
613 ICE_SHARED_BW /* for shared profile */
616 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
617 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
618 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
619 #define ICE_SCHED_NO_PRIORITY 0
620 #define ICE_SCHED_NO_BW_WT 0
621 #define ICE_SCHED_DFLT_RL_PROF_ID 0
622 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
623 #define ICE_SCHED_DFLT_BW_WT 4
624 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
625 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
627 /* Access Macros for Tx Sched RL Profile data */
628 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
629 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
630 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
631 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
632 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
634 /* The following tree example shows the naming conventions followed under
635 * ice_port_info struct for default scheduler tree topology.
639 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
643 * / |-> num_elements (range:1 - 9)
644 * * | implies num_of_layers
648 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
649 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
650 * need TEID of (a) to add queues.
653 * -> has 8 branches (one for each TC)
654 * -> First branch (TC0) has 4 elements
656 * -> (a) is the topmost layer node created by firmware on branch 0
658 * Note: Above asterisk tree covers only basic terminology and scenario.
659 * Refer to the documentation for more info.
662 /* Data structure for saving BW information */
670 ICE_BW_TYPE_CNT /* This must be last */
678 struct ice_bw_type_info {
679 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
681 struct ice_bw cir_bw;
682 struct ice_bw eir_bw;
686 /* VSI queue context structure for given TC */
690 /* bw_t_info saves queue BW information */
691 struct ice_bw_type_info bw_t_info;
694 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
695 struct ice_sched_vsi_info {
696 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
697 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
698 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
699 /* bw_t_info saves VSI BW information */
700 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
703 /* CEE or IEEE 802.1Qaz ETS Configuration data */
704 struct ice_dcb_ets_cfg {
708 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
709 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
710 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
713 /* CEE or IEEE 802.1Qaz PFC Configuration data */
714 struct ice_dcb_pfc_cfg {
721 /* CEE or IEEE 802.1Qaz Application Priority data */
722 struct ice_dcb_app_priority_table {
728 #define ICE_MAX_USER_PRIORITY 8
729 #define ICE_DCBX_MAX_APPS 32
730 #define ICE_LLDPDU_SIZE 1500
731 #define ICE_TLV_STATUS_OPER 0x1
732 #define ICE_TLV_STATUS_SYNC 0x2
733 #define ICE_TLV_STATUS_ERR 0x4
734 #define ICE_APP_PROT_ID_FCOE 0x8906
735 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
736 #define ICE_APP_PROT_ID_FIP 0x8914
737 #define ICE_APP_SEL_ETHTYPE 0x1
738 #define ICE_APP_SEL_TCPIP 0x2
739 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
740 #define ICE_CEE_APP_SEL_TCPIP 0x1
742 struct ice_dcbx_cfg {
744 u32 tlv_status; /* CEE mode TLV status */
745 struct ice_dcb_ets_cfg etscfg;
746 struct ice_dcb_ets_cfg etsrec;
747 struct ice_dcb_pfc_cfg pfc;
748 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
750 #define ICE_DCBX_MODE_CEE 0x1
751 #define ICE_DCBX_MODE_IEEE 0x2
753 #define ICE_DCBX_APPS_NON_WILLING 0x1
757 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
758 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
759 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
760 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
764 struct ice_port_info {
765 struct ice_sched_node *root; /* Root Node per Port */
766 struct ice_hw *hw; /* back pointer to HW instance */
767 u32 last_node_teid; /* scheduler last node info */
768 u16 sw_id; /* Initial switch ID belongs to port */
771 #define ICE_SCHED_PORT_STATE_INIT 0x0
772 #define ICE_SCHED_PORT_STATE_READY 0x1
774 #define ICE_LPORT_MASK 0xff
775 u16 dflt_tx_vsi_rule_id;
777 u16 dflt_rx_vsi_rule_id;
779 struct ice_fc_info fc;
780 struct ice_mac_info mac;
781 struct ice_phy_info phy;
782 struct ice_lock sched_lock; /* protect access to TXSched tree */
783 struct ice_sched_node *
784 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
785 struct ice_bw_type_info root_node_bw_t_info;
786 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
787 struct ice_qos_cfg qos_cfg;
791 struct ice_switch_info {
792 struct LIST_HEAD_TYPE vsi_list_map_head;
793 struct ice_sw_recipe *recp_list;
794 u16 prof_res_bm_init;
795 u16 max_used_prof_index;
797 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
800 /* Port hardware description */
804 struct ice_aqc_layer_props *layer_info;
805 struct ice_port_info *port_info;
806 /* 2D Array for each Tx Sched RL Profile type */
807 struct ice_sched_rl_profile **cir_profiles;
808 struct ice_sched_rl_profile **eir_profiles;
809 struct ice_sched_rl_profile **srl_profiles;
810 /* PSM clock frequency for calculating RL profile params */
812 u64 debug_mask; /* BITMAP for debug mask */
813 enum ice_mac_type mac_type;
815 u16 fd_ctr_base; /* FD counter base index */
819 u16 subsystem_device_id;
820 u16 subsystem_vendor_id;
823 u8 pf_id; /* device profile info */
825 u16 max_burst_size; /* driver sets this value */
827 /* Tx Scheduler values */
828 u8 num_tx_sched_layers;
829 u8 num_tx_sched_phys_layers;
832 u8 sw_entry_point_layer;
833 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
834 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
835 /* List contain profile ID(s) and other params per layer */
836 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
837 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
838 u8 evb_veb; /* true for VEB, false for VEPA */
839 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
840 struct ice_bus_info bus;
841 struct ice_nvm_info nvm;
842 struct ice_hw_dev_caps dev_caps; /* device capabilities */
843 struct ice_hw_func_caps func_caps; /* function capabilities */
845 struct ice_switch_info *switch_info; /* switch filter lists */
847 /* Control Queue info */
848 struct ice_ctl_q_info adminq;
849 struct ice_ctl_q_info mailboxq;
850 /* Additional function to send AdminQ command */
851 int (*aq_send_cmd_fn)(void *param, struct ice_aq_desc *desc,
852 void *buf, u16 buf_size);
853 void *aq_send_cmd_param;
854 u8 dcf_enabled; /* Device Config Function */
856 u8 api_branch; /* API branch version */
857 u8 api_maj_ver; /* API major version */
858 u8 api_min_ver; /* API minor version */
859 u8 api_patch; /* API patch version */
860 u8 fw_branch; /* firmware branch version */
861 u8 fw_maj_ver; /* firmware major version */
862 u8 fw_min_ver; /* firmware minor version */
863 u8 fw_patch; /* firmware patch version */
864 u32 fw_build; /* firmware build number */
866 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
867 * register. Used for determining the ITR/INTRL granularity during
870 #define ICE_MAX_AGG_BW_200G 0x0
871 #define ICE_MAX_AGG_BW_100G 0X1
872 #define ICE_MAX_AGG_BW_50G 0x2
873 #define ICE_MAX_AGG_BW_25G 0x3
874 /* ITR granularity for different speeds */
875 #define ICE_ITR_GRAN_ABOVE_25 2
876 #define ICE_ITR_GRAN_MAX_25 4
877 /* ITR granularity in 1 us */
879 /* INTRL granularity for different speeds */
880 #define ICE_INTRL_GRAN_ABOVE_25 4
881 #define ICE_INTRL_GRAN_MAX_25 8
882 /* INTRL granularity in 1 us */
885 u8 ucast_shared; /* true if VSIs can share unicast addr */
887 #define ICE_PHY_PER_NAC 1
888 #define ICE_MAX_QUAD 2
889 #define ICE_NUM_QUAD_TYPE 2
890 #define ICE_PORTS_PER_QUAD 4
891 #define ICE_PHY_0_LAST_QUAD 1
892 #define ICE_PORTS_PER_PHY 8
893 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
895 /* Active package version (currently active) */
896 struct ice_pkg_ver active_pkg_ver;
898 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
899 u8 active_pkg_in_nvm;
901 enum ice_aq_err pkg_dwnld_status;
903 /* Driver's package ver - (from the Metadata seg) */
904 struct ice_pkg_ver pkg_ver;
905 u8 pkg_name[ICE_PKG_NAME_SIZE];
907 /* Driver's Ice package version (from the Ice seg) */
908 struct ice_pkg_ver ice_pkg_ver;
909 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
911 /* Pointer to the ice segment */
914 /* Pointer to allocated copy of pkg memory */
919 struct ice_lock tnl_lock;
920 struct ice_tunnel_table tnl;
922 struct ice_acl_tbl *acl_tbl;
923 struct ice_fd_hw_prof **acl_prof;
924 u16 acl_fltr_cnt[ICE_FLTR_PTYPE_MAX];
925 /* HW block tables */
926 struct ice_blk_info blk[ICE_BLK_COUNT];
927 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
928 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
929 /* Flow Director filter info */
930 int fdir_active_fltr;
932 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
933 struct LIST_HEAD_TYPE fdir_list_head;
935 /* Book-keeping of side-band filter count per flow-type.
936 * This is used to detect and handle input set changes for
937 * respective flow-type.
939 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
941 struct ice_fd_hw_prof **fdir_prof;
942 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
943 struct ice_lock rss_locks; /* protect RSS configuration */
944 struct LIST_HEAD_TYPE rss_list_head;
947 /* Statistics collected by each port, VSI, VEB, and S-channel */
948 struct ice_eth_stats {
949 u64 rx_bytes; /* gorc */
950 u64 rx_unicast; /* uprc */
951 u64 rx_multicast; /* mprc */
952 u64 rx_broadcast; /* bprc */
953 u64 rx_discards; /* rdpc */
954 u64 rx_unknown_protocol; /* rupp */
955 u64 tx_bytes; /* gotc */
956 u64 tx_unicast; /* uptc */
957 u64 tx_multicast; /* mptc */
958 u64 tx_broadcast; /* bptc */
959 u64 tx_discards; /* tdpc */
960 u64 tx_errors; /* tepc */
961 u64 rx_no_desc; /* repc */
962 u64 rx_errors; /* repc */
967 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
968 struct ice_veb_up_stats {
969 u64 up_rx_pkts[ICE_MAX_UP];
970 u64 up_rx_bytes[ICE_MAX_UP];
971 u64 up_tx_pkts[ICE_MAX_UP];
972 u64 up_tx_bytes[ICE_MAX_UP];
975 /* Statistics collected by the MAC */
976 struct ice_hw_port_stats {
977 /* eth stats collected by the port */
978 struct ice_eth_stats eth;
979 /* additional port specific stats */
980 u64 tx_dropped_link_down; /* tdold */
981 u64 crc_errors; /* crcerrs */
982 u64 illegal_bytes; /* illerrc */
983 u64 error_bytes; /* errbc */
984 u64 mac_local_faults; /* mlfc */
985 u64 mac_remote_faults; /* mrfc */
986 u64 rx_len_errors; /* rlec */
987 u64 link_xon_rx; /* lxonrxc */
988 u64 link_xoff_rx; /* lxoffrxc */
989 u64 link_xon_tx; /* lxontxc */
990 u64 link_xoff_tx; /* lxofftxc */
991 u64 priority_xon_rx[8]; /* pxonrxc[8] */
992 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
993 u64 priority_xon_tx[8]; /* pxontxc[8] */
994 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
995 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
996 u64 rx_size_64; /* prc64 */
997 u64 rx_size_127; /* prc127 */
998 u64 rx_size_255; /* prc255 */
999 u64 rx_size_511; /* prc511 */
1000 u64 rx_size_1023; /* prc1023 */
1001 u64 rx_size_1522; /* prc1522 */
1002 u64 rx_size_big; /* prc9522 */
1003 u64 rx_undersize; /* ruc */
1004 u64 rx_fragments; /* rfc */
1005 u64 rx_oversize; /* roc */
1006 u64 rx_jabber; /* rjc */
1007 u64 tx_size_64; /* ptc64 */
1008 u64 tx_size_127; /* ptc127 */
1009 u64 tx_size_255; /* ptc255 */
1010 u64 tx_size_511; /* ptc511 */
1011 u64 tx_size_1023; /* ptc1023 */
1012 u64 tx_size_1522; /* ptc1522 */
1013 u64 tx_size_big; /* ptc9522 */
1014 u64 mac_short_pkt_dropped; /* mspdc */
1015 /* flow director stats */
1020 enum ice_sw_fwd_act_type {
1022 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1029 /* Checksum and Shadow RAM pointers */
1030 #define ICE_SR_NVM_CTRL_WORD 0x00
1031 #define ICE_SR_PHY_ANALOG_PTR 0x04
1032 #define ICE_SR_OPTION_ROM_PTR 0x05
1033 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1034 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1035 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1036 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
1037 #define ICE_SR_EMP_IMAGE_PTR 0x0B
1038 #define ICE_SR_PE_IMAGE_PTR 0x0C
1039 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
1040 #define ICE_SR_MNG_CFG_PTR 0x0E
1041 #define ICE_SR_EMP_MODULE_PTR 0x0F
1042 #define ICE_SR_PBA_BLOCK_PTR 0x16
1043 #define ICE_SR_BOOT_CFG_PTR 0x132
1044 #define ICE_SR_NVM_WOL_CFG 0x19
1045 #define ICE_NVM_OROM_VER_OFF 0x02
1046 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1047 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
1048 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
1049 #define ICE_SR_NVM_MAP_VER 0x29
1050 #define ICE_SR_NVM_IMAGE_VER 0x2A
1051 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
1052 #define ICE_SR_NVM_EETRACK_LO 0x2D
1053 #define ICE_SR_NVM_EETRACK_HI 0x2E
1054 #define ICE_NVM_VER_LO_SHIFT 0
1055 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1056 #define ICE_NVM_VER_HI_SHIFT 12
1057 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1058 #define ICE_OEM_EETRACK_ID 0xffffffff
1059 #define ICE_OROM_VER_PATCH_SHIFT 0
1060 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1061 #define ICE_OROM_VER_BUILD_SHIFT 8
1062 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1063 #define ICE_OROM_VER_SHIFT 24
1064 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1065 #define ICE_SR_VPD_PTR 0x2F
1066 #define ICE_SR_PXE_SETUP_PTR 0x30
1067 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
1068 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1069 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1070 #define ICE_SR_VLAN_CFG_PTR 0x37
1071 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1072 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1073 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1074 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1075 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
1076 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1077 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
1078 #define ICE_SR_PFA_PTR 0x40
1079 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
1080 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1081 #define ICE_SR_NVM_BANK_SIZE 0x43
1082 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1083 #define ICE_SR_OROM_BANK_SIZE 0x45
1084 #define ICE_SR_NETLIST_BANK_PTR 0x46
1085 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1086 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1087 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1088 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1089 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
1090 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1092 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1093 #define ICE_SR_VPD_SIZE_WORDS 512
1094 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1095 #define ICE_SR_CTRL_WORD_1_S 0x06
1096 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1098 /* Shadow RAM related */
1099 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1100 #define ICE_SR_BUF_ALIGNMENT 4096
1101 #define ICE_SR_WORDS_IN_1KB 512
1102 /* Checksum should be calculated such that after adding all the words,
1103 * including the checksum word itself, the sum should be 0xBABA.
1105 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1107 /* Link override related */
1108 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1109 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1110 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1111 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1112 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1113 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1114 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1115 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1117 #define ICE_PBA_FLAG_DFLT 0xFAFA
1118 /* Hash redirection LUT for VSI - maximum array size */
1119 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1122 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1123 * This is needed to determine the BAR0 space for the VFs
1125 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1126 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1127 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1129 /* AQ API version for LLDP_FILTER_CONTROL */
1130 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1131 #define ICE_FW_API_LLDP_FLTR_MIN 7
1132 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1133 #endif /* _ICE_TYPE_H_ */