1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
19 #define ICE_BYTES_PER_WORD 2
20 #define ICE_BYTES_PER_DWORD 4
21 #define ICE_MAX_TRAFFIC_CLASS 8
24 * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
25 * @a: value to round up
26 * @b: arbitrary multiple
28 * Round up to the next multiple of the arbitrary b.
29 * Note, when b is a power of 2 use ICE_ALIGN() instead.
31 #define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
33 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
35 #define IS_ASCII(_ch) ((_ch) < 0x80)
37 #define ice_struct_size(ptr, field, num) \
38 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
40 #include "ice_status.h"
41 #include "ice_hw_autogen.h"
42 #include "ice_devids.h"
43 #include "ice_osdep.h"
44 #include "ice_bitops.h" /* Must come before ice_controlq.h */
45 #include "ice_controlq.h"
46 #include "ice_lan_tx_rx.h"
47 #include "ice_flex_type.h"
48 #include "ice_protocol_type.h"
51 * ice_is_pow2 - check if integer value is a power of 2
52 * @val: unsigned integer to be validated
54 static inline bool ice_is_pow2(u64 val)
56 return (val && !(val & (val - 1)));
60 * ice_ilog2 - Calculates integer log base 2 of a number
61 * @n: number on which to perform operation
63 static inline int ice_ilog2(u64 n)
67 for (i = 63; i >= 0; i--)
68 if (((u64)1 << i) & n)
74 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
76 return ice_is_bit_set(&bitmap, tc);
79 #define DIV_64BIT(n, d) ((n) / (d))
81 static inline u64 round_up_64bit(u64 a, u32 b)
83 return DIV_64BIT(((a) + (b) / 2), (b));
86 static inline u32 ice_round_to_num(u32 N, u32 R)
88 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
89 ((((N) + (R) - 1) / (R)) * (R)));
92 /* Driver always calls main vsi_handle first */
93 #define ICE_MAIN_VSI_HANDLE 0
95 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
96 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
98 /* Data type manipulation macros. */
99 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
100 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
101 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
102 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF))
104 /* debug masks - set these bits in hw->debug_mask to control output */
105 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
106 #define ICE_DBG_INIT BIT_ULL(1)
107 #define ICE_DBG_RELEASE BIT_ULL(2)
108 #define ICE_DBG_FW_LOG BIT_ULL(3)
109 #define ICE_DBG_LINK BIT_ULL(4)
110 #define ICE_DBG_PHY BIT_ULL(5)
111 #define ICE_DBG_QCTX BIT_ULL(6)
112 #define ICE_DBG_NVM BIT_ULL(7)
113 #define ICE_DBG_LAN BIT_ULL(8)
114 #define ICE_DBG_FLOW BIT_ULL(9)
115 #define ICE_DBG_DCB BIT_ULL(10)
116 #define ICE_DBG_DIAG BIT_ULL(11)
117 #define ICE_DBG_FD BIT_ULL(12)
118 #define ICE_DBG_SW BIT_ULL(13)
119 #define ICE_DBG_SCHED BIT_ULL(14)
121 #define ICE_DBG_PKG BIT_ULL(16)
122 #define ICE_DBG_RES BIT_ULL(17)
123 #define ICE_DBG_ACL BIT_ULL(18)
124 #define ICE_DBG_AQ_MSG BIT_ULL(24)
125 #define ICE_DBG_AQ_DESC BIT_ULL(25)
126 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
127 #define ICE_DBG_AQ_CMD BIT_ULL(27)
128 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
130 ICE_DBG_AQ_DESC_BUF | \
133 #define ICE_DBG_USER BIT_ULL(31)
134 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
136 #define __ALWAYS_UNUSED
138 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
139 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
140 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
141 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
143 enum ice_aq_res_ids {
146 ICE_CHANGE_LOCK_RES_ID,
147 ICE_GLOBAL_CFG_LOCK_RES_ID
150 /* FW update timeout definitions are in milliseconds */
151 #define ICE_NVM_TIMEOUT 180000
152 #define ICE_CHANGE_LOCK_TIMEOUT 1000
153 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
155 enum ice_aq_res_access_type {
160 struct ice_driver_ver {
165 u8 driver_string[32];
178 enum ice_phy_cache_mode {
191 struct ice_phy_cache_mode_data {
193 enum ice_fec_mode curr_user_fec_req;
194 enum ice_fc_mode curr_user_fc_req;
195 u16 curr_user_speed_req;
199 enum ice_set_fc_aq_failures {
200 ICE_SET_FC_AQ_FAIL_NONE = 0,
201 ICE_SET_FC_AQ_FAIL_GET,
202 ICE_SET_FC_AQ_FAIL_SET,
203 ICE_SET_FC_AQ_FAIL_UPDATE
206 /* These are structs for managing the hardware information and the operations */
215 enum ice_media_type {
216 ICE_MEDIA_UNKNOWN = 0,
224 /* Software VSI types. */
227 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
231 struct ice_link_status {
232 /* Refer to ice_aq_phy_type for bits definition */
235 u8 topo_media_conflict;
239 u8 lse_ena; /* Link Status Event notification */
245 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
246 * ice_aqc_get_phy_caps structure
248 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
251 /* Different data queue types: These are mainly for SW consumption. */
260 /* Different reset sources for which a disable queue AQ call has to be made in
261 * order to clean the Tx scheduler as a part of the reset
263 enum ice_disq_rst_src {
268 /* PHY info such as phy_type, etc... */
269 struct ice_phy_info {
270 struct ice_link_status link_info;
271 struct ice_link_status link_info_old;
274 enum ice_media_type media_type;
276 /* Please refer to struct ice_aqc_get_link_status_data to get
277 * detail of enable bit in curr_user_speed_req
279 u16 curr_user_speed_req;
280 enum ice_fec_mode curr_user_fec_req;
281 enum ice_fc_mode curr_user_fc_req;
282 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
285 #define ICE_MAX_NUM_MIRROR_RULES 64
287 /* protocol enumeration for filters */
288 enum ice_fltr_ptype {
289 /* NONE - used for undef/error */
290 ICE_FLTR_PTYPE_NONF_NONE = 0,
291 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
292 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
293 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
294 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
295 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
296 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
297 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
298 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
299 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
300 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
301 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
302 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
303 ICE_FLTR_PTYPE_NONF_IPV4_AH,
304 ICE_FLTR_PTYPE_NONF_IPV6_AH,
305 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
306 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
307 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
308 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
309 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
310 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
311 ICE_FLTR_PTYPE_NON_IP_L2,
312 ICE_FLTR_PTYPE_FRAG_IPV4,
313 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
314 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
315 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
316 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
321 ICE_FD_HW_SEG_NON_TUN = 0,
326 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
327 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
329 struct ice_fd_hw_prof {
330 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
332 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
333 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
336 /* Common HW capabilities for SW use */
337 struct ice_hw_common_caps {
338 /* Write CSR protection */
341 /* switching mode supported - EVB switching (including cloud) */
342 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
344 /* Manageablity mode & supported protocols over MCTP */
346 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
347 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
348 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
350 u32 mgmt_protocols_mctp;
351 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
352 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
353 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
354 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
358 /* DCB capabilities */
359 u32 active_tc_bitmap;
362 /* RSS related capabilities */
363 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
364 u32 rss_table_entry_width; /* RSS Entry width in bits */
367 u32 num_rxq; /* Number/Total Rx queues */
368 u32 rxq_first_id; /* First queue ID for Rx queues */
369 u32 num_txq; /* Number/Total Tx queues */
370 u32 txq_first_id; /* First queue ID for Tx queues */
373 u32 num_msix_vectors;
374 u32 msix_vector_first_id;
376 /* Max MTU for function or device */
380 u32 num_wol_proxy_fltr;
381 u32 wol_proxy_vsi_seid;
383 /* LED/SDP pin count */
387 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
388 #define ICE_MAX_SUPPORTED_GPIO_LED 12
389 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
390 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
391 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
393 /* EVB capabilities */
394 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
395 u8 evb_802_1_qbh; /* Bridge Port Extension */
401 /* WoL and APM support */
402 #define ICE_WOL_SUPPORT_M BIT(0)
403 #define ICE_ACPI_PROG_MTHD_M BIT(1)
404 #define ICE_PROXY_SUPPORT_M BIT(2)
408 bool nvm_unified_update;
409 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
412 /* Function specific capabilities */
413 struct ice_hw_func_caps {
414 struct ice_hw_common_caps common_cap;
416 u32 fd_fltr_guar; /* Number of filters guaranteed */
417 u32 fd_fltr_best_effort; /* Number of best effort filters */
420 /* Device wide capabilities */
421 struct ice_hw_dev_caps {
422 struct ice_hw_common_caps common_cap;
423 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
424 u32 num_flow_director_fltr; /* Number of FD filters available */
428 /* Information about MAC such as address, etc... */
429 struct ice_mac_info {
430 u8 lan_addr[ETH_ALEN];
431 u8 perm_addr[ETH_ALEN];
432 u8 port_addr[ETH_ALEN];
433 u8 wol_addr[ETH_ALEN];
440 ice_bus_embedded, /* Is device Embedded versus card */
445 enum ice_pcie_bus_speed {
446 ice_pcie_speed_unknown = 0xff,
447 ice_pcie_speed_2_5GT = 0x14,
448 ice_pcie_speed_5_0GT = 0x15,
449 ice_pcie_speed_8_0GT = 0x16,
450 ice_pcie_speed_16_0GT = 0x17
454 enum ice_pcie_link_width {
455 ice_pcie_lnk_width_resrv = 0x00,
456 ice_pcie_lnk_x1 = 0x01,
457 ice_pcie_lnk_x2 = 0x02,
458 ice_pcie_lnk_x4 = 0x04,
459 ice_pcie_lnk_x8 = 0x08,
460 ice_pcie_lnk_x12 = 0x0C,
461 ice_pcie_lnk_x16 = 0x10,
462 ice_pcie_lnk_x32 = 0x20,
463 ice_pcie_lnk_width_unknown = 0xff,
466 /* Reset types used to determine which kind of reset was requested. These
467 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
468 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
469 * because its reset source is different than the other types listed.
481 struct ice_bus_info {
482 enum ice_pcie_bus_speed speed;
483 enum ice_pcie_link_width width;
484 enum ice_bus_type type;
491 /* Flow control (FC) parameters */
493 enum ice_fc_mode current_mode; /* FC mode in effect */
494 enum ice_fc_mode req_mode; /* FC mode requested by caller */
497 /* Option ROM version information */
498 struct ice_orom_info {
499 u8 major; /* Major version of OROM */
500 u8 patch; /* Patch version of OROM */
501 u16 build; /* Build version of OROM */
504 /* NVM Information */
505 struct ice_nvm_info {
506 struct ice_orom_info orom; /* Option ROM version info */
507 u32 eetrack; /* NVM data version */
508 u16 sr_words; /* Shadow RAM size in words */
509 u32 flash_size; /* Size of available flash in bytes */
510 u8 major_ver; /* major version of dev starter */
511 u8 minor_ver; /* minor version of dev starter */
512 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
515 struct ice_link_default_override_tlv {
517 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
518 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
519 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
520 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
521 #define ICE_LINK_OVERRIDE_EN BIT(3)
522 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
523 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
525 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
526 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
527 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
528 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
529 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
531 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
537 #define ICE_NVM_VER_LEN 32
539 /* Max number of port to queue branches w.r.t topology */
540 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
542 #define ice_for_each_traffic_class(_i) \
543 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
545 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
546 * to driver defined policy for default aggregator
548 #define ICE_INVAL_TEID 0xFFFFFFFF
549 #define ICE_DFLT_AGG_ID 0
551 struct ice_sched_node {
552 struct ice_sched_node *parent;
553 struct ice_sched_node *sibling; /* next sibling in the same layer */
554 struct ice_sched_node **children;
555 struct ice_aqc_txsched_elem_data info;
556 u32 agg_id; /* aggregator group ID */
558 u8 in_use; /* suspended or in use */
559 u8 tx_sched_layer; /* Logical Layer (1-9) */
563 #define ICE_SCHED_NODE_OWNER_LAN 0
564 #define ICE_SCHED_NODE_OWNER_AE 1
565 #define ICE_SCHED_NODE_OWNER_RDMA 2
568 /* Access Macros for Tx Sched Elements data */
569 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
570 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
571 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
572 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
573 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
574 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
575 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
576 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
577 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
578 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
579 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
581 struct ice_sched_rl_profile {
582 u32 rate; /* In Kbps */
583 struct ice_aqc_rl_profile_elem info;
586 /* The aggregator type determines if identifier is for a VSI group,
587 * aggregator group, aggregator of queues, or queue group.
590 ICE_AGG_TYPE_UNKNOWN = 0,
592 ICE_AGG_TYPE_AGG, /* aggregator */
598 /* Rate limit types */
601 ICE_MIN_BW, /* for CIR profile */
602 ICE_MAX_BW, /* for EIR profile */
603 ICE_SHARED_BW /* for shared profile */
606 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
607 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
608 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
609 #define ICE_SCHED_NO_PRIORITY 0
610 #define ICE_SCHED_NO_BW_WT 0
611 #define ICE_SCHED_DFLT_RL_PROF_ID 0
612 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
613 #define ICE_SCHED_DFLT_BW_WT 1
614 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
615 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
617 /* Access Macros for Tx Sched RL Profile data */
618 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
619 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
620 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
621 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
622 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
624 /* The following tree example shows the naming conventions followed under
625 * ice_port_info struct for default scheduler tree topology.
629 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
633 * / |-> num_elements (range:1 - 9)
634 * * | implies num_of_layers
638 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
639 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
640 * need TEID of (a) to add queues.
643 * -> has 8 branches (one for each TC)
644 * -> First branch (TC0) has 4 elements
646 * -> (a) is the topmost layer node created by firmware on branch 0
648 * Note: Above asterisk tree covers only basic terminology and scenario.
649 * Refer to the documentation for more info.
652 /* Data structure for saving BW information */
660 ICE_BW_TYPE_CNT /* This must be last */
668 struct ice_bw_type_info {
669 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
671 struct ice_bw cir_bw;
672 struct ice_bw eir_bw;
676 /* VSI queue context structure for given TC */
680 /* bw_t_info saves queue BW information */
681 struct ice_bw_type_info bw_t_info;
684 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
685 struct ice_sched_vsi_info {
686 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
687 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
688 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
689 /* bw_t_info saves VSI BW information */
690 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
693 /* CEE or IEEE 802.1Qaz ETS Configuration data */
694 struct ice_dcb_ets_cfg {
698 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
699 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
700 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
703 /* CEE or IEEE 802.1Qaz PFC Configuration data */
704 struct ice_dcb_pfc_cfg {
711 /* CEE or IEEE 802.1Qaz Application Priority data */
712 struct ice_dcb_app_priority_table {
718 #define ICE_MAX_USER_PRIORITY 8
719 #define ICE_DCBX_MAX_APPS 32
720 #define ICE_LLDPDU_SIZE 1500
721 #define ICE_TLV_STATUS_OPER 0x1
722 #define ICE_TLV_STATUS_SYNC 0x2
723 #define ICE_TLV_STATUS_ERR 0x4
724 #define ICE_APP_PROT_ID_FCOE 0x8906
725 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
726 #define ICE_APP_PROT_ID_FIP 0x8914
727 #define ICE_APP_SEL_ETHTYPE 0x1
728 #define ICE_APP_SEL_TCPIP 0x2
729 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
730 #define ICE_CEE_APP_SEL_TCPIP 0x1
732 struct ice_dcbx_cfg {
734 u32 tlv_status; /* CEE mode TLV status */
735 struct ice_dcb_ets_cfg etscfg;
736 struct ice_dcb_ets_cfg etsrec;
737 struct ice_dcb_pfc_cfg pfc;
738 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
740 #define ICE_DCBX_MODE_CEE 0x1
741 #define ICE_DCBX_MODE_IEEE 0x2
743 #define ICE_DCBX_APPS_NON_WILLING 0x1
746 struct ice_port_info {
747 struct ice_sched_node *root; /* Root Node per Port */
748 struct ice_hw *hw; /* back pointer to HW instance */
749 u32 last_node_teid; /* scheduler last node info */
750 u16 sw_id; /* Initial switch ID belongs to port */
753 #define ICE_SCHED_PORT_STATE_INIT 0x0
754 #define ICE_SCHED_PORT_STATE_READY 0x1
756 #define ICE_LPORT_MASK 0xff
757 u16 dflt_tx_vsi_rule_id;
759 u16 dflt_rx_vsi_rule_id;
761 struct ice_fc_info fc;
762 struct ice_mac_info mac;
763 struct ice_phy_info phy;
764 struct ice_lock sched_lock; /* protect access to TXSched tree */
765 struct ice_sched_node *
766 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
767 /* List contain profile ID(s) and other params per layer */
768 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
769 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
770 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
772 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
773 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
774 /* LLDP/DCBX Status */
775 u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */
780 struct ice_switch_info {
781 struct LIST_HEAD_TYPE vsi_list_map_head;
782 struct ice_sw_recipe *recp_list;
783 u16 prof_res_bm_init;
785 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
788 /* Port hardware description */
792 struct ice_aqc_layer_props *layer_info;
793 struct ice_port_info *port_info;
794 /* 2D Array for each Tx Sched RL Profile type */
795 struct ice_sched_rl_profile **cir_profiles;
796 struct ice_sched_rl_profile **eir_profiles;
797 struct ice_sched_rl_profile **srl_profiles;
798 /* PSM clock frequency for calculating RL profile params */
800 u64 debug_mask; /* BITMAP for debug mask */
801 enum ice_mac_type mac_type;
803 u16 fd_ctr_base; /* FD counter base index */
807 u16 subsystem_device_id;
808 u16 subsystem_vendor_id;
811 u8 pf_id; /* device profile info */
813 u16 max_burst_size; /* driver sets this value */
815 /* Tx Scheduler values */
816 u8 num_tx_sched_layers;
817 u8 num_tx_sched_phys_layers;
820 u8 sw_entry_point_layer;
821 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
822 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
823 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
824 u8 evb_veb; /* true for VEB, false for VEPA */
825 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
826 struct ice_bus_info bus;
827 struct ice_nvm_info nvm;
828 struct ice_hw_dev_caps dev_caps; /* device capabilities */
829 struct ice_hw_func_caps func_caps; /* function capabilities */
831 struct ice_switch_info *switch_info; /* switch filter lists */
833 /* Control Queue info */
834 struct ice_ctl_q_info adminq;
835 struct ice_ctl_q_info mailboxq;
836 /* Additional function to send AdminQ command */
837 int (*aq_send_cmd_fn)(void *param, struct ice_aq_desc *desc,
838 void *buf, u16 buf_size);
839 void *aq_send_cmd_param;
840 u8 dcf_enabled; /* Device Config Function */
842 u8 api_branch; /* API branch version */
843 u8 api_maj_ver; /* API major version */
844 u8 api_min_ver; /* API minor version */
845 u8 api_patch; /* API patch version */
846 u8 fw_branch; /* firmware branch version */
847 u8 fw_maj_ver; /* firmware major version */
848 u8 fw_min_ver; /* firmware minor version */
849 u8 fw_patch; /* firmware patch version */
850 u32 fw_build; /* firmware build number */
852 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
853 * register. Used for determining the ITR/INTRL granularity during
856 #define ICE_MAX_AGG_BW_200G 0x0
857 #define ICE_MAX_AGG_BW_100G 0X1
858 #define ICE_MAX_AGG_BW_50G 0x2
859 #define ICE_MAX_AGG_BW_25G 0x3
860 /* ITR granularity for different speeds */
861 #define ICE_ITR_GRAN_ABOVE_25 2
862 #define ICE_ITR_GRAN_MAX_25 4
863 /* ITR granularity in 1 us */
865 /* INTRL granularity for different speeds */
866 #define ICE_INTRL_GRAN_ABOVE_25 4
867 #define ICE_INTRL_GRAN_MAX_25 8
868 /* INTRL granularity in 1 us */
871 u8 ucast_shared; /* true if VSIs can share unicast addr */
873 #define ICE_PHY_PER_NAC 1
874 #define ICE_MAX_QUAD 2
875 #define ICE_NUM_QUAD_TYPE 2
876 #define ICE_PORTS_PER_QUAD 4
877 #define ICE_PHY_0_LAST_QUAD 1
878 #define ICE_PORTS_PER_PHY 8
879 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
881 /* Active package version (currently active) */
882 struct ice_pkg_ver active_pkg_ver;
884 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
885 u8 active_pkg_in_nvm;
887 enum ice_aq_err pkg_dwnld_status;
889 /* Driver's package ver - (from the Metadata seg) */
890 struct ice_pkg_ver pkg_ver;
891 u8 pkg_name[ICE_PKG_NAME_SIZE];
893 /* Driver's Ice package version (from the Ice seg) */
894 struct ice_pkg_ver ice_pkg_ver;
895 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
897 /* Pointer to the ice segment */
900 /* Pointer to allocated copy of pkg memory */
905 struct ice_lock tnl_lock;
906 struct ice_tunnel_table tnl;
908 struct ice_acl_tbl *acl_tbl;
909 struct ice_fd_hw_prof **acl_prof;
910 u16 acl_fltr_cnt[ICE_FLTR_PTYPE_MAX];
911 /* HW block tables */
912 struct ice_blk_info blk[ICE_BLK_COUNT];
913 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
914 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
915 /* Flow Director filter info */
916 int fdir_active_fltr;
918 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
919 struct LIST_HEAD_TYPE fdir_list_head;
921 /* Book-keeping of side-band filter count per flow-type.
922 * This is used to detect and handle input set changes for
923 * respective flow-type.
925 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
927 struct ice_fd_hw_prof **fdir_prof;
928 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
929 struct ice_lock rss_locks; /* protect RSS configuration */
930 struct LIST_HEAD_TYPE rss_list_head;
933 /* Statistics collected by each port, VSI, VEB, and S-channel */
934 struct ice_eth_stats {
935 u64 rx_bytes; /* gorc */
936 u64 rx_unicast; /* uprc */
937 u64 rx_multicast; /* mprc */
938 u64 rx_broadcast; /* bprc */
939 u64 rx_discards; /* rdpc */
940 u64 rx_unknown_protocol; /* rupp */
941 u64 tx_bytes; /* gotc */
942 u64 tx_unicast; /* uptc */
943 u64 tx_multicast; /* mptc */
944 u64 tx_broadcast; /* bptc */
945 u64 tx_discards; /* tdpc */
946 u64 tx_errors; /* tepc */
947 u64 rx_no_desc; /* repc */
948 u64 rx_errors; /* repc */
953 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
954 struct ice_veb_up_stats {
955 u64 up_rx_pkts[ICE_MAX_UP];
956 u64 up_rx_bytes[ICE_MAX_UP];
957 u64 up_tx_pkts[ICE_MAX_UP];
958 u64 up_tx_bytes[ICE_MAX_UP];
961 /* Statistics collected by the MAC */
962 struct ice_hw_port_stats {
963 /* eth stats collected by the port */
964 struct ice_eth_stats eth;
965 /* additional port specific stats */
966 u64 tx_dropped_link_down; /* tdold */
967 u64 crc_errors; /* crcerrs */
968 u64 illegal_bytes; /* illerrc */
969 u64 error_bytes; /* errbc */
970 u64 mac_local_faults; /* mlfc */
971 u64 mac_remote_faults; /* mrfc */
972 u64 rx_len_errors; /* rlec */
973 u64 link_xon_rx; /* lxonrxc */
974 u64 link_xoff_rx; /* lxoffrxc */
975 u64 link_xon_tx; /* lxontxc */
976 u64 link_xoff_tx; /* lxofftxc */
977 u64 priority_xon_rx[8]; /* pxonrxc[8] */
978 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
979 u64 priority_xon_tx[8]; /* pxontxc[8] */
980 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
981 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
982 u64 rx_size_64; /* prc64 */
983 u64 rx_size_127; /* prc127 */
984 u64 rx_size_255; /* prc255 */
985 u64 rx_size_511; /* prc511 */
986 u64 rx_size_1023; /* prc1023 */
987 u64 rx_size_1522; /* prc1522 */
988 u64 rx_size_big; /* prc9522 */
989 u64 rx_undersize; /* ruc */
990 u64 rx_fragments; /* rfc */
991 u64 rx_oversize; /* roc */
992 u64 rx_jabber; /* rjc */
993 u64 tx_size_64; /* ptc64 */
994 u64 tx_size_127; /* ptc127 */
995 u64 tx_size_255; /* ptc255 */
996 u64 tx_size_511; /* ptc511 */
997 u64 tx_size_1023; /* ptc1023 */
998 u64 tx_size_1522; /* ptc1522 */
999 u64 tx_size_big; /* ptc9522 */
1000 u64 mac_short_pkt_dropped; /* mspdc */
1001 /* flow director stats */
1006 enum ice_sw_fwd_act_type {
1008 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1015 /* Checksum and Shadow RAM pointers */
1016 #define ICE_SR_NVM_CTRL_WORD 0x00
1017 #define ICE_SR_PHY_ANALOG_PTR 0x04
1018 #define ICE_SR_OPTION_ROM_PTR 0x05
1019 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1020 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1021 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1022 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
1023 #define ICE_SR_EMP_IMAGE_PTR 0x0B
1024 #define ICE_SR_PE_IMAGE_PTR 0x0C
1025 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
1026 #define ICE_SR_MNG_CFG_PTR 0x0E
1027 #define ICE_SR_EMP_MODULE_PTR 0x0F
1028 #define ICE_SR_PBA_BLOCK_PTR 0x16
1029 #define ICE_SR_BOOT_CFG_PTR 0x132
1030 #define ICE_SR_NVM_WOL_CFG 0x19
1031 #define ICE_NVM_OROM_VER_OFF 0x02
1032 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1033 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
1034 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
1035 #define ICE_SR_NVM_MAP_VER 0x29
1036 #define ICE_SR_NVM_IMAGE_VER 0x2A
1037 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
1038 #define ICE_SR_NVM_EETRACK_LO 0x2D
1039 #define ICE_SR_NVM_EETRACK_HI 0x2E
1040 #define ICE_NVM_VER_LO_SHIFT 0
1041 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1042 #define ICE_NVM_VER_HI_SHIFT 12
1043 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1044 #define ICE_OEM_EETRACK_ID 0xffffffff
1045 #define ICE_OROM_VER_PATCH_SHIFT 0
1046 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1047 #define ICE_OROM_VER_BUILD_SHIFT 8
1048 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1049 #define ICE_OROM_VER_SHIFT 24
1050 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1051 #define ICE_SR_VPD_PTR 0x2F
1052 #define ICE_SR_PXE_SETUP_PTR 0x30
1053 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
1054 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1055 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1056 #define ICE_SR_VLAN_CFG_PTR 0x37
1057 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1058 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1059 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1060 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1061 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
1062 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1063 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
1064 #define ICE_SR_PFA_PTR 0x40
1065 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
1066 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1067 #define ICE_SR_NVM_BANK_SIZE 0x43
1068 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1069 #define ICE_SR_OROM_BANK_SIZE 0x45
1070 #define ICE_SR_NETLIST_BANK_PTR 0x46
1071 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1072 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1073 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1074 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1075 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
1076 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1078 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1079 #define ICE_SR_VPD_SIZE_WORDS 512
1080 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1081 #define ICE_SR_CTRL_WORD_1_S 0x06
1082 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1084 /* Shadow RAM related */
1085 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1086 #define ICE_SR_BUF_ALIGNMENT 4096
1087 #define ICE_SR_WORDS_IN_1KB 512
1088 /* Checksum should be calculated such that after adding all the words,
1089 * including the checksum word itself, the sum should be 0xBABA.
1091 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1093 /* Link override related */
1094 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1095 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1096 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1097 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1098 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1099 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1100 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1101 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1103 #define ICE_PBA_FLAG_DFLT 0xFAFA
1104 /* Hash redirection LUT for VSI - maximum array size */
1105 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1108 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1109 * This is needed to determine the BAR0 space for the VFs
1111 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1112 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1113 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1115 #endif /* _ICE_TYPE_H_ */