1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
19 #define ICE_BYTES_PER_WORD 2
20 #define ICE_BYTES_PER_DWORD 4
21 #define ICE_MAX_TRAFFIC_CLASS 8
24 * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
25 * @a: value to round up
26 * @b: arbitrary multiple
28 * Round up to the next multiple of the arbitrary b.
29 * Note, when b is a power of 2 use ICE_ALIGN() instead.
31 #define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
33 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
35 #define IS_ASCII(_ch) ((_ch) < 0x80)
37 #define STRUCT_HACK_VAR_LEN
39 * ice_struct_size - size of struct with C99 flexible array member
40 * @ptr: pointer to structure
41 * @field: flexible array member (last member of the structure)
42 * @num: number of elements of that flexible array member
44 #define ice_struct_size(ptr, field, num) \
45 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
47 #ifndef FLEX_ARRAY_SIZE
48 #define FLEX_ARRAY_SIZE(_ptr, _mem, cnt) ((cnt) * sizeof(_ptr->_mem[0]))
49 #endif /* FLEX_ARRAY_SIZE */
51 #include "ice_status.h"
52 #include "ice_hw_autogen.h"
53 #include "ice_devids.h"
54 #include "ice_osdep.h"
55 #include "ice_bitops.h" /* Must come before ice_controlq.h */
56 #include "ice_controlq.h"
57 #include "ice_lan_tx_rx.h"
58 #include "ice_flex_type.h"
59 #include "ice_protocol_type.h"
60 #include "ice_vlan_mode.h"
63 * ice_is_pow2 - check if integer value is a power of 2
64 * @val: unsigned integer to be validated
66 static inline bool ice_is_pow2(u64 val)
68 return (val && !(val & (val - 1)));
72 * ice_ilog2 - Calculates integer log base 2 of a number
73 * @n: number on which to perform operation
75 static inline int ice_ilog2(u64 n)
79 for (i = 63; i >= 0; i--)
80 if (((u64)1 << i) & n)
86 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
88 return ice_is_bit_set(&bitmap, tc);
91 #define DIV_64BIT(n, d) ((n) / (d))
93 static inline u64 round_up_64bit(u64 a, u32 b)
95 return DIV_64BIT(((a) + (b) / 2), (b));
98 static inline u32 ice_round_to_num(u32 N, u32 R)
100 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
101 ((((N) + (R) - 1) / (R)) * (R)));
104 /* Driver always calls main vsi_handle first */
105 #define ICE_MAIN_VSI_HANDLE 0
107 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
108 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
110 /* Data type manipulation macros. */
111 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
112 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
113 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
114 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF))
116 /* debug masks - set these bits in hw->debug_mask to control output */
117 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
118 #define ICE_DBG_INIT BIT_ULL(1)
119 #define ICE_DBG_RELEASE BIT_ULL(2)
120 #define ICE_DBG_FW_LOG BIT_ULL(3)
121 #define ICE_DBG_LINK BIT_ULL(4)
122 #define ICE_DBG_PHY BIT_ULL(5)
123 #define ICE_DBG_QCTX BIT_ULL(6)
124 #define ICE_DBG_NVM BIT_ULL(7)
125 #define ICE_DBG_LAN BIT_ULL(8)
126 #define ICE_DBG_FLOW BIT_ULL(9)
127 #define ICE_DBG_DCB BIT_ULL(10)
128 #define ICE_DBG_DIAG BIT_ULL(11)
129 #define ICE_DBG_FD BIT_ULL(12)
130 #define ICE_DBG_SW BIT_ULL(13)
131 #define ICE_DBG_SCHED BIT_ULL(14)
133 #define ICE_DBG_PKG BIT_ULL(16)
134 #define ICE_DBG_RES BIT_ULL(17)
135 #define ICE_DBG_ACL BIT_ULL(18)
136 #define ICE_DBG_AQ_MSG BIT_ULL(24)
137 #define ICE_DBG_AQ_DESC BIT_ULL(25)
138 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
139 #define ICE_DBG_AQ_CMD BIT_ULL(27)
140 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
142 ICE_DBG_AQ_DESC_BUF | \
145 #define ICE_DBG_USER BIT_ULL(31)
146 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
148 #define __ALWAYS_UNUSED
150 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
151 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
152 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
153 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
155 enum ice_aq_res_ids {
158 ICE_CHANGE_LOCK_RES_ID,
159 ICE_GLOBAL_CFG_LOCK_RES_ID
162 /* FW update timeout definitions are in milliseconds */
163 #define ICE_NVM_TIMEOUT 180000
164 #define ICE_CHANGE_LOCK_TIMEOUT 1000
165 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
167 enum ice_aq_res_access_type {
172 struct ice_driver_ver {
177 u8 driver_string[32];
190 enum ice_phy_cache_mode {
203 struct ice_phy_cache_mode_data {
205 enum ice_fec_mode curr_user_fec_req;
206 enum ice_fc_mode curr_user_fc_req;
207 u16 curr_user_speed_req;
211 enum ice_set_fc_aq_failures {
212 ICE_SET_FC_AQ_FAIL_NONE = 0,
213 ICE_SET_FC_AQ_FAIL_GET,
214 ICE_SET_FC_AQ_FAIL_SET,
215 ICE_SET_FC_AQ_FAIL_UPDATE
218 /* These are structs for managing the hardware information and the operations */
227 enum ice_media_type {
228 ICE_MEDIA_UNKNOWN = 0,
236 /* Software VSI types. */
239 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
243 struct ice_link_status {
244 /* Refer to ice_aq_phy_type for bits definition */
247 u8 topo_media_conflict;
251 u8 lse_ena; /* Link Status Event notification */
257 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
258 * ice_aqc_get_phy_caps structure
260 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
263 /* Different data queue types: These are mainly for SW consumption. */
272 /* Different reset sources for which a disable queue AQ call has to be made in
273 * order to clean the Tx scheduler as a part of the reset
275 enum ice_disq_rst_src {
280 /* PHY info such as phy_type, etc... */
281 struct ice_phy_info {
282 struct ice_link_status link_info;
283 struct ice_link_status link_info_old;
286 enum ice_media_type media_type;
288 /* Please refer to struct ice_aqc_get_link_status_data to get
289 * detail of enable bit in curr_user_speed_req
291 u16 curr_user_speed_req;
292 enum ice_fec_mode curr_user_fec_req;
293 enum ice_fc_mode curr_user_fc_req;
294 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
297 #define ICE_MAX_NUM_MIRROR_RULES 64
299 /* protocol enumeration for filters */
300 enum ice_fltr_ptype {
301 /* NONE - used for undef/error */
302 ICE_FLTR_PTYPE_NONF_NONE = 0,
303 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
304 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
305 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
306 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
307 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
308 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
309 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
310 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
311 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
312 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_OTHER,
313 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_IPV6_OTHER,
314 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
315 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
316 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
317 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
318 ICE_FLTR_PTYPE_NONF_IPV4_AH,
319 ICE_FLTR_PTYPE_NONF_IPV6_AH,
320 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
321 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
322 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
323 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
324 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
325 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
326 ICE_FLTR_PTYPE_NON_IP_L2,
327 ICE_FLTR_PTYPE_NONF_ECPRI_TP0,
328 ICE_FLTR_PTYPE_NONF_IPV4_UDP_ECPRI_TP0,
329 ICE_FLTR_PTYPE_FRAG_IPV4,
330 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
331 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
332 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
333 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
334 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN,
339 ICE_FD_HW_SEG_NON_TUN = 0,
344 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
345 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
347 struct ice_fd_hw_prof {
348 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
350 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
351 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
354 /* Common HW capabilities for SW use */
355 struct ice_hw_common_caps {
356 /* Write CSR protection */
359 /* switching mode supported - EVB switching (including cloud) */
360 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
362 /* Manageablity mode & supported protocols over MCTP */
364 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
365 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
366 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
368 u32 mgmt_protocols_mctp;
369 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
370 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
371 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
372 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
376 /* DCB capabilities */
377 u32 active_tc_bitmap;
380 /* RSS related capabilities */
381 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
382 u32 rss_table_entry_width; /* RSS Entry width in bits */
385 u32 num_rxq; /* Number/Total Rx queues */
386 u32 rxq_first_id; /* First queue ID for Rx queues */
387 u32 num_txq; /* Number/Total Tx queues */
388 u32 txq_first_id; /* First queue ID for Tx queues */
391 u32 num_msix_vectors;
392 u32 msix_vector_first_id;
394 /* Max MTU for function or device */
398 u32 num_wol_proxy_fltr;
399 u32 wol_proxy_vsi_seid;
401 /* LED/SDP pin count */
405 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
406 #define ICE_MAX_SUPPORTED_GPIO_LED 12
407 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
408 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
409 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
411 /* EVB capabilities */
412 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
413 u8 evb_802_1_qbh; /* Bridge Port Extension */
419 /* WoL and APM support */
420 #define ICE_WOL_SUPPORT_M BIT(0)
421 #define ICE_ACPI_PROG_MTHD_M BIT(1)
422 #define ICE_PROXY_SUPPORT_M BIT(2)
426 bool sec_rev_disabled;
427 bool update_disabled;
428 bool nvm_unified_update;
429 #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0)
430 #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1)
431 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
434 /* Function specific capabilities */
435 struct ice_hw_func_caps {
436 struct ice_hw_common_caps common_cap;
438 u32 fd_fltr_guar; /* Number of filters guaranteed */
439 u32 fd_fltr_best_effort; /* Number of best effort filters */
442 /* Device wide capabilities */
443 struct ice_hw_dev_caps {
444 struct ice_hw_common_caps common_cap;
445 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
446 u32 num_flow_director_fltr; /* Number of FD filters available */
450 /* Information about MAC such as address, etc... */
451 struct ice_mac_info {
452 u8 lan_addr[ETH_ALEN];
453 u8 perm_addr[ETH_ALEN];
454 u8 port_addr[ETH_ALEN];
455 u8 wol_addr[ETH_ALEN];
462 ice_bus_embedded, /* Is device Embedded versus card */
467 enum ice_pcie_bus_speed {
468 ice_pcie_speed_unknown = 0xff,
469 ice_pcie_speed_2_5GT = 0x14,
470 ice_pcie_speed_5_0GT = 0x15,
471 ice_pcie_speed_8_0GT = 0x16,
472 ice_pcie_speed_16_0GT = 0x17
476 enum ice_pcie_link_width {
477 ice_pcie_lnk_width_resrv = 0x00,
478 ice_pcie_lnk_x1 = 0x01,
479 ice_pcie_lnk_x2 = 0x02,
480 ice_pcie_lnk_x4 = 0x04,
481 ice_pcie_lnk_x8 = 0x08,
482 ice_pcie_lnk_x12 = 0x0C,
483 ice_pcie_lnk_x16 = 0x10,
484 ice_pcie_lnk_x32 = 0x20,
485 ice_pcie_lnk_width_unknown = 0xff,
488 /* Reset types used to determine which kind of reset was requested. These
489 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
490 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
491 * because its reset source is different than the other types listed.
503 struct ice_bus_info {
504 enum ice_pcie_bus_speed speed;
505 enum ice_pcie_link_width width;
506 enum ice_bus_type type;
513 /* Flow control (FC) parameters */
515 enum ice_fc_mode current_mode; /* FC mode in effect */
516 enum ice_fc_mode req_mode; /* FC mode requested by caller */
519 /* Option ROM version information */
520 struct ice_orom_info {
521 u8 major; /* Major version of OROM */
522 u8 patch; /* Patch version of OROM */
523 u16 build; /* Build version of OROM */
524 u32 srev; /* Security revision */
527 /* NVM version information */
528 struct ice_nvm_info {
535 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
536 * of the flash image.
538 enum ice_flash_bank {
539 ICE_INVALID_FLASH_BANK,
544 /* Enumeration of which flash bank is desired to read from, either the active
545 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
546 * code which just wants to read the active or inactive flash bank.
548 enum ice_bank_select {
549 ICE_ACTIVE_FLASH_BANK,
550 ICE_INACTIVE_FLASH_BANK,
553 /* information for accessing NVM, OROM, and Netlist flash banks */
554 struct ice_bank_info {
555 u32 nvm_ptr; /* Pointer to 1st NVM bank */
556 u32 nvm_size; /* Size of NVM bank */
557 u32 orom_ptr; /* Pointer to 1st OROM bank */
558 u32 orom_size; /* Size of OROM bank */
559 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
560 u32 netlist_size; /* Size of Netlist bank */
561 enum ice_flash_bank nvm_bank; /* Active NVM bank */
562 enum ice_flash_bank orom_bank; /* Active OROM bank */
563 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
566 /* Flash Chip Information */
567 struct ice_flash_info {
568 struct ice_orom_info orom; /* Option ROM version info */
569 struct ice_nvm_info nvm; /* NVM version information */
570 struct ice_bank_info banks; /* Flash Bank information */
571 u16 sr_words; /* Shadow RAM size in words */
572 u32 flash_size; /* Size of available flash in bytes */
573 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
576 struct ice_link_default_override_tlv {
578 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
579 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
580 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
581 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
582 #define ICE_LINK_OVERRIDE_EN BIT(3)
583 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
584 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
586 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
587 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
588 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
589 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
590 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
592 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
598 #define ICE_NVM_VER_LEN 32
600 /* Max number of port to queue branches w.r.t topology */
601 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
603 #define ice_for_each_traffic_class(_i) \
604 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
606 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
607 * to driver defined policy for default aggregator
609 #define ICE_INVAL_TEID 0xFFFFFFFF
610 #define ICE_DFLT_AGG_ID 0
612 struct ice_sched_node {
613 struct ice_sched_node *parent;
614 struct ice_sched_node *sibling; /* next sibling in the same layer */
615 struct ice_sched_node **children;
616 struct ice_aqc_txsched_elem_data info;
617 u32 agg_id; /* aggregator group ID */
619 u8 in_use; /* suspended or in use */
620 u8 tx_sched_layer; /* Logical Layer (1-9) */
624 #define ICE_SCHED_NODE_OWNER_LAN 0
625 #define ICE_SCHED_NODE_OWNER_AE 1
626 #define ICE_SCHED_NODE_OWNER_RDMA 2
629 /* Access Macros for Tx Sched Elements data */
630 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
631 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
632 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
633 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
634 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
635 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
636 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
637 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
638 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
639 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
640 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
642 struct ice_sched_rl_profile {
643 u32 rate; /* In Kbps */
644 struct ice_aqc_rl_profile_elem info;
647 /* The aggregator type determines if identifier is for a VSI group,
648 * aggregator group, aggregator of queues, or queue group.
651 ICE_AGG_TYPE_UNKNOWN = 0,
653 ICE_AGG_TYPE_AGG, /* aggregator */
659 /* Rate limit types */
662 ICE_MIN_BW, /* for CIR profile */
663 ICE_MAX_BW, /* for EIR profile */
664 ICE_SHARED_BW /* for shared profile */
667 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
668 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
669 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
670 #define ICE_SCHED_NO_PRIORITY 0
671 #define ICE_SCHED_NO_BW_WT 0
672 #define ICE_SCHED_DFLT_RL_PROF_ID 0
673 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
674 #define ICE_SCHED_DFLT_BW_WT 4
675 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
676 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
678 /* Access Macros for Tx Sched RL Profile data */
679 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
680 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
681 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
682 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
683 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
685 /* The following tree example shows the naming conventions followed under
686 * ice_port_info struct for default scheduler tree topology.
690 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
694 * / |-> num_elements (range:1 - 9)
695 * * | implies num_of_layers
699 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
700 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
701 * need TEID of (a) to add queues.
704 * -> has 8 branches (one for each TC)
705 * -> First branch (TC0) has 4 elements
707 * -> (a) is the topmost layer node created by firmware on branch 0
709 * Note: Above asterisk tree covers only basic terminology and scenario.
710 * Refer to the documentation for more info.
713 /* Data structure for saving BW information */
721 ICE_BW_TYPE_CNT /* This must be last */
729 struct ice_bw_type_info {
730 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
732 struct ice_bw cir_bw;
733 struct ice_bw eir_bw;
737 /* VSI queue context structure for given TC */
741 /* bw_t_info saves queue BW information */
742 struct ice_bw_type_info bw_t_info;
745 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
746 struct ice_sched_vsi_info {
747 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
748 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
749 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
750 /* bw_t_info saves VSI BW information */
751 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
754 /* CEE or IEEE 802.1Qaz ETS Configuration data */
755 struct ice_dcb_ets_cfg {
759 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
760 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
761 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
764 /* CEE or IEEE 802.1Qaz PFC Configuration data */
765 struct ice_dcb_pfc_cfg {
772 /* CEE or IEEE 802.1Qaz Application Priority data */
773 struct ice_dcb_app_priority_table {
779 #define ICE_MAX_USER_PRIORITY 8
780 #define ICE_DCBX_MAX_APPS 32
781 #define ICE_LLDPDU_SIZE 1500
782 #define ICE_TLV_STATUS_OPER 0x1
783 #define ICE_TLV_STATUS_SYNC 0x2
784 #define ICE_TLV_STATUS_ERR 0x4
785 #define ICE_APP_PROT_ID_FCOE 0x8906
786 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
787 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
788 #define ICE_APP_PROT_ID_FIP 0x8914
789 #define ICE_APP_SEL_ETHTYPE 0x1
790 #define ICE_APP_SEL_TCPIP 0x2
791 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
792 #define ICE_CEE_APP_SEL_TCPIP 0x1
794 struct ice_dcbx_cfg {
796 u32 tlv_status; /* CEE mode TLV status */
797 struct ice_dcb_ets_cfg etscfg;
798 struct ice_dcb_ets_cfg etsrec;
799 struct ice_dcb_pfc_cfg pfc;
800 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
802 #define ICE_DCBX_MODE_CEE 0x1
803 #define ICE_DCBX_MODE_IEEE 0x2
805 #define ICE_DCBX_APPS_NON_WILLING 0x1
809 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
810 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
811 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
812 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
816 struct ice_port_info {
817 struct ice_sched_node *root; /* Root Node per Port */
818 struct ice_hw *hw; /* back pointer to HW instance */
819 u32 last_node_teid; /* scheduler last node info */
820 u16 sw_id; /* Initial switch ID belongs to port */
823 #define ICE_SCHED_PORT_STATE_INIT 0x0
824 #define ICE_SCHED_PORT_STATE_READY 0x1
826 #define ICE_LPORT_MASK 0xff
827 u16 dflt_tx_vsi_rule_id;
829 u16 dflt_rx_vsi_rule_id;
831 struct ice_fc_info fc;
832 struct ice_mac_info mac;
833 struct ice_phy_info phy;
834 struct ice_lock sched_lock; /* protect access to TXSched tree */
835 struct ice_sched_node *
836 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
837 struct ice_bw_type_info root_node_bw_t_info;
838 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
839 struct ice_qos_cfg qos_cfg;
843 struct ice_switch_info {
844 struct LIST_HEAD_TYPE vsi_list_map_head;
845 struct ice_sw_recipe *recp_list;
846 u16 prof_res_bm_init;
847 u16 max_used_prof_index;
849 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
852 /* Port hardware description */
856 struct ice_aqc_layer_props *layer_info;
857 struct ice_port_info *port_info;
858 /* 2D Array for each Tx Sched RL Profile type */
859 struct ice_sched_rl_profile **cir_profiles;
860 struct ice_sched_rl_profile **eir_profiles;
861 struct ice_sched_rl_profile **srl_profiles;
862 /* PSM clock frequency for calculating RL profile params */
864 u64 debug_mask; /* BITMAP for debug mask */
865 enum ice_mac_type mac_type;
867 u16 fd_ctr_base; /* FD counter base index */
871 u16 subsystem_device_id;
872 u16 subsystem_vendor_id;
875 u8 pf_id; /* device profile info */
877 u16 max_burst_size; /* driver sets this value */
879 /* Tx Scheduler values */
880 u8 num_tx_sched_layers;
881 u8 num_tx_sched_phys_layers;
884 u8 sw_entry_point_layer;
885 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
886 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
887 /* List contain profile ID(s) and other params per layer */
888 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
889 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
890 u8 evb_veb; /* true for VEB, false for VEPA */
891 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
892 struct ice_bus_info bus;
893 struct ice_flash_info flash;
894 struct ice_hw_dev_caps dev_caps; /* device capabilities */
895 struct ice_hw_func_caps func_caps; /* function capabilities */
897 struct ice_switch_info *switch_info; /* switch filter lists */
899 /* Control Queue info */
900 struct ice_ctl_q_info adminq;
901 struct ice_ctl_q_info mailboxq;
902 /* Additional function to send AdminQ command */
903 int (*aq_send_cmd_fn)(void *param, struct ice_aq_desc *desc,
904 void *buf, u16 buf_size);
905 void *aq_send_cmd_param;
906 u8 dcf_enabled; /* Device Config Function */
908 u8 api_branch; /* API branch version */
909 u8 api_maj_ver; /* API major version */
910 u8 api_min_ver; /* API minor version */
911 u8 api_patch; /* API patch version */
912 u8 fw_branch; /* firmware branch version */
913 u8 fw_maj_ver; /* firmware major version */
914 u8 fw_min_ver; /* firmware minor version */
915 u8 fw_patch; /* firmware patch version */
916 u32 fw_build; /* firmware build number */
918 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
919 * register. Used for determining the ITR/INTRL granularity during
922 #define ICE_MAX_AGG_BW_200G 0x0
923 #define ICE_MAX_AGG_BW_100G 0X1
924 #define ICE_MAX_AGG_BW_50G 0x2
925 #define ICE_MAX_AGG_BW_25G 0x3
926 /* ITR granularity for different speeds */
927 #define ICE_ITR_GRAN_ABOVE_25 2
928 #define ICE_ITR_GRAN_MAX_25 4
929 /* ITR granularity in 1 us */
931 /* INTRL granularity for different speeds */
932 #define ICE_INTRL_GRAN_ABOVE_25 4
933 #define ICE_INTRL_GRAN_MAX_25 8
934 /* INTRL granularity in 1 us */
937 u8 ucast_shared; /* true if VSIs can share unicast addr */
939 #define ICE_PHY_PER_NAC 1
940 #define ICE_MAX_QUAD 2
941 #define ICE_NUM_QUAD_TYPE 2
942 #define ICE_PORTS_PER_QUAD 4
943 #define ICE_PHY_0_LAST_QUAD 1
944 #define ICE_PORTS_PER_PHY 8
945 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
947 /* Active package version (currently active) */
948 struct ice_pkg_ver active_pkg_ver;
950 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
951 u8 active_pkg_in_nvm;
953 enum ice_aq_err pkg_dwnld_status;
955 /* Driver's package ver - (from the Ice Metadata section) */
956 struct ice_pkg_ver pkg_ver;
957 u8 pkg_name[ICE_PKG_NAME_SIZE];
959 /* Driver's Ice segment format version and id (from the Ice seg) */
960 struct ice_pkg_ver ice_seg_fmt_ver;
961 u8 ice_seg_id[ICE_SEG_ID_SIZE];
963 /* Pointer to the ice segment */
966 /* Pointer to allocated copy of pkg memory */
971 struct ice_lock tnl_lock;
972 struct ice_tunnel_table tnl;
974 struct ice_acl_tbl *acl_tbl;
975 struct ice_fd_hw_prof **acl_prof;
976 u16 acl_fltr_cnt[ICE_FLTR_PTYPE_MAX];
977 /* HW block tables */
978 struct ice_blk_info blk[ICE_BLK_COUNT];
979 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
980 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
981 /* Flow Director filter info */
982 int fdir_active_fltr;
984 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
985 struct LIST_HEAD_TYPE fdir_list_head;
987 /* Book-keeping of side-band filter count per flow-type.
988 * This is used to detect and handle input set changes for
989 * respective flow-type.
991 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
993 struct ice_fd_hw_prof **fdir_prof;
994 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
995 struct ice_lock rss_locks; /* protect RSS configuration */
996 struct LIST_HEAD_TYPE rss_list_head;
997 struct ice_vlan_mode_ops vlan_mode_ops;
1000 /* Statistics collected by each port, VSI, VEB, and S-channel */
1001 struct ice_eth_stats {
1002 u64 rx_bytes; /* gorc */
1003 u64 rx_unicast; /* uprc */
1004 u64 rx_multicast; /* mprc */
1005 u64 rx_broadcast; /* bprc */
1006 u64 rx_discards; /* rdpc */
1007 u64 rx_unknown_protocol; /* rupp */
1008 u64 tx_bytes; /* gotc */
1009 u64 tx_unicast; /* uptc */
1010 u64 tx_multicast; /* mptc */
1011 u64 tx_broadcast; /* bptc */
1012 u64 tx_discards; /* tdpc */
1013 u64 tx_errors; /* tepc */
1014 u64 rx_no_desc; /* repc */
1015 u64 rx_errors; /* repc */
1018 #define ICE_MAX_UP 8
1020 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
1021 struct ice_veb_up_stats {
1022 u64 up_rx_pkts[ICE_MAX_UP];
1023 u64 up_rx_bytes[ICE_MAX_UP];
1024 u64 up_tx_pkts[ICE_MAX_UP];
1025 u64 up_tx_bytes[ICE_MAX_UP];
1028 /* Statistics collected by the MAC */
1029 struct ice_hw_port_stats {
1030 /* eth stats collected by the port */
1031 struct ice_eth_stats eth;
1032 /* additional port specific stats */
1033 u64 tx_dropped_link_down; /* tdold */
1034 u64 crc_errors; /* crcerrs */
1035 u64 illegal_bytes; /* illerrc */
1036 u64 error_bytes; /* errbc */
1037 u64 mac_local_faults; /* mlfc */
1038 u64 mac_remote_faults; /* mrfc */
1039 u64 rx_len_errors; /* rlec */
1040 u64 link_xon_rx; /* lxonrxc */
1041 u64 link_xoff_rx; /* lxoffrxc */
1042 u64 link_xon_tx; /* lxontxc */
1043 u64 link_xoff_tx; /* lxofftxc */
1044 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1045 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1046 u64 priority_xon_tx[8]; /* pxontxc[8] */
1047 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1048 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1049 u64 rx_size_64; /* prc64 */
1050 u64 rx_size_127; /* prc127 */
1051 u64 rx_size_255; /* prc255 */
1052 u64 rx_size_511; /* prc511 */
1053 u64 rx_size_1023; /* prc1023 */
1054 u64 rx_size_1522; /* prc1522 */
1055 u64 rx_size_big; /* prc9522 */
1056 u64 rx_undersize; /* ruc */
1057 u64 rx_fragments; /* rfc */
1058 u64 rx_oversize; /* roc */
1059 u64 rx_jabber; /* rjc */
1060 u64 tx_size_64; /* ptc64 */
1061 u64 tx_size_127; /* ptc127 */
1062 u64 tx_size_255; /* ptc255 */
1063 u64 tx_size_511; /* ptc511 */
1064 u64 tx_size_1023; /* ptc1023 */
1065 u64 tx_size_1522; /* ptc1522 */
1066 u64 tx_size_big; /* ptc9522 */
1067 u64 mac_short_pkt_dropped; /* mspdc */
1068 /* flow director stats */
1073 enum ice_sw_fwd_act_type {
1075 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1082 struct ice_aq_get_set_rss_lut_params {
1083 u16 vsi_handle; /* software VSI handle */
1084 u16 lut_size; /* size of the LUT buffer */
1085 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1086 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1087 u8 global_lut_id; /* only valid when lut_type is global */
1090 /* Checksum and Shadow RAM pointers */
1091 #define ICE_SR_NVM_CTRL_WORD 0x00
1092 #define ICE_SR_PHY_ANALOG_PTR 0x04
1093 #define ICE_SR_OPTION_ROM_PTR 0x05
1094 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1095 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1096 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1097 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
1098 #define ICE_SR_EMP_IMAGE_PTR 0x0B
1099 #define ICE_SR_PE_IMAGE_PTR 0x0C
1100 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
1101 #define ICE_SR_MNG_CFG_PTR 0x0E
1102 #define ICE_SR_EMP_MODULE_PTR 0x0F
1103 #define ICE_SR_PBA_BLOCK_PTR 0x16
1104 #define ICE_SR_BOOT_CFG_PTR 0x132
1105 #define ICE_SR_NVM_WOL_CFG 0x19
1106 #define ICE_NVM_OROM_VER_OFF 0x02
1107 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1108 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
1109 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
1110 #define ICE_SR_NVM_MAP_VER 0x29
1111 #define ICE_SR_NVM_IMAGE_VER 0x2A
1112 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
1113 #define ICE_SR_NVM_EETRACK_LO 0x2D
1114 #define ICE_SR_NVM_EETRACK_HI 0x2E
1115 #define ICE_NVM_VER_LO_SHIFT 0
1116 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1117 #define ICE_NVM_VER_HI_SHIFT 12
1118 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1119 #define ICE_OEM_EETRACK_ID 0xffffffff
1120 #define ICE_OROM_VER_PATCH_SHIFT 0
1121 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1122 #define ICE_OROM_VER_BUILD_SHIFT 8
1123 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1124 #define ICE_OROM_VER_SHIFT 24
1125 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1126 #define ICE_SR_VPD_PTR 0x2F
1127 #define ICE_SR_PXE_SETUP_PTR 0x30
1128 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
1129 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1130 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1131 #define ICE_SR_VLAN_CFG_PTR 0x37
1132 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1133 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1134 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1135 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1136 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
1137 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1138 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
1139 #define ICE_SR_PFA_PTR 0x40
1140 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
1141 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1142 #define ICE_SR_NVM_BANK_SIZE 0x43
1143 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1144 #define ICE_SR_OROM_BANK_SIZE 0x45
1145 #define ICE_SR_NETLIST_BANK_PTR 0x46
1146 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1147 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1148 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1149 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1150 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
1151 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1153 /* CSS Header words */
1154 #define ICE_NVM_CSS_SREV_L 0x14
1155 #define ICE_NVM_CSS_SREV_H 0x15
1157 /* Length of CSS header section in words */
1158 #define ICE_CSS_HEADER_LENGTH 330
1160 /* Offset of Shadow RAM copy in the NVM bank area. */
1161 #define ICE_NVM_SR_COPY_WORD_OFFSET ROUND_UP(ICE_CSS_HEADER_LENGTH, 32)
1163 /* Size in bytes of Option ROM trailer */
1164 #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH)
1166 /* The Link Topology Netlist section is stored as a series of words. It is
1167 * stored in the NVM as a TLV, with the first two words containing the type
1170 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1171 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1172 #define ICE_NETLIST_LEN_OFFSET 0x0001
1174 /* The Link Topology section follows the TLV header. When reading the netlist
1175 * using ice_read_netlist_module, we need to account for the 2-word TLV
1178 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1180 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1181 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1183 #define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0)
1185 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1186 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1187 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1189 /* netlist ID block field offsets (word offsets) */
1190 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1191 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1192 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1193 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1194 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1195 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1196 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1197 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1198 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1199 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1201 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1202 #define ICE_SR_VPD_SIZE_WORDS 512
1203 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1204 #define ICE_SR_CTRL_WORD_1_S 0x06
1205 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1206 #define ICE_SR_CTRL_WORD_VALID 0x1
1207 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1208 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1209 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1211 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1213 /* Shadow RAM related */
1214 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1215 #define ICE_SR_BUF_ALIGNMENT 4096
1216 #define ICE_SR_WORDS_IN_1KB 512
1217 /* Checksum should be calculated such that after adding all the words,
1218 * including the checksum word itself, the sum should be 0xBABA.
1220 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1222 /* Link override related */
1223 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1224 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1225 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1226 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1227 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1228 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1229 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1230 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1232 #define ICE_PBA_FLAG_DFLT 0xFAFA
1233 /* Hash redirection LUT for VSI - maximum array size */
1234 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1237 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1238 * This is needed to determine the BAR0 space for the VFs
1240 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1241 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1242 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1244 /* AQ API version for LLDP_FILTER_CONTROL */
1245 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1246 #define ICE_FW_API_LLDP_FLTR_MIN 7
1247 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1249 /* AQ API version for report default configuration */
1250 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1251 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1252 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1253 #endif /* _ICE_TYPE_H_ */