1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
17 #define ICE_BYTES_PER_WORD 2
18 #define ICE_BYTES_PER_DWORD 4
19 #define ICE_MAX_TRAFFIC_CLASS 8
22 #include "ice_status.h"
23 #include "ice_hw_autogen.h"
24 #include "ice_devids.h"
25 #include "ice_osdep.h"
26 #include "ice_controlq.h"
27 #include "ice_lan_tx_rx.h"
28 #include "ice_flex_type.h"
29 #include "ice_protocol_type.h"
31 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
33 return ice_is_bit_set(&bitmap, tc);
37 #define DIV_64BIT(n, d) ((n) / (d))
38 #endif /* DIV_64BIT */
40 static inline u64 round_up_64bit(u64 a, u32 b)
42 return DIV_64BIT(((a) + (b) / 2), (b));
45 static inline u32 ice_round_to_num(u32 N, u32 R)
47 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
48 ((((N) + (R) - 1) / (R)) * (R)));
51 /* Driver always calls main vsi_handle first */
52 #define ICE_MAIN_VSI_HANDLE 0
54 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
55 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
57 /* Data type manipulation macros. */
58 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
59 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
60 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
62 /* debug masks - set these bits in hw->debug_mask to control output */
63 #define ICE_DBG_INIT BIT_ULL(1)
64 #define ICE_DBG_RELEASE BIT_ULL(2)
66 #define ICE_DBG_LINK BIT_ULL(4)
67 #define ICE_DBG_PHY BIT_ULL(5)
68 #define ICE_DBG_QCTX BIT_ULL(6)
69 #define ICE_DBG_NVM BIT_ULL(7)
70 #define ICE_DBG_LAN BIT_ULL(8)
71 #define ICE_DBG_FLOW BIT_ULL(9)
72 #define ICE_DBG_DCB BIT_ULL(10)
73 #define ICE_DBG_DIAG BIT_ULL(11)
74 #define ICE_DBG_FD BIT_ULL(12)
75 #define ICE_DBG_SW BIT_ULL(13)
76 #define ICE_DBG_SCHED BIT_ULL(14)
78 #define ICE_DBG_PKG BIT_ULL(16)
79 #define ICE_DBG_RES BIT_ULL(17)
80 #define ICE_DBG_AQ_MSG BIT_ULL(24)
81 #define ICE_DBG_AQ_DESC BIT_ULL(25)
82 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
83 #define ICE_DBG_AQ_CMD BIT_ULL(27)
84 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
86 ICE_DBG_AQ_DESC_BUF | \
89 #define ICE_DBG_USER BIT_ULL(31)
90 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
100 ICE_CHANGE_LOCK_RES_ID,
101 ICE_GLOBAL_CFG_LOCK_RES_ID
104 /* FW update timeout definitions are in milliseconds */
105 #define ICE_NVM_TIMEOUT 180000
106 #define ICE_CHANGE_LOCK_TIMEOUT 1000
107 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
109 enum ice_aq_res_access_type {
114 struct ice_driver_ver {
119 u8 driver_string[32];
138 enum ice_set_fc_aq_failures {
139 ICE_SET_FC_AQ_FAIL_NONE = 0,
140 ICE_SET_FC_AQ_FAIL_GET,
141 ICE_SET_FC_AQ_FAIL_SET,
142 ICE_SET_FC_AQ_FAIL_UPDATE
145 /* These are structs for managing the hardware information and the operations */
153 enum ice_media_type {
154 ICE_MEDIA_UNKNOWN = 0,
161 /* Software VSI types. */
166 #endif /* ADQ_SUPPORT */
169 struct ice_link_status {
170 /* Refer to ice_aq_phy_type for bits definition */
173 u8 topo_media_conflict;
177 u8 lse_ena; /* Link Status Event notification */
183 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
184 * ice_aqc_get_phy_caps structure
186 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
189 /* Different data queue types: These are mainly for SW consumption. */
198 /* Different reset sources for which a disable queue AQ call has to be made in
199 * order to clean the TX scheduler as a part of the reset
201 enum ice_disq_rst_src {
206 /* PHY info such as phy_type, etc... */
207 struct ice_phy_info {
208 struct ice_link_status link_info;
209 struct ice_link_status link_info_old;
212 enum ice_media_type media_type;
216 #define ICE_MAX_NUM_MIRROR_RULES 64
218 /* Common HW capabilities for SW use */
219 struct ice_hw_common_caps {
220 /* Write CSR protection */
223 /* switching mode supported - EVB switching (including cloud) */
224 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
226 /* Manageablity mode & supported protocols over MCTP */
228 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
229 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
230 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
232 u32 mgmt_protocols_mctp;
233 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
234 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
235 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
236 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
241 /* RSS related capabilities */
242 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
243 u32 rss_table_entry_width; /* RSS Entry width in bits */
246 u32 num_rxq; /* Number/Total RX queues */
247 u32 rxq_first_id; /* First queue ID for RX queues */
248 u32 num_txq; /* Number/Total TX queues */
249 u32 txq_first_id; /* First queue ID for TX queues */
252 u32 num_msix_vectors;
253 u32 msix_vector_first_id;
255 /* Max MTU for function or device */
259 u32 num_wol_proxy_fltr;
260 u32 wol_proxy_vsi_seid;
262 /* LED/SDP pin count */
266 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
267 #define ICE_MAX_SUPPORTED_GPIO_LED 12
268 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
269 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
270 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
272 /* EVB capabilities */
273 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
274 u8 evb_802_1_qbh; /* Bridge Port Extension */
279 /* WoL and APM support */
280 #define ICE_WOL_SUPPORT_M BIT(0)
281 #define ICE_ACPI_PROG_MTHD_M BIT(1)
282 #define ICE_PROXY_SUPPORT_M BIT(2)
289 /* Function specific capabilities */
290 struct ice_hw_func_caps {
291 struct ice_hw_common_caps common_cap;
295 /* Device wide capabilities */
296 struct ice_hw_dev_caps {
297 struct ice_hw_common_caps common_cap;
298 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
302 /* Information about MAC such as address, etc... */
303 struct ice_mac_info {
304 u8 lan_addr[ETH_ALEN];
305 u8 perm_addr[ETH_ALEN];
306 u8 port_addr[ETH_ALEN];
307 u8 wol_addr[ETH_ALEN];
314 ice_bus_embedded, /* Is device Embedded versus card */
319 enum ice_pcie_bus_speed {
320 ice_pcie_speed_unknown = 0xff,
321 ice_pcie_speed_2_5GT = 0x14,
322 ice_pcie_speed_5_0GT = 0x15,
323 ice_pcie_speed_8_0GT = 0x16,
324 ice_pcie_speed_16_0GT = 0x17
328 enum ice_pcie_link_width {
329 ice_pcie_lnk_width_resrv = 0x00,
330 ice_pcie_lnk_x1 = 0x01,
331 ice_pcie_lnk_x2 = 0x02,
332 ice_pcie_lnk_x4 = 0x04,
333 ice_pcie_lnk_x8 = 0x08,
334 ice_pcie_lnk_x12 = 0x0C,
335 ice_pcie_lnk_x16 = 0x10,
336 ice_pcie_lnk_x32 = 0x20,
337 ice_pcie_lnk_width_unknown = 0xff,
340 /* Reset types used to determine which kind of reset was requested. These
341 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
342 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
343 * because its reset source is different than the other types listed.
355 struct ice_bus_info {
356 enum ice_pcie_bus_speed speed;
357 enum ice_pcie_link_width width;
358 enum ice_bus_type type;
365 /* Flow control (FC) parameters */
367 enum ice_fc_mode current_mode; /* FC mode in effect */
368 enum ice_fc_mode req_mode; /* FC mode requested by caller */
371 /* NVM Information */
372 struct ice_nvm_info {
373 u32 eetrack; /* NVM data version */
374 u32 oem_ver; /* OEM version info */
375 u16 sr_words; /* Shadow RAM size in words */
376 u16 ver; /* NVM package version */
377 u8 blank_nvm_mode; /* is NVM empty (no FW present)*/
380 /* Max number of port to queue branches w.r.t topology */
381 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
382 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
383 * to driver defined policy for default aggregator
385 #define ICE_INVAL_TEID 0xFFFFFFFF
386 #define ICE_DFLT_AGG_ID 0
388 struct ice_sched_node {
389 struct ice_sched_node *parent;
390 struct ice_sched_node *sibling; /* next sibling in the same layer */
391 struct ice_sched_node **children;
392 struct ice_aqc_txsched_elem_data info;
393 u32 agg_id; /* aggregator group id */
395 u8 in_use; /* suspended or in use */
396 u8 tx_sched_layer; /* Logical Layer (1-9) */
400 #define ICE_SCHED_NODE_OWNER_LAN 0
401 #define ICE_SCHED_NODE_OWNER_AE 1
402 #define ICE_SCHED_NODE_OWNER_RDMA 2
405 /* Access Macros for Tx Sched Elements data */
406 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
407 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
408 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
409 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
410 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
411 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
412 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
413 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
414 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
415 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
416 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
418 struct ice_sched_rl_profle {
419 u32 rate; /* In Kbps */
420 struct ice_aqc_rl_profile_elem info;
423 /* The aggregator type determines if identifier is for a VSI group,
424 * aggregator group, aggregator of queues, or queue group.
427 ICE_AGG_TYPE_UNKNOWN = 0,
429 ICE_AGG_TYPE_AGG, /* aggregator */
435 /* Rate limit types */
438 ICE_MIN_BW, /* for cir profile */
439 ICE_MAX_BW, /* for eir profile */
440 ICE_SHARED_BW /* for shared profile */
443 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
444 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
445 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
446 #define ICE_SCHED_NO_PRIORITY 0
447 #define ICE_SCHED_NO_BW_WT 0
448 #define ICE_SCHED_DFLT_RL_PROF_ID 0
449 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
450 #define ICE_SCHED_DFLT_BW_WT 1
451 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
452 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
454 /* Access Macros for Tx Sched RL Profile data */
455 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
456 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
457 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
458 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
459 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
462 /* The following tree example shows the naming conventions followed under
463 * ice_port_info struct for default scheduler tree topology.
467 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
471 * / |-> num_elements (range:1 - 9)
472 * * | implies num_of_layers
476 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
477 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
478 * need teid of (a) to add queues.
481 * -> has 8 branches (one for each TC)
482 * -> First branch (TC0) has 4 elements
484 * -> (a) is the topmost layer node created by firmware on branch 0
486 * Note: Above asterisk tree covers only basic terminology and scenario.
487 * Refer to the documentation for more info.
490 /* Data structure for saving bw information */
498 ICE_BW_TYPE_CNT /* This must be last */
506 struct ice_bw_type_info {
507 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
509 struct ice_bw cir_bw;
510 struct ice_bw eir_bw;
514 /* vsi type list entry to locate corresponding vsi/ag nodes */
515 struct ice_sched_vsi_info {
516 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
517 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
518 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
519 /* bw_t_info saves VSI bw information */
520 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
523 #if !defined(NO_DCB_SUPPORT) || defined(ADQ_SUPPORT)
524 /* CEE or IEEE 802.1Qaz ETS Configuration data */
525 struct ice_dcb_ets_cfg {
529 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
530 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
531 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
534 /* CEE or IEEE 802.1Qaz PFC Configuration data */
535 struct ice_dcb_pfc_cfg {
542 /* CEE or IEEE 802.1Qaz Application Priority data */
543 struct ice_dcb_app_priority_table {
549 #define ICE_MAX_USER_PRIORITY 8
550 #define ICE_DCBX_MAX_APPS 32
551 #define ICE_LLDPDU_SIZE 1500
552 #define ICE_TLV_STATUS_OPER 0x1
553 #define ICE_TLV_STATUS_SYNC 0x2
554 #define ICE_TLV_STATUS_ERR 0x4
555 #define ICE_APP_PROT_ID_FCOE 0x8906
556 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
557 #define ICE_APP_PROT_ID_FIP 0x8914
558 #define ICE_APP_SEL_ETHTYPE 0x1
559 #define ICE_APP_SEL_TCPIP 0x2
560 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
561 #define ICE_CEE_APP_SEL_TCPIP 0x1
563 struct ice_dcbx_cfg {
565 u32 tlv_status; /* CEE mode TLV status */
566 struct ice_dcb_ets_cfg etscfg;
567 struct ice_dcb_ets_cfg etsrec;
568 struct ice_dcb_pfc_cfg pfc;
569 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
571 #define ICE_DCBX_MODE_CEE 0x1
572 #define ICE_DCBX_MODE_IEEE 0x2
574 #define ICE_DCBX_APPS_NON_WILLING 0x1
576 #endif /* !NO_DCB_SUPPORT || ADQ_SUPPORT */
578 struct ice_port_info {
579 struct ice_sched_node *root; /* Root Node per Port */
580 struct ice_hw *hw; /* back pointer to hw instance */
581 u32 last_node_teid; /* scheduler last node info */
582 u16 sw_id; /* Initial switch ID belongs to port */
585 #define ICE_SCHED_PORT_STATE_INIT 0x0
586 #define ICE_SCHED_PORT_STATE_READY 0x1
587 u16 dflt_tx_vsi_rule_id;
589 u16 dflt_rx_vsi_rule_id;
591 struct ice_fc_info fc;
592 struct ice_mac_info mac;
593 struct ice_phy_info phy;
594 struct ice_lock sched_lock; /* protect access to TXSched tree */
595 /* List contain profile id(s) and other params per layer */
596 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
597 #if !defined(NO_DCB_SUPPORT) || defined(ADQ_SUPPORT)
598 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
599 #endif /* !NO_DCB_SUPPORT || ADQ_SUPPORT */
601 #define ICE_LPORT_MASK 0xff
605 struct ice_switch_info {
606 struct LIST_HEAD_TYPE vsi_list_map_head;
607 struct ice_sw_recipe *recp_list;
610 /* FW logging configuration */
611 struct ice_fw_log_evnt {
612 u8 cfg : 4; /* New event enables to configure */
613 u8 cur : 4; /* Current/active event enables */
616 struct ice_fw_log_cfg {
617 u8 cq_en : 1; /* FW logging is enabled via the control queue */
618 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
619 u8 actv_evnts; /* Cumulation of currently enabled log events */
621 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
622 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
623 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
624 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
625 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
628 /* Port hardware description */
632 struct ice_aqc_layer_props *layer_info;
633 struct ice_port_info *port_info;
634 /* 2D Array for each Tx Sched RL Profile type */
635 struct ice_sched_rl_profile **cir_profiles;
636 struct ice_sched_rl_profile **eir_profiles;
637 struct ice_sched_rl_profile **srl_profiles;
638 u64 debug_mask; /* BITMAP for debug mask */
639 enum ice_mac_type mac_type;
644 u16 subsystem_device_id;
645 u16 subsystem_vendor_id;
648 u8 pf_id; /* device profile info */
650 u16 max_burst_size; /* driver sets this value */
651 /* TX Scheduler values */
652 u16 num_tx_sched_layers;
653 u16 num_tx_sched_phys_layers;
656 u8 sw_entry_point_layer;
657 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
658 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
659 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
660 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
661 u8 evb_veb; /* true for VEB, false for VEPA */
662 u8 reset_ongoing; /* true if hw is in reset, false otherwise */
663 struct ice_bus_info bus;
664 struct ice_nvm_info nvm;
665 struct ice_hw_dev_caps dev_caps; /* device capabilities */
666 struct ice_hw_func_caps func_caps; /* function capabilities */
668 struct ice_switch_info *switch_info; /* switch filter lists */
670 /* Control Queue info */
671 struct ice_ctl_q_info adminq;
672 struct ice_ctl_q_info mailboxq;
674 u8 api_branch; /* API branch version */
675 u8 api_maj_ver; /* API major version */
676 u8 api_min_ver; /* API minor version */
677 u8 api_patch; /* API patch version */
678 u8 fw_branch; /* firmware branch version */
679 u8 fw_maj_ver; /* firmware major version */
680 u8 fw_min_ver; /* firmware minor version */
681 u8 fw_patch; /* firmware patch version */
682 u32 fw_build; /* firmware build number */
684 struct ice_fw_log_cfg fw_log;
686 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
687 * register. Used for determining the itr/intrl granularity during
690 #define ICE_MAX_AGG_BW_200G 0x0
691 #define ICE_MAX_AGG_BW_100G 0X1
692 #define ICE_MAX_AGG_BW_50G 0x2
693 #define ICE_MAX_AGG_BW_25G 0x3
694 /* ITR granularity for different speeds */
695 #define ICE_ITR_GRAN_ABOVE_25 2
696 #define ICE_ITR_GRAN_MAX_25 4
697 /* ITR granularity in 1 us */
699 /* INTRL granularity for different speeds */
700 #define ICE_INTRL_GRAN_ABOVE_25 4
701 #define ICE_INTRL_GRAN_MAX_25 8
702 /* INTRL granularity in 1 us */
705 u8 ucast_shared; /* true if VSIs can share unicast addr */
709 /* Statistics collected by each port, VSI, VEB, and S-channel */
710 struct ice_eth_stats {
711 u64 rx_bytes; /* gorc */
712 u64 rx_unicast; /* uprc */
713 u64 rx_multicast; /* mprc */
714 u64 rx_broadcast; /* bprc */
715 u64 rx_discards; /* rdpc */
716 u64 rx_unknown_protocol; /* rupp */
717 u64 tx_bytes; /* gotc */
718 u64 tx_unicast; /* uptc */
719 u64 tx_multicast; /* mptc */
720 u64 tx_broadcast; /* bptc */
721 u64 tx_discards; /* tdpc */
722 u64 tx_errors; /* tepc */
727 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
728 struct ice_veb_up_stats {
729 u64 up_rx_pkts[ICE_MAX_UP];
730 u64 up_rx_bytes[ICE_MAX_UP];
731 u64 up_tx_pkts[ICE_MAX_UP];
732 u64 up_tx_bytes[ICE_MAX_UP];
735 /* Statistics collected by the MAC */
736 struct ice_hw_port_stats {
737 /* eth stats collected by the port */
738 struct ice_eth_stats eth;
739 /* additional port specific stats */
740 u64 tx_dropped_link_down; /* tdold */
741 u64 crc_errors; /* crcerrs */
742 u64 illegal_bytes; /* illerrc */
743 u64 error_bytes; /* errbc */
744 u64 mac_local_faults; /* mlfc */
745 u64 mac_remote_faults; /* mrfc */
746 u64 rx_len_errors; /* rlec */
747 u64 link_xon_rx; /* lxonrxc */
748 u64 link_xoff_rx; /* lxoffrxc */
749 u64 link_xon_tx; /* lxontxc */
750 u64 link_xoff_tx; /* lxofftxc */
751 u64 rx_size_64; /* prc64 */
752 u64 rx_size_127; /* prc127 */
753 u64 rx_size_255; /* prc255 */
754 u64 rx_size_511; /* prc511 */
755 u64 rx_size_1023; /* prc1023 */
756 u64 rx_size_1522; /* prc1522 */
757 u64 rx_size_big; /* prc9522 */
758 u64 rx_undersize; /* ruc */
759 u64 rx_fragments; /* rfc */
760 u64 rx_oversize; /* roc */
761 u64 rx_jabber; /* rjc */
762 u64 tx_size_64; /* ptc64 */
763 u64 tx_size_127; /* ptc127 */
764 u64 tx_size_255; /* ptc255 */
765 u64 tx_size_511; /* ptc511 */
766 u64 tx_size_1023; /* ptc1023 */
767 u64 tx_size_1522; /* ptc1522 */
768 u64 tx_size_big; /* ptc9522 */
769 u64 mac_short_pkt_dropped; /* mspdc */
772 enum ice_sw_fwd_act_type {
774 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
781 /* Checksum and Shadow RAM pointers */
782 #define ICE_SR_NVM_CTRL_WORD 0x00
783 #define ICE_SR_PHY_ANALOG_PTR 0x04
784 #define ICE_SR_OPTION_ROM_PTR 0x05
785 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
786 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
787 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
788 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
789 #define ICE_SR_EMP_IMAGE_PTR 0x0B
790 #define ICE_SR_PE_IMAGE_PTR 0x0C
791 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
792 #define ICE_SR_MNG_CFG_PTR 0x0E
793 #define ICE_SR_EMP_MODULE_PTR 0x0F
794 #define ICE_SR_PBA_FLAGS 0x15
795 #define ICE_SR_PBA_BLOCK_PTR 0x16
796 #define ICE_SR_BOOT_CFG_PTR 0x17
797 #define ICE_SR_NVM_WOL_CFG 0x19
798 #define ICE_NVM_OEM_VER_OFF 0x83
799 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
800 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
801 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
802 #define ICE_SR_NVM_MAP_VER 0x29
803 #define ICE_SR_NVM_IMAGE_VER 0x2A
804 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
805 #define ICE_SR_NVM_EETRACK_LO 0x2D
806 #define ICE_SR_NVM_EETRACK_HI 0x2E
807 #define ICE_NVM_VER_LO_SHIFT 0
808 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
809 #define ICE_NVM_VER_HI_SHIFT 12
810 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
811 #define ICE_OEM_EETRACK_ID 0xffffffff
812 #define ICE_OEM_VER_PATCH_SHIFT 0
813 #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT)
814 #define ICE_OEM_VER_BUILD_SHIFT 8
815 #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT)
816 #define ICE_OEM_VER_SHIFT 24
817 #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT)
818 #define ICE_SR_VPD_PTR 0x2F
819 #define ICE_SR_PXE_SETUP_PTR 0x30
820 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
821 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
822 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
823 #define ICE_SR_VLAN_CFG_PTR 0x37
824 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
825 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
826 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
827 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
828 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
829 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
830 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
831 #define ICE_SR_PFA_PTR 0x40
832 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
833 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
834 #define ICE_SR_NVM_BANK_SIZE 0x43
835 #define ICE_SR_1ND_OROM_BANK_PTR 0x44
836 #define ICE_SR_OROM_BANK_SIZE 0x45
837 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
838 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
839 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
841 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
842 #define ICE_SR_VPD_SIZE_WORDS 512
843 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
844 #define ICE_SR_CTRL_WORD_1_S 0x06
845 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
847 /* Shadow RAM related */
848 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
849 #define ICE_SR_BUF_ALIGNMENT 4096
850 #define ICE_SR_WORDS_IN_1KB 512
851 /* Checksum should be calculated such that after adding all the words,
852 * including the checksum word itself, the sum should be 0xBABA.
854 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
856 #define ICE_PBA_FLAG_DFLT 0xFAFA
857 /* Hash redirection LUT for VSI - maximum array size */
858 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
861 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
862 * This is needed to determine the BAR0 space for the VFs
864 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
865 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
866 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
868 #endif /* _ICE_TYPE_H_ */