1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
21 #define ICE_BYTES_PER_WORD 2
22 #define ICE_BYTES_PER_DWORD 4
23 #define ICE_MAX_TRAFFIC_CLASS 8
25 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
27 #define IS_ASCII(_ch) ((_ch) < 0x80)
29 #include "ice_status.h"
30 #include "ice_hw_autogen.h"
31 #include "ice_devids.h"
32 #include "ice_osdep.h"
33 #include "ice_bitops.h" /* Must come before ice_controlq.h */
34 #include "ice_controlq.h"
35 #include "ice_lan_tx_rx.h"
36 #include "ice_flex_type.h"
37 #include "ice_protocol_type.h"
39 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
41 return ice_is_bit_set(&bitmap, tc);
44 #define DIV_64BIT(n, d) ((n) / (d))
46 static inline u64 round_up_64bit(u64 a, u32 b)
48 return DIV_64BIT(((a) + (b) / 2), (b));
51 static inline u32 ice_round_to_num(u32 N, u32 R)
53 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
54 ((((N) + (R) - 1) / (R)) * (R)));
57 /* Driver always calls main vsi_handle first */
58 #define ICE_MAIN_VSI_HANDLE 0
60 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
61 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
63 /* Data type manipulation macros. */
64 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
65 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
66 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
68 /* debug masks - set these bits in hw->debug_mask to control output */
69 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
70 #define ICE_DBG_INIT BIT_ULL(1)
71 #define ICE_DBG_RELEASE BIT_ULL(2)
72 #define ICE_DBG_FW_LOG BIT_ULL(3)
73 #define ICE_DBG_LINK BIT_ULL(4)
74 #define ICE_DBG_PHY BIT_ULL(5)
75 #define ICE_DBG_QCTX BIT_ULL(6)
76 #define ICE_DBG_NVM BIT_ULL(7)
77 #define ICE_DBG_LAN BIT_ULL(8)
78 #define ICE_DBG_FLOW BIT_ULL(9)
79 #define ICE_DBG_DCB BIT_ULL(10)
80 #define ICE_DBG_DIAG BIT_ULL(11)
81 #define ICE_DBG_FD BIT_ULL(12)
82 #define ICE_DBG_SW BIT_ULL(13)
83 #define ICE_DBG_SCHED BIT_ULL(14)
85 #define ICE_DBG_PKG BIT_ULL(16)
86 #define ICE_DBG_RES BIT_ULL(17)
87 #define ICE_DBG_AQ_MSG BIT_ULL(24)
88 #define ICE_DBG_AQ_DESC BIT_ULL(25)
89 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
90 #define ICE_DBG_AQ_CMD BIT_ULL(27)
91 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
93 ICE_DBG_AQ_DESC_BUF | \
96 #define ICE_DBG_USER BIT_ULL(31)
97 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
99 #ifndef __ALWAYS_UNUSED
100 #define __ALWAYS_UNUSED
107 enum ice_aq_res_ids {
110 ICE_CHANGE_LOCK_RES_ID,
111 ICE_GLOBAL_CFG_LOCK_RES_ID
114 /* FW update timeout definitions are in milliseconds */
115 #define ICE_NVM_TIMEOUT 180000
116 #define ICE_CHANGE_LOCK_TIMEOUT 1000
117 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
119 enum ice_aq_res_access_type {
124 struct ice_driver_ver {
129 u8 driver_string[32];
141 enum ice_phy_cache_mode {
154 struct ice_phy_cache_mode_data {
156 enum ice_fec_mode curr_user_fec_req;
157 enum ice_fc_mode curr_user_fc_req;
158 u16 curr_user_speed_req;
162 enum ice_set_fc_aq_failures {
163 ICE_SET_FC_AQ_FAIL_NONE = 0,
164 ICE_SET_FC_AQ_FAIL_GET,
165 ICE_SET_FC_AQ_FAIL_SET,
166 ICE_SET_FC_AQ_FAIL_UPDATE
169 /* These are structs for managing the hardware information and the operations */
177 enum ice_media_type {
178 ICE_MEDIA_UNKNOWN = 0,
185 /* Software VSI types. */
188 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
192 struct ice_link_status {
193 /* Refer to ice_aq_phy_type for bits definition */
196 u8 topo_media_conflict;
200 u8 lse_ena; /* Link Status Event notification */
206 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
207 * ice_aqc_get_phy_caps structure
209 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
212 /* Different data queue types: These are mainly for SW consumption. */
221 /* Different reset sources for which a disable queue AQ call has to be made in
222 * order to clean the Tx scheduler as a part of the reset
224 enum ice_disq_rst_src {
229 /* PHY info such as phy_type, etc... */
230 struct ice_phy_info {
231 struct ice_link_status link_info;
232 struct ice_link_status link_info_old;
235 enum ice_media_type media_type;
237 /* Please refer to struct ice_aqc_get_link_status_data to get
238 * detail of enable bit in curr_user_speed_req
240 u16 curr_user_speed_req;
241 enum ice_fec_mode curr_user_fec_req;
242 enum ice_fc_mode curr_user_fc_req;
243 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
246 #define ICE_MAX_NUM_MIRROR_RULES 64
248 /* protocol enumeration for filters */
249 enum ice_fltr_ptype {
250 /* NONE - used for undef/error */
251 ICE_FLTR_PTYPE_NONF_NONE = 0,
252 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
253 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
254 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
255 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
256 ICE_FLTR_PTYPE_FRAG_IPV4,
257 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
258 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
259 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
260 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
264 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
265 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
267 struct ice_fd_hw_prof {
268 struct ice_flow_seg_info *fdir_seg;
270 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER];
271 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
274 /* Common HW capabilities for SW use */
275 struct ice_hw_common_caps {
276 /* Write CSR protection */
279 /* switching mode supported - EVB switching (including cloud) */
280 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
282 /* Manageablity mode & supported protocols over MCTP */
284 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
285 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
286 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
288 u32 mgmt_protocols_mctp;
289 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
290 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
291 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
292 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
296 /* DCB capabilities */
297 u32 active_tc_bitmap;
300 /* RSS related capabilities */
301 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
302 u32 rss_table_entry_width; /* RSS Entry width in bits */
305 u32 num_rxq; /* Number/Total Rx queues */
306 u32 rxq_first_id; /* First queue ID for Rx queues */
307 u32 num_txq; /* Number/Total Tx queues */
308 u32 txq_first_id; /* First queue ID for Tx queues */
311 u32 num_msix_vectors;
312 u32 msix_vector_first_id;
314 /* Max MTU for function or device */
318 u32 num_wol_proxy_fltr;
319 u32 wol_proxy_vsi_seid;
321 /* LED/SDP pin count */
325 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
326 #define ICE_MAX_SUPPORTED_GPIO_LED 12
327 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
328 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
329 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
331 /* EVB capabilities */
332 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
333 u8 evb_802_1_qbh; /* Bridge Port Extension */
339 /* WoL and APM support */
340 #define ICE_WOL_SUPPORT_M BIT(0)
341 #define ICE_ACPI_PROG_MTHD_M BIT(1)
342 #define ICE_PROXY_SUPPORT_M BIT(2)
349 /* Function specific capabilities */
350 struct ice_hw_func_caps {
351 struct ice_hw_common_caps common_cap;
353 u32 fd_fltr_guar; /* Number of filters guaranteed */
354 u32 fd_fltr_best_effort; /* Number of best effort filters */
357 /* Device wide capabilities */
358 struct ice_hw_dev_caps {
359 struct ice_hw_common_caps common_cap;
360 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
361 u32 num_flow_director_fltr; /* Number of FD filters available */
366 /* Information about MAC such as address, etc... */
367 struct ice_mac_info {
368 u8 lan_addr[ETH_ALEN];
369 u8 perm_addr[ETH_ALEN];
370 u8 port_addr[ETH_ALEN];
371 u8 wol_addr[ETH_ALEN];
378 ice_bus_embedded, /* Is device Embedded versus card */
383 enum ice_pcie_bus_speed {
384 ice_pcie_speed_unknown = 0xff,
385 ice_pcie_speed_2_5GT = 0x14,
386 ice_pcie_speed_5_0GT = 0x15,
387 ice_pcie_speed_8_0GT = 0x16,
388 ice_pcie_speed_16_0GT = 0x17
392 enum ice_pcie_link_width {
393 ice_pcie_lnk_width_resrv = 0x00,
394 ice_pcie_lnk_x1 = 0x01,
395 ice_pcie_lnk_x2 = 0x02,
396 ice_pcie_lnk_x4 = 0x04,
397 ice_pcie_lnk_x8 = 0x08,
398 ice_pcie_lnk_x12 = 0x0C,
399 ice_pcie_lnk_x16 = 0x10,
400 ice_pcie_lnk_x32 = 0x20,
401 ice_pcie_lnk_width_unknown = 0xff,
404 /* Reset types used to determine which kind of reset was requested. These
405 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
406 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
407 * because its reset source is different than the other types listed.
419 struct ice_bus_info {
420 enum ice_pcie_bus_speed speed;
421 enum ice_pcie_link_width width;
422 enum ice_bus_type type;
429 /* Flow control (FC) parameters */
431 enum ice_fc_mode current_mode; /* FC mode in effect */
432 enum ice_fc_mode req_mode; /* FC mode requested by caller */
435 /* NVM Information */
436 struct ice_nvm_info {
437 u32 eetrack; /* NVM data version */
438 u32 oem_ver; /* OEM version info */
439 u16 sr_words; /* Shadow RAM size in words */
440 u16 ver; /* dev starter version */
441 u8 blank_nvm_mode; /* is NVM empty (no FW present)*/
444 #define ICE_NVM_VER_LEN 32
446 /* Max number of port to queue branches w.r.t topology */
447 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
449 #define ice_for_each_traffic_class(_i) \
450 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
452 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
453 * to driver defined policy for default aggregator
455 #define ICE_INVAL_TEID 0xFFFFFFFF
456 #define ICE_DFLT_AGG_ID 0
458 struct ice_sched_node {
459 struct ice_sched_node *parent;
460 struct ice_sched_node *sibling; /* next sibling in the same layer */
461 struct ice_sched_node **children;
462 struct ice_aqc_txsched_elem_data info;
463 u32 agg_id; /* aggregator group ID */
465 u8 in_use; /* suspended or in use */
466 u8 tx_sched_layer; /* Logical Layer (1-9) */
470 #define ICE_SCHED_NODE_OWNER_LAN 0
471 #define ICE_SCHED_NODE_OWNER_AE 1
472 #define ICE_SCHED_NODE_OWNER_RDMA 2
475 /* Access Macros for Tx Sched Elements data */
476 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
477 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
478 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
479 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
480 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
481 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
482 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
483 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
484 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
485 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
486 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
488 struct ice_sched_rl_profle {
489 u32 rate; /* In Kbps */
490 struct ice_aqc_rl_profile_elem info;
493 /* The aggregator type determines if identifier is for a VSI group,
494 * aggregator group, aggregator of queues, or queue group.
497 ICE_AGG_TYPE_UNKNOWN = 0,
499 ICE_AGG_TYPE_AGG, /* aggregator */
505 /* Rate limit types */
508 ICE_MIN_BW, /* for CIR profile */
509 ICE_MAX_BW, /* for EIR profile */
510 ICE_SHARED_BW /* for shared profile */
513 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
514 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
515 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
516 #define ICE_SCHED_NO_PRIORITY 0
517 #define ICE_SCHED_NO_BW_WT 0
518 #define ICE_SCHED_DFLT_RL_PROF_ID 0
519 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
520 #define ICE_SCHED_DFLT_BW_WT 1
521 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
522 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
524 /* Access Macros for Tx Sched RL Profile data */
525 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
526 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
527 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
528 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
529 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
532 /* The following tree example shows the naming conventions followed under
533 * ice_port_info struct for default scheduler tree topology.
537 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
541 * / |-> num_elements (range:1 - 9)
542 * * | implies num_of_layers
546 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
547 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
548 * need TEID of (a) to add queues.
551 * -> has 8 branches (one for each TC)
552 * -> First branch (TC0) has 4 elements
554 * -> (a) is the topmost layer node created by firmware on branch 0
556 * Note: Above asterisk tree covers only basic terminology and scenario.
557 * Refer to the documentation for more info.
560 /* Data structure for saving BW information */
568 ICE_BW_TYPE_CNT /* This must be last */
576 struct ice_bw_type_info {
577 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
579 struct ice_bw cir_bw;
580 struct ice_bw eir_bw;
584 /* VSI queue context structure for given TC */
588 /* bw_t_info saves queue BW information */
589 struct ice_bw_type_info bw_t_info;
592 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
593 struct ice_sched_vsi_info {
594 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
595 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
596 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
597 /* bw_t_info saves VSI BW information */
598 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
601 /* CEE or IEEE 802.1Qaz ETS Configuration data */
602 struct ice_dcb_ets_cfg {
606 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
607 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
608 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
611 /* CEE or IEEE 802.1Qaz PFC Configuration data */
612 struct ice_dcb_pfc_cfg {
619 /* CEE or IEEE 802.1Qaz Application Priority data */
620 struct ice_dcb_app_priority_table {
626 #define ICE_MAX_USER_PRIORITY 8
627 #define ICE_DCBX_MAX_APPS 32
628 #define ICE_LLDPDU_SIZE 1500
629 #define ICE_TLV_STATUS_OPER 0x1
630 #define ICE_TLV_STATUS_SYNC 0x2
631 #define ICE_TLV_STATUS_ERR 0x4
632 #define ICE_APP_PROT_ID_FCOE 0x8906
633 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
634 #define ICE_APP_PROT_ID_FIP 0x8914
635 #define ICE_APP_SEL_ETHTYPE 0x1
636 #define ICE_APP_SEL_TCPIP 0x2
637 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
638 #define ICE_CEE_APP_SEL_TCPIP 0x1
640 struct ice_dcbx_cfg {
642 u32 tlv_status; /* CEE mode TLV status */
643 struct ice_dcb_ets_cfg etscfg;
644 struct ice_dcb_ets_cfg etsrec;
645 struct ice_dcb_pfc_cfg pfc;
646 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
648 #define ICE_DCBX_MODE_CEE 0x1
649 #define ICE_DCBX_MODE_IEEE 0x2
651 #define ICE_DCBX_APPS_NON_WILLING 0x1
654 struct ice_port_info {
655 struct ice_sched_node *root; /* Root Node per Port */
656 struct ice_hw *hw; /* back pointer to HW instance */
657 u32 last_node_teid; /* scheduler last node info */
658 u16 sw_id; /* Initial switch ID belongs to port */
661 #define ICE_SCHED_PORT_STATE_INIT 0x0
662 #define ICE_SCHED_PORT_STATE_READY 0x1
664 #define ICE_LPORT_MASK 0xff
665 u16 dflt_tx_vsi_rule_id;
667 u16 dflt_rx_vsi_rule_id;
669 struct ice_fc_info fc;
670 struct ice_mac_info mac;
671 struct ice_phy_info phy;
672 struct ice_lock sched_lock; /* protect access to TXSched tree */
673 struct ice_sched_node *
674 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
675 /* List contain profile ID(s) and other params per layer */
676 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
677 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
678 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
680 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
681 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
682 /* LLDP/DCBX Status */
683 u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */
688 struct ice_switch_info {
689 struct LIST_HEAD_TYPE vsi_list_map_head;
690 struct ice_sw_recipe *recp_list;
694 /* Port hardware description */
698 struct ice_aqc_layer_props *layer_info;
699 struct ice_port_info *port_info;
700 /* 2D Array for each Tx Sched RL Profile type */
701 struct ice_sched_rl_profile **cir_profiles;
702 struct ice_sched_rl_profile **eir_profiles;
703 struct ice_sched_rl_profile **srl_profiles;
704 u64 debug_mask; /* BITMAP for debug mask */
705 enum ice_mac_type mac_type;
707 u16 fd_ctr_base; /* FD counter base index */
711 u16 subsystem_device_id;
712 u16 subsystem_vendor_id;
715 u8 pf_id; /* device profile info */
717 u16 max_burst_size; /* driver sets this value */
719 /* Tx Scheduler values */
720 u16 num_tx_sched_layers;
721 u16 num_tx_sched_phys_layers;
724 u8 sw_entry_point_layer;
725 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
726 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
727 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
728 u8 evb_veb; /* true for VEB, false for VEPA */
729 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
730 struct ice_bus_info bus;
731 struct ice_nvm_info nvm;
732 struct ice_hw_dev_caps dev_caps; /* device capabilities */
733 struct ice_hw_func_caps func_caps; /* function capabilities */
735 struct ice_switch_info *switch_info; /* switch filter lists */
737 /* Control Queue info */
738 struct ice_ctl_q_info adminq;
739 struct ice_ctl_q_info mailboxq;
741 u8 api_branch; /* API branch version */
742 u8 api_maj_ver; /* API major version */
743 u8 api_min_ver; /* API minor version */
744 u8 api_patch; /* API patch version */
745 u8 fw_branch; /* firmware branch version */
746 u8 fw_maj_ver; /* firmware major version */
747 u8 fw_min_ver; /* firmware minor version */
748 u8 fw_patch; /* firmware patch version */
749 u32 fw_build; /* firmware build number */
752 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
753 * register. Used for determining the itr/intrl granularity during
756 #define ICE_MAX_AGG_BW_200G 0x0
757 #define ICE_MAX_AGG_BW_100G 0X1
758 #define ICE_MAX_AGG_BW_50G 0x2
759 #define ICE_MAX_AGG_BW_25G 0x3
760 /* ITR granularity for different speeds */
761 #define ICE_ITR_GRAN_ABOVE_25 2
762 #define ICE_ITR_GRAN_MAX_25 4
763 /* ITR granularity in 1 us */
765 /* INTRL granularity for different speeds */
766 #define ICE_INTRL_GRAN_ABOVE_25 4
767 #define ICE_INTRL_GRAN_MAX_25 8
768 /* INTRL granularity in 1 us */
771 u8 ucast_shared; /* true if VSIs can share unicast addr */
773 /* Active package version (currently active) */
774 struct ice_pkg_ver active_pkg_ver;
775 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
776 u8 active_pkg_in_nvm;
778 /* Driver's package ver - (from the Metadata seg) */
779 struct ice_pkg_ver pkg_ver;
780 u8 pkg_name[ICE_PKG_NAME_SIZE];
782 /* Driver's Ice package version (from the Ice seg) */
783 struct ice_pkg_ver ice_pkg_ver;
784 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
786 /* Pointer to the ice segment */
789 /* Pointer to allocated copy of pkg memory */
794 struct ice_tunnel_table tnl;
796 #define ICE_PKG_FILENAME "package_file"
797 #define ICE_PKG_FILENAME_EXT "pkg"
798 #define ICE_PKG_FILE_MAJ_VER 1
799 #define ICE_PKG_FILE_MIN_VER 0
801 /* HW block tables */
802 struct ice_blk_info blk[ICE_BLK_COUNT];
803 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
804 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
805 /* Flow Director filter info */
806 int fdir_active_fltr;
808 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
809 struct LIST_HEAD_TYPE fdir_list_head;
811 /* Book-keeping of side-band filter count per flow-type.
812 * This is used to detect and handle input set changes for
813 * respective flow-type.
815 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
817 struct ice_fd_hw_prof **fdir_prof;
818 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
819 struct ice_lock rss_locks; /* protect RSS configuration */
820 struct LIST_HEAD_TYPE rss_list_head;
823 /* Statistics collected by each port, VSI, VEB, and S-channel */
824 struct ice_eth_stats {
825 u64 rx_bytes; /* gorc */
826 u64 rx_unicast; /* uprc */
827 u64 rx_multicast; /* mprc */
828 u64 rx_broadcast; /* bprc */
829 u64 rx_discards; /* rdpc */
830 u64 rx_unknown_protocol; /* rupp */
831 u64 tx_bytes; /* gotc */
832 u64 tx_unicast; /* uptc */
833 u64 tx_multicast; /* mptc */
834 u64 tx_broadcast; /* bptc */
835 u64 tx_discards; /* tdpc */
836 u64 tx_errors; /* tepc */
837 u64 rx_no_desc; /* repc */
838 u64 rx_errors; /* repc */
843 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
844 struct ice_veb_up_stats {
845 u64 up_rx_pkts[ICE_MAX_UP];
846 u64 up_rx_bytes[ICE_MAX_UP];
847 u64 up_tx_pkts[ICE_MAX_UP];
848 u64 up_tx_bytes[ICE_MAX_UP];
851 /* Statistics collected by the MAC */
852 struct ice_hw_port_stats {
853 /* eth stats collected by the port */
854 struct ice_eth_stats eth;
855 /* additional port specific stats */
856 u64 tx_dropped_link_down; /* tdold */
857 u64 crc_errors; /* crcerrs */
858 u64 illegal_bytes; /* illerrc */
859 u64 error_bytes; /* errbc */
860 u64 mac_local_faults; /* mlfc */
861 u64 mac_remote_faults; /* mrfc */
862 u64 rx_len_errors; /* rlec */
863 u64 link_xon_rx; /* lxonrxc */
864 u64 link_xoff_rx; /* lxoffrxc */
865 u64 link_xon_tx; /* lxontxc */
866 u64 link_xoff_tx; /* lxofftxc */
867 u64 priority_xon_rx[8]; /* pxonrxc[8] */
868 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
869 u64 priority_xon_tx[8]; /* pxontxc[8] */
870 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
871 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
872 u64 rx_size_64; /* prc64 */
873 u64 rx_size_127; /* prc127 */
874 u64 rx_size_255; /* prc255 */
875 u64 rx_size_511; /* prc511 */
876 u64 rx_size_1023; /* prc1023 */
877 u64 rx_size_1522; /* prc1522 */
878 u64 rx_size_big; /* prc9522 */
879 u64 rx_undersize; /* ruc */
880 u64 rx_fragments; /* rfc */
881 u64 rx_oversize; /* roc */
882 u64 rx_jabber; /* rjc */
883 u64 tx_size_64; /* ptc64 */
884 u64 tx_size_127; /* ptc127 */
885 u64 tx_size_255; /* ptc255 */
886 u64 tx_size_511; /* ptc511 */
887 u64 tx_size_1023; /* ptc1023 */
888 u64 tx_size_1522; /* ptc1522 */
889 u64 tx_size_big; /* ptc9522 */
890 u64 mac_short_pkt_dropped; /* mspdc */
891 /* flow director stats */
896 enum ice_sw_fwd_act_type {
898 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
905 /* Checksum and Shadow RAM pointers */
906 #define ICE_SR_NVM_CTRL_WORD 0x00
907 #define ICE_SR_PHY_ANALOG_PTR 0x04
908 #define ICE_SR_OPTION_ROM_PTR 0x05
909 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
910 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
911 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
912 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
913 #define ICE_SR_EMP_IMAGE_PTR 0x0B
914 #define ICE_SR_PE_IMAGE_PTR 0x0C
915 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
916 #define ICE_SR_MNG_CFG_PTR 0x0E
917 #define ICE_SR_EMP_MODULE_PTR 0x0F
918 #define ICE_SR_PBA_BLOCK_PTR 0x16
919 #define ICE_SR_BOOT_CFG_PTR 0x132
920 #define ICE_SR_NVM_WOL_CFG 0x19
921 #define ICE_NVM_OEM_VER_OFF 0x02
922 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
923 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
924 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
925 #define ICE_SR_NVM_MAP_VER 0x29
926 #define ICE_SR_NVM_IMAGE_VER 0x2A
927 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
928 #define ICE_SR_NVM_EETRACK_LO 0x2D
929 #define ICE_SR_NVM_EETRACK_HI 0x2E
930 #define ICE_NVM_VER_LO_SHIFT 0
931 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
932 #define ICE_NVM_VER_HI_SHIFT 12
933 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
934 #define ICE_OEM_EETRACK_ID 0xffffffff
935 #define ICE_OEM_VER_PATCH_SHIFT 0
936 #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT)
937 #define ICE_OEM_VER_BUILD_SHIFT 8
938 #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT)
939 #define ICE_OEM_VER_SHIFT 24
940 #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT)
941 #define ICE_SR_VPD_PTR 0x2F
942 #define ICE_SR_PXE_SETUP_PTR 0x30
943 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
944 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
945 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
946 #define ICE_SR_VLAN_CFG_PTR 0x37
947 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
948 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
949 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
950 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
951 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
952 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
953 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
954 #define ICE_SR_PFA_PTR 0x40
955 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
956 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
957 #define ICE_SR_NVM_BANK_SIZE 0x43
958 #define ICE_SR_1ND_OROM_BANK_PTR 0x44
959 #define ICE_SR_OROM_BANK_SIZE 0x45
960 #define ICE_SR_NETLIST_BANK_PTR 0x46
961 #define ICE_SR_NETLIST_BANK_SIZE 0x47
962 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
963 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
964 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
965 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
967 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
968 #define ICE_SR_VPD_SIZE_WORDS 512
969 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
970 #define ICE_SR_CTRL_WORD_1_S 0x06
971 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
973 /* Shadow RAM related */
974 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
975 #define ICE_SR_BUF_ALIGNMENT 4096
976 #define ICE_SR_WORDS_IN_1KB 512
977 /* Checksum should be calculated such that after adding all the words,
978 * including the checksum word itself, the sum should be 0xBABA.
980 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
982 #define ICE_PBA_FLAG_DFLT 0xFAFA
983 /* Hash redirection LUT for VSI - maximum array size */
984 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
987 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
988 * This is needed to determine the BAR0 space for the VFs
990 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
991 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
992 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
994 #endif /* _ICE_TYPE_H_ */