1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
19 #define ICE_BYTES_PER_WORD 2
20 #define ICE_BYTES_PER_DWORD 4
21 #define ICE_MAX_TRAFFIC_CLASS 8
24 * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
25 * @a: value to round up
26 * @b: arbitrary multiple
28 * Round up to the next multiple of the arbitrary b.
29 * Note, when b is a power of 2 use ICE_ALIGN() instead.
31 #define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
33 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
35 #define IS_ASCII(_ch) ((_ch) < 0x80)
37 #define STRUCT_HACK_VAR_LEN
39 * ice_struct_size - size of struct with C99 flexible array member
40 * @ptr: pointer to structure
41 * @field: flexible array member (last member of the structure)
42 * @num: number of elements of that flexible array member
44 #define ice_struct_size(ptr, field, num) \
45 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
47 #define FLEX_ARRAY_SIZE(_ptr, _mem, cnt) ((cnt) * sizeof(_ptr->_mem[0]))
49 #include "ice_status.h"
50 #include "ice_hw_autogen.h"
51 #include "ice_devids.h"
52 #include "ice_osdep.h"
53 #include "ice_bitops.h" /* Must come before ice_controlq.h */
54 #include "ice_controlq.h"
55 #include "ice_lan_tx_rx.h"
56 #include "ice_flex_type.h"
57 #include "ice_protocol_type.h"
58 #include "ice_vlan_mode.h"
61 * ice_is_pow2 - check if integer value is a power of 2
62 * @val: unsigned integer to be validated
64 static inline bool ice_is_pow2(u64 val)
66 return (val && !(val & (val - 1)));
70 * ice_ilog2 - Calculates integer log base 2 of a number
71 * @n: number on which to perform operation
73 static inline int ice_ilog2(u64 n)
77 for (i = 63; i >= 0; i--)
78 if (((u64)1 << i) & n)
84 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
86 return ice_is_bit_set(&bitmap, tc);
89 #define DIV_64BIT(n, d) ((n) / (d))
91 static inline u64 round_up_64bit(u64 a, u32 b)
93 return DIV_64BIT(((a) + (b) / 2), (b));
96 static inline u32 ice_round_to_num(u32 N, u32 R)
98 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
99 ((((N) + (R) - 1) / (R)) * (R)));
102 /* Driver always calls main vsi_handle first */
103 #define ICE_MAIN_VSI_HANDLE 0
105 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
106 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
108 /* Data type manipulation macros. */
109 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
110 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
111 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
112 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF))
114 /* debug masks - set these bits in hw->debug_mask to control output */
115 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
116 #define ICE_DBG_INIT BIT_ULL(1)
117 #define ICE_DBG_RELEASE BIT_ULL(2)
118 #define ICE_DBG_FW_LOG BIT_ULL(3)
119 #define ICE_DBG_LINK BIT_ULL(4)
120 #define ICE_DBG_PHY BIT_ULL(5)
121 #define ICE_DBG_QCTX BIT_ULL(6)
122 #define ICE_DBG_NVM BIT_ULL(7)
123 #define ICE_DBG_LAN BIT_ULL(8)
124 #define ICE_DBG_FLOW BIT_ULL(9)
125 #define ICE_DBG_DCB BIT_ULL(10)
126 #define ICE_DBG_DIAG BIT_ULL(11)
127 #define ICE_DBG_FD BIT_ULL(12)
128 #define ICE_DBG_SW BIT_ULL(13)
129 #define ICE_DBG_SCHED BIT_ULL(14)
131 #define ICE_DBG_PKG BIT_ULL(16)
132 #define ICE_DBG_RES BIT_ULL(17)
133 #define ICE_DBG_ACL BIT_ULL(18)
134 #define ICE_DBG_AQ_MSG BIT_ULL(24)
135 #define ICE_DBG_AQ_DESC BIT_ULL(25)
136 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
137 #define ICE_DBG_AQ_CMD BIT_ULL(27)
138 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
140 ICE_DBG_AQ_DESC_BUF | \
143 #define ICE_DBG_USER BIT_ULL(31)
144 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
146 #define __ALWAYS_UNUSED
148 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
149 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
150 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
151 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
153 enum ice_aq_res_ids {
156 ICE_CHANGE_LOCK_RES_ID,
157 ICE_GLOBAL_CFG_LOCK_RES_ID
160 /* FW update timeout definitions are in milliseconds */
161 #define ICE_NVM_TIMEOUT 180000
162 #define ICE_CHANGE_LOCK_TIMEOUT 1000
163 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
165 enum ice_aq_res_access_type {
170 struct ice_driver_ver {
175 u8 driver_string[32];
188 enum ice_phy_cache_mode {
201 struct ice_phy_cache_mode_data {
203 enum ice_fec_mode curr_user_fec_req;
204 enum ice_fc_mode curr_user_fc_req;
205 u16 curr_user_speed_req;
209 enum ice_set_fc_aq_failures {
210 ICE_SET_FC_AQ_FAIL_NONE = 0,
211 ICE_SET_FC_AQ_FAIL_GET,
212 ICE_SET_FC_AQ_FAIL_SET,
213 ICE_SET_FC_AQ_FAIL_UPDATE
216 /* These are structs for managing the hardware information and the operations */
225 enum ice_media_type {
226 ICE_MEDIA_UNKNOWN = 0,
234 /* Software VSI types. */
237 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
241 struct ice_link_status {
242 /* Refer to ice_aq_phy_type for bits definition */
245 u8 topo_media_conflict;
250 u8 lse_ena; /* Link Status Event notification */
256 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
257 * ice_aqc_get_phy_caps structure
259 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
262 /* Different data queue types: These are mainly for SW consumption. */
271 /* Different reset sources for which a disable queue AQ call has to be made in
272 * order to clean the Tx scheduler as a part of the reset
274 enum ice_disq_rst_src {
279 /* PHY info such as phy_type, etc... */
280 struct ice_phy_info {
281 struct ice_link_status link_info;
282 struct ice_link_status link_info_old;
285 enum ice_media_type media_type;
287 /* Please refer to struct ice_aqc_get_link_status_data to get
288 * detail of enable bit in curr_user_speed_req
290 u16 curr_user_speed_req;
291 enum ice_fec_mode curr_user_fec_req;
292 enum ice_fc_mode curr_user_fc_req;
293 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
296 #define ICE_MAX_NUM_MIRROR_RULES 64
298 /* protocol enumeration for filters */
299 enum ice_fltr_ptype {
300 /* NONE - used for undef/error */
301 ICE_FLTR_PTYPE_NONF_NONE = 0,
302 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
303 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
304 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
305 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
306 ICE_FLTR_PTYPE_NONF_IPV4_GTPU,
307 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH,
308 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW,
309 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP,
310 ICE_FLTR_PTYPE_NONF_IPV6_GTPU,
311 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH,
312 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_DW,
313 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_UP,
314 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4,
315 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
316 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
317 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,
318 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,
319 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,
320 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4,
321 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP,
322 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP,
323 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4,
324 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_UDP,
325 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_TCP,
326 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4,
327 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_UDP,
328 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_TCP,
329 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
330 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
331 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
332 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_OTHER,
333 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_IPV6_OTHER,
334 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
335 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
336 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
337 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
338 ICE_FLTR_PTYPE_NONF_IPV4_AH,
339 ICE_FLTR_PTYPE_NONF_IPV6_AH,
340 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
341 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
342 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
343 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
344 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
345 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
346 ICE_FLTR_PTYPE_NON_IP_L2,
347 ICE_FLTR_PTYPE_NONF_ECPRI_TP0,
348 ICE_FLTR_PTYPE_NONF_IPV4_UDP_ECPRI_TP0,
349 ICE_FLTR_PTYPE_FRAG_IPV4,
350 ICE_FLTR_PTYPE_FRAG_IPV6,
351 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
352 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
353 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
354 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
355 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN,
356 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_UDP,
357 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_TCP,
358 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_SCTP,
359 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_OTHER,
364 ICE_FD_HW_SEG_NON_TUN = 0,
369 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
370 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
372 struct ice_fd_hw_prof {
373 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
375 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
376 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
379 /* Common HW capabilities for SW use */
380 struct ice_hw_common_caps {
381 /* Write CSR protection */
384 /* switching mode supported - EVB switching (including cloud) */
385 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
387 /* Manageablity mode & supported protocols over MCTP */
389 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
390 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
391 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
393 u32 mgmt_protocols_mctp;
394 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
395 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
396 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
397 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
401 /* DCB capabilities */
402 u32 active_tc_bitmap;
405 /* RSS related capabilities */
406 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
407 u32 rss_table_entry_width; /* RSS Entry width in bits */
410 u32 num_rxq; /* Number/Total Rx queues */
411 u32 rxq_first_id; /* First queue ID for Rx queues */
412 u32 num_txq; /* Number/Total Tx queues */
413 u32 txq_first_id; /* First queue ID for Tx queues */
416 u32 num_msix_vectors;
417 u32 msix_vector_first_id;
419 /* Max MTU for function or device */
423 u32 num_wol_proxy_fltr;
424 u32 wol_proxy_vsi_seid;
426 /* LED/SDP pin count */
430 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
431 #define ICE_MAX_SUPPORTED_GPIO_LED 12
432 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
433 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
434 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
436 /* EVB capabilities */
437 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
438 u8 evb_802_1_qbh; /* Bridge Port Extension */
444 /* WoL and APM support */
445 #define ICE_WOL_SUPPORT_M BIT(0)
446 #define ICE_ACPI_PROG_MTHD_M BIT(1)
447 #define ICE_PROXY_SUPPORT_M BIT(2)
451 bool sec_rev_disabled;
452 bool update_disabled;
453 bool nvm_unified_update;
454 #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0)
455 #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1)
456 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
458 /* External topology device images within the NVM */
459 #define ICE_EXT_TOPO_DEV_IMG_COUNT 4
460 u32 ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT];
461 u32 ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT];
462 u8 ext_topo_dev_img_part_num[ICE_EXT_TOPO_DEV_IMG_COUNT];
463 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_S 8
464 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_M \
465 MAKEMASK(0xFF, ICE_EXT_TOPO_DEV_IMG_PART_NUM_S)
466 bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
467 #define ICE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0)
468 bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
469 #define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1)
472 /* Function specific capabilities */
473 struct ice_hw_func_caps {
474 struct ice_hw_common_caps common_cap;
476 u32 fd_fltr_guar; /* Number of filters guaranteed */
477 u32 fd_fltr_best_effort; /* Number of best effort filters */
480 /* Device wide capabilities */
481 struct ice_hw_dev_caps {
482 struct ice_hw_common_caps common_cap;
483 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
484 u32 num_flow_director_fltr; /* Number of FD filters available */
488 /* Information about MAC such as address, etc... */
489 struct ice_mac_info {
490 u8 lan_addr[ETH_ALEN];
491 u8 perm_addr[ETH_ALEN];
492 u8 port_addr[ETH_ALEN];
493 u8 wol_addr[ETH_ALEN];
500 ice_bus_embedded, /* Is device Embedded versus card */
505 enum ice_pcie_bus_speed {
506 ice_pcie_speed_unknown = 0xff,
507 ice_pcie_speed_2_5GT = 0x14,
508 ice_pcie_speed_5_0GT = 0x15,
509 ice_pcie_speed_8_0GT = 0x16,
510 ice_pcie_speed_16_0GT = 0x17
514 enum ice_pcie_link_width {
515 ice_pcie_lnk_width_resrv = 0x00,
516 ice_pcie_lnk_x1 = 0x01,
517 ice_pcie_lnk_x2 = 0x02,
518 ice_pcie_lnk_x4 = 0x04,
519 ice_pcie_lnk_x8 = 0x08,
520 ice_pcie_lnk_x12 = 0x0C,
521 ice_pcie_lnk_x16 = 0x10,
522 ice_pcie_lnk_x32 = 0x20,
523 ice_pcie_lnk_width_unknown = 0xff,
526 /* Reset types used to determine which kind of reset was requested. These
527 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
528 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
529 * because its reset source is different than the other types listed.
541 struct ice_bus_info {
542 enum ice_pcie_bus_speed speed;
543 enum ice_pcie_link_width width;
544 enum ice_bus_type type;
551 /* Flow control (FC) parameters */
553 enum ice_fc_mode current_mode; /* FC mode in effect */
554 enum ice_fc_mode req_mode; /* FC mode requested by caller */
557 /* Option ROM version information */
558 struct ice_orom_info {
559 u8 major; /* Major version of OROM */
560 u8 patch; /* Patch version of OROM */
561 u16 build; /* Build version of OROM */
562 u32 srev; /* Security revision */
565 /* NVM version information */
566 struct ice_nvm_info {
573 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
574 * of the flash image.
576 enum ice_flash_bank {
577 ICE_INVALID_FLASH_BANK,
582 /* Enumeration of which flash bank is desired to read from, either the active
583 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
584 * code which just wants to read the active or inactive flash bank.
586 enum ice_bank_select {
587 ICE_ACTIVE_FLASH_BANK,
588 ICE_INACTIVE_FLASH_BANK,
591 /* information for accessing NVM, OROM, and Netlist flash banks */
592 struct ice_bank_info {
593 u32 nvm_ptr; /* Pointer to 1st NVM bank */
594 u32 nvm_size; /* Size of NVM bank */
595 u32 orom_ptr; /* Pointer to 1st OROM bank */
596 u32 orom_size; /* Size of OROM bank */
597 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
598 u32 netlist_size; /* Size of Netlist bank */
599 enum ice_flash_bank nvm_bank; /* Active NVM bank */
600 enum ice_flash_bank orom_bank; /* Active OROM bank */
601 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
604 /* Flash Chip Information */
605 struct ice_flash_info {
606 struct ice_orom_info orom; /* Option ROM version info */
607 struct ice_nvm_info nvm; /* NVM version information */
608 struct ice_bank_info banks; /* Flash Bank information */
609 u16 sr_words; /* Shadow RAM size in words */
610 u32 flash_size; /* Size of available flash in bytes */
611 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
614 struct ice_link_default_override_tlv {
616 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
617 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
618 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
619 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
620 #define ICE_LINK_OVERRIDE_EN BIT(3)
621 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
622 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
624 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
625 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
626 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
627 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
628 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
630 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
636 #define ICE_NVM_VER_LEN 32
638 /* Max number of port to queue branches w.r.t topology */
639 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
641 #define ice_for_each_traffic_class(_i) \
642 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
644 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
645 * to driver defined policy for default aggregator
647 #define ICE_INVAL_TEID 0xFFFFFFFF
648 #define ICE_DFLT_AGG_ID 0
650 struct ice_sched_node {
651 struct ice_sched_node *parent;
652 struct ice_sched_node *sibling; /* next sibling in the same layer */
653 struct ice_sched_node **children;
654 struct ice_aqc_txsched_elem_data info;
655 u32 agg_id; /* aggregator group ID */
657 u8 in_use; /* suspended or in use */
658 u8 tx_sched_layer; /* Logical Layer (1-9) */
662 #define ICE_SCHED_NODE_OWNER_LAN 0
663 #define ICE_SCHED_NODE_OWNER_AE 1
664 #define ICE_SCHED_NODE_OWNER_RDMA 2
667 /* Access Macros for Tx Sched Elements data */
668 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
669 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
670 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
671 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
672 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
673 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
674 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
675 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
676 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
677 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
678 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
680 struct ice_sched_rl_profile {
681 u32 rate; /* In Kbps */
682 struct ice_aqc_rl_profile_elem info;
685 /* The aggregator type determines if identifier is for a VSI group,
686 * aggregator group, aggregator of queues, or queue group.
689 ICE_AGG_TYPE_UNKNOWN = 0,
691 ICE_AGG_TYPE_AGG, /* aggregator */
697 /* Rate limit types */
700 ICE_MIN_BW, /* for CIR profile */
701 ICE_MAX_BW, /* for EIR profile */
702 ICE_SHARED_BW /* for shared profile */
705 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
706 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
707 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
708 #define ICE_SCHED_NO_PRIORITY 0
709 #define ICE_SCHED_NO_BW_WT 0
710 #define ICE_SCHED_DFLT_RL_PROF_ID 0
711 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
712 #define ICE_SCHED_DFLT_BW_WT 4
713 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
714 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
716 /* Access Macros for Tx Sched RL Profile data */
717 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
718 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
719 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
720 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
721 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
723 /* The following tree example shows the naming conventions followed under
724 * ice_port_info struct for default scheduler tree topology.
728 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
732 * / |-> num_elements (range:1 - 9)
733 * * | implies num_of_layers
737 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
738 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
739 * need TEID of (a) to add queues.
742 * -> has 8 branches (one for each TC)
743 * -> First branch (TC0) has 4 elements
745 * -> (a) is the topmost layer node created by firmware on branch 0
747 * Note: Above asterisk tree covers only basic terminology and scenario.
748 * Refer to the documentation for more info.
751 /* Data structure for saving BW information */
759 ICE_BW_TYPE_CNT /* This must be last */
767 struct ice_bw_type_info {
768 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
770 struct ice_bw cir_bw;
771 struct ice_bw eir_bw;
775 /* VSI queue context structure for given TC */
779 /* bw_t_info saves queue BW information */
780 struct ice_bw_type_info bw_t_info;
783 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
784 struct ice_sched_vsi_info {
785 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
786 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
787 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
788 /* bw_t_info saves VSI BW information */
789 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
792 /* CEE or IEEE 802.1Qaz ETS Configuration data */
793 struct ice_dcb_ets_cfg {
797 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
798 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
799 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
802 /* CEE or IEEE 802.1Qaz PFC Configuration data */
803 struct ice_dcb_pfc_cfg {
810 /* CEE or IEEE 802.1Qaz Application Priority data */
811 struct ice_dcb_app_priority_table {
817 #define ICE_MAX_USER_PRIORITY 8
818 #define ICE_DCBX_MAX_APPS 64
819 #define ICE_DSCP_NUM_VAL 64
820 #define ICE_LLDPDU_SIZE 1500
821 #define ICE_TLV_STATUS_OPER 0x1
822 #define ICE_TLV_STATUS_SYNC 0x2
823 #define ICE_TLV_STATUS_ERR 0x4
824 #define ICE_APP_PROT_ID_FCOE 0x8906
825 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
826 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
827 #define ICE_APP_PROT_ID_FIP 0x8914
828 #define ICE_APP_SEL_ETHTYPE 0x1
829 #define ICE_APP_SEL_TCPIP 0x2
830 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
831 #define ICE_CEE_APP_SEL_TCPIP 0x1
833 struct ice_dcbx_cfg {
835 u32 tlv_status; /* CEE mode TLV status */
836 struct ice_dcb_ets_cfg etscfg;
837 struct ice_dcb_ets_cfg etsrec;
838 struct ice_dcb_pfc_cfg pfc;
839 #define ICE_QOS_MODE_VLAN 0x0
840 #define ICE_QOS_MODE_DSCP 0x1
842 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
843 /* when DSCP mapping defined by user set its bit to 1 */
844 ice_declare_bitmap(dscp_mapped, ICE_DSCP_NUM_VAL);
845 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
846 u8 dscp_map[ICE_DSCP_NUM_VAL];
848 #define ICE_DCBX_MODE_CEE 0x1
849 #define ICE_DCBX_MODE_IEEE 0x2
851 #define ICE_DCBX_APPS_NON_WILLING 0x1
855 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
856 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
857 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
858 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
862 struct ice_port_info {
863 struct ice_sched_node *root; /* Root Node per Port */
864 struct ice_hw *hw; /* back pointer to HW instance */
865 u32 last_node_teid; /* scheduler last node info */
866 u16 sw_id; /* Initial switch ID belongs to port */
869 #define ICE_SCHED_PORT_STATE_INIT 0x0
870 #define ICE_SCHED_PORT_STATE_READY 0x1
872 #define ICE_LPORT_MASK 0xff
873 u16 dflt_tx_vsi_rule_id;
875 u16 dflt_rx_vsi_rule_id;
877 struct ice_fc_info fc;
878 struct ice_mac_info mac;
879 struct ice_phy_info phy;
880 struct ice_lock sched_lock; /* protect access to TXSched tree */
881 struct ice_sched_node *
882 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
883 struct ice_bw_type_info root_node_bw_t_info;
884 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
885 struct ice_qos_cfg qos_cfg;
889 struct ice_switch_info {
890 struct LIST_HEAD_TYPE vsi_list_map_head;
891 struct ice_sw_recipe *recp_list;
892 u16 prof_res_bm_init;
893 u16 max_used_prof_index;
895 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
898 /* Port hardware description */
902 struct ice_aqc_layer_props *layer_info;
903 struct ice_port_info *port_info;
904 /* 2D Array for each Tx Sched RL Profile type */
905 struct ice_sched_rl_profile **cir_profiles;
906 struct ice_sched_rl_profile **eir_profiles;
907 struct ice_sched_rl_profile **srl_profiles;
908 /* PSM clock frequency for calculating RL profile params */
910 u64 debug_mask; /* BITMAP for debug mask */
911 enum ice_mac_type mac_type;
913 u16 fd_ctr_base; /* FD counter base index */
917 u16 subsystem_device_id;
918 u16 subsystem_vendor_id;
921 u8 pf_id; /* device profile info */
923 u16 max_burst_size; /* driver sets this value */
925 /* Tx Scheduler values */
926 u8 num_tx_sched_layers;
927 u8 num_tx_sched_phys_layers;
930 u8 sw_entry_point_layer;
931 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
932 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
933 /* List contain profile ID(s) and other params per layer */
934 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
935 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
936 u8 evb_veb; /* true for VEB, false for VEPA */
937 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
938 struct ice_bus_info bus;
939 struct ice_flash_info flash;
940 struct ice_hw_dev_caps dev_caps; /* device capabilities */
941 struct ice_hw_func_caps func_caps; /* function capabilities */
943 struct ice_switch_info *switch_info; /* switch filter lists */
945 /* Control Queue info */
946 struct ice_ctl_q_info adminq;
947 struct ice_ctl_q_info mailboxq;
948 /* Additional function to send AdminQ command */
949 int (*aq_send_cmd_fn)(void *param, struct ice_aq_desc *desc,
950 void *buf, u16 buf_size);
951 void *aq_send_cmd_param;
952 u8 dcf_enabled; /* Device Config Function */
954 u8 api_branch; /* API branch version */
955 u8 api_maj_ver; /* API major version */
956 u8 api_min_ver; /* API minor version */
957 u8 api_patch; /* API patch version */
958 u8 fw_branch; /* firmware branch version */
959 u8 fw_maj_ver; /* firmware major version */
960 u8 fw_min_ver; /* firmware minor version */
961 u8 fw_patch; /* firmware patch version */
962 u32 fw_build; /* firmware build number */
964 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
965 * register. Used for determining the ITR/INTRL granularity during
968 #define ICE_MAX_AGG_BW_200G 0x0
969 #define ICE_MAX_AGG_BW_100G 0X1
970 #define ICE_MAX_AGG_BW_50G 0x2
971 #define ICE_MAX_AGG_BW_25G 0x3
972 /* ITR granularity for different speeds */
973 #define ICE_ITR_GRAN_ABOVE_25 2
974 #define ICE_ITR_GRAN_MAX_25 4
975 /* ITR granularity in 1 us */
977 /* INTRL granularity for different speeds */
978 #define ICE_INTRL_GRAN_ABOVE_25 4
979 #define ICE_INTRL_GRAN_MAX_25 8
980 /* INTRL granularity in 1 us */
983 u8 ucast_shared; /* true if VSIs can share unicast addr */
985 #define ICE_PHY_PER_NAC 1
986 #define ICE_MAX_QUAD 2
987 #define ICE_NUM_QUAD_TYPE 2
988 #define ICE_PORTS_PER_QUAD 4
989 #define ICE_PHY_0_LAST_QUAD 1
990 #define ICE_PORTS_PER_PHY 8
991 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
993 /* Active package version (currently active) */
994 struct ice_pkg_ver active_pkg_ver;
996 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
997 u8 active_pkg_in_nvm;
999 enum ice_aq_err pkg_dwnld_status;
1001 /* Driver's package ver - (from the Ice Metadata section) */
1002 struct ice_pkg_ver pkg_ver;
1003 u8 pkg_name[ICE_PKG_NAME_SIZE];
1005 /* Driver's Ice segment format version and id (from the Ice seg) */
1006 struct ice_pkg_ver ice_seg_fmt_ver;
1007 u8 ice_seg_id[ICE_SEG_ID_SIZE];
1009 /* Pointer to the ice segment */
1010 struct ice_seg *seg;
1012 /* Pointer to allocated copy of pkg memory */
1016 /* tunneling info */
1017 struct ice_lock tnl_lock;
1018 struct ice_tunnel_table tnl;
1019 /* dvm boost update information */
1020 struct ice_dvm_table dvm_upd;
1022 struct ice_acl_tbl *acl_tbl;
1023 struct ice_fd_hw_prof **acl_prof;
1024 u16 acl_fltr_cnt[ICE_FLTR_PTYPE_MAX];
1025 /* HW block tables */
1026 struct ice_blk_info blk[ICE_BLK_COUNT];
1027 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
1028 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
1029 /* Flow Director filter info */
1030 int fdir_active_fltr;
1032 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
1033 struct LIST_HEAD_TYPE fdir_list_head;
1035 /* Book-keeping of side-band filter count per flow-type.
1036 * This is used to detect and handle input set changes for
1037 * respective flow-type.
1039 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
1041 struct ice_fd_hw_prof **fdir_prof;
1042 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
1043 struct ice_lock rss_locks; /* protect RSS configuration */
1044 struct LIST_HEAD_TYPE rss_list_head;
1045 ice_declare_bitmap(hw_ptype, ICE_FLOW_PTYPE_MAX);
1049 /* Statistics collected by each port, VSI, VEB, and S-channel */
1050 struct ice_eth_stats {
1051 u64 rx_bytes; /* gorc */
1052 u64 rx_unicast; /* uprc */
1053 u64 rx_multicast; /* mprc */
1054 u64 rx_broadcast; /* bprc */
1055 u64 rx_discards; /* rdpc */
1056 u64 rx_unknown_protocol; /* rupp */
1057 u64 tx_bytes; /* gotc */
1058 u64 tx_unicast; /* uptc */
1059 u64 tx_multicast; /* mptc */
1060 u64 tx_broadcast; /* bptc */
1061 u64 tx_discards; /* tdpc */
1062 u64 tx_errors; /* tepc */
1063 u64 rx_no_desc; /* repc */
1064 u64 rx_errors; /* repc */
1067 #define ICE_MAX_UP 8
1069 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
1070 struct ice_veb_up_stats {
1071 u64 up_rx_pkts[ICE_MAX_UP];
1072 u64 up_rx_bytes[ICE_MAX_UP];
1073 u64 up_tx_pkts[ICE_MAX_UP];
1074 u64 up_tx_bytes[ICE_MAX_UP];
1077 /* Statistics collected by the MAC */
1078 struct ice_hw_port_stats {
1079 /* eth stats collected by the port */
1080 struct ice_eth_stats eth;
1081 /* additional port specific stats */
1082 u64 tx_dropped_link_down; /* tdold */
1083 u64 crc_errors; /* crcerrs */
1084 u64 illegal_bytes; /* illerrc */
1085 u64 error_bytes; /* errbc */
1086 u64 mac_local_faults; /* mlfc */
1087 u64 mac_remote_faults; /* mrfc */
1088 u64 rx_len_errors; /* rlec */
1089 u64 link_xon_rx; /* lxonrxc */
1090 u64 link_xoff_rx; /* lxoffrxc */
1091 u64 link_xon_tx; /* lxontxc */
1092 u64 link_xoff_tx; /* lxofftxc */
1093 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1094 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1095 u64 priority_xon_tx[8]; /* pxontxc[8] */
1096 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1097 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1098 u64 rx_size_64; /* prc64 */
1099 u64 rx_size_127; /* prc127 */
1100 u64 rx_size_255; /* prc255 */
1101 u64 rx_size_511; /* prc511 */
1102 u64 rx_size_1023; /* prc1023 */
1103 u64 rx_size_1522; /* prc1522 */
1104 u64 rx_size_big; /* prc9522 */
1105 u64 rx_undersize; /* ruc */
1106 u64 rx_fragments; /* rfc */
1107 u64 rx_oversize; /* roc */
1108 u64 rx_jabber; /* rjc */
1109 u64 tx_size_64; /* ptc64 */
1110 u64 tx_size_127; /* ptc127 */
1111 u64 tx_size_255; /* ptc255 */
1112 u64 tx_size_511; /* ptc511 */
1113 u64 tx_size_1023; /* ptc1023 */
1114 u64 tx_size_1522; /* ptc1522 */
1115 u64 tx_size_big; /* ptc9522 */
1116 u64 mac_short_pkt_dropped; /* mspdc */
1117 /* flow director stats */
1122 enum ice_sw_fwd_act_type {
1124 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1131 struct ice_aq_get_set_rss_lut_params {
1132 u16 vsi_handle; /* software VSI handle */
1133 u16 lut_size; /* size of the LUT buffer */
1134 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1135 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1136 u8 global_lut_id; /* only valid when lut_type is global */
1139 /* Checksum and Shadow RAM pointers */
1140 #define ICE_SR_NVM_CTRL_WORD 0x00
1141 #define ICE_SR_PHY_ANALOG_PTR 0x04
1142 #define ICE_SR_OPTION_ROM_PTR 0x05
1143 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1144 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1145 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1146 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
1147 #define ICE_SR_EMP_IMAGE_PTR 0x0B
1148 #define ICE_SR_PE_IMAGE_PTR 0x0C
1149 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
1150 #define ICE_SR_MNG_CFG_PTR 0x0E
1151 #define ICE_SR_EMP_MODULE_PTR 0x0F
1152 #define ICE_SR_PBA_BLOCK_PTR 0x16
1153 #define ICE_SR_BOOT_CFG_PTR 0x132
1154 #define ICE_SR_NVM_WOL_CFG 0x19
1155 #define ICE_NVM_OROM_VER_OFF 0x02
1156 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1157 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
1158 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
1159 #define ICE_SR_NVM_MAP_VER 0x29
1160 #define ICE_SR_NVM_IMAGE_VER 0x2A
1161 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
1162 #define ICE_SR_NVM_EETRACK_LO 0x2D
1163 #define ICE_SR_NVM_EETRACK_HI 0x2E
1164 #define ICE_NVM_VER_LO_SHIFT 0
1165 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1166 #define ICE_NVM_VER_HI_SHIFT 12
1167 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1168 #define ICE_OEM_EETRACK_ID 0xffffffff
1169 #define ICE_OROM_VER_PATCH_SHIFT 0
1170 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1171 #define ICE_OROM_VER_BUILD_SHIFT 8
1172 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1173 #define ICE_OROM_VER_SHIFT 24
1174 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1175 #define ICE_SR_VPD_PTR 0x2F
1176 #define ICE_SR_PXE_SETUP_PTR 0x30
1177 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
1178 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1179 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1180 #define ICE_SR_VLAN_CFG_PTR 0x37
1181 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1182 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1183 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1184 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1185 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
1186 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1187 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
1188 #define ICE_SR_PFA_PTR 0x40
1189 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
1190 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1191 #define ICE_SR_NVM_BANK_SIZE 0x43
1192 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1193 #define ICE_SR_OROM_BANK_SIZE 0x45
1194 #define ICE_SR_NETLIST_BANK_PTR 0x46
1195 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1196 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1197 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1198 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1199 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
1200 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1202 /* CSS Header words */
1203 #define ICE_NVM_CSS_SREV_L 0x14
1204 #define ICE_NVM_CSS_SREV_H 0x15
1206 /* Length of CSS header section in words */
1207 #define ICE_CSS_HEADER_LENGTH 330
1209 /* Offset of Shadow RAM copy in the NVM bank area. */
1210 #define ICE_NVM_SR_COPY_WORD_OFFSET ROUND_UP(ICE_CSS_HEADER_LENGTH, 32)
1212 /* Size in bytes of Option ROM trailer */
1213 #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH)
1215 /* The Link Topology Netlist section is stored as a series of words. It is
1216 * stored in the NVM as a TLV, with the first two words containing the type
1219 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1220 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1221 #define ICE_NETLIST_LEN_OFFSET 0x0001
1223 /* The Link Topology section follows the TLV header. When reading the netlist
1224 * using ice_read_netlist_module, we need to account for the 2-word TLV
1227 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1229 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1230 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1232 #define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0)
1234 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1235 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1236 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1238 /* netlist ID block field offsets (word offsets) */
1239 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1240 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1241 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1242 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1243 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1244 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1245 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1246 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1247 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1248 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1250 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1251 #define ICE_SR_VPD_SIZE_WORDS 512
1252 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1253 #define ICE_SR_CTRL_WORD_1_S 0x06
1254 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1255 #define ICE_SR_CTRL_WORD_VALID 0x1
1256 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1257 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1258 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1260 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1262 /* Shadow RAM related */
1263 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1264 #define ICE_SR_BUF_ALIGNMENT 4096
1265 #define ICE_SR_WORDS_IN_1KB 512
1266 /* Checksum should be calculated such that after adding all the words,
1267 * including the checksum word itself, the sum should be 0xBABA.
1269 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1271 /* Link override related */
1272 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1273 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1274 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1275 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1276 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1277 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1278 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1279 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1281 #define ICE_PBA_FLAG_DFLT 0xFAFA
1282 /* Hash redirection LUT for VSI - maximum array size */
1283 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1286 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1287 * This is needed to determine the BAR0 space for the VFs
1289 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1290 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1291 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1293 /* AQ API version for LLDP_FILTER_CONTROL */
1294 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1295 #define ICE_FW_API_LLDP_FLTR_MIN 7
1296 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1298 /* AQ API version for report default configuration */
1299 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1300 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1301 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1302 #endif /* _ICE_TYPE_H_ */