1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
17 #define ICE_BYTES_PER_WORD 2
18 #define ICE_BYTES_PER_DWORD 4
19 #define ICE_MAX_TRAFFIC_CLASS 8
22 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
25 #include "ice_status.h"
26 #include "ice_hw_autogen.h"
27 #include "ice_devids.h"
28 #include "ice_osdep.h"
29 #include "ice_controlq.h"
30 #include "ice_lan_tx_rx.h"
31 #include "ice_flex_type.h"
32 #include "ice_protocol_type.h"
34 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
36 return ice_is_bit_set(&bitmap, tc);
40 #define DIV_64BIT(n, d) ((n) / (d))
41 #endif /* DIV_64BIT */
43 static inline u64 round_up_64bit(u64 a, u32 b)
45 return DIV_64BIT(((a) + (b) / 2), (b));
48 static inline u32 ice_round_to_num(u32 N, u32 R)
50 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
51 ((((N) + (R) - 1) / (R)) * (R)));
54 /* Driver always calls main vsi_handle first */
55 #define ICE_MAIN_VSI_HANDLE 0
57 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
58 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
60 /* Data type manipulation macros. */
61 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
62 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
63 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
65 /* debug masks - set these bits in hw->debug_mask to control output */
66 #define ICE_DBG_INIT BIT_ULL(1)
67 #define ICE_DBG_RELEASE BIT_ULL(2)
69 #define ICE_DBG_LINK BIT_ULL(4)
70 #define ICE_DBG_PHY BIT_ULL(5)
71 #define ICE_DBG_QCTX BIT_ULL(6)
72 #define ICE_DBG_NVM BIT_ULL(7)
73 #define ICE_DBG_LAN BIT_ULL(8)
74 #define ICE_DBG_FLOW BIT_ULL(9)
75 #define ICE_DBG_DCB BIT_ULL(10)
76 #define ICE_DBG_DIAG BIT_ULL(11)
77 #define ICE_DBG_FD BIT_ULL(12)
78 #define ICE_DBG_SW BIT_ULL(13)
79 #define ICE_DBG_SCHED BIT_ULL(14)
81 #define ICE_DBG_PKG BIT_ULL(16)
82 #define ICE_DBG_RES BIT_ULL(17)
83 #define ICE_DBG_AQ_MSG BIT_ULL(24)
84 #define ICE_DBG_AQ_DESC BIT_ULL(25)
85 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
86 #define ICE_DBG_AQ_CMD BIT_ULL(27)
87 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
89 ICE_DBG_AQ_DESC_BUF | \
92 #define ICE_DBG_USER BIT_ULL(31)
93 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
100 enum ice_aq_res_ids {
103 ICE_CHANGE_LOCK_RES_ID,
104 ICE_GLOBAL_CFG_LOCK_RES_ID
107 /* FW update timeout definitions are in milliseconds */
108 #define ICE_NVM_TIMEOUT 180000
109 #define ICE_CHANGE_LOCK_TIMEOUT 1000
110 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
112 enum ice_aq_res_access_type {
117 struct ice_driver_ver {
122 u8 driver_string[32];
141 enum ice_set_fc_aq_failures {
142 ICE_SET_FC_AQ_FAIL_NONE = 0,
143 ICE_SET_FC_AQ_FAIL_GET,
144 ICE_SET_FC_AQ_FAIL_SET,
145 ICE_SET_FC_AQ_FAIL_UPDATE
148 /* These are structs for managing the hardware information and the operations */
156 enum ice_media_type {
157 ICE_MEDIA_UNKNOWN = 0,
164 /* Software VSI types. */
169 #endif /* ADQ_SUPPORT */
172 struct ice_link_status {
173 /* Refer to ice_aq_phy_type for bits definition */
176 u8 topo_media_conflict;
180 u8 lse_ena; /* Link Status Event notification */
186 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
187 * ice_aqc_get_phy_caps structure
189 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
192 /* Different data queue types: These are mainly for SW consumption. */
201 /* Different reset sources for which a disable queue AQ call has to be made in
202 * order to clean the Tx scheduler as a part of the reset
204 enum ice_disq_rst_src {
209 /* PHY info such as phy_type, etc... */
210 struct ice_phy_info {
211 struct ice_link_status link_info;
212 struct ice_link_status link_info_old;
215 enum ice_media_type media_type;
219 #define ICE_MAX_NUM_MIRROR_RULES 64
221 /* Common HW capabilities for SW use */
222 struct ice_hw_common_caps {
223 /* Write CSR protection */
226 /* switching mode supported - EVB switching (including cloud) */
227 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
229 /* Manageablity mode & supported protocols over MCTP */
231 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
232 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
233 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
235 u32 mgmt_protocols_mctp;
236 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
237 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
238 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
239 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
244 /* RSS related capabilities */
245 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
246 u32 rss_table_entry_width; /* RSS Entry width in bits */
249 u32 num_rxq; /* Number/Total Rx queues */
250 u32 rxq_first_id; /* First queue ID for Rx queues */
251 u32 num_txq; /* Number/Total Tx queues */
252 u32 txq_first_id; /* First queue ID for Tx queues */
255 u32 num_msix_vectors;
256 u32 msix_vector_first_id;
258 /* Max MTU for function or device */
262 u32 num_wol_proxy_fltr;
263 u32 wol_proxy_vsi_seid;
265 /* LED/SDP pin count */
269 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
270 #define ICE_MAX_SUPPORTED_GPIO_LED 12
271 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
272 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
273 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
275 /* EVB capabilities */
276 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
277 u8 evb_802_1_qbh; /* Bridge Port Extension */
282 /* WoL and APM support */
283 #define ICE_WOL_SUPPORT_M BIT(0)
284 #define ICE_ACPI_PROG_MTHD_M BIT(1)
285 #define ICE_PROXY_SUPPORT_M BIT(2)
292 /* Function specific capabilities */
293 struct ice_hw_func_caps {
294 struct ice_hw_common_caps common_cap;
298 /* Device wide capabilities */
299 struct ice_hw_dev_caps {
300 struct ice_hw_common_caps common_cap;
301 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
305 /* Information about MAC such as address, etc... */
306 struct ice_mac_info {
307 u8 lan_addr[ETH_ALEN];
308 u8 perm_addr[ETH_ALEN];
309 u8 port_addr[ETH_ALEN];
310 u8 wol_addr[ETH_ALEN];
317 ice_bus_embedded, /* Is device Embedded versus card */
322 enum ice_pcie_bus_speed {
323 ice_pcie_speed_unknown = 0xff,
324 ice_pcie_speed_2_5GT = 0x14,
325 ice_pcie_speed_5_0GT = 0x15,
326 ice_pcie_speed_8_0GT = 0x16,
327 ice_pcie_speed_16_0GT = 0x17
331 enum ice_pcie_link_width {
332 ice_pcie_lnk_width_resrv = 0x00,
333 ice_pcie_lnk_x1 = 0x01,
334 ice_pcie_lnk_x2 = 0x02,
335 ice_pcie_lnk_x4 = 0x04,
336 ice_pcie_lnk_x8 = 0x08,
337 ice_pcie_lnk_x12 = 0x0C,
338 ice_pcie_lnk_x16 = 0x10,
339 ice_pcie_lnk_x32 = 0x20,
340 ice_pcie_lnk_width_unknown = 0xff,
343 /* Reset types used to determine which kind of reset was requested. These
344 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
345 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
346 * because its reset source is different than the other types listed.
358 struct ice_bus_info {
359 enum ice_pcie_bus_speed speed;
360 enum ice_pcie_link_width width;
361 enum ice_bus_type type;
368 /* Flow control (FC) parameters */
370 enum ice_fc_mode current_mode; /* FC mode in effect */
371 enum ice_fc_mode req_mode; /* FC mode requested by caller */
374 /* NVM Information */
375 struct ice_nvm_info {
376 u32 eetrack; /* NVM data version */
377 u32 oem_ver; /* OEM version info */
378 u16 sr_words; /* Shadow RAM size in words */
379 u16 ver; /* NVM package version */
380 u8 blank_nvm_mode; /* is NVM empty (no FW present)*/
383 /* Max number of port to queue branches w.r.t topology */
384 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
386 #define ice_for_each_traffic_class(_i) \
387 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
389 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
390 * to driver defined policy for default aggregator
392 #define ICE_INVAL_TEID 0xFFFFFFFF
393 #define ICE_DFLT_AGG_ID 0
395 struct ice_sched_node {
396 struct ice_sched_node *parent;
397 struct ice_sched_node *sibling; /* next sibling in the same layer */
398 struct ice_sched_node **children;
399 struct ice_aqc_txsched_elem_data info;
400 u32 agg_id; /* aggregator group ID */
402 u8 in_use; /* suspended or in use */
403 u8 tx_sched_layer; /* Logical Layer (1-9) */
407 #define ICE_SCHED_NODE_OWNER_LAN 0
408 #define ICE_SCHED_NODE_OWNER_AE 1
409 #define ICE_SCHED_NODE_OWNER_RDMA 2
412 /* Access Macros for Tx Sched Elements data */
413 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
414 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
415 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
416 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
417 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
418 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
419 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
420 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
421 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
422 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
423 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
425 struct ice_sched_rl_profle {
426 u32 rate; /* In Kbps */
427 struct ice_aqc_rl_profile_elem info;
430 /* The aggregator type determines if identifier is for a VSI group,
431 * aggregator group, aggregator of queues, or queue group.
434 ICE_AGG_TYPE_UNKNOWN = 0,
436 ICE_AGG_TYPE_AGG, /* aggregator */
442 /* Rate limit types */
445 ICE_MIN_BW, /* for CIR profile */
446 ICE_MAX_BW, /* for EIR profile */
447 ICE_SHARED_BW /* for shared profile */
450 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
451 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
452 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
453 #define ICE_SCHED_NO_PRIORITY 0
454 #define ICE_SCHED_NO_BW_WT 0
455 #define ICE_SCHED_DFLT_RL_PROF_ID 0
456 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
457 #define ICE_SCHED_DFLT_BW_WT 1
458 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
459 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
461 /* Access Macros for Tx Sched RL Profile data */
462 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
463 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
464 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
465 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
466 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
469 /* The following tree example shows the naming conventions followed under
470 * ice_port_info struct for default scheduler tree topology.
474 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
478 * / |-> num_elements (range:1 - 9)
479 * * | implies num_of_layers
483 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
484 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
485 * need TEID of (a) to add queues.
488 * -> has 8 branches (one for each TC)
489 * -> First branch (TC0) has 4 elements
491 * -> (a) is the topmost layer node created by firmware on branch 0
493 * Note: Above asterisk tree covers only basic terminology and scenario.
494 * Refer to the documentation for more info.
497 /* Data structure for saving BW information */
505 ICE_BW_TYPE_CNT /* This must be last */
513 struct ice_bw_type_info {
514 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
516 struct ice_bw cir_bw;
517 struct ice_bw eir_bw;
521 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
522 struct ice_sched_vsi_info {
523 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
524 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
525 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
526 /* bw_t_info saves VSI BW information */
527 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
530 #if !defined(NO_DCB_SUPPORT) || defined(ADQ_SUPPORT)
531 /* CEE or IEEE 802.1Qaz ETS Configuration data */
532 struct ice_dcb_ets_cfg {
536 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
537 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
538 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
541 /* CEE or IEEE 802.1Qaz PFC Configuration data */
542 struct ice_dcb_pfc_cfg {
549 /* CEE or IEEE 802.1Qaz Application Priority data */
550 struct ice_dcb_app_priority_table {
556 #define ICE_MAX_USER_PRIORITY 8
557 #define ICE_DCBX_MAX_APPS 32
558 #define ICE_LLDPDU_SIZE 1500
559 #define ICE_TLV_STATUS_OPER 0x1
560 #define ICE_TLV_STATUS_SYNC 0x2
561 #define ICE_TLV_STATUS_ERR 0x4
562 #define ICE_APP_PROT_ID_FCOE 0x8906
563 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
564 #define ICE_APP_PROT_ID_FIP 0x8914
565 #define ICE_APP_SEL_ETHTYPE 0x1
566 #define ICE_APP_SEL_TCPIP 0x2
567 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
568 #define ICE_CEE_APP_SEL_TCPIP 0x1
570 struct ice_dcbx_cfg {
572 u32 tlv_status; /* CEE mode TLV status */
573 struct ice_dcb_ets_cfg etscfg;
574 struct ice_dcb_ets_cfg etsrec;
575 struct ice_dcb_pfc_cfg pfc;
576 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
578 #define ICE_DCBX_MODE_CEE 0x1
579 #define ICE_DCBX_MODE_IEEE 0x2
581 #define ICE_DCBX_APPS_NON_WILLING 0x1
583 #endif /* !NO_DCB_SUPPORT || ADQ_SUPPORT */
585 struct ice_port_info {
586 struct ice_sched_node *root; /* Root Node per Port */
587 struct ice_hw *hw; /* back pointer to HW instance */
588 u32 last_node_teid; /* scheduler last node info */
589 u16 sw_id; /* Initial switch ID belongs to port */
592 #define ICE_SCHED_PORT_STATE_INIT 0x0
593 #define ICE_SCHED_PORT_STATE_READY 0x1
594 u16 dflt_tx_vsi_rule_id;
596 u16 dflt_rx_vsi_rule_id;
598 struct ice_fc_info fc;
599 struct ice_mac_info mac;
600 struct ice_phy_info phy;
601 struct ice_lock sched_lock; /* protect access to TXSched tree */
602 /* List contain profile ID(s) and other params per layer */
603 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
604 #if !defined(NO_DCB_SUPPORT) || defined(ADQ_SUPPORT)
605 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
606 #endif /* !NO_DCB_SUPPORT || ADQ_SUPPORT */
608 #define ICE_LPORT_MASK 0xff
612 struct ice_switch_info {
613 struct LIST_HEAD_TYPE vsi_list_map_head;
614 struct ice_sw_recipe *recp_list;
617 /* FW logging configuration */
618 struct ice_fw_log_evnt {
619 u8 cfg : 4; /* New event enables to configure */
620 u8 cur : 4; /* Current/active event enables */
623 struct ice_fw_log_cfg {
624 u8 cq_en : 1; /* FW logging is enabled via the control queue */
625 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
626 u8 actv_evnts; /* Cumulation of currently enabled log events */
628 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
629 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
630 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
631 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
632 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
635 /* Port hardware description */
639 struct ice_aqc_layer_props *layer_info;
640 struct ice_port_info *port_info;
641 /* 2D Array for each Tx Sched RL Profile type */
642 struct ice_sched_rl_profile **cir_profiles;
643 struct ice_sched_rl_profile **eir_profiles;
644 struct ice_sched_rl_profile **srl_profiles;
645 u64 debug_mask; /* BITMAP for debug mask */
646 enum ice_mac_type mac_type;
651 u16 subsystem_device_id;
652 u16 subsystem_vendor_id;
655 u8 pf_id; /* device profile info */
657 u16 max_burst_size; /* driver sets this value */
658 /* Tx Scheduler values */
659 u16 num_tx_sched_layers;
660 u16 num_tx_sched_phys_layers;
663 u8 sw_entry_point_layer;
664 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
665 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
666 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
667 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
668 u8 evb_veb; /* true for VEB, false for VEPA */
669 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
670 struct ice_bus_info bus;
671 struct ice_nvm_info nvm;
672 struct ice_hw_dev_caps dev_caps; /* device capabilities */
673 struct ice_hw_func_caps func_caps; /* function capabilities */
675 struct ice_switch_info *switch_info; /* switch filter lists */
677 /* Control Queue info */
678 struct ice_ctl_q_info adminq;
679 struct ice_ctl_q_info mailboxq;
681 u8 api_branch; /* API branch version */
682 u8 api_maj_ver; /* API major version */
683 u8 api_min_ver; /* API minor version */
684 u8 api_patch; /* API patch version */
685 u8 fw_branch; /* firmware branch version */
686 u8 fw_maj_ver; /* firmware major version */
687 u8 fw_min_ver; /* firmware minor version */
688 u8 fw_patch; /* firmware patch version */
689 u32 fw_build; /* firmware build number */
691 struct ice_fw_log_cfg fw_log;
693 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
694 * register. Used for determining the itr/intrl granularity during
697 #define ICE_MAX_AGG_BW_200G 0x0
698 #define ICE_MAX_AGG_BW_100G 0X1
699 #define ICE_MAX_AGG_BW_50G 0x2
700 #define ICE_MAX_AGG_BW_25G 0x3
701 /* ITR granularity for different speeds */
702 #define ICE_ITR_GRAN_ABOVE_25 2
703 #define ICE_ITR_GRAN_MAX_25 4
704 /* ITR granularity in 1 us */
706 /* INTRL granularity for different speeds */
707 #define ICE_INTRL_GRAN_ABOVE_25 4
708 #define ICE_INTRL_GRAN_MAX_25 8
709 /* INTRL granularity in 1 us */
712 u8 ucast_shared; /* true if VSIs can share unicast addr */
714 /* Active package version (currently active) */
715 struct ice_pkg_ver active_pkg_ver;
716 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
718 /* Driver's package ver - (from the Metadata seg) */
719 struct ice_pkg_ver pkg_ver;
720 u8 pkg_name[ICE_PKG_NAME_SIZE];
722 /* Driver's Ice package version (from the Ice seg) */
723 struct ice_pkg_ver ice_pkg_ver;
724 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
726 /* Pointer to the ice segment */
729 /* Pointer to allocated copy of pkg memory */
734 struct ice_tunnel_table tnl;
736 #define ICE_PKG_FILENAME "package_file"
737 #define ICE_PKG_FILENAME_EXT "pkg"
738 #define ICE_PKG_FILE_MAJ_VER 1
739 #define ICE_PKG_FILE_MIN_VER 0
741 /* HW block tables */
742 struct ice_blk_info blk[ICE_BLK_COUNT];
743 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
744 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
747 /* Statistics collected by each port, VSI, VEB, and S-channel */
748 struct ice_eth_stats {
749 u64 rx_bytes; /* gorc */
750 u64 rx_unicast; /* uprc */
751 u64 rx_multicast; /* mprc */
752 u64 rx_broadcast; /* bprc */
753 u64 rx_discards; /* rdpc */
754 u64 rx_unknown_protocol; /* rupp */
755 u64 tx_bytes; /* gotc */
756 u64 tx_unicast; /* uptc */
757 u64 tx_multicast; /* mptc */
758 u64 tx_broadcast; /* bptc */
759 u64 tx_discards; /* tdpc */
760 u64 tx_errors; /* tepc */
765 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
766 struct ice_veb_up_stats {
767 u64 up_rx_pkts[ICE_MAX_UP];
768 u64 up_rx_bytes[ICE_MAX_UP];
769 u64 up_tx_pkts[ICE_MAX_UP];
770 u64 up_tx_bytes[ICE_MAX_UP];
773 /* Statistics collected by the MAC */
774 struct ice_hw_port_stats {
775 /* eth stats collected by the port */
776 struct ice_eth_stats eth;
777 /* additional port specific stats */
778 u64 tx_dropped_link_down; /* tdold */
779 u64 crc_errors; /* crcerrs */
780 u64 illegal_bytes; /* illerrc */
781 u64 error_bytes; /* errbc */
782 u64 mac_local_faults; /* mlfc */
783 u64 mac_remote_faults; /* mrfc */
784 u64 rx_len_errors; /* rlec */
785 u64 link_xon_rx; /* lxonrxc */
786 u64 link_xoff_rx; /* lxoffrxc */
787 u64 link_xon_tx; /* lxontxc */
788 u64 link_xoff_tx; /* lxofftxc */
789 u64 rx_size_64; /* prc64 */
790 u64 rx_size_127; /* prc127 */
791 u64 rx_size_255; /* prc255 */
792 u64 rx_size_511; /* prc511 */
793 u64 rx_size_1023; /* prc1023 */
794 u64 rx_size_1522; /* prc1522 */
795 u64 rx_size_big; /* prc9522 */
796 u64 rx_undersize; /* ruc */
797 u64 rx_fragments; /* rfc */
798 u64 rx_oversize; /* roc */
799 u64 rx_jabber; /* rjc */
800 u64 tx_size_64; /* ptc64 */
801 u64 tx_size_127; /* ptc127 */
802 u64 tx_size_255; /* ptc255 */
803 u64 tx_size_511; /* ptc511 */
804 u64 tx_size_1023; /* ptc1023 */
805 u64 tx_size_1522; /* ptc1522 */
806 u64 tx_size_big; /* ptc9522 */
807 u64 mac_short_pkt_dropped; /* mspdc */
810 enum ice_sw_fwd_act_type {
812 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
819 /* Checksum and Shadow RAM pointers */
820 #define ICE_SR_NVM_CTRL_WORD 0x00
821 #define ICE_SR_PHY_ANALOG_PTR 0x04
822 #define ICE_SR_OPTION_ROM_PTR 0x05
823 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
824 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
825 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
826 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
827 #define ICE_SR_EMP_IMAGE_PTR 0x0B
828 #define ICE_SR_PE_IMAGE_PTR 0x0C
829 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
830 #define ICE_SR_MNG_CFG_PTR 0x0E
831 #define ICE_SR_EMP_MODULE_PTR 0x0F
832 #define ICE_SR_PBA_FLAGS 0x15
833 #define ICE_SR_PBA_BLOCK_PTR 0x16
834 #define ICE_SR_BOOT_CFG_PTR 0x17
835 #define ICE_SR_NVM_WOL_CFG 0x19
836 #define ICE_NVM_OEM_VER_OFF 0x83
837 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
838 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
839 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
840 #define ICE_SR_NVM_MAP_VER 0x29
841 #define ICE_SR_NVM_IMAGE_VER 0x2A
842 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
843 #define ICE_SR_NVM_EETRACK_LO 0x2D
844 #define ICE_SR_NVM_EETRACK_HI 0x2E
845 #define ICE_NVM_VER_LO_SHIFT 0
846 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
847 #define ICE_NVM_VER_HI_SHIFT 12
848 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
849 #define ICE_OEM_EETRACK_ID 0xffffffff
850 #define ICE_OEM_VER_PATCH_SHIFT 0
851 #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT)
852 #define ICE_OEM_VER_BUILD_SHIFT 8
853 #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT)
854 #define ICE_OEM_VER_SHIFT 24
855 #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT)
856 #define ICE_SR_VPD_PTR 0x2F
857 #define ICE_SR_PXE_SETUP_PTR 0x30
858 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
859 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
860 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
861 #define ICE_SR_VLAN_CFG_PTR 0x37
862 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
863 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
864 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
865 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
866 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
867 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
868 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
869 #define ICE_SR_PFA_PTR 0x40
870 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
871 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
872 #define ICE_SR_NVM_BANK_SIZE 0x43
873 #define ICE_SR_1ND_OROM_BANK_PTR 0x44
874 #define ICE_SR_OROM_BANK_SIZE 0x45
875 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
876 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
877 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
879 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
880 #define ICE_SR_VPD_SIZE_WORDS 512
881 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
882 #define ICE_SR_CTRL_WORD_1_S 0x06
883 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
885 /* Shadow RAM related */
886 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
887 #define ICE_SR_BUF_ALIGNMENT 4096
888 #define ICE_SR_WORDS_IN_1KB 512
889 /* Checksum should be calculated such that after adding all the words,
890 * including the checksum word itself, the sum should be 0xBABA.
892 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
894 #define ICE_PBA_FLAG_DFLT 0xFAFA
895 /* Hash redirection LUT for VSI - maximum array size */
896 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
899 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
900 * This is needed to determine the BAR0 space for the VFs
902 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
903 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
904 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
906 #endif /* _ICE_TYPE_H_ */