1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
19 #define ICE_BYTES_PER_WORD 2
20 #define ICE_BYTES_PER_DWORD 4
21 #define ICE_MAX_TRAFFIC_CLASS 8
24 * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
25 * @a: value to round up
26 * @b: arbitrary multiple
28 * Round up to the next multiple of the arbitrary b.
29 * Note, when b is a power of 2 use ICE_ALIGN() instead.
31 #define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
33 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
35 #define IS_ASCII(_ch) ((_ch) < 0x80)
37 #define STRUCT_HACK_VAR_LEN
39 * ice_struct_size - size of struct with C99 flexible array member
40 * @ptr: pointer to structure
41 * @field: flexible array member (last member of the structure)
42 * @num: number of elements of that flexible array member
44 #define ice_struct_size(ptr, field, num) \
45 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
47 #define FLEX_ARRAY_SIZE(_ptr, _mem, cnt) ((cnt) * sizeof(_ptr->_mem[0]))
49 #include "ice_status.h"
50 #include "ice_hw_autogen.h"
51 #include "ice_devids.h"
52 #include "ice_osdep.h"
53 #include "ice_bitops.h" /* Must come before ice_controlq.h */
54 #include "ice_controlq.h"
55 #include "ice_lan_tx_rx.h"
56 #include "ice_flex_type.h"
57 #include "ice_protocol_type.h"
58 #include "ice_vlan_mode.h"
61 * ice_is_pow2 - check if integer value is a power of 2
62 * @val: unsigned integer to be validated
64 static inline bool ice_is_pow2(u64 val)
66 return (val && !(val & (val - 1)));
70 * ice_ilog2 - Calculates integer log base 2 of a number
71 * @n: number on which to perform operation
73 static inline int ice_ilog2(u64 n)
77 for (i = 63; i >= 0; i--)
78 if (((u64)1 << i) & n)
84 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
86 return ice_is_bit_set(&bitmap, tc);
89 #define DIV_64BIT(n, d) ((n) / (d))
91 static inline u64 round_up_64bit(u64 a, u32 b)
93 return DIV_64BIT(((a) + (b) / 2), (b));
96 static inline u32 ice_round_to_num(u32 N, u32 R)
98 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
99 ((((N) + (R) - 1) / (R)) * (R)));
102 /* Driver always calls main vsi_handle first */
103 #define ICE_MAIN_VSI_HANDLE 0
105 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
106 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
108 /* Data type manipulation macros. */
109 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
110 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
111 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
112 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF))
114 /* debug masks - set these bits in hw->debug_mask to control output */
115 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
116 #define ICE_DBG_INIT BIT_ULL(1)
117 #define ICE_DBG_RELEASE BIT_ULL(2)
118 #define ICE_DBG_FW_LOG BIT_ULL(3)
119 #define ICE_DBG_LINK BIT_ULL(4)
120 #define ICE_DBG_PHY BIT_ULL(5)
121 #define ICE_DBG_QCTX BIT_ULL(6)
122 #define ICE_DBG_NVM BIT_ULL(7)
123 #define ICE_DBG_LAN BIT_ULL(8)
124 #define ICE_DBG_FLOW BIT_ULL(9)
125 #define ICE_DBG_DCB BIT_ULL(10)
126 #define ICE_DBG_DIAG BIT_ULL(11)
127 #define ICE_DBG_FD BIT_ULL(12)
128 #define ICE_DBG_SW BIT_ULL(13)
129 #define ICE_DBG_SCHED BIT_ULL(14)
131 #define ICE_DBG_PKG BIT_ULL(16)
132 #define ICE_DBG_RES BIT_ULL(17)
133 #define ICE_DBG_ACL BIT_ULL(18)
134 #define ICE_DBG_AQ_MSG BIT_ULL(24)
135 #define ICE_DBG_AQ_DESC BIT_ULL(25)
136 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
137 #define ICE_DBG_AQ_CMD BIT_ULL(27)
138 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
140 ICE_DBG_AQ_DESC_BUF | \
143 #define ICE_DBG_USER BIT_ULL(31)
144 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
146 #define __ALWAYS_UNUSED
148 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
149 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
150 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
151 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
153 enum ice_aq_res_ids {
156 ICE_CHANGE_LOCK_RES_ID,
157 ICE_GLOBAL_CFG_LOCK_RES_ID
160 /* FW update timeout definitions are in milliseconds */
161 #define ICE_NVM_TIMEOUT 180000
162 #define ICE_CHANGE_LOCK_TIMEOUT 1000
163 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
165 enum ice_aq_res_access_type {
170 struct ice_driver_ver {
175 u8 driver_string[32];
188 enum ice_phy_cache_mode {
201 struct ice_phy_cache_mode_data {
203 enum ice_fec_mode curr_user_fec_req;
204 enum ice_fc_mode curr_user_fc_req;
205 u16 curr_user_speed_req;
209 enum ice_set_fc_aq_failures {
210 ICE_SET_FC_AQ_FAIL_NONE = 0,
211 ICE_SET_FC_AQ_FAIL_GET,
212 ICE_SET_FC_AQ_FAIL_SET,
213 ICE_SET_FC_AQ_FAIL_UPDATE
216 /* These are structs for managing the hardware information and the operations */
225 enum ice_media_type {
226 ICE_MEDIA_UNKNOWN = 0,
234 /* Software VSI types. */
237 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
241 struct ice_link_status {
242 /* Refer to ice_aq_phy_type for bits definition */
245 u8 topo_media_conflict;
250 u8 lse_ena; /* Link Status Event notification */
256 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
257 * ice_aqc_get_phy_caps structure
259 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
262 /* Different data queue types: These are mainly for SW consumption. */
271 /* Different reset sources for which a disable queue AQ call has to be made in
272 * order to clean the Tx scheduler as a part of the reset
274 enum ice_disq_rst_src {
279 /* PHY info such as phy_type, etc... */
280 struct ice_phy_info {
281 struct ice_link_status link_info;
282 struct ice_link_status link_info_old;
285 enum ice_media_type media_type;
287 /* Please refer to struct ice_aqc_get_link_status_data to get
288 * detail of enable bit in curr_user_speed_req
290 u16 curr_user_speed_req;
291 enum ice_fec_mode curr_user_fec_req;
292 enum ice_fc_mode curr_user_fc_req;
293 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
296 #define ICE_MAX_NUM_MIRROR_RULES 64
298 /* protocol enumeration for filters */
299 enum ice_fltr_ptype {
300 /* NONE - used for undef/error */
301 ICE_FLTR_PTYPE_NONF_NONE = 0,
302 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
303 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
304 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
305 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
306 ICE_FLTR_PTYPE_NONF_IPV4_GTPU,
307 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH,
308 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW,
309 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP,
310 ICE_FLTR_PTYPE_NONF_IPV6_GTPU,
311 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH,
312 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_DW,
313 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_UP,
314 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4,
315 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
316 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
317 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,
318 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,
319 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,
320 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4,
321 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP,
322 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP,
323 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4,
324 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_UDP,
325 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_TCP,
326 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4,
327 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_UDP,
328 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_TCP,
329 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
330 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
331 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
332 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_OTHER,
333 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_IPV6_OTHER,
334 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
335 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
336 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
337 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
338 ICE_FLTR_PTYPE_NONF_IPV4_AH,
339 ICE_FLTR_PTYPE_NONF_IPV6_AH,
340 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
341 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
342 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
343 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
344 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
345 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
346 ICE_FLTR_PTYPE_NON_IP_L2,
347 ICE_FLTR_PTYPE_NONF_ECPRI_TP0,
348 ICE_FLTR_PTYPE_NONF_IPV4_UDP_ECPRI_TP0,
349 ICE_FLTR_PTYPE_FRAG_IPV4,
350 ICE_FLTR_PTYPE_FRAG_IPV6,
351 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
352 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
353 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
354 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
355 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN,
356 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_UDP,
357 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_TCP,
358 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_SCTP,
359 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_OTHER,
364 ICE_FD_HW_SEG_NON_TUN = 0,
369 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
370 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
372 struct ice_fd_hw_prof {
373 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
375 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
376 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
379 /* Common HW capabilities for SW use */
380 struct ice_hw_common_caps {
381 /* Write CSR protection */
384 /* switching mode supported - EVB switching (including cloud) */
385 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
387 /* Manageablity mode & supported protocols over MCTP */
389 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
390 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
391 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
393 u32 mgmt_protocols_mctp;
394 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
395 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
396 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
397 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
401 /* DCB capabilities */
402 u32 active_tc_bitmap;
405 /* RSS related capabilities */
406 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
407 u32 rss_table_entry_width; /* RSS Entry width in bits */
410 u32 num_rxq; /* Number/Total Rx queues */
411 u32 rxq_first_id; /* First queue ID for Rx queues */
412 u32 num_txq; /* Number/Total Tx queues */
413 u32 txq_first_id; /* First queue ID for Tx queues */
416 u32 num_msix_vectors;
417 u32 msix_vector_first_id;
419 /* Max MTU for function or device */
423 u32 num_wol_proxy_fltr;
424 u32 wol_proxy_vsi_seid;
426 /* LED/SDP pin count */
430 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
431 #define ICE_MAX_SUPPORTED_GPIO_LED 12
432 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
433 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
434 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
436 /* EVB capabilities */
437 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
438 u8 evb_802_1_qbh; /* Bridge Port Extension */
445 /* WoL and APM support */
446 #define ICE_WOL_SUPPORT_M BIT(0)
447 #define ICE_ACPI_PROG_MTHD_M BIT(1)
448 #define ICE_PROXY_SUPPORT_M BIT(2)
452 bool sec_rev_disabled;
453 bool update_disabled;
454 bool nvm_unified_update;
455 #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0)
456 #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1)
457 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
459 /* External topology device images within the NVM */
460 #define ICE_EXT_TOPO_DEV_IMG_COUNT 4
461 u32 ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT];
462 u32 ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT];
463 u8 ext_topo_dev_img_part_num[ICE_EXT_TOPO_DEV_IMG_COUNT];
464 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_S 8
465 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_M \
466 MAKEMASK(0xFF, ICE_EXT_TOPO_DEV_IMG_PART_NUM_S)
467 bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
468 #define ICE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0)
469 bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
470 #define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1)
473 /* IEEE 1588 TIME_SYNC specific info */
474 /* Function specific definitions */
475 #define ICE_TS_FUNC_ENA_M BIT(0)
476 #define ICE_TS_SRC_TMR_OWND_M BIT(1)
477 #define ICE_TS_TMR_ENA_M BIT(2)
478 #define ICE_TS_TMR_IDX_OWND_S 4
479 #define ICE_TS_TMR_IDX_OWND_M BIT(4)
480 #define ICE_TS_CLK_FREQ_S 16
481 #define ICE_TS_CLK_FREQ_M MAKEMASK(0x7, ICE_TS_CLK_FREQ_S)
482 #define ICE_TS_CLK_SRC_S 20
483 #define ICE_TS_CLK_SRC_M BIT(20)
484 #define ICE_TS_TMR_IDX_ASSOC_S 24
485 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
487 /* TIME_REF clock rate specification */
488 enum ice_time_ref_freq {
489 ICE_TIME_REF_FREQ_25_000 = 0,
490 ICE_TIME_REF_FREQ_122_880 = 1,
491 ICE_TIME_REF_FREQ_125_000 = 2,
492 ICE_TIME_REF_FREQ_153_600 = 3,
493 ICE_TIME_REF_FREQ_156_250 = 4,
494 ICE_TIME_REF_FREQ_245_760 = 5,
496 NUM_ICE_TIME_REF_FREQ
499 /* Clock source specification */
501 ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */
502 ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */
507 struct ice_ts_func_info {
508 /* Function specific info */
509 enum ice_time_ref_freq time_ref;
519 /* Device specific definitions */
520 #define ICE_TS_TMR0_OWNR_M 0x7
521 #define ICE_TS_TMR0_OWND_M BIT(3)
522 #define ICE_TS_TMR1_OWNR_S 4
523 #define ICE_TS_TMR1_OWNR_M MAKEMASK(0x7, ICE_TS_TMR1_OWNR_S)
524 #define ICE_TS_TMR1_OWND_M BIT(7)
525 #define ICE_TS_DEV_ENA_M BIT(24)
526 #define ICE_TS_TMR0_ENA_M BIT(25)
527 #define ICE_TS_TMR1_ENA_M BIT(26)
529 struct ice_ts_dev_info {
530 /* Device specific info */
542 /* Function specific capabilities */
543 struct ice_hw_func_caps {
544 struct ice_hw_common_caps common_cap;
546 u32 fd_fltr_guar; /* Number of filters guaranteed */
547 u32 fd_fltr_best_effort; /* Number of best effort filters */
548 struct ice_ts_func_info ts_func_info;
551 /* Device wide capabilities */
552 struct ice_hw_dev_caps {
553 struct ice_hw_common_caps common_cap;
554 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
555 u32 num_flow_director_fltr; /* Number of FD filters available */
556 struct ice_ts_dev_info ts_dev_info;
560 /* Information about MAC such as address, etc... */
561 struct ice_mac_info {
562 u8 lan_addr[ETH_ALEN];
563 u8 perm_addr[ETH_ALEN];
564 u8 port_addr[ETH_ALEN];
565 u8 wol_addr[ETH_ALEN];
572 ice_bus_embedded, /* Is device Embedded versus card */
577 enum ice_pcie_bus_speed {
578 ice_pcie_speed_unknown = 0xff,
579 ice_pcie_speed_2_5GT = 0x14,
580 ice_pcie_speed_5_0GT = 0x15,
581 ice_pcie_speed_8_0GT = 0x16,
582 ice_pcie_speed_16_0GT = 0x17
586 enum ice_pcie_link_width {
587 ice_pcie_lnk_width_resrv = 0x00,
588 ice_pcie_lnk_x1 = 0x01,
589 ice_pcie_lnk_x2 = 0x02,
590 ice_pcie_lnk_x4 = 0x04,
591 ice_pcie_lnk_x8 = 0x08,
592 ice_pcie_lnk_x12 = 0x0C,
593 ice_pcie_lnk_x16 = 0x10,
594 ice_pcie_lnk_x32 = 0x20,
595 ice_pcie_lnk_width_unknown = 0xff,
598 /* Reset types used to determine which kind of reset was requested. These
599 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
600 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
601 * because its reset source is different than the other types listed.
613 struct ice_bus_info {
614 enum ice_pcie_bus_speed speed;
615 enum ice_pcie_link_width width;
616 enum ice_bus_type type;
623 /* Flow control (FC) parameters */
625 enum ice_fc_mode current_mode; /* FC mode in effect */
626 enum ice_fc_mode req_mode; /* FC mode requested by caller */
629 /* Option ROM version information */
630 struct ice_orom_info {
631 u8 major; /* Major version of OROM */
632 u8 patch; /* Patch version of OROM */
633 u16 build; /* Build version of OROM */
634 u32 srev; /* Security revision */
637 /* NVM version information */
638 struct ice_nvm_info {
645 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
646 * of the flash image.
648 enum ice_flash_bank {
649 ICE_INVALID_FLASH_BANK,
654 /* Enumeration of which flash bank is desired to read from, either the active
655 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
656 * code which just wants to read the active or inactive flash bank.
658 enum ice_bank_select {
659 ICE_ACTIVE_FLASH_BANK,
660 ICE_INACTIVE_FLASH_BANK,
663 /* information for accessing NVM, OROM, and Netlist flash banks */
664 struct ice_bank_info {
665 u32 nvm_ptr; /* Pointer to 1st NVM bank */
666 u32 nvm_size; /* Size of NVM bank */
667 u32 orom_ptr; /* Pointer to 1st OROM bank */
668 u32 orom_size; /* Size of OROM bank */
669 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
670 u32 netlist_size; /* Size of Netlist bank */
671 enum ice_flash_bank nvm_bank; /* Active NVM bank */
672 enum ice_flash_bank orom_bank; /* Active OROM bank */
673 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
676 /* Flash Chip Information */
677 struct ice_flash_info {
678 struct ice_orom_info orom; /* Option ROM version info */
679 struct ice_nvm_info nvm; /* NVM version information */
680 struct ice_bank_info banks; /* Flash Bank information */
681 u16 sr_words; /* Shadow RAM size in words */
682 u32 flash_size; /* Size of available flash in bytes */
683 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
686 struct ice_link_default_override_tlv {
688 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
689 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
690 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
691 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
692 #define ICE_LINK_OVERRIDE_EN BIT(3)
693 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
694 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
696 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
697 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
698 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
699 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
700 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
702 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
708 #define ICE_NVM_VER_LEN 32
710 /* Max number of port to queue branches w.r.t topology */
711 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
713 #define ice_for_each_traffic_class(_i) \
714 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
716 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
717 * to driver defined policy for default aggregator
719 #define ICE_INVAL_TEID 0xFFFFFFFF
720 #define ICE_DFLT_AGG_ID 0
722 struct ice_sched_node {
723 struct ice_sched_node *parent;
724 struct ice_sched_node *sibling; /* next sibling in the same layer */
725 struct ice_sched_node **children;
726 struct ice_aqc_txsched_elem_data info;
727 u32 agg_id; /* aggregator group ID */
729 u8 in_use; /* suspended or in use */
730 u8 tx_sched_layer; /* Logical Layer (1-9) */
734 #define ICE_SCHED_NODE_OWNER_LAN 0
735 #define ICE_SCHED_NODE_OWNER_AE 1
736 #define ICE_SCHED_NODE_OWNER_RDMA 2
739 /* Access Macros for Tx Sched Elements data */
740 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
741 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
742 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
743 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
744 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
745 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
746 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
747 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
748 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
749 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
750 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
752 struct ice_sched_rl_profile {
753 u32 rate; /* In Kbps */
754 struct ice_aqc_rl_profile_elem info;
757 /* The aggregator type determines if identifier is for a VSI group,
758 * aggregator group, aggregator of queues, or queue group.
761 ICE_AGG_TYPE_UNKNOWN = 0,
763 ICE_AGG_TYPE_AGG, /* aggregator */
769 /* Rate limit types */
772 ICE_MIN_BW, /* for CIR profile */
773 ICE_MAX_BW, /* for EIR profile */
774 ICE_SHARED_BW /* for shared profile */
777 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
778 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
779 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
780 #define ICE_SCHED_NO_PRIORITY 0
781 #define ICE_SCHED_NO_BW_WT 0
782 #define ICE_SCHED_DFLT_RL_PROF_ID 0
783 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
784 #define ICE_SCHED_DFLT_BW_WT 4
785 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
786 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
788 /* Access Macros for Tx Sched RL Profile data */
789 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
790 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
791 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
792 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
793 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
795 /* The following tree example shows the naming conventions followed under
796 * ice_port_info struct for default scheduler tree topology.
800 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
804 * / |-> num_elements (range:1 - 9)
805 * * | implies num_of_layers
809 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
810 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
811 * need TEID of (a) to add queues.
814 * -> has 8 branches (one for each TC)
815 * -> First branch (TC0) has 4 elements
817 * -> (a) is the topmost layer node created by firmware on branch 0
819 * Note: Above asterisk tree covers only basic terminology and scenario.
820 * Refer to the documentation for more info.
823 /* Data structure for saving BW information */
831 ICE_BW_TYPE_CNT /* This must be last */
839 struct ice_bw_type_info {
840 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
842 struct ice_bw cir_bw;
843 struct ice_bw eir_bw;
847 /* VSI queue context structure for given TC */
851 /* bw_t_info saves queue BW information */
852 struct ice_bw_type_info bw_t_info;
855 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
856 struct ice_sched_vsi_info {
857 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
858 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
859 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
860 /* bw_t_info saves VSI BW information */
861 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
864 /* CEE or IEEE 802.1Qaz ETS Configuration data */
865 struct ice_dcb_ets_cfg {
869 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
870 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
871 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
874 /* CEE or IEEE 802.1Qaz PFC Configuration data */
875 struct ice_dcb_pfc_cfg {
882 /* CEE or IEEE 802.1Qaz Application Priority data */
883 struct ice_dcb_app_priority_table {
889 #define ICE_MAX_USER_PRIORITY 8
890 #define ICE_DCBX_MAX_APPS 64
891 #define ICE_DSCP_NUM_VAL 64
892 #define ICE_LLDPDU_SIZE 1500
893 #define ICE_TLV_STATUS_OPER 0x1
894 #define ICE_TLV_STATUS_SYNC 0x2
895 #define ICE_TLV_STATUS_ERR 0x4
896 #define ICE_APP_PROT_ID_FCOE 0x8906
897 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
898 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
899 #define ICE_APP_PROT_ID_FIP 0x8914
900 #define ICE_APP_SEL_ETHTYPE 0x1
901 #define ICE_APP_SEL_TCPIP 0x2
902 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
903 #define ICE_CEE_APP_SEL_TCPIP 0x1
905 struct ice_dcbx_cfg {
907 u32 tlv_status; /* CEE mode TLV status */
908 struct ice_dcb_ets_cfg etscfg;
909 struct ice_dcb_ets_cfg etsrec;
910 struct ice_dcb_pfc_cfg pfc;
911 #define ICE_QOS_MODE_VLAN 0x0
912 #define ICE_QOS_MODE_DSCP 0x1
914 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
915 /* when DSCP mapping defined by user set its bit to 1 */
916 ice_declare_bitmap(dscp_mapped, ICE_DSCP_NUM_VAL);
917 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
918 u8 dscp_map[ICE_DSCP_NUM_VAL];
920 #define ICE_DCBX_MODE_CEE 0x1
921 #define ICE_DCBX_MODE_IEEE 0x2
923 #define ICE_DCBX_APPS_NON_WILLING 0x1
927 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
928 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
929 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
930 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
934 struct ice_port_info {
935 struct ice_sched_node *root; /* Root Node per Port */
936 struct ice_hw *hw; /* back pointer to HW instance */
937 u32 last_node_teid; /* scheduler last node info */
938 u16 sw_id; /* Initial switch ID belongs to port */
941 #define ICE_SCHED_PORT_STATE_INIT 0x0
942 #define ICE_SCHED_PORT_STATE_READY 0x1
944 #define ICE_LPORT_MASK 0xff
945 u16 dflt_tx_vsi_rule_id;
947 u16 dflt_rx_vsi_rule_id;
949 struct ice_fc_info fc;
950 struct ice_mac_info mac;
951 struct ice_phy_info phy;
952 struct ice_lock sched_lock; /* protect access to TXSched tree */
953 struct ice_sched_node *
954 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
955 struct ice_bw_type_info root_node_bw_t_info;
956 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
957 struct ice_qos_cfg qos_cfg;
961 struct ice_switch_info {
962 struct LIST_HEAD_TYPE vsi_list_map_head;
963 struct ice_sw_recipe *recp_list;
964 u16 prof_res_bm_init;
965 u16 max_used_prof_index;
967 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
970 /* Port hardware description */
974 struct ice_aqc_layer_props *layer_info;
975 struct ice_port_info *port_info;
976 /* 2D Array for each Tx Sched RL Profile type */
977 struct ice_sched_rl_profile **cir_profiles;
978 struct ice_sched_rl_profile **eir_profiles;
979 struct ice_sched_rl_profile **srl_profiles;
980 /* PSM clock frequency for calculating RL profile params */
982 u64 debug_mask; /* BITMAP for debug mask */
983 enum ice_mac_type mac_type;
985 u16 fd_ctr_base; /* FD counter base index */
989 u16 subsystem_device_id;
990 u16 subsystem_vendor_id;
993 u8 pf_id; /* device profile info */
995 u16 max_burst_size; /* driver sets this value */
997 /* Tx Scheduler values */
998 u8 num_tx_sched_layers;
999 u8 num_tx_sched_phys_layers;
1000 u8 flattened_layers;
1002 u8 sw_entry_point_layer;
1003 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1004 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
1005 /* List contain profile ID(s) and other params per layer */
1006 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1007 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
1008 u8 evb_veb; /* true for VEB, false for VEPA */
1009 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
1010 struct ice_bus_info bus;
1011 struct ice_flash_info flash;
1012 struct ice_hw_dev_caps dev_caps; /* device capabilities */
1013 struct ice_hw_func_caps func_caps; /* function capabilities */
1015 struct ice_switch_info *switch_info; /* switch filter lists */
1017 /* Control Queue info */
1018 struct ice_ctl_q_info adminq;
1019 struct ice_ctl_q_info mailboxq;
1020 /* Additional function to send AdminQ command */
1021 int (*aq_send_cmd_fn)(void *param, struct ice_aq_desc *desc,
1022 void *buf, u16 buf_size);
1023 void *aq_send_cmd_param;
1024 u8 dcf_enabled; /* Device Config Function */
1026 u8 api_branch; /* API branch version */
1027 u8 api_maj_ver; /* API major version */
1028 u8 api_min_ver; /* API minor version */
1029 u8 api_patch; /* API patch version */
1030 u8 fw_branch; /* firmware branch version */
1031 u8 fw_maj_ver; /* firmware major version */
1032 u8 fw_min_ver; /* firmware minor version */
1033 u8 fw_patch; /* firmware patch version */
1034 u32 fw_build; /* firmware build number */
1036 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
1037 * register. Used for determining the ITR/INTRL granularity during
1040 #define ICE_MAX_AGG_BW_200G 0x0
1041 #define ICE_MAX_AGG_BW_100G 0X1
1042 #define ICE_MAX_AGG_BW_50G 0x2
1043 #define ICE_MAX_AGG_BW_25G 0x3
1044 /* ITR granularity for different speeds */
1045 #define ICE_ITR_GRAN_ABOVE_25 2
1046 #define ICE_ITR_GRAN_MAX_25 4
1047 /* ITR granularity in 1 us */
1049 /* INTRL granularity for different speeds */
1050 #define ICE_INTRL_GRAN_ABOVE_25 4
1051 #define ICE_INTRL_GRAN_MAX_25 8
1052 /* INTRL granularity in 1 us */
1055 u8 ucast_shared; /* true if VSIs can share unicast addr */
1057 #define ICE_PHY_PER_NAC 1
1058 #define ICE_MAX_QUAD 2
1059 #define ICE_NUM_QUAD_TYPE 2
1060 #define ICE_PORTS_PER_QUAD 4
1061 #define ICE_PHY_0_LAST_QUAD 1
1062 #define ICE_PORTS_PER_PHY 8
1063 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
1065 /* Active package version (currently active) */
1066 struct ice_pkg_ver active_pkg_ver;
1067 u32 active_track_id;
1068 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
1069 u8 active_pkg_in_nvm;
1071 enum ice_aq_err pkg_dwnld_status;
1073 /* Driver's package ver - (from the Ice Metadata section) */
1074 struct ice_pkg_ver pkg_ver;
1075 u8 pkg_name[ICE_PKG_NAME_SIZE];
1077 /* Driver's Ice segment format version and id (from the Ice seg) */
1078 struct ice_pkg_ver ice_seg_fmt_ver;
1079 u8 ice_seg_id[ICE_SEG_ID_SIZE];
1081 /* Pointer to the ice segment */
1082 struct ice_seg *seg;
1084 /* Pointer to allocated copy of pkg memory */
1088 /* tunneling info */
1089 struct ice_lock tnl_lock;
1090 struct ice_tunnel_table tnl;
1091 /* dvm boost update information */
1092 struct ice_dvm_table dvm_upd;
1094 struct ice_acl_tbl *acl_tbl;
1095 struct ice_fd_hw_prof **acl_prof;
1096 u16 acl_fltr_cnt[ICE_FLTR_PTYPE_MAX];
1097 /* HW block tables */
1098 struct ice_blk_info blk[ICE_BLK_COUNT];
1099 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
1100 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
1101 /* Flow Director filter info */
1102 int fdir_active_fltr;
1104 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
1105 struct LIST_HEAD_TYPE fdir_list_head;
1107 /* Book-keeping of side-band filter count per flow-type.
1108 * This is used to detect and handle input set changes for
1109 * respective flow-type.
1111 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
1113 struct ice_fd_hw_prof **fdir_prof;
1114 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
1115 struct ice_lock rss_locks; /* protect RSS configuration */
1116 struct LIST_HEAD_TYPE rss_list_head;
1117 ice_declare_bitmap(hw_ptype, ICE_FLOW_PTYPE_MAX);
1121 /* Statistics collected by each port, VSI, VEB, and S-channel */
1122 struct ice_eth_stats {
1123 u64 rx_bytes; /* gorc */
1124 u64 rx_unicast; /* uprc */
1125 u64 rx_multicast; /* mprc */
1126 u64 rx_broadcast; /* bprc */
1127 u64 rx_discards; /* rdpc */
1128 u64 rx_unknown_protocol; /* rupp */
1129 u64 tx_bytes; /* gotc */
1130 u64 tx_unicast; /* uptc */
1131 u64 tx_multicast; /* mptc */
1132 u64 tx_broadcast; /* bptc */
1133 u64 tx_discards; /* tdpc */
1134 u64 tx_errors; /* tepc */
1135 u64 rx_no_desc; /* repc */
1136 u64 rx_errors; /* repc */
1139 #define ICE_MAX_UP 8
1141 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
1142 struct ice_veb_up_stats {
1143 u64 up_rx_pkts[ICE_MAX_UP];
1144 u64 up_rx_bytes[ICE_MAX_UP];
1145 u64 up_tx_pkts[ICE_MAX_UP];
1146 u64 up_tx_bytes[ICE_MAX_UP];
1149 /* Statistics collected by the MAC */
1150 struct ice_hw_port_stats {
1151 /* eth stats collected by the port */
1152 struct ice_eth_stats eth;
1153 /* additional port specific stats */
1154 u64 tx_dropped_link_down; /* tdold */
1155 u64 crc_errors; /* crcerrs */
1156 u64 illegal_bytes; /* illerrc */
1157 u64 error_bytes; /* errbc */
1158 u64 mac_local_faults; /* mlfc */
1159 u64 mac_remote_faults; /* mrfc */
1160 u64 rx_len_errors; /* rlec */
1161 u64 link_xon_rx; /* lxonrxc */
1162 u64 link_xoff_rx; /* lxoffrxc */
1163 u64 link_xon_tx; /* lxontxc */
1164 u64 link_xoff_tx; /* lxofftxc */
1165 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1166 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1167 u64 priority_xon_tx[8]; /* pxontxc[8] */
1168 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1169 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1170 u64 rx_size_64; /* prc64 */
1171 u64 rx_size_127; /* prc127 */
1172 u64 rx_size_255; /* prc255 */
1173 u64 rx_size_511; /* prc511 */
1174 u64 rx_size_1023; /* prc1023 */
1175 u64 rx_size_1522; /* prc1522 */
1176 u64 rx_size_big; /* prc9522 */
1177 u64 rx_undersize; /* ruc */
1178 u64 rx_fragments; /* rfc */
1179 u64 rx_oversize; /* roc */
1180 u64 rx_jabber; /* rjc */
1181 u64 tx_size_64; /* ptc64 */
1182 u64 tx_size_127; /* ptc127 */
1183 u64 tx_size_255; /* ptc255 */
1184 u64 tx_size_511; /* ptc511 */
1185 u64 tx_size_1023; /* ptc1023 */
1186 u64 tx_size_1522; /* ptc1522 */
1187 u64 tx_size_big; /* ptc9522 */
1188 u64 mac_short_pkt_dropped; /* mspdc */
1189 /* flow director stats */
1194 enum ice_sw_fwd_act_type {
1196 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1203 struct ice_aq_get_set_rss_lut_params {
1204 u16 vsi_handle; /* software VSI handle */
1205 u16 lut_size; /* size of the LUT buffer */
1206 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1207 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1208 u8 global_lut_id; /* only valid when lut_type is global */
1211 /* Checksum and Shadow RAM pointers */
1212 #define ICE_SR_NVM_CTRL_WORD 0x00
1213 #define ICE_SR_PHY_ANALOG_PTR 0x04
1214 #define ICE_SR_OPTION_ROM_PTR 0x05
1215 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1216 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1217 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1218 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
1219 #define ICE_SR_EMP_IMAGE_PTR 0x0B
1220 #define ICE_SR_PE_IMAGE_PTR 0x0C
1221 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
1222 #define ICE_SR_MNG_CFG_PTR 0x0E
1223 #define ICE_SR_EMP_MODULE_PTR 0x0F
1224 #define ICE_SR_PBA_BLOCK_PTR 0x16
1225 #define ICE_SR_BOOT_CFG_PTR 0x132
1226 #define ICE_SR_NVM_WOL_CFG 0x19
1227 #define ICE_NVM_OROM_VER_OFF 0x02
1228 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1229 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
1230 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
1231 #define ICE_SR_NVM_MAP_VER 0x29
1232 #define ICE_SR_NVM_IMAGE_VER 0x2A
1233 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
1234 #define ICE_SR_NVM_EETRACK_LO 0x2D
1235 #define ICE_SR_NVM_EETRACK_HI 0x2E
1236 #define ICE_NVM_VER_LO_SHIFT 0
1237 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1238 #define ICE_NVM_VER_HI_SHIFT 12
1239 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1240 #define ICE_OEM_EETRACK_ID 0xffffffff
1241 #define ICE_OROM_VER_PATCH_SHIFT 0
1242 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1243 #define ICE_OROM_VER_BUILD_SHIFT 8
1244 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1245 #define ICE_OROM_VER_SHIFT 24
1246 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1247 #define ICE_SR_VPD_PTR 0x2F
1248 #define ICE_SR_PXE_SETUP_PTR 0x30
1249 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
1250 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1251 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1252 #define ICE_SR_VLAN_CFG_PTR 0x37
1253 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1254 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1255 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1256 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1257 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
1258 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1259 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
1260 #define ICE_SR_PFA_PTR 0x40
1261 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
1262 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1263 #define ICE_SR_NVM_BANK_SIZE 0x43
1264 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1265 #define ICE_SR_OROM_BANK_SIZE 0x45
1266 #define ICE_SR_NETLIST_BANK_PTR 0x46
1267 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1268 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1269 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1270 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1271 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
1272 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1274 /* CSS Header words */
1275 #define ICE_NVM_CSS_SREV_L 0x14
1276 #define ICE_NVM_CSS_SREV_H 0x15
1278 /* Length of CSS header section in words */
1279 #define ICE_CSS_HEADER_LENGTH 330
1281 /* Offset of Shadow RAM copy in the NVM bank area. */
1282 #define ICE_NVM_SR_COPY_WORD_OFFSET ROUND_UP(ICE_CSS_HEADER_LENGTH, 32)
1284 /* Size in bytes of Option ROM trailer */
1285 #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH)
1287 /* The Link Topology Netlist section is stored as a series of words. It is
1288 * stored in the NVM as a TLV, with the first two words containing the type
1291 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1292 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1293 #define ICE_NETLIST_LEN_OFFSET 0x0001
1295 /* The Link Topology section follows the TLV header. When reading the netlist
1296 * using ice_read_netlist_module, we need to account for the 2-word TLV
1299 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1301 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1302 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1304 #define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0)
1306 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1307 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1308 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1310 /* netlist ID block field offsets (word offsets) */
1311 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1312 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1313 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1314 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1315 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1316 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1317 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1318 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1319 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1320 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1322 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1323 #define ICE_SR_VPD_SIZE_WORDS 512
1324 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1325 #define ICE_SR_CTRL_WORD_1_S 0x06
1326 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1327 #define ICE_SR_CTRL_WORD_VALID 0x1
1328 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1329 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1330 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1332 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1334 /* Shadow RAM related */
1335 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1336 #define ICE_SR_BUF_ALIGNMENT 4096
1337 #define ICE_SR_WORDS_IN_1KB 512
1338 /* Checksum should be calculated such that after adding all the words,
1339 * including the checksum word itself, the sum should be 0xBABA.
1341 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1343 /* Link override related */
1344 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1345 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1346 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1347 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1348 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1349 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1350 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1351 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1353 #define ICE_PBA_FLAG_DFLT 0xFAFA
1354 /* Hash redirection LUT for VSI - maximum array size */
1355 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1358 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1359 * This is needed to determine the BAR0 space for the VFs
1361 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1362 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1363 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1365 /* AQ API version for LLDP_FILTER_CONTROL */
1366 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1367 #define ICE_FW_API_LLDP_FLTR_MIN 7
1368 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1370 /* AQ API version for report default configuration */
1371 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1372 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1373 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1374 #endif /* _ICE_TYPE_H_ */