1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
17 #include <rte_atomic.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
22 #include <rte_malloc.h>
23 #include <rte_memzone.h>
29 #define ICE_DCF_AQ_LEN 32
30 #define ICE_DCF_AQ_BUF_SZ 4096
32 #define ICE_DCF_ARQ_MAX_RETRIES 200
33 #define ICE_DCF_ARQ_CHECK_TIME 2 /* msecs */
35 #define ICE_DCF_VF_RES_BUF_SZ \
36 (sizeof(struct virtchnl_vf_resource) + \
37 IAVF_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource))
39 static __rte_always_inline int
40 ice_dcf_send_cmd_req_no_irq(struct ice_dcf_hw *hw, enum virtchnl_ops op,
41 uint8_t *req_msg, uint16_t req_msglen)
43 return iavf_aq_send_msg_to_pf(&hw->avf, op, IAVF_SUCCESS,
44 req_msg, req_msglen, NULL);
48 ice_dcf_recv_cmd_rsp_no_irq(struct ice_dcf_hw *hw, enum virtchnl_ops op,
49 uint8_t *rsp_msgbuf, uint16_t rsp_buflen,
52 struct iavf_arq_event_info event;
53 enum virtchnl_ops v_op;
57 event.buf_len = rsp_buflen;
58 event.msg_buf = rsp_msgbuf;
61 err = iavf_clean_arq_element(&hw->avf, &event, NULL);
62 if (err != IAVF_SUCCESS)
65 v_op = rte_le_to_cpu_32(event.desc.cookie_high);
69 if (rsp_msglen != NULL)
70 *rsp_msglen = event.msg_len;
71 return rte_le_to_cpu_32(event.desc.cookie_low);
74 rte_delay_ms(ICE_DCF_ARQ_CHECK_TIME);
75 } while (i++ < ICE_DCF_ARQ_MAX_RETRIES);
80 static __rte_always_inline void
81 ice_dcf_aq_cmd_clear(struct ice_dcf_hw *hw, struct dcf_virtchnl_cmd *cmd)
83 rte_spinlock_lock(&hw->vc_cmd_queue_lock);
85 TAILQ_REMOVE(&hw->vc_cmd_queue, cmd, next);
87 rte_spinlock_unlock(&hw->vc_cmd_queue_lock);
90 static __rte_always_inline void
91 ice_dcf_vc_cmd_set(struct ice_dcf_hw *hw, struct dcf_virtchnl_cmd *cmd)
93 cmd->v_ret = IAVF_ERR_NOT_READY;
97 rte_spinlock_lock(&hw->vc_cmd_queue_lock);
99 TAILQ_INSERT_TAIL(&hw->vc_cmd_queue, cmd, next);
101 rte_spinlock_unlock(&hw->vc_cmd_queue_lock);
104 static __rte_always_inline int
105 ice_dcf_vc_cmd_send(struct ice_dcf_hw *hw, struct dcf_virtchnl_cmd *cmd)
107 return iavf_aq_send_msg_to_pf(&hw->avf,
108 cmd->v_op, IAVF_SUCCESS,
109 cmd->req_msg, cmd->req_msglen, NULL);
112 static __rte_always_inline void
113 ice_dcf_aq_cmd_handle(struct ice_dcf_hw *hw, struct iavf_arq_event_info *info)
115 struct dcf_virtchnl_cmd *cmd;
116 enum virtchnl_ops v_op;
117 enum iavf_status v_ret;
120 aq_op = rte_le_to_cpu_16(info->desc.opcode);
121 if (unlikely(aq_op != iavf_aqc_opc_send_msg_to_vf)) {
123 "Request %u is not supported yet", aq_op);
127 v_op = rte_le_to_cpu_32(info->desc.cookie_high);
128 if (v_op == VIRTCHNL_OP_EVENT) {
129 if (hw->vc_event_msg_cb != NULL)
130 hw->vc_event_msg_cb(hw,
136 v_ret = rte_le_to_cpu_32(info->desc.cookie_low);
138 rte_spinlock_lock(&hw->vc_cmd_queue_lock);
140 TAILQ_FOREACH(cmd, &hw->vc_cmd_queue, next) {
141 if (cmd->v_op == v_op && cmd->pending) {
143 cmd->rsp_msglen = RTE_MIN(info->msg_len,
145 if (likely(cmd->rsp_msglen != 0))
146 rte_memcpy(cmd->rsp_msgbuf, info->msg_buf,
149 /* prevent compiler reordering */
150 rte_compiler_barrier();
156 rte_spinlock_unlock(&hw->vc_cmd_queue_lock);
160 ice_dcf_handle_virtchnl_msg(struct ice_dcf_hw *hw)
162 struct iavf_arq_event_info info;
163 uint16_t pending = 1;
166 info.buf_len = ICE_DCF_AQ_BUF_SZ;
167 info.msg_buf = hw->arq_buf;
170 ret = iavf_clean_arq_element(&hw->avf, &info, &pending);
171 if (ret != IAVF_SUCCESS)
174 ice_dcf_aq_cmd_handle(hw, &info);
179 ice_dcf_init_check_api_version(struct ice_dcf_hw *hw)
181 #define ICE_CPF_VIRTCHNL_VERSION_MAJOR_START 1
182 #define ICE_CPF_VIRTCHNL_VERSION_MINOR_START 1
183 struct virtchnl_version_info version, *pver;
186 version.major = VIRTCHNL_VERSION_MAJOR;
187 version.minor = VIRTCHNL_VERSION_MINOR;
188 err = ice_dcf_send_cmd_req_no_irq(hw, VIRTCHNL_OP_VERSION,
189 (uint8_t *)&version, sizeof(version));
191 PMD_INIT_LOG(ERR, "Failed to send OP_VERSION");
195 pver = &hw->virtchnl_version;
196 err = ice_dcf_recv_cmd_rsp_no_irq(hw, VIRTCHNL_OP_VERSION,
197 (uint8_t *)pver, sizeof(*pver), NULL);
199 PMD_INIT_LOG(ERR, "Failed to get response of OP_VERSION");
204 "Peer PF API version: %u.%u", pver->major, pver->minor);
206 if (pver->major < ICE_CPF_VIRTCHNL_VERSION_MAJOR_START ||
207 (pver->major == ICE_CPF_VIRTCHNL_VERSION_MAJOR_START &&
208 pver->minor < ICE_CPF_VIRTCHNL_VERSION_MINOR_START)) {
210 "VIRTCHNL API version should not be lower than (%u.%u)",
211 ICE_CPF_VIRTCHNL_VERSION_MAJOR_START,
212 ICE_CPF_VIRTCHNL_VERSION_MAJOR_START);
214 } else if (pver->major > VIRTCHNL_VERSION_MAJOR ||
215 (pver->major == VIRTCHNL_VERSION_MAJOR &&
216 pver->minor > VIRTCHNL_VERSION_MINOR)) {
218 "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
219 pver->major, pver->minor,
220 VIRTCHNL_VERSION_MAJOR, VIRTCHNL_VERSION_MINOR);
224 PMD_INIT_LOG(DEBUG, "Peer is supported PF host");
230 ice_dcf_get_vf_resource(struct ice_dcf_hw *hw)
235 caps = VIRTCHNL_VF_OFFLOAD_WB_ON_ITR | VIRTCHNL_VF_OFFLOAD_RX_POLLING |
236 VIRTCHNL_VF_CAP_ADV_LINK_SPEED | VIRTCHNL_VF_CAP_DCF |
237 VIRTCHNL_VF_OFFLOAD_VLAN_V2 |
238 VF_BASE_MODE_OFFLOADS | VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC;
240 err = ice_dcf_send_cmd_req_no_irq(hw, VIRTCHNL_OP_GET_VF_RESOURCES,
241 (uint8_t *)&caps, sizeof(caps));
243 PMD_DRV_LOG(ERR, "Failed to send msg OP_GET_VF_RESOURCE");
247 err = ice_dcf_recv_cmd_rsp_no_irq(hw, VIRTCHNL_OP_GET_VF_RESOURCES,
248 (uint8_t *)hw->vf_res,
249 ICE_DCF_VF_RES_BUF_SZ, NULL);
251 PMD_DRV_LOG(ERR, "Failed to get response of OP_GET_VF_RESOURCE");
255 iavf_vf_parse_hw_config(&hw->avf, hw->vf_res);
258 for (i = 0; i < hw->vf_res->num_vsis; i++) {
259 if (hw->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
260 hw->vsi_res = &hw->vf_res->vsi_res[i];
264 PMD_DRV_LOG(ERR, "no LAN VSI found");
268 hw->vsi_id = hw->vsi_res->vsi_id;
269 PMD_DRV_LOG(DEBUG, "VSI ID is %u", hw->vsi_id);
275 ice_dcf_get_vf_vsi_map(struct ice_dcf_hw *hw)
277 struct virtchnl_dcf_vsi_map *vsi_map;
278 uint32_t valid_msg_len;
282 err = ice_dcf_send_cmd_req_no_irq(hw, VIRTCHNL_OP_DCF_GET_VSI_MAP,
285 PMD_DRV_LOG(ERR, "Failed to send msg OP_DCF_GET_VSI_MAP");
289 err = ice_dcf_recv_cmd_rsp_no_irq(hw, VIRTCHNL_OP_DCF_GET_VSI_MAP,
290 hw->arq_buf, ICE_DCF_AQ_BUF_SZ,
293 PMD_DRV_LOG(ERR, "Failed to get response of OP_DCF_GET_VSI_MAP");
297 vsi_map = (struct virtchnl_dcf_vsi_map *)hw->arq_buf;
298 valid_msg_len = (vsi_map->num_vfs - 1) * sizeof(vsi_map->vf_vsi[0]) +
300 if (len != valid_msg_len) {
301 PMD_DRV_LOG(ERR, "invalid vf vsi map response with length %u",
306 if (hw->num_vfs != 0 && hw->num_vfs != vsi_map->num_vfs) {
307 PMD_DRV_LOG(ERR, "The number VSI map (%u) doesn't match the number of VFs (%u)",
308 vsi_map->num_vfs, hw->num_vfs);
312 len = vsi_map->num_vfs * sizeof(vsi_map->vf_vsi[0]);
314 if (!hw->vf_vsi_map) {
315 hw->vf_vsi_map = rte_zmalloc("vf_vsi_ctx", len, 0);
316 if (!hw->vf_vsi_map) {
317 PMD_DRV_LOG(ERR, "Failed to alloc memory for VSI context");
321 hw->num_vfs = vsi_map->num_vfs;
322 hw->pf_vsi_id = vsi_map->pf_vsi;
325 if (!memcmp(hw->vf_vsi_map, vsi_map->vf_vsi, len)) {
326 PMD_DRV_LOG(DEBUG, "VF VSI map doesn't change");
330 rte_memcpy(hw->vf_vsi_map, vsi_map->vf_vsi, len);
335 ice_dcf_mode_disable(struct ice_dcf_hw *hw)
339 err = ice_dcf_send_cmd_req_no_irq(hw, VIRTCHNL_OP_DCF_DISABLE,
342 PMD_DRV_LOG(ERR, "Failed to send msg OP_DCF_DISABLE");
346 err = ice_dcf_recv_cmd_rsp_no_irq(hw, VIRTCHNL_OP_DCF_DISABLE,
347 hw->arq_buf, ICE_DCF_AQ_BUF_SZ, NULL);
350 "Failed to get response of OP_DCF_DISABLE %d",
359 ice_dcf_check_reset_done(struct ice_dcf_hw *hw)
361 #define ICE_DCF_RESET_WAIT_CNT 50
362 struct iavf_hw *avf = &hw->avf;
365 for (i = 0; i < ICE_DCF_RESET_WAIT_CNT; i++) {
366 reset = IAVF_READ_REG(avf, IAVF_VFGEN_RSTAT) &
367 IAVF_VFGEN_RSTAT_VFR_STATE_MASK;
368 reset = reset >> IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT;
370 if (reset == VIRTCHNL_VFR_VFACTIVE ||
371 reset == VIRTCHNL_VFR_COMPLETED)
377 if (i >= ICE_DCF_RESET_WAIT_CNT)
384 ice_dcf_enable_irq0(struct ice_dcf_hw *hw)
386 struct iavf_hw *avf = &hw->avf;
388 /* Enable admin queue interrupt trigger */
389 IAVF_WRITE_REG(avf, IAVF_VFINT_ICR0_ENA1,
390 IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK);
391 IAVF_WRITE_REG(avf, IAVF_VFINT_DYN_CTL01,
392 IAVF_VFINT_DYN_CTL01_INTENA_MASK |
393 IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK |
394 IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK);
396 IAVF_WRITE_FLUSH(avf);
400 ice_dcf_disable_irq0(struct ice_dcf_hw *hw)
402 struct iavf_hw *avf = &hw->avf;
404 /* Disable all interrupt types */
405 IAVF_WRITE_REG(avf, IAVF_VFINT_ICR0_ENA1, 0);
406 IAVF_WRITE_REG(avf, IAVF_VFINT_DYN_CTL01,
407 IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK);
409 IAVF_WRITE_FLUSH(avf);
413 ice_dcf_dev_interrupt_handler(void *param)
415 struct ice_dcf_hw *hw = param;
417 ice_dcf_disable_irq0(hw);
419 ice_dcf_handle_virtchnl_msg(hw);
421 ice_dcf_enable_irq0(hw);
425 ice_dcf_execute_virtchnl_cmd(struct ice_dcf_hw *hw,
426 struct dcf_virtchnl_cmd *cmd)
431 if ((cmd->req_msg && !cmd->req_msglen) ||
432 (!cmd->req_msg && cmd->req_msglen) ||
433 (cmd->rsp_msgbuf && !cmd->rsp_buflen) ||
434 (!cmd->rsp_msgbuf && cmd->rsp_buflen))
437 rte_spinlock_lock(&hw->vc_cmd_send_lock);
438 ice_dcf_vc_cmd_set(hw, cmd);
440 err = ice_dcf_vc_cmd_send(hw, cmd);
442 PMD_DRV_LOG(ERR, "fail to send cmd %d", cmd->v_op);
450 rte_delay_ms(ICE_DCF_ARQ_CHECK_TIME);
451 } while (i++ < ICE_DCF_ARQ_MAX_RETRIES);
453 if (cmd->v_ret != IAVF_SUCCESS) {
456 "No response (%d times) or return failure (%d) for cmd %d",
457 i, cmd->v_ret, cmd->v_op);
461 ice_dcf_aq_cmd_clear(hw, cmd);
462 rte_spinlock_unlock(&hw->vc_cmd_send_lock);
467 ice_dcf_send_aq_cmd(void *dcf_hw, struct ice_aq_desc *desc,
468 void *buf, uint16_t buf_size)
470 struct dcf_virtchnl_cmd desc_cmd, buff_cmd;
471 struct ice_dcf_hw *hw = dcf_hw;
475 if ((buf && !buf_size) || (!buf && buf_size) ||
476 buf_size > ICE_DCF_AQ_BUF_SZ)
479 desc_cmd.v_op = VIRTCHNL_OP_DCF_CMD_DESC;
480 desc_cmd.req_msglen = sizeof(*desc);
481 desc_cmd.req_msg = (uint8_t *)desc;
482 desc_cmd.rsp_buflen = sizeof(*desc);
483 desc_cmd.rsp_msgbuf = (uint8_t *)desc;
486 return ice_dcf_execute_virtchnl_cmd(hw, &desc_cmd);
488 desc->flags |= rte_cpu_to_le_16(ICE_AQ_FLAG_BUF);
490 buff_cmd.v_op = VIRTCHNL_OP_DCF_CMD_BUFF;
491 buff_cmd.req_msglen = buf_size;
492 buff_cmd.req_msg = buf;
493 buff_cmd.rsp_buflen = buf_size;
494 buff_cmd.rsp_msgbuf = buf;
496 rte_spinlock_lock(&hw->vc_cmd_send_lock);
497 ice_dcf_vc_cmd_set(hw, &desc_cmd);
498 ice_dcf_vc_cmd_set(hw, &buff_cmd);
500 if (ice_dcf_vc_cmd_send(hw, &desc_cmd) ||
501 ice_dcf_vc_cmd_send(hw, &buff_cmd)) {
503 PMD_DRV_LOG(ERR, "fail to send OP_DCF_CMD_DESC/BUFF");
508 if (!desc_cmd.pending && !buff_cmd.pending)
511 rte_delay_ms(ICE_DCF_ARQ_CHECK_TIME);
512 } while (i++ < ICE_DCF_ARQ_MAX_RETRIES);
514 if (desc_cmd.v_ret != IAVF_SUCCESS || buff_cmd.v_ret != IAVF_SUCCESS) {
517 "No response (%d times) or return failure (desc: %d / buff: %d)",
518 i, desc_cmd.v_ret, buff_cmd.v_ret);
522 ice_dcf_aq_cmd_clear(hw, &desc_cmd);
523 ice_dcf_aq_cmd_clear(hw, &buff_cmd);
524 rte_spinlock_unlock(&hw->vc_cmd_send_lock);
530 ice_dcf_handle_vsi_update_event(struct ice_dcf_hw *hw)
532 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(hw->eth_dev);
535 rte_spinlock_lock(&hw->vc_cmd_send_lock);
537 rte_intr_disable(&pci_dev->intr_handle);
538 ice_dcf_disable_irq0(hw);
540 if (ice_dcf_get_vf_resource(hw) || ice_dcf_get_vf_vsi_map(hw) < 0)
543 rte_intr_enable(&pci_dev->intr_handle);
544 ice_dcf_enable_irq0(hw);
546 rte_spinlock_unlock(&hw->vc_cmd_send_lock);
552 ice_dcf_get_supported_rxdid(struct ice_dcf_hw *hw)
556 err = ice_dcf_send_cmd_req_no_irq(hw,
557 VIRTCHNL_OP_GET_SUPPORTED_RXDIDS,
560 PMD_INIT_LOG(ERR, "Failed to send OP_GET_SUPPORTED_RXDIDS");
564 err = ice_dcf_recv_cmd_rsp_no_irq(hw, VIRTCHNL_OP_GET_SUPPORTED_RXDIDS,
565 (uint8_t *)&hw->supported_rxdid,
566 sizeof(uint64_t), NULL);
568 PMD_INIT_LOG(ERR, "Failed to get response of OP_GET_SUPPORTED_RXDIDS");
576 ice_dcf_init_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw)
578 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
581 hw->avf.hw_addr = pci_dev->mem_resource[0].addr;
584 hw->avf.bus.bus_id = pci_dev->addr.bus;
585 hw->avf.bus.device = pci_dev->addr.devid;
586 hw->avf.bus.func = pci_dev->addr.function;
588 hw->avf.device_id = pci_dev->id.device_id;
589 hw->avf.vendor_id = pci_dev->id.vendor_id;
590 hw->avf.subsystem_device_id = pci_dev->id.subsystem_device_id;
591 hw->avf.subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
593 hw->avf.aq.num_arq_entries = ICE_DCF_AQ_LEN;
594 hw->avf.aq.num_asq_entries = ICE_DCF_AQ_LEN;
595 hw->avf.aq.arq_buf_size = ICE_DCF_AQ_BUF_SZ;
596 hw->avf.aq.asq_buf_size = ICE_DCF_AQ_BUF_SZ;
598 rte_spinlock_init(&hw->vc_cmd_send_lock);
599 rte_spinlock_init(&hw->vc_cmd_queue_lock);
600 TAILQ_INIT(&hw->vc_cmd_queue);
602 hw->arq_buf = rte_zmalloc("arq_buf", ICE_DCF_AQ_BUF_SZ, 0);
603 if (hw->arq_buf == NULL) {
604 PMD_INIT_LOG(ERR, "unable to allocate AdminQ buffer memory");
608 ret = iavf_set_mac_type(&hw->avf);
610 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", ret);
614 ret = ice_dcf_check_reset_done(hw);
616 PMD_INIT_LOG(ERR, "VF is still resetting");
620 ret = iavf_init_adminq(&hw->avf);
622 PMD_INIT_LOG(ERR, "init_adminq failed: %d", ret);
626 if (ice_dcf_init_check_api_version(hw)) {
627 PMD_INIT_LOG(ERR, "check_api version failed");
631 hw->vf_res = rte_zmalloc("vf_res", ICE_DCF_VF_RES_BUF_SZ, 0);
632 if (hw->vf_res == NULL) {
633 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
637 if (ice_dcf_get_vf_resource(hw)) {
638 PMD_INIT_LOG(ERR, "Failed to get VF resource");
642 if (ice_dcf_get_vf_vsi_map(hw) < 0) {
643 PMD_INIT_LOG(ERR, "Failed to get VF VSI map");
644 ice_dcf_mode_disable(hw);
648 /* Allocate memory for RSS info */
649 if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF) {
650 hw->rss_key = rte_zmalloc(NULL,
651 hw->vf_res->rss_key_size, 0);
653 PMD_INIT_LOG(ERR, "unable to allocate rss_key memory");
656 hw->rss_lut = rte_zmalloc("rss_lut",
657 hw->vf_res->rss_lut_size, 0);
659 PMD_INIT_LOG(ERR, "unable to allocate rss_lut memory");
664 if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
665 if (ice_dcf_get_supported_rxdid(hw) != 0) {
666 PMD_INIT_LOG(ERR, "failed to do get supported rxdid");
671 hw->eth_dev = eth_dev;
672 rte_intr_callback_register(&pci_dev->intr_handle,
673 ice_dcf_dev_interrupt_handler, hw);
674 rte_intr_enable(&pci_dev->intr_handle);
675 ice_dcf_enable_irq0(hw);
680 rte_free(hw->rss_key);
681 rte_free(hw->rss_lut);
683 rte_free(hw->vf_res);
685 iavf_shutdown_adminq(&hw->avf);
687 rte_free(hw->arq_buf);
693 ice_dcf_uninit_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw)
695 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
696 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
698 ice_dcf_disable_irq0(hw);
699 rte_intr_disable(intr_handle);
700 rte_intr_callback_unregister(intr_handle,
701 ice_dcf_dev_interrupt_handler, hw);
703 ice_dcf_mode_disable(hw);
704 iavf_shutdown_adminq(&hw->avf);
706 rte_free(hw->arq_buf);
707 rte_free(hw->vf_vsi_map);
708 rte_free(hw->vf_res);
709 rte_free(hw->rss_lut);
710 rte_free(hw->rss_key);
714 ice_dcf_configure_rss_key(struct ice_dcf_hw *hw)
716 struct virtchnl_rss_key *rss_key;
717 struct dcf_virtchnl_cmd args;
720 len = sizeof(*rss_key) + hw->vf_res->rss_key_size - 1;
721 rss_key = rte_zmalloc("rss_key", len, 0);
725 rss_key->vsi_id = hw->vsi_res->vsi_id;
726 rss_key->key_len = hw->vf_res->rss_key_size;
727 rte_memcpy(rss_key->key, hw->rss_key, hw->vf_res->rss_key_size);
729 args.v_op = VIRTCHNL_OP_CONFIG_RSS_KEY;
730 args.req_msglen = len;
731 args.req_msg = (uint8_t *)rss_key;
734 args.rsp_msgbuf = NULL;
737 err = ice_dcf_execute_virtchnl_cmd(hw, &args);
739 PMD_INIT_LOG(ERR, "Failed to execute OP_CONFIG_RSS_KEY");
746 ice_dcf_configure_rss_lut(struct ice_dcf_hw *hw)
748 struct virtchnl_rss_lut *rss_lut;
749 struct dcf_virtchnl_cmd args;
752 len = sizeof(*rss_lut) + hw->vf_res->rss_lut_size - 1;
753 rss_lut = rte_zmalloc("rss_lut", len, 0);
757 rss_lut->vsi_id = hw->vsi_res->vsi_id;
758 rss_lut->lut_entries = hw->vf_res->rss_lut_size;
759 rte_memcpy(rss_lut->lut, hw->rss_lut, hw->vf_res->rss_lut_size);
761 args.v_op = VIRTCHNL_OP_CONFIG_RSS_LUT;
762 args.req_msglen = len;
763 args.req_msg = (uint8_t *)rss_lut;
766 args.rsp_msgbuf = NULL;
769 err = ice_dcf_execute_virtchnl_cmd(hw, &args);
771 PMD_INIT_LOG(ERR, "Failed to execute OP_CONFIG_RSS_LUT");
778 ice_dcf_init_rss(struct ice_dcf_hw *hw)
780 struct rte_eth_dev *dev = hw->eth_dev;
781 struct rte_eth_rss_conf *rss_conf;
785 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
786 nb_q = dev->data->nb_rx_queues;
788 if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) {
789 PMD_DRV_LOG(DEBUG, "RSS is not supported");
792 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
793 PMD_DRV_LOG(WARNING, "RSS is enabled by PF by default");
794 /* set all lut items to default queue */
795 memset(hw->rss_lut, 0, hw->vf_res->rss_lut_size);
796 return ice_dcf_configure_rss_lut(hw);
799 /* In IAVF, RSS enablement is set by PF driver. It is not supported
800 * to set based on rss_conf->rss_hf.
803 /* configure RSS key */
804 if (!rss_conf->rss_key)
805 /* Calculate the default hash key */
806 for (i = 0; i < hw->vf_res->rss_key_size; i++)
807 hw->rss_key[i] = (uint8_t)rte_rand();
809 rte_memcpy(hw->rss_key, rss_conf->rss_key,
810 RTE_MIN(rss_conf->rss_key_len,
811 hw->vf_res->rss_key_size));
813 /* init RSS LUT table */
814 for (i = 0, j = 0; i < hw->vf_res->rss_lut_size; i++, j++) {
819 /* send virtchnnl ops to configure rss*/
820 ret = ice_dcf_configure_rss_lut(hw);
823 ret = ice_dcf_configure_rss_key(hw);
830 #define IAVF_RXDID_LEGACY_0 0
831 #define IAVF_RXDID_LEGACY_1 1
832 #define IAVF_RXDID_COMMS_GENERIC 16
835 ice_dcf_configure_queues(struct ice_dcf_hw *hw)
837 struct ice_rx_queue **rxq =
838 (struct ice_rx_queue **)hw->eth_dev->data->rx_queues;
839 struct ice_tx_queue **txq =
840 (struct ice_tx_queue **)hw->eth_dev->data->tx_queues;
841 struct virtchnl_vsi_queue_config_info *vc_config;
842 struct virtchnl_queue_pair_info *vc_qp;
843 struct dcf_virtchnl_cmd args;
847 size = sizeof(*vc_config) +
848 sizeof(vc_config->qpair[0]) * hw->num_queue_pairs;
849 vc_config = rte_zmalloc("cfg_queue", size, 0);
853 vc_config->vsi_id = hw->vsi_res->vsi_id;
854 vc_config->num_queue_pairs = hw->num_queue_pairs;
856 for (i = 0, vc_qp = vc_config->qpair;
857 i < hw->num_queue_pairs;
859 vc_qp->txq.vsi_id = hw->vsi_res->vsi_id;
860 vc_qp->txq.queue_id = i;
861 if (i < hw->eth_dev->data->nb_tx_queues) {
862 vc_qp->txq.ring_len = txq[i]->nb_tx_desc;
863 vc_qp->txq.dma_ring_addr = txq[i]->tx_ring_dma;
865 vc_qp->rxq.vsi_id = hw->vsi_res->vsi_id;
866 vc_qp->rxq.queue_id = i;
867 vc_qp->rxq.max_pkt_size = rxq[i]->max_pkt_len;
869 if (i >= hw->eth_dev->data->nb_rx_queues)
872 vc_qp->rxq.ring_len = rxq[i]->nb_rx_desc;
873 vc_qp->rxq.dma_ring_addr = rxq[i]->rx_ring_dma;
874 vc_qp->rxq.databuffer_size = rxq[i]->rx_buf_len;
876 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
877 if (hw->vf_res->vf_cap_flags &
878 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC &&
879 hw->supported_rxdid &
880 BIT(IAVF_RXDID_COMMS_GENERIC)) {
881 vc_qp->rxq.rxdid = IAVF_RXDID_COMMS_GENERIC;
882 PMD_DRV_LOG(NOTICE, "request RXDID == %d in "
883 "Queue[%d]", vc_qp->rxq.rxdid, i);
885 PMD_DRV_LOG(ERR, "RXDID 16 is not supported");
889 if (hw->vf_res->vf_cap_flags &
890 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC &&
891 hw->supported_rxdid &
892 BIT(IAVF_RXDID_LEGACY_0)) {
893 vc_qp->rxq.rxdid = IAVF_RXDID_LEGACY_0;
894 PMD_DRV_LOG(NOTICE, "request RXDID == %d in "
895 "Queue[%d]", vc_qp->rxq.rxdid, i);
897 PMD_DRV_LOG(ERR, "RXDID == 0 is not supported");
901 ice_select_rxd_to_pkt_fields_handler(rxq[i], vc_qp->rxq.rxdid);
904 memset(&args, 0, sizeof(args));
905 args.v_op = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
906 args.req_msg = (uint8_t *)vc_config;
907 args.req_msglen = size;
909 err = ice_dcf_execute_virtchnl_cmd(hw, &args);
911 PMD_DRV_LOG(ERR, "Failed to execute command of"
912 " VIRTCHNL_OP_CONFIG_VSI_QUEUES");
919 ice_dcf_config_irq_map(struct ice_dcf_hw *hw)
921 struct virtchnl_irq_map_info *map_info;
922 struct virtchnl_vector_map *vecmap;
923 struct dcf_virtchnl_cmd args;
926 len = sizeof(struct virtchnl_irq_map_info) +
927 sizeof(struct virtchnl_vector_map) * hw->nb_msix;
929 map_info = rte_zmalloc("map_info", len, 0);
933 map_info->num_vectors = hw->nb_msix;
934 for (i = 0; i < hw->nb_msix; i++) {
935 vecmap = &map_info->vecmap[i];
936 vecmap->vsi_id = hw->vsi_res->vsi_id;
937 vecmap->rxitr_idx = 0;
938 vecmap->vector_id = hw->msix_base + i;
940 vecmap->rxq_map = hw->rxq_map[hw->msix_base + i];
943 memset(&args, 0, sizeof(args));
944 args.v_op = VIRTCHNL_OP_CONFIG_IRQ_MAP;
945 args.req_msg = (u8 *)map_info;
946 args.req_msglen = len;
948 err = ice_dcf_execute_virtchnl_cmd(hw, &args);
950 PMD_DRV_LOG(ERR, "fail to execute command OP_CONFIG_IRQ_MAP");
957 ice_dcf_switch_queue(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on)
959 struct virtchnl_queue_select queue_select;
960 struct dcf_virtchnl_cmd args;
963 memset(&queue_select, 0, sizeof(queue_select));
964 queue_select.vsi_id = hw->vsi_res->vsi_id;
966 queue_select.rx_queues |= 1 << qid;
968 queue_select.tx_queues |= 1 << qid;
970 memset(&args, 0, sizeof(args));
972 args.v_op = VIRTCHNL_OP_ENABLE_QUEUES;
974 args.v_op = VIRTCHNL_OP_DISABLE_QUEUES;
976 args.req_msg = (u8 *)&queue_select;
977 args.req_msglen = sizeof(queue_select);
979 err = ice_dcf_execute_virtchnl_cmd(hw, &args);
981 PMD_DRV_LOG(ERR, "Failed to execute command of %s",
982 on ? "OP_ENABLE_QUEUES" : "OP_DISABLE_QUEUES");
988 ice_dcf_disable_queues(struct ice_dcf_hw *hw)
990 struct virtchnl_queue_select queue_select;
991 struct dcf_virtchnl_cmd args;
994 memset(&queue_select, 0, sizeof(queue_select));
995 queue_select.vsi_id = hw->vsi_res->vsi_id;
997 queue_select.rx_queues = BIT(hw->eth_dev->data->nb_rx_queues) - 1;
998 queue_select.tx_queues = BIT(hw->eth_dev->data->nb_tx_queues) - 1;
1000 memset(&args, 0, sizeof(args));
1001 args.v_op = VIRTCHNL_OP_DISABLE_QUEUES;
1002 args.req_msg = (u8 *)&queue_select;
1003 args.req_msglen = sizeof(queue_select);
1005 err = ice_dcf_execute_virtchnl_cmd(hw, &args);
1008 "Failed to execute command of OP_DISABLE_QUEUES");
1014 ice_dcf_query_stats(struct ice_dcf_hw *hw,
1015 struct virtchnl_eth_stats *pstats)
1017 struct virtchnl_queue_select q_stats;
1018 struct dcf_virtchnl_cmd args;
1021 memset(&q_stats, 0, sizeof(q_stats));
1022 q_stats.vsi_id = hw->vsi_res->vsi_id;
1024 args.v_op = VIRTCHNL_OP_GET_STATS;
1025 args.req_msg = (uint8_t *)&q_stats;
1026 args.req_msglen = sizeof(q_stats);
1027 args.rsp_msglen = sizeof(*pstats);
1028 args.rsp_msgbuf = (uint8_t *)pstats;
1029 args.rsp_buflen = sizeof(*pstats);
1031 err = ice_dcf_execute_virtchnl_cmd(hw, &args);
1033 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
1041 ice_dcf_add_del_all_mac_addr(struct ice_dcf_hw *hw, bool add)
1043 struct virtchnl_ether_addr_list *list;
1044 struct rte_ether_addr *addr;
1045 struct dcf_virtchnl_cmd args;
1048 len = sizeof(struct virtchnl_ether_addr_list);
1049 addr = hw->eth_dev->data->mac_addrs;
1050 len += sizeof(struct virtchnl_ether_addr);
1052 list = rte_zmalloc(NULL, len, 0);
1054 PMD_DRV_LOG(ERR, "fail to allocate memory");
1058 rte_memcpy(list->list[0].addr, addr->addr_bytes,
1059 sizeof(addr->addr_bytes));
1060 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1061 addr->addr_bytes[0], addr->addr_bytes[1],
1062 addr->addr_bytes[2], addr->addr_bytes[3],
1063 addr->addr_bytes[4], addr->addr_bytes[5]);
1065 list->vsi_id = hw->vsi_res->vsi_id;
1066 list->num_elements = 1;
1068 memset(&args, 0, sizeof(args));
1069 args.v_op = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1070 VIRTCHNL_OP_DEL_ETH_ADDR;
1071 args.req_msg = (uint8_t *)list;
1072 args.req_msglen = len;
1073 err = ice_dcf_execute_virtchnl_cmd(hw, &args);
1075 PMD_DRV_LOG(ERR, "fail to execute command %s",
1076 add ? "OP_ADD_ETHER_ADDRESS" :
1077 "OP_DEL_ETHER_ADDRESS");