1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
11 #include <rte_interrupts.h>
12 #include <rte_debug.h>
14 #include <rte_atomic.h>
16 #include <rte_ether.h>
17 #include <rte_ethdev_pci.h>
18 #include <rte_kvargs.h>
19 #include <rte_malloc.h>
20 #include <rte_memzone.h>
23 #include <iavf_devids.h>
25 #include "ice_generic_flow.h"
26 #include "ice_dcf_ethdev.h"
30 ice_dcf_recv_pkts(__rte_unused void *rx_queue,
31 __rte_unused struct rte_mbuf **bufs,
32 __rte_unused uint16_t nb_pkts)
38 ice_dcf_xmit_pkts(__rte_unused void *tx_queue,
39 __rte_unused struct rte_mbuf **bufs,
40 __rte_unused uint16_t nb_pkts)
46 ice_dcf_init_rxq(struct rte_eth_dev *dev, struct ice_rx_queue *rxq)
48 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
49 struct rte_eth_dev_data *dev_data = dev->data;
50 struct iavf_hw *hw = &dcf_ad->real_hw.avf;
51 uint16_t buf_size, max_pkt_len, len;
53 buf_size = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
55 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
56 len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
57 max_pkt_len = RTE_MIN(len, dev->data->dev_conf.rxmode.max_rx_pkt_len);
59 /* Check if the jumbo frame and maximum packet length are set
62 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
63 if (max_pkt_len <= RTE_ETHER_MAX_LEN ||
64 max_pkt_len > ICE_FRAME_SIZE_MAX) {
65 PMD_DRV_LOG(ERR, "maximum packet length must be "
66 "larger than %u and smaller than %u, "
67 "as jumbo frame is enabled",
68 (uint32_t)RTE_ETHER_MAX_LEN,
69 (uint32_t)ICE_FRAME_SIZE_MAX);
73 if (max_pkt_len < RTE_ETHER_MIN_LEN ||
74 max_pkt_len > RTE_ETHER_MAX_LEN) {
75 PMD_DRV_LOG(ERR, "maximum packet length must be "
76 "larger than %u and smaller than %u, "
77 "as jumbo frame is disabled",
78 (uint32_t)RTE_ETHER_MIN_LEN,
79 (uint32_t)RTE_ETHER_MAX_LEN);
84 rxq->max_pkt_len = max_pkt_len;
85 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
86 (rxq->max_pkt_len + 2 * ICE_VLAN_TAG_SIZE) > buf_size) {
87 dev_data->scattered_rx = 1;
89 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
90 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
97 ice_dcf_init_rx_queues(struct rte_eth_dev *dev)
99 struct ice_rx_queue **rxq =
100 (struct ice_rx_queue **)dev->data->rx_queues;
103 for (i = 0; i < dev->data->nb_rx_queues; i++) {
104 if (!rxq[i] || !rxq[i]->q_set)
106 ret = ice_dcf_init_rxq(dev, rxq[i]);
111 ice_set_rx_function(dev);
112 ice_set_tx_function(dev);
117 #define IAVF_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
118 #define IAVF_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
120 #define IAVF_ITR_INDEX_DEFAULT 0
121 #define IAVF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
122 #define IAVF_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
124 static inline uint16_t
125 iavf_calc_itr_interval(int16_t interval)
127 if (interval < 0 || interval > IAVF_QUEUE_ITR_INTERVAL_MAX)
128 interval = IAVF_QUEUE_ITR_INTERVAL_DEFAULT;
130 /* Convert to hardware count, as writing each 1 represents 2 us */
135 ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev,
136 struct rte_intr_handle *intr_handle)
138 struct ice_dcf_adapter *adapter = dev->data->dev_private;
139 struct ice_dcf_hw *hw = &adapter->real_hw;
140 uint16_t interval, i;
143 if (rte_intr_cap_multiple(intr_handle) &&
144 dev->data->dev_conf.intr_conf.rxq) {
145 if (rte_intr_efd_enable(intr_handle, dev->data->nb_rx_queues))
149 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
150 intr_handle->intr_vec =
151 rte_zmalloc("intr_vec",
152 dev->data->nb_rx_queues * sizeof(int), 0);
153 if (!intr_handle->intr_vec) {
154 PMD_DRV_LOG(ERR, "Failed to allocate %d rx intr_vec",
155 dev->data->nb_rx_queues);
160 if (!dev->data->dev_conf.intr_conf.rxq ||
161 !rte_intr_dp_is_en(intr_handle)) {
162 /* Rx interrupt disabled, Map interrupt only for writeback */
164 if (hw->vf_res->vf_cap_flags &
165 VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) {
166 /* If WB_ON_ITR supports, enable it */
167 hw->msix_base = IAVF_RX_VEC_START;
168 IAVF_WRITE_REG(&hw->avf,
169 IAVF_VFINT_DYN_CTLN1(hw->msix_base - 1),
170 IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK |
171 IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);
173 /* If no WB_ON_ITR offload flags, need to set
174 * interrupt for descriptor write back.
176 hw->msix_base = IAVF_MISC_VEC_ID;
180 iavf_calc_itr_interval(IAVF_QUEUE_ITR_INTERVAL_MAX);
181 IAVF_WRITE_REG(&hw->avf, IAVF_VFINT_DYN_CTL01,
182 IAVF_VFINT_DYN_CTL01_INTENA_MASK |
183 (IAVF_ITR_INDEX_DEFAULT <<
184 IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
186 IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT));
188 IAVF_WRITE_FLUSH(&hw->avf);
189 /* map all queues to the same interrupt */
190 for (i = 0; i < dev->data->nb_rx_queues; i++)
191 hw->rxq_map[hw->msix_base] |= 1 << i;
193 if (!rte_intr_allow_others(intr_handle)) {
195 hw->msix_base = IAVF_MISC_VEC_ID;
196 for (i = 0; i < dev->data->nb_rx_queues; i++) {
197 hw->rxq_map[hw->msix_base] |= 1 << i;
198 intr_handle->intr_vec[i] = IAVF_MISC_VEC_ID;
201 "vector %u are mapping to all Rx queues",
204 /* If Rx interrupt is reuquired, and we can use
205 * multi interrupts, then the vec is from 1
207 hw->nb_msix = RTE_MIN(hw->vf_res->max_vectors,
208 intr_handle->nb_efd);
209 hw->msix_base = IAVF_MISC_VEC_ID;
210 vec = IAVF_MISC_VEC_ID;
211 for (i = 0; i < dev->data->nb_rx_queues; i++) {
212 hw->rxq_map[vec] |= 1 << i;
213 intr_handle->intr_vec[i] = vec++;
214 if (vec >= hw->nb_msix)
215 vec = IAVF_RX_VEC_START;
218 "%u vectors are mapping to %u Rx queues",
219 hw->nb_msix, dev->data->nb_rx_queues);
223 if (ice_dcf_config_irq_map(hw)) {
224 PMD_DRV_LOG(ERR, "config interrupt mapping failed");
231 alloc_rxq_mbufs(struct ice_rx_queue *rxq)
233 volatile union ice_32b_rx_flex_desc *rxd;
234 struct rte_mbuf *mbuf = NULL;
238 for (i = 0; i < rxq->nb_rx_desc; i++) {
239 mbuf = rte_mbuf_raw_alloc(rxq->mp);
240 if (unlikely(!mbuf)) {
241 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
245 rte_mbuf_refcnt_set(mbuf, 1);
247 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
249 mbuf->port = rxq->port_id;
252 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
254 rxd = &rxq->rx_ring[i];
255 rxd->read.pkt_addr = dma_addr;
256 rxd->read.hdr_addr = 0;
260 rxq->sw_ring[i].mbuf = (void *)mbuf;
267 ice_dcf_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
269 struct ice_dcf_adapter *ad = dev->data->dev_private;
270 struct iavf_hw *hw = &ad->real_hw.avf;
271 struct ice_rx_queue *rxq;
274 if (rx_queue_id >= dev->data->nb_rx_queues)
277 rxq = dev->data->rx_queues[rx_queue_id];
279 err = alloc_rxq_mbufs(rxq);
281 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
287 /* Init the RX tail register. */
288 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
289 IAVF_WRITE_FLUSH(hw);
291 /* Ready to switch the queue on */
292 err = ice_dcf_switch_queue(&ad->real_hw, rx_queue_id, true, true);
294 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
299 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
305 reset_rx_queue(struct ice_rx_queue *rxq)
313 len = rxq->nb_rx_desc + ICE_RX_MAX_BURST;
315 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
316 ((volatile char *)rxq->rx_ring)[i] = 0;
318 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
320 for (i = 0; i < ICE_RX_MAX_BURST; i++)
321 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
324 rxq->rx_nb_avail = 0;
325 rxq->rx_next_avail = 0;
326 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
330 rxq->pkt_first_seg = NULL;
331 rxq->pkt_last_seg = NULL;
335 reset_tx_queue(struct ice_tx_queue *txq)
337 struct ice_tx_entry *txe;
342 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
347 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
348 for (i = 0; i < size; i++)
349 ((volatile char *)txq->tx_ring)[i] = 0;
351 prev = (uint16_t)(txq->nb_tx_desc - 1);
352 for (i = 0; i < txq->nb_tx_desc; i++) {
353 txq->tx_ring[i].cmd_type_offset_bsz =
354 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
357 txe[prev].next_id = i;
364 txq->last_desc_cleaned = txq->nb_tx_desc - 1;
365 txq->nb_tx_free = txq->nb_tx_desc - 1;
367 txq->tx_next_dd = txq->tx_rs_thresh - 1;
368 txq->tx_next_rs = txq->tx_rs_thresh - 1;
372 ice_dcf_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
374 struct ice_dcf_adapter *ad = dev->data->dev_private;
375 struct ice_dcf_hw *hw = &ad->real_hw;
376 struct ice_rx_queue *rxq;
379 if (rx_queue_id >= dev->data->nb_rx_queues)
382 err = ice_dcf_switch_queue(hw, rx_queue_id, true, false);
384 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
389 rxq = dev->data->rx_queues[rx_queue_id];
390 rxq->rx_rel_mbufs(rxq);
392 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
398 ice_dcf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
400 struct ice_dcf_adapter *ad = dev->data->dev_private;
401 struct iavf_hw *hw = &ad->real_hw.avf;
402 struct ice_tx_queue *txq;
405 if (tx_queue_id >= dev->data->nb_tx_queues)
408 txq = dev->data->tx_queues[tx_queue_id];
410 /* Init the RX tail register. */
411 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(tx_queue_id);
412 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
413 IAVF_WRITE_FLUSH(hw);
415 /* Ready to switch the queue on */
416 err = ice_dcf_switch_queue(&ad->real_hw, tx_queue_id, false, true);
419 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
424 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
430 ice_dcf_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
432 struct ice_dcf_adapter *ad = dev->data->dev_private;
433 struct ice_dcf_hw *hw = &ad->real_hw;
434 struct ice_tx_queue *txq;
437 if (tx_queue_id >= dev->data->nb_tx_queues)
440 err = ice_dcf_switch_queue(hw, tx_queue_id, false, false);
442 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
447 txq = dev->data->tx_queues[tx_queue_id];
448 txq->tx_rel_mbufs(txq);
450 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
456 ice_dcf_start_queues(struct rte_eth_dev *dev)
458 struct ice_rx_queue *rxq;
459 struct ice_tx_queue *txq;
463 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
464 txq = dev->data->tx_queues[nb_txq];
465 if (txq->tx_deferred_start)
467 if (ice_dcf_tx_queue_start(dev, nb_txq) != 0) {
468 PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_txq);
473 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
474 rxq = dev->data->rx_queues[nb_rxq];
475 if (rxq->rx_deferred_start)
477 if (ice_dcf_rx_queue_start(dev, nb_rxq) != 0) {
478 PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_rxq);
485 /* stop the started queues if failed to start all queues */
487 for (i = 0; i < nb_rxq; i++)
488 ice_dcf_rx_queue_stop(dev, i);
490 for (i = 0; i < nb_txq; i++)
491 ice_dcf_tx_queue_stop(dev, i);
497 ice_dcf_dev_start(struct rte_eth_dev *dev)
499 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
500 struct rte_intr_handle *intr_handle = dev->intr_handle;
501 struct ice_adapter *ad = &dcf_ad->parent;
502 struct ice_dcf_hw *hw = &dcf_ad->real_hw;
505 ad->pf.adapter_stopped = 0;
507 hw->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
508 dev->data->nb_tx_queues);
510 ret = ice_dcf_init_rx_queues(dev);
512 PMD_DRV_LOG(ERR, "Fail to init queues");
516 if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF) {
517 ret = ice_dcf_init_rss(hw);
519 PMD_DRV_LOG(ERR, "Failed to configure RSS");
524 ret = ice_dcf_configure_queues(hw);
526 PMD_DRV_LOG(ERR, "Fail to config queues");
530 ret = ice_dcf_config_rx_queues_irqs(dev, intr_handle);
532 PMD_DRV_LOG(ERR, "Fail to config rx queues' irqs");
536 if (dev->data->dev_conf.intr_conf.rxq != 0) {
537 rte_intr_disable(intr_handle);
538 rte_intr_enable(intr_handle);
541 ret = ice_dcf_start_queues(dev);
543 PMD_DRV_LOG(ERR, "Failed to enable queues");
547 dev->data->dev_link.link_status = ETH_LINK_UP;
553 ice_dcf_stop_queues(struct rte_eth_dev *dev)
555 struct ice_dcf_adapter *ad = dev->data->dev_private;
556 struct ice_dcf_hw *hw = &ad->real_hw;
557 struct ice_rx_queue *rxq;
558 struct ice_tx_queue *txq;
561 /* Stop All queues */
562 ret = ice_dcf_disable_queues(hw);
564 PMD_DRV_LOG(WARNING, "Fail to stop queues");
566 for (i = 0; i < dev->data->nb_tx_queues; i++) {
567 txq = dev->data->tx_queues[i];
570 txq->tx_rel_mbufs(txq);
572 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
574 for (i = 0; i < dev->data->nb_rx_queues; i++) {
575 rxq = dev->data->rx_queues[i];
578 rxq->rx_rel_mbufs(rxq);
580 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
585 ice_dcf_dev_stop(struct rte_eth_dev *dev)
587 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
588 struct rte_intr_handle *intr_handle = dev->intr_handle;
589 struct ice_adapter *ad = &dcf_ad->parent;
591 if (ad->pf.adapter_stopped == 1) {
592 PMD_DRV_LOG(DEBUG, "Port is already stopped");
596 ice_dcf_stop_queues(dev);
598 rte_intr_efd_disable(intr_handle);
599 if (intr_handle->intr_vec) {
600 rte_free(intr_handle->intr_vec);
601 intr_handle->intr_vec = NULL;
604 dev->data->dev_link.link_status = ETH_LINK_DOWN;
605 ad->pf.adapter_stopped = 1;
609 ice_dcf_dev_configure(struct rte_eth_dev *dev)
611 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
612 struct ice_adapter *ad = &dcf_ad->parent;
614 ad->rx_bulk_alloc_allowed = true;
615 ad->tx_simple_allowed = true;
617 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
618 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
624 ice_dcf_dev_info_get(struct rte_eth_dev *dev,
625 struct rte_eth_dev_info *dev_info)
627 struct ice_dcf_adapter *adapter = dev->data->dev_private;
628 struct ice_dcf_hw *hw = &adapter->real_hw;
630 dev_info->max_mac_addrs = 1;
631 dev_info->max_rx_queues = hw->vsi_res->num_queue_pairs;
632 dev_info->max_tx_queues = hw->vsi_res->num_queue_pairs;
633 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
634 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
635 dev_info->hash_key_size = hw->vf_res->rss_key_size;
636 dev_info->reta_size = hw->vf_res->rss_lut_size;
637 dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL;
639 dev_info->rx_offload_capa =
640 DEV_RX_OFFLOAD_VLAN_STRIP |
641 DEV_RX_OFFLOAD_IPV4_CKSUM |
642 DEV_RX_OFFLOAD_UDP_CKSUM |
643 DEV_RX_OFFLOAD_TCP_CKSUM |
644 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
645 DEV_RX_OFFLOAD_SCATTER |
646 DEV_RX_OFFLOAD_JUMBO_FRAME |
647 DEV_RX_OFFLOAD_VLAN_FILTER |
648 DEV_RX_OFFLOAD_RSS_HASH;
649 dev_info->tx_offload_capa =
650 DEV_TX_OFFLOAD_VLAN_INSERT |
651 DEV_TX_OFFLOAD_IPV4_CKSUM |
652 DEV_TX_OFFLOAD_UDP_CKSUM |
653 DEV_TX_OFFLOAD_TCP_CKSUM |
654 DEV_TX_OFFLOAD_SCTP_CKSUM |
655 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
656 DEV_TX_OFFLOAD_TCP_TSO |
657 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
658 DEV_TX_OFFLOAD_GRE_TNL_TSO |
659 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
660 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
661 DEV_TX_OFFLOAD_MULTI_SEGS;
663 dev_info->default_rxconf = (struct rte_eth_rxconf) {
665 .pthresh = ICE_DEFAULT_RX_PTHRESH,
666 .hthresh = ICE_DEFAULT_RX_HTHRESH,
667 .wthresh = ICE_DEFAULT_RX_WTHRESH,
669 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
674 dev_info->default_txconf = (struct rte_eth_txconf) {
676 .pthresh = ICE_DEFAULT_TX_PTHRESH,
677 .hthresh = ICE_DEFAULT_TX_HTHRESH,
678 .wthresh = ICE_DEFAULT_TX_WTHRESH,
680 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
681 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
685 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
686 .nb_max = ICE_MAX_RING_DESC,
687 .nb_min = ICE_MIN_RING_DESC,
688 .nb_align = ICE_ALIGN_RING_DESC,
691 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
692 .nb_max = ICE_MAX_RING_DESC,
693 .nb_min = ICE_MIN_RING_DESC,
694 .nb_align = ICE_ALIGN_RING_DESC,
701 ice_dcf_dev_promiscuous_enable(__rte_unused struct rte_eth_dev *dev)
707 ice_dcf_dev_promiscuous_disable(__rte_unused struct rte_eth_dev *dev)
713 ice_dcf_dev_allmulticast_enable(__rte_unused struct rte_eth_dev *dev)
719 ice_dcf_dev_allmulticast_disable(__rte_unused struct rte_eth_dev *dev)
725 ice_dcf_dev_filter_ctrl(struct rte_eth_dev *dev,
726 enum rte_filter_type filter_type,
727 enum rte_filter_op filter_op,
735 switch (filter_type) {
736 case RTE_ETH_FILTER_GENERIC:
737 if (filter_op != RTE_ETH_FILTER_GET)
739 *(const void **)arg = &ice_flow_ops;
743 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
752 #define ICE_DCF_32_BIT_WIDTH (CHAR_BIT * 4)
753 #define ICE_DCF_48_BIT_WIDTH (CHAR_BIT * 6)
754 #define ICE_DCF_48_BIT_MASK RTE_LEN2MASK(ICE_DCF_48_BIT_WIDTH, uint64_t)
757 ice_dcf_stat_update_48(uint64_t *offset, uint64_t *stat)
759 if (*stat >= *offset)
760 *stat = *stat - *offset;
762 *stat = (uint64_t)((*stat +
763 ((uint64_t)1 << ICE_DCF_48_BIT_WIDTH)) - *offset);
765 *stat &= ICE_DCF_48_BIT_MASK;
769 ice_dcf_stat_update_32(uint64_t *offset, uint64_t *stat)
771 if (*stat >= *offset)
772 *stat = (uint64_t)(*stat - *offset);
774 *stat = (uint64_t)((*stat +
775 ((uint64_t)1 << ICE_DCF_32_BIT_WIDTH)) - *offset);
779 ice_dcf_update_stats(struct virtchnl_eth_stats *oes,
780 struct virtchnl_eth_stats *nes)
782 ice_dcf_stat_update_48(&oes->rx_bytes, &nes->rx_bytes);
783 ice_dcf_stat_update_48(&oes->rx_unicast, &nes->rx_unicast);
784 ice_dcf_stat_update_48(&oes->rx_multicast, &nes->rx_multicast);
785 ice_dcf_stat_update_48(&oes->rx_broadcast, &nes->rx_broadcast);
786 ice_dcf_stat_update_32(&oes->rx_discards, &nes->rx_discards);
787 ice_dcf_stat_update_48(&oes->tx_bytes, &nes->tx_bytes);
788 ice_dcf_stat_update_48(&oes->tx_unicast, &nes->tx_unicast);
789 ice_dcf_stat_update_48(&oes->tx_multicast, &nes->tx_multicast);
790 ice_dcf_stat_update_48(&oes->tx_broadcast, &nes->tx_broadcast);
791 ice_dcf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
792 ice_dcf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
797 ice_dcf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
799 struct ice_dcf_adapter *ad = dev->data->dev_private;
800 struct ice_dcf_hw *hw = &ad->real_hw;
801 struct virtchnl_eth_stats pstats;
804 ret = ice_dcf_query_stats(hw, &pstats);
806 ice_dcf_update_stats(&hw->eth_stats_offset, &pstats);
807 stats->ipackets = pstats.rx_unicast + pstats.rx_multicast +
808 pstats.rx_broadcast - pstats.rx_discards;
809 stats->opackets = pstats.tx_broadcast + pstats.tx_multicast +
811 stats->imissed = pstats.rx_discards;
812 stats->oerrors = pstats.tx_errors + pstats.tx_discards;
813 stats->ibytes = pstats.rx_bytes;
814 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN;
815 stats->obytes = pstats.tx_bytes;
817 PMD_DRV_LOG(ERR, "Get statistics failed");
823 ice_dcf_stats_reset(struct rte_eth_dev *dev)
825 struct ice_dcf_adapter *ad = dev->data->dev_private;
826 struct ice_dcf_hw *hw = &ad->real_hw;
827 struct virtchnl_eth_stats pstats;
830 /* read stat values to clear hardware registers */
831 ret = ice_dcf_query_stats(hw, &pstats);
835 /* set stats offset base on current values */
836 hw->eth_stats_offset = pstats;
842 ice_dcf_dev_close(struct rte_eth_dev *dev)
844 struct ice_dcf_adapter *adapter = dev->data->dev_private;
846 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
850 dev->rx_pkt_burst = NULL;
851 dev->tx_pkt_burst = NULL;
853 ice_dcf_uninit_parent_adapter(dev);
854 ice_dcf_uninit_hw(dev, &adapter->real_hw);
858 ice_dcf_link_update(__rte_unused struct rte_eth_dev *dev,
859 __rte_unused int wait_to_complete)
864 static const struct eth_dev_ops ice_dcf_eth_dev_ops = {
865 .dev_start = ice_dcf_dev_start,
866 .dev_stop = ice_dcf_dev_stop,
867 .dev_close = ice_dcf_dev_close,
868 .dev_configure = ice_dcf_dev_configure,
869 .dev_infos_get = ice_dcf_dev_info_get,
870 .rx_queue_setup = ice_rx_queue_setup,
871 .tx_queue_setup = ice_tx_queue_setup,
872 .rx_queue_release = ice_rx_queue_release,
873 .tx_queue_release = ice_tx_queue_release,
874 .rx_queue_start = ice_dcf_rx_queue_start,
875 .tx_queue_start = ice_dcf_tx_queue_start,
876 .rx_queue_stop = ice_dcf_rx_queue_stop,
877 .tx_queue_stop = ice_dcf_tx_queue_stop,
878 .link_update = ice_dcf_link_update,
879 .stats_get = ice_dcf_stats_get,
880 .stats_reset = ice_dcf_stats_reset,
881 .promiscuous_enable = ice_dcf_dev_promiscuous_enable,
882 .promiscuous_disable = ice_dcf_dev_promiscuous_disable,
883 .allmulticast_enable = ice_dcf_dev_allmulticast_enable,
884 .allmulticast_disable = ice_dcf_dev_allmulticast_disable,
885 .filter_ctrl = ice_dcf_dev_filter_ctrl,
889 ice_dcf_dev_init(struct rte_eth_dev *eth_dev)
891 struct ice_dcf_adapter *adapter = eth_dev->data->dev_private;
893 eth_dev->dev_ops = &ice_dcf_eth_dev_ops;
894 eth_dev->rx_pkt_burst = ice_dcf_recv_pkts;
895 eth_dev->tx_pkt_burst = ice_dcf_xmit_pkts;
897 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
900 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
902 adapter->real_hw.vc_event_msg_cb = ice_dcf_handle_pf_event_msg;
903 if (ice_dcf_init_hw(eth_dev, &adapter->real_hw) != 0) {
904 PMD_INIT_LOG(ERR, "Failed to init DCF hardware");
908 if (ice_dcf_init_parent_adapter(eth_dev) != 0) {
909 PMD_INIT_LOG(ERR, "Failed to init DCF parent adapter");
910 ice_dcf_uninit_hw(eth_dev, &adapter->real_hw);
918 ice_dcf_dev_uninit(struct rte_eth_dev *eth_dev)
920 ice_dcf_dev_close(eth_dev);
926 ice_dcf_cap_check_handler(__rte_unused const char *key,
927 const char *value, __rte_unused void *opaque)
929 if (strcmp(value, "dcf"))
936 ice_dcf_cap_selected(struct rte_devargs *devargs)
938 struct rte_kvargs *kvlist;
939 const char *key = "cap";
945 kvlist = rte_kvargs_parse(devargs->args, NULL);
949 if (!rte_kvargs_count(kvlist, key))
952 /* dcf capability selected when there's a key-value pair: cap=dcf */
953 if (rte_kvargs_process(kvlist, key,
954 ice_dcf_cap_check_handler, NULL) < 0)
960 rte_kvargs_free(kvlist);
964 static int eth_ice_dcf_pci_probe(__rte_unused struct rte_pci_driver *pci_drv,
965 struct rte_pci_device *pci_dev)
967 if (!ice_dcf_cap_selected(pci_dev->device.devargs))
970 return rte_eth_dev_pci_generic_probe(pci_dev,
971 sizeof(struct ice_dcf_adapter),
975 static int eth_ice_dcf_pci_remove(struct rte_pci_device *pci_dev)
977 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dcf_dev_uninit);
980 static const struct rte_pci_id pci_id_ice_dcf_map[] = {
981 { RTE_PCI_DEVICE(IAVF_INTEL_VENDOR_ID, IAVF_DEV_ID_ADAPTIVE_VF) },
982 { .vendor_id = 0, /* sentinel */ },
985 static struct rte_pci_driver rte_ice_dcf_pmd = {
986 .id_table = pci_id_ice_dcf_map,
987 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
988 .probe = eth_ice_dcf_pci_probe,
989 .remove = eth_ice_dcf_pci_remove,
992 RTE_PMD_REGISTER_PCI(net_ice_dcf, rte_ice_dcf_pmd);
993 RTE_PMD_REGISTER_PCI_TABLE(net_ice_dcf, pci_id_ice_dcf_map);
994 RTE_PMD_REGISTER_KMOD_DEP(net_ice_dcf, "* igb_uio | vfio-pci");
995 RTE_PMD_REGISTER_PARAM_STRING(net_ice_dcf, "cap=dcf");