1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
10 #include <rte_interrupts.h>
11 #include <rte_debug.h>
13 #include <rte_atomic.h>
15 #include <rte_ether.h>
16 #include <ethdev_pci.h>
17 #include <rte_kvargs.h>
18 #include <rte_malloc.h>
19 #include <rte_memzone.h>
22 #include <iavf_devids.h>
24 #include "ice_generic_flow.h"
25 #include "ice_dcf_ethdev.h"
29 ice_dcf_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
30 struct rte_eth_udp_tunnel *udp_tunnel);
32 ice_dcf_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
33 struct rte_eth_udp_tunnel *udp_tunnel);
36 ice_dcf_recv_pkts(__rte_unused void *rx_queue,
37 __rte_unused struct rte_mbuf **bufs,
38 __rte_unused uint16_t nb_pkts)
44 ice_dcf_xmit_pkts(__rte_unused void *tx_queue,
45 __rte_unused struct rte_mbuf **bufs,
46 __rte_unused uint16_t nb_pkts)
52 ice_dcf_init_rxq(struct rte_eth_dev *dev, struct ice_rx_queue *rxq)
54 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
55 struct rte_eth_dev_data *dev_data = dev->data;
56 struct iavf_hw *hw = &dcf_ad->real_hw.avf;
57 uint16_t buf_size, max_pkt_len, len;
59 buf_size = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
61 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
62 len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
63 max_pkt_len = RTE_MIN(len, dev->data->dev_conf.rxmode.max_rx_pkt_len);
65 /* Check if the jumbo frame and maximum packet length are set
68 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
69 if (max_pkt_len <= ICE_ETH_MAX_LEN ||
70 max_pkt_len > ICE_FRAME_SIZE_MAX) {
71 PMD_DRV_LOG(ERR, "maximum packet length must be "
72 "larger than %u and smaller than %u, "
73 "as jumbo frame is enabled",
74 (uint32_t)ICE_ETH_MAX_LEN,
75 (uint32_t)ICE_FRAME_SIZE_MAX);
79 if (max_pkt_len < RTE_ETHER_MIN_LEN ||
80 max_pkt_len > ICE_ETH_MAX_LEN) {
81 PMD_DRV_LOG(ERR, "maximum packet length must be "
82 "larger than %u and smaller than %u, "
83 "as jumbo frame is disabled",
84 (uint32_t)RTE_ETHER_MIN_LEN,
85 (uint32_t)ICE_ETH_MAX_LEN);
90 rxq->max_pkt_len = max_pkt_len;
91 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
92 (rxq->max_pkt_len + 2 * ICE_VLAN_TAG_SIZE) > buf_size) {
93 dev_data->scattered_rx = 1;
95 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
96 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
103 ice_dcf_init_rx_queues(struct rte_eth_dev *dev)
105 struct ice_rx_queue **rxq =
106 (struct ice_rx_queue **)dev->data->rx_queues;
109 for (i = 0; i < dev->data->nb_rx_queues; i++) {
110 if (!rxq[i] || !rxq[i]->q_set)
112 ret = ice_dcf_init_rxq(dev, rxq[i]);
117 ice_set_rx_function(dev);
118 ice_set_tx_function(dev);
123 #define IAVF_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
124 #define IAVF_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
126 #define IAVF_ITR_INDEX_DEFAULT 0
127 #define IAVF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
128 #define IAVF_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
130 static inline uint16_t
131 iavf_calc_itr_interval(int16_t interval)
133 if (interval < 0 || interval > IAVF_QUEUE_ITR_INTERVAL_MAX)
134 interval = IAVF_QUEUE_ITR_INTERVAL_DEFAULT;
136 /* Convert to hardware count, as writing each 1 represents 2 us */
141 ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev,
142 struct rte_intr_handle *intr_handle)
144 struct ice_dcf_adapter *adapter = dev->data->dev_private;
145 struct ice_dcf_hw *hw = &adapter->real_hw;
146 uint16_t interval, i;
149 if (rte_intr_cap_multiple(intr_handle) &&
150 dev->data->dev_conf.intr_conf.rxq) {
151 if (rte_intr_efd_enable(intr_handle, dev->data->nb_rx_queues))
155 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
156 intr_handle->intr_vec =
157 rte_zmalloc("intr_vec",
158 dev->data->nb_rx_queues * sizeof(int), 0);
159 if (!intr_handle->intr_vec) {
160 PMD_DRV_LOG(ERR, "Failed to allocate %d rx intr_vec",
161 dev->data->nb_rx_queues);
166 if (!dev->data->dev_conf.intr_conf.rxq ||
167 !rte_intr_dp_is_en(intr_handle)) {
168 /* Rx interrupt disabled, Map interrupt only for writeback */
170 if (hw->vf_res->vf_cap_flags &
171 VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) {
172 /* If WB_ON_ITR supports, enable it */
173 hw->msix_base = IAVF_RX_VEC_START;
174 IAVF_WRITE_REG(&hw->avf,
175 IAVF_VFINT_DYN_CTLN1(hw->msix_base - 1),
176 IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK |
177 IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);
179 /* If no WB_ON_ITR offload flags, need to set
180 * interrupt for descriptor write back.
182 hw->msix_base = IAVF_MISC_VEC_ID;
186 iavf_calc_itr_interval(IAVF_QUEUE_ITR_INTERVAL_MAX);
187 IAVF_WRITE_REG(&hw->avf, IAVF_VFINT_DYN_CTL01,
188 IAVF_VFINT_DYN_CTL01_INTENA_MASK |
189 (IAVF_ITR_INDEX_DEFAULT <<
190 IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
192 IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT));
194 IAVF_WRITE_FLUSH(&hw->avf);
195 /* map all queues to the same interrupt */
196 for (i = 0; i < dev->data->nb_rx_queues; i++)
197 hw->rxq_map[hw->msix_base] |= 1 << i;
199 if (!rte_intr_allow_others(intr_handle)) {
201 hw->msix_base = IAVF_MISC_VEC_ID;
202 for (i = 0; i < dev->data->nb_rx_queues; i++) {
203 hw->rxq_map[hw->msix_base] |= 1 << i;
204 intr_handle->intr_vec[i] = IAVF_MISC_VEC_ID;
207 "vector %u are mapping to all Rx queues",
210 /* If Rx interrupt is reuquired, and we can use
211 * multi interrupts, then the vec is from 1
213 hw->nb_msix = RTE_MIN(hw->vf_res->max_vectors,
214 intr_handle->nb_efd);
215 hw->msix_base = IAVF_MISC_VEC_ID;
216 vec = IAVF_MISC_VEC_ID;
217 for (i = 0; i < dev->data->nb_rx_queues; i++) {
218 hw->rxq_map[vec] |= 1 << i;
219 intr_handle->intr_vec[i] = vec++;
220 if (vec >= hw->nb_msix)
221 vec = IAVF_RX_VEC_START;
224 "%u vectors are mapping to %u Rx queues",
225 hw->nb_msix, dev->data->nb_rx_queues);
229 if (ice_dcf_config_irq_map(hw)) {
230 PMD_DRV_LOG(ERR, "config interrupt mapping failed");
237 alloc_rxq_mbufs(struct ice_rx_queue *rxq)
239 volatile union ice_rx_flex_desc *rxd;
240 struct rte_mbuf *mbuf = NULL;
244 for (i = 0; i < rxq->nb_rx_desc; i++) {
245 mbuf = rte_mbuf_raw_alloc(rxq->mp);
246 if (unlikely(!mbuf)) {
247 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
251 rte_mbuf_refcnt_set(mbuf, 1);
253 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
255 mbuf->port = rxq->port_id;
258 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
260 rxd = &rxq->rx_ring[i];
261 rxd->read.pkt_addr = dma_addr;
262 rxd->read.hdr_addr = 0;
263 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
268 rxq->sw_ring[i].mbuf = (void *)mbuf;
275 ice_dcf_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
277 struct ice_dcf_adapter *ad = dev->data->dev_private;
278 struct iavf_hw *hw = &ad->real_hw.avf;
279 struct ice_rx_queue *rxq;
282 if (rx_queue_id >= dev->data->nb_rx_queues)
285 rxq = dev->data->rx_queues[rx_queue_id];
287 err = alloc_rxq_mbufs(rxq);
289 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
295 /* Init the RX tail register. */
296 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
297 IAVF_WRITE_FLUSH(hw);
299 /* Ready to switch the queue on */
300 err = ice_dcf_switch_queue(&ad->real_hw, rx_queue_id, true, true);
302 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
307 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
313 reset_rx_queue(struct ice_rx_queue *rxq)
321 len = rxq->nb_rx_desc + ICE_RX_MAX_BURST;
323 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
324 ((volatile char *)rxq->rx_ring)[i] = 0;
326 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
328 for (i = 0; i < ICE_RX_MAX_BURST; i++)
329 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
332 rxq->rx_nb_avail = 0;
333 rxq->rx_next_avail = 0;
334 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
338 rxq->pkt_first_seg = NULL;
339 rxq->pkt_last_seg = NULL;
343 reset_tx_queue(struct ice_tx_queue *txq)
345 struct ice_tx_entry *txe;
350 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
355 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
356 for (i = 0; i < size; i++)
357 ((volatile char *)txq->tx_ring)[i] = 0;
359 prev = (uint16_t)(txq->nb_tx_desc - 1);
360 for (i = 0; i < txq->nb_tx_desc; i++) {
361 txq->tx_ring[i].cmd_type_offset_bsz =
362 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
365 txe[prev].next_id = i;
372 txq->last_desc_cleaned = txq->nb_tx_desc - 1;
373 txq->nb_tx_free = txq->nb_tx_desc - 1;
375 txq->tx_next_dd = txq->tx_rs_thresh - 1;
376 txq->tx_next_rs = txq->tx_rs_thresh - 1;
380 ice_dcf_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
382 struct ice_dcf_adapter *ad = dev->data->dev_private;
383 struct ice_dcf_hw *hw = &ad->real_hw;
384 struct ice_rx_queue *rxq;
387 if (rx_queue_id >= dev->data->nb_rx_queues)
390 err = ice_dcf_switch_queue(hw, rx_queue_id, true, false);
392 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
397 rxq = dev->data->rx_queues[rx_queue_id];
398 rxq->rx_rel_mbufs(rxq);
400 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
406 ice_dcf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
408 struct ice_dcf_adapter *ad = dev->data->dev_private;
409 struct iavf_hw *hw = &ad->real_hw.avf;
410 struct ice_tx_queue *txq;
413 if (tx_queue_id >= dev->data->nb_tx_queues)
416 txq = dev->data->tx_queues[tx_queue_id];
418 /* Init the RX tail register. */
419 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(tx_queue_id);
420 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
421 IAVF_WRITE_FLUSH(hw);
423 /* Ready to switch the queue on */
424 err = ice_dcf_switch_queue(&ad->real_hw, tx_queue_id, false, true);
427 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
432 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
438 ice_dcf_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
440 struct ice_dcf_adapter *ad = dev->data->dev_private;
441 struct ice_dcf_hw *hw = &ad->real_hw;
442 struct ice_tx_queue *txq;
445 if (tx_queue_id >= dev->data->nb_tx_queues)
448 err = ice_dcf_switch_queue(hw, tx_queue_id, false, false);
450 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
455 txq = dev->data->tx_queues[tx_queue_id];
456 txq->tx_rel_mbufs(txq);
458 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
464 ice_dcf_start_queues(struct rte_eth_dev *dev)
466 struct ice_rx_queue *rxq;
467 struct ice_tx_queue *txq;
471 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
472 txq = dev->data->tx_queues[nb_txq];
473 if (txq->tx_deferred_start)
475 if (ice_dcf_tx_queue_start(dev, nb_txq) != 0) {
476 PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_txq);
481 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
482 rxq = dev->data->rx_queues[nb_rxq];
483 if (rxq->rx_deferred_start)
485 if (ice_dcf_rx_queue_start(dev, nb_rxq) != 0) {
486 PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_rxq);
493 /* stop the started queues if failed to start all queues */
495 for (i = 0; i < nb_rxq; i++)
496 ice_dcf_rx_queue_stop(dev, i);
498 for (i = 0; i < nb_txq; i++)
499 ice_dcf_tx_queue_stop(dev, i);
505 ice_dcf_dev_start(struct rte_eth_dev *dev)
507 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
508 struct rte_intr_handle *intr_handle = dev->intr_handle;
509 struct ice_adapter *ad = &dcf_ad->parent;
510 struct ice_dcf_hw *hw = &dcf_ad->real_hw;
513 ad->pf.adapter_stopped = 0;
515 hw->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
516 dev->data->nb_tx_queues);
518 ret = ice_dcf_init_rx_queues(dev);
520 PMD_DRV_LOG(ERR, "Fail to init queues");
524 if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF) {
525 ret = ice_dcf_init_rss(hw);
527 PMD_DRV_LOG(ERR, "Failed to configure RSS");
532 ret = ice_dcf_configure_queues(hw);
534 PMD_DRV_LOG(ERR, "Fail to config queues");
538 ret = ice_dcf_config_rx_queues_irqs(dev, intr_handle);
540 PMD_DRV_LOG(ERR, "Fail to config rx queues' irqs");
544 if (dev->data->dev_conf.intr_conf.rxq != 0) {
545 rte_intr_disable(intr_handle);
546 rte_intr_enable(intr_handle);
549 ret = ice_dcf_start_queues(dev);
551 PMD_DRV_LOG(ERR, "Failed to enable queues");
555 ret = ice_dcf_add_del_all_mac_addr(hw, true);
557 PMD_DRV_LOG(ERR, "Failed to add mac addr");
561 dev->data->dev_link.link_status = ETH_LINK_UP;
567 ice_dcf_stop_queues(struct rte_eth_dev *dev)
569 struct ice_dcf_adapter *ad = dev->data->dev_private;
570 struct ice_dcf_hw *hw = &ad->real_hw;
571 struct ice_rx_queue *rxq;
572 struct ice_tx_queue *txq;
575 /* Stop All queues */
576 ret = ice_dcf_disable_queues(hw);
578 PMD_DRV_LOG(WARNING, "Fail to stop queues");
580 for (i = 0; i < dev->data->nb_tx_queues; i++) {
581 txq = dev->data->tx_queues[i];
584 txq->tx_rel_mbufs(txq);
586 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
588 for (i = 0; i < dev->data->nb_rx_queues; i++) {
589 rxq = dev->data->rx_queues[i];
592 rxq->rx_rel_mbufs(rxq);
594 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
599 ice_dcf_dev_stop(struct rte_eth_dev *dev)
601 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
602 struct rte_intr_handle *intr_handle = dev->intr_handle;
603 struct ice_adapter *ad = &dcf_ad->parent;
605 if (ad->pf.adapter_stopped == 1) {
606 PMD_DRV_LOG(DEBUG, "Port is already stopped");
610 /* Stop the VF representors for this device */
611 ice_dcf_vf_repr_stop_all(dcf_ad);
613 ice_dcf_stop_queues(dev);
615 rte_intr_efd_disable(intr_handle);
616 if (intr_handle->intr_vec) {
617 rte_free(intr_handle->intr_vec);
618 intr_handle->intr_vec = NULL;
621 ice_dcf_add_del_all_mac_addr(&dcf_ad->real_hw, false);
622 dev->data->dev_link.link_status = ETH_LINK_DOWN;
623 ad->pf.adapter_stopped = 1;
629 ice_dcf_dev_configure(struct rte_eth_dev *dev)
631 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
632 struct ice_adapter *ad = &dcf_ad->parent;
634 ad->rx_bulk_alloc_allowed = true;
635 ad->tx_simple_allowed = true;
637 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
638 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
644 ice_dcf_dev_info_get(struct rte_eth_dev *dev,
645 struct rte_eth_dev_info *dev_info)
647 struct ice_dcf_adapter *adapter = dev->data->dev_private;
648 struct ice_dcf_hw *hw = &adapter->real_hw;
650 dev_info->max_mac_addrs = 1;
651 dev_info->max_rx_queues = hw->vsi_res->num_queue_pairs;
652 dev_info->max_tx_queues = hw->vsi_res->num_queue_pairs;
653 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
654 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
655 dev_info->hash_key_size = hw->vf_res->rss_key_size;
656 dev_info->reta_size = hw->vf_res->rss_lut_size;
657 dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL;
659 dev_info->rx_offload_capa =
660 DEV_RX_OFFLOAD_VLAN_STRIP |
661 DEV_RX_OFFLOAD_IPV4_CKSUM |
662 DEV_RX_OFFLOAD_UDP_CKSUM |
663 DEV_RX_OFFLOAD_TCP_CKSUM |
664 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
665 DEV_RX_OFFLOAD_SCATTER |
666 DEV_RX_OFFLOAD_JUMBO_FRAME |
667 DEV_RX_OFFLOAD_VLAN_FILTER |
668 DEV_RX_OFFLOAD_RSS_HASH;
669 dev_info->tx_offload_capa =
670 DEV_TX_OFFLOAD_VLAN_INSERT |
671 DEV_TX_OFFLOAD_IPV4_CKSUM |
672 DEV_TX_OFFLOAD_UDP_CKSUM |
673 DEV_TX_OFFLOAD_TCP_CKSUM |
674 DEV_TX_OFFLOAD_SCTP_CKSUM |
675 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
676 DEV_TX_OFFLOAD_TCP_TSO |
677 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
678 DEV_TX_OFFLOAD_GRE_TNL_TSO |
679 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
680 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
681 DEV_TX_OFFLOAD_MULTI_SEGS;
683 dev_info->default_rxconf = (struct rte_eth_rxconf) {
685 .pthresh = ICE_DEFAULT_RX_PTHRESH,
686 .hthresh = ICE_DEFAULT_RX_HTHRESH,
687 .wthresh = ICE_DEFAULT_RX_WTHRESH,
689 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
694 dev_info->default_txconf = (struct rte_eth_txconf) {
696 .pthresh = ICE_DEFAULT_TX_PTHRESH,
697 .hthresh = ICE_DEFAULT_TX_HTHRESH,
698 .wthresh = ICE_DEFAULT_TX_WTHRESH,
700 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
701 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
705 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
706 .nb_max = ICE_MAX_RING_DESC,
707 .nb_min = ICE_MIN_RING_DESC,
708 .nb_align = ICE_ALIGN_RING_DESC,
711 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
712 .nb_max = ICE_MAX_RING_DESC,
713 .nb_min = ICE_MIN_RING_DESC,
714 .nb_align = ICE_ALIGN_RING_DESC,
721 ice_dcf_dev_promiscuous_enable(__rte_unused struct rte_eth_dev *dev)
727 ice_dcf_dev_promiscuous_disable(__rte_unused struct rte_eth_dev *dev)
733 ice_dcf_dev_allmulticast_enable(__rte_unused struct rte_eth_dev *dev)
739 ice_dcf_dev_allmulticast_disable(__rte_unused struct rte_eth_dev *dev)
745 ice_dcf_dev_flow_ops_get(struct rte_eth_dev *dev,
746 const struct rte_flow_ops **ops)
751 *ops = &ice_flow_ops;
755 #define ICE_DCF_32_BIT_WIDTH (CHAR_BIT * 4)
756 #define ICE_DCF_48_BIT_WIDTH (CHAR_BIT * 6)
757 #define ICE_DCF_48_BIT_MASK RTE_LEN2MASK(ICE_DCF_48_BIT_WIDTH, uint64_t)
760 ice_dcf_stat_update_48(uint64_t *offset, uint64_t *stat)
762 if (*stat >= *offset)
763 *stat = *stat - *offset;
765 *stat = (uint64_t)((*stat +
766 ((uint64_t)1 << ICE_DCF_48_BIT_WIDTH)) - *offset);
768 *stat &= ICE_DCF_48_BIT_MASK;
772 ice_dcf_stat_update_32(uint64_t *offset, uint64_t *stat)
774 if (*stat >= *offset)
775 *stat = (uint64_t)(*stat - *offset);
777 *stat = (uint64_t)((*stat +
778 ((uint64_t)1 << ICE_DCF_32_BIT_WIDTH)) - *offset);
782 ice_dcf_update_stats(struct virtchnl_eth_stats *oes,
783 struct virtchnl_eth_stats *nes)
785 ice_dcf_stat_update_48(&oes->rx_bytes, &nes->rx_bytes);
786 ice_dcf_stat_update_48(&oes->rx_unicast, &nes->rx_unicast);
787 ice_dcf_stat_update_48(&oes->rx_multicast, &nes->rx_multicast);
788 ice_dcf_stat_update_48(&oes->rx_broadcast, &nes->rx_broadcast);
789 ice_dcf_stat_update_32(&oes->rx_discards, &nes->rx_discards);
790 ice_dcf_stat_update_48(&oes->tx_bytes, &nes->tx_bytes);
791 ice_dcf_stat_update_48(&oes->tx_unicast, &nes->tx_unicast);
792 ice_dcf_stat_update_48(&oes->tx_multicast, &nes->tx_multicast);
793 ice_dcf_stat_update_48(&oes->tx_broadcast, &nes->tx_broadcast);
794 ice_dcf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
795 ice_dcf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
800 ice_dcf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
802 struct ice_dcf_adapter *ad = dev->data->dev_private;
803 struct ice_dcf_hw *hw = &ad->real_hw;
804 struct virtchnl_eth_stats pstats;
807 ret = ice_dcf_query_stats(hw, &pstats);
809 ice_dcf_update_stats(&hw->eth_stats_offset, &pstats);
810 stats->ipackets = pstats.rx_unicast + pstats.rx_multicast +
811 pstats.rx_broadcast - pstats.rx_discards;
812 stats->opackets = pstats.tx_broadcast + pstats.tx_multicast +
814 stats->imissed = pstats.rx_discards;
815 stats->oerrors = pstats.tx_errors + pstats.tx_discards;
816 stats->ibytes = pstats.rx_bytes;
817 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN;
818 stats->obytes = pstats.tx_bytes;
820 PMD_DRV_LOG(ERR, "Get statistics failed");
826 ice_dcf_stats_reset(struct rte_eth_dev *dev)
828 struct ice_dcf_adapter *ad = dev->data->dev_private;
829 struct ice_dcf_hw *hw = &ad->real_hw;
830 struct virtchnl_eth_stats pstats;
833 /* read stat values to clear hardware registers */
834 ret = ice_dcf_query_stats(hw, &pstats);
838 /* set stats offset base on current values */
839 hw->eth_stats_offset = pstats;
845 ice_dcf_free_repr_info(struct ice_dcf_adapter *dcf_adapter)
847 if (dcf_adapter->repr_infos) {
848 rte_free(dcf_adapter->repr_infos);
849 dcf_adapter->repr_infos = NULL;
854 ice_dcf_init_repr_info(struct ice_dcf_adapter *dcf_adapter)
856 dcf_adapter->repr_infos =
857 rte_calloc("ice_dcf_rep_info",
858 dcf_adapter->real_hw.num_vfs,
859 sizeof(dcf_adapter->repr_infos[0]), 0);
860 if (!dcf_adapter->repr_infos) {
861 PMD_DRV_LOG(ERR, "Failed to alloc memory for VF representors\n");
869 ice_dcf_dev_close(struct rte_eth_dev *dev)
871 struct ice_dcf_adapter *adapter = dev->data->dev_private;
873 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
876 ice_dcf_free_repr_info(adapter);
877 ice_dcf_uninit_parent_adapter(dev);
878 ice_dcf_uninit_hw(dev, &adapter->real_hw);
884 ice_dcf_link_update(__rte_unused struct rte_eth_dev *dev,
885 __rte_unused int wait_to_complete)
890 /* Add UDP tunneling port */
892 ice_dcf_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
893 struct rte_eth_udp_tunnel *udp_tunnel)
895 struct ice_dcf_adapter *adapter = dev->data->dev_private;
896 struct ice_adapter *parent_adapter = &adapter->parent;
897 struct ice_hw *parent_hw = &parent_adapter->hw;
903 switch (udp_tunnel->prot_type) {
904 case RTE_TUNNEL_TYPE_VXLAN:
905 ret = ice_create_tunnel(parent_hw, TNL_VXLAN,
906 udp_tunnel->udp_port);
908 case RTE_TUNNEL_TYPE_ECPRI:
909 ret = ice_create_tunnel(parent_hw, TNL_ECPRI,
910 udp_tunnel->udp_port);
913 PMD_DRV_LOG(ERR, "Invalid tunnel type");
921 /* Delete UDP tunneling port */
923 ice_dcf_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
924 struct rte_eth_udp_tunnel *udp_tunnel)
926 struct ice_dcf_adapter *adapter = dev->data->dev_private;
927 struct ice_adapter *parent_adapter = &adapter->parent;
928 struct ice_hw *parent_hw = &parent_adapter->hw;
934 switch (udp_tunnel->prot_type) {
935 case RTE_TUNNEL_TYPE_VXLAN:
936 case RTE_TUNNEL_TYPE_ECPRI:
937 ret = ice_destroy_tunnel(parent_hw, udp_tunnel->udp_port, 0);
940 PMD_DRV_LOG(ERR, "Invalid tunnel type");
948 static const struct eth_dev_ops ice_dcf_eth_dev_ops = {
949 .dev_start = ice_dcf_dev_start,
950 .dev_stop = ice_dcf_dev_stop,
951 .dev_close = ice_dcf_dev_close,
952 .dev_configure = ice_dcf_dev_configure,
953 .dev_infos_get = ice_dcf_dev_info_get,
954 .rx_queue_setup = ice_rx_queue_setup,
955 .tx_queue_setup = ice_tx_queue_setup,
956 .rx_queue_release = ice_rx_queue_release,
957 .tx_queue_release = ice_tx_queue_release,
958 .rx_queue_start = ice_dcf_rx_queue_start,
959 .tx_queue_start = ice_dcf_tx_queue_start,
960 .rx_queue_stop = ice_dcf_rx_queue_stop,
961 .tx_queue_stop = ice_dcf_tx_queue_stop,
962 .link_update = ice_dcf_link_update,
963 .stats_get = ice_dcf_stats_get,
964 .stats_reset = ice_dcf_stats_reset,
965 .promiscuous_enable = ice_dcf_dev_promiscuous_enable,
966 .promiscuous_disable = ice_dcf_dev_promiscuous_disable,
967 .allmulticast_enable = ice_dcf_dev_allmulticast_enable,
968 .allmulticast_disable = ice_dcf_dev_allmulticast_disable,
969 .flow_ops_get = ice_dcf_dev_flow_ops_get,
970 .udp_tunnel_port_add = ice_dcf_dev_udp_tunnel_port_add,
971 .udp_tunnel_port_del = ice_dcf_dev_udp_tunnel_port_del,
975 ice_dcf_dev_init(struct rte_eth_dev *eth_dev)
977 struct ice_dcf_adapter *adapter = eth_dev->data->dev_private;
979 eth_dev->dev_ops = &ice_dcf_eth_dev_ops;
980 eth_dev->rx_pkt_burst = ice_dcf_recv_pkts;
981 eth_dev->tx_pkt_burst = ice_dcf_xmit_pkts;
983 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
986 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
988 adapter->real_hw.vc_event_msg_cb = ice_dcf_handle_pf_event_msg;
989 if (ice_dcf_init_hw(eth_dev, &adapter->real_hw) != 0) {
990 PMD_INIT_LOG(ERR, "Failed to init DCF hardware");
994 if (ice_dcf_init_parent_adapter(eth_dev) != 0) {
995 PMD_INIT_LOG(ERR, "Failed to init DCF parent adapter");
996 ice_dcf_uninit_hw(eth_dev, &adapter->real_hw);
1004 ice_dcf_dev_uninit(struct rte_eth_dev *eth_dev)
1006 ice_dcf_dev_close(eth_dev);
1012 ice_dcf_cap_check_handler(__rte_unused const char *key,
1013 const char *value, __rte_unused void *opaque)
1015 if (strcmp(value, "dcf"))
1022 ice_dcf_cap_selected(struct rte_devargs *devargs)
1024 struct rte_kvargs *kvlist;
1025 const char *key = "cap";
1028 if (devargs == NULL)
1031 kvlist = rte_kvargs_parse(devargs->args, NULL);
1035 if (!rte_kvargs_count(kvlist, key))
1038 /* dcf capability selected when there's a key-value pair: cap=dcf */
1039 if (rte_kvargs_process(kvlist, key,
1040 ice_dcf_cap_check_handler, NULL) < 0)
1046 rte_kvargs_free(kvlist);
1051 eth_ice_dcf_pci_probe(__rte_unused struct rte_pci_driver *pci_drv,
1052 struct rte_pci_device *pci_dev)
1054 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
1055 struct ice_dcf_vf_repr_param repr_param;
1056 char repr_name[RTE_ETH_NAME_MAX_LEN];
1057 struct ice_dcf_adapter *dcf_adapter;
1058 struct rte_eth_dev *dcf_ethdev;
1059 uint16_t dcf_vsi_id;
1062 if (!ice_dcf_cap_selected(pci_dev->device.devargs))
1065 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, ð_da);
1069 ret = rte_eth_dev_pci_generic_probe(pci_dev,
1070 sizeof(struct ice_dcf_adapter),
1072 if (ret || !eth_da.nb_representor_ports)
1074 if (eth_da.type != RTE_ETH_REPRESENTOR_VF)
1077 dcf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1078 if (dcf_ethdev == NULL)
1081 dcf_adapter = dcf_ethdev->data->dev_private;
1082 ret = ice_dcf_init_repr_info(dcf_adapter);
1086 if (eth_da.nb_representor_ports > dcf_adapter->real_hw.num_vfs ||
1087 eth_da.nb_representor_ports >= RTE_MAX_ETHPORTS) {
1088 PMD_DRV_LOG(ERR, "the number of port representors is too large: %u",
1089 eth_da.nb_representor_ports);
1090 ice_dcf_free_repr_info(dcf_adapter);
1094 dcf_vsi_id = dcf_adapter->real_hw.vsi_id | VIRTCHNL_DCF_VF_VSI_VALID;
1096 repr_param.dcf_eth_dev = dcf_ethdev;
1097 repr_param.switch_domain_id = 0;
1099 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1100 uint16_t vf_id = eth_da.representor_ports[i];
1101 struct rte_eth_dev *vf_rep_eth_dev;
1103 if (vf_id >= dcf_adapter->real_hw.num_vfs) {
1104 PMD_DRV_LOG(ERR, "VF ID %u is out of range (0 ~ %u)",
1105 vf_id, dcf_adapter->real_hw.num_vfs - 1);
1110 if (dcf_adapter->real_hw.vf_vsi_map[vf_id] == dcf_vsi_id) {
1111 PMD_DRV_LOG(ERR, "VF ID %u is DCF's ID.\n", vf_id);
1116 repr_param.vf_id = vf_id;
1117 snprintf(repr_name, sizeof(repr_name), "net_%s_representor_%u",
1118 pci_dev->device.name, vf_id);
1119 ret = rte_eth_dev_create(&pci_dev->device, repr_name,
1120 sizeof(struct ice_dcf_vf_repr),
1121 NULL, NULL, ice_dcf_vf_repr_init,
1124 PMD_DRV_LOG(ERR, "failed to create DCF VF representor %s",
1129 vf_rep_eth_dev = rte_eth_dev_allocated(repr_name);
1130 if (!vf_rep_eth_dev) {
1132 "Failed to find the ethdev for DCF VF representor: %s",
1138 dcf_adapter->repr_infos[vf_id].vf_rep_eth_dev = vf_rep_eth_dev;
1139 dcf_adapter->num_reprs++;
1146 eth_ice_dcf_pci_remove(struct rte_pci_device *pci_dev)
1148 struct rte_eth_dev *eth_dev;
1150 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1154 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1155 return rte_eth_dev_pci_generic_remove(pci_dev,
1156 ice_dcf_vf_repr_uninit);
1158 return rte_eth_dev_pci_generic_remove(pci_dev,
1159 ice_dcf_dev_uninit);
1162 static const struct rte_pci_id pci_id_ice_dcf_map[] = {
1163 { RTE_PCI_DEVICE(IAVF_INTEL_VENDOR_ID, IAVF_DEV_ID_ADAPTIVE_VF) },
1164 { .vendor_id = 0, /* sentinel */ },
1167 static struct rte_pci_driver rte_ice_dcf_pmd = {
1168 .id_table = pci_id_ice_dcf_map,
1169 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1170 .probe = eth_ice_dcf_pci_probe,
1171 .remove = eth_ice_dcf_pci_remove,
1174 RTE_PMD_REGISTER_PCI(net_ice_dcf, rte_ice_dcf_pmd);
1175 RTE_PMD_REGISTER_PCI_TABLE(net_ice_dcf, pci_id_ice_dcf_map);
1176 RTE_PMD_REGISTER_KMOD_DEP(net_ice_dcf, "* igb_uio | vfio-pci");
1177 RTE_PMD_REGISTER_PARAM_STRING(net_ice_dcf, "cap=dcf");