1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
11 #include <rte_interrupts.h>
12 #include <rte_debug.h>
14 #include <rte_atomic.h>
16 #include <rte_ether.h>
17 #include <ethdev_pci.h>
18 #include <rte_kvargs.h>
19 #include <rte_malloc.h>
20 #include <rte_memzone.h>
23 #include <iavf_devids.h>
25 #include "ice_generic_flow.h"
26 #include "ice_dcf_ethdev.h"
30 ice_dcf_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
31 struct rte_eth_udp_tunnel *udp_tunnel);
33 ice_dcf_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
34 struct rte_eth_udp_tunnel *udp_tunnel);
37 ice_dcf_dev_init(struct rte_eth_dev *eth_dev);
40 ice_dcf_dev_uninit(struct rte_eth_dev *eth_dev);
43 ice_dcf_recv_pkts(__rte_unused void *rx_queue,
44 __rte_unused struct rte_mbuf **bufs,
45 __rte_unused uint16_t nb_pkts)
51 ice_dcf_xmit_pkts(__rte_unused void *tx_queue,
52 __rte_unused struct rte_mbuf **bufs,
53 __rte_unused uint16_t nb_pkts)
59 ice_dcf_init_rxq(struct rte_eth_dev *dev, struct ice_rx_queue *rxq)
61 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
62 struct rte_eth_dev_data *dev_data = dev->data;
63 struct iavf_hw *hw = &dcf_ad->real_hw.avf;
64 uint16_t buf_size, max_pkt_len;
66 buf_size = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
68 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
69 max_pkt_len = RTE_MIN(ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
70 dev->data->mtu + ICE_ETH_OVERHEAD);
72 /* Check maximum packet length is set correctly. */
73 if (max_pkt_len <= RTE_ETHER_MIN_LEN ||
74 max_pkt_len > ICE_FRAME_SIZE_MAX) {
75 PMD_DRV_LOG(ERR, "maximum packet length must be "
76 "larger than %u and smaller than %u",
77 (uint32_t)RTE_ETHER_MIN_LEN,
78 (uint32_t)ICE_FRAME_SIZE_MAX);
82 rxq->max_pkt_len = max_pkt_len;
83 if ((dev_data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) ||
84 (rxq->max_pkt_len + 2 * RTE_VLAN_HLEN) > buf_size) {
85 dev_data->scattered_rx = 1;
87 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
88 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
95 ice_dcf_init_rx_queues(struct rte_eth_dev *dev)
97 struct ice_rx_queue **rxq =
98 (struct ice_rx_queue **)dev->data->rx_queues;
101 for (i = 0; i < dev->data->nb_rx_queues; i++) {
102 if (!rxq[i] || !rxq[i]->q_set)
104 ret = ice_dcf_init_rxq(dev, rxq[i]);
109 ice_set_rx_function(dev);
110 ice_set_tx_function(dev);
115 #define IAVF_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
116 #define IAVF_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
118 #define IAVF_ITR_INDEX_DEFAULT 0
119 #define IAVF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
120 #define IAVF_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
122 static inline uint16_t
123 iavf_calc_itr_interval(int16_t interval)
125 if (interval < 0 || interval > IAVF_QUEUE_ITR_INTERVAL_MAX)
126 interval = IAVF_QUEUE_ITR_INTERVAL_DEFAULT;
128 /* Convert to hardware count, as writing each 1 represents 2 us */
133 ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev,
134 struct rte_intr_handle *intr_handle)
136 struct ice_dcf_adapter *adapter = dev->data->dev_private;
137 struct ice_dcf_hw *hw = &adapter->real_hw;
138 uint16_t interval, i;
141 if (rte_intr_cap_multiple(intr_handle) &&
142 dev->data->dev_conf.intr_conf.rxq) {
143 if (rte_intr_efd_enable(intr_handle, dev->data->nb_rx_queues))
147 if (rte_intr_dp_is_en(intr_handle)) {
148 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
149 dev->data->nb_rx_queues)) {
150 PMD_DRV_LOG(ERR, "Failed to allocate %d rx intr_vec",
151 dev->data->nb_rx_queues);
156 if (!dev->data->dev_conf.intr_conf.rxq ||
157 !rte_intr_dp_is_en(intr_handle)) {
158 /* Rx interrupt disabled, Map interrupt only for writeback */
160 if (hw->vf_res->vf_cap_flags &
161 VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) {
162 /* If WB_ON_ITR supports, enable it */
163 hw->msix_base = IAVF_RX_VEC_START;
164 /* Set the ITR for index zero, to 2us to make sure that
165 * we leave time for aggregation to occur, but don't
166 * increase latency dramatically.
168 IAVF_WRITE_REG(&hw->avf,
169 IAVF_VFINT_DYN_CTLN1(hw->msix_base - 1),
170 (0 << IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
171 IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
172 (2UL << IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
174 /* If no WB_ON_ITR offload flags, need to set
175 * interrupt for descriptor write back.
177 hw->msix_base = IAVF_MISC_VEC_ID;
181 iavf_calc_itr_interval(IAVF_QUEUE_ITR_INTERVAL_MAX);
182 IAVF_WRITE_REG(&hw->avf, IAVF_VFINT_DYN_CTL01,
183 IAVF_VFINT_DYN_CTL01_INTENA_MASK |
184 (IAVF_ITR_INDEX_DEFAULT <<
185 IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
187 IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT));
189 IAVF_WRITE_FLUSH(&hw->avf);
190 /* map all queues to the same interrupt */
191 for (i = 0; i < dev->data->nb_rx_queues; i++)
192 hw->rxq_map[hw->msix_base] |= 1 << i;
194 if (!rte_intr_allow_others(intr_handle)) {
196 hw->msix_base = IAVF_MISC_VEC_ID;
197 for (i = 0; i < dev->data->nb_rx_queues; i++) {
198 hw->rxq_map[hw->msix_base] |= 1 << i;
199 rte_intr_vec_list_index_set(intr_handle,
200 i, IAVF_MISC_VEC_ID);
203 "vector %u are mapping to all Rx queues",
206 /* If Rx interrupt is required, and we can use
207 * multi interrupts, then the vec is from 1
209 hw->nb_msix = RTE_MIN(hw->vf_res->max_vectors,
210 rte_intr_nb_efd_get(intr_handle));
211 hw->msix_base = IAVF_MISC_VEC_ID;
212 vec = IAVF_MISC_VEC_ID;
213 for (i = 0; i < dev->data->nb_rx_queues; i++) {
214 hw->rxq_map[vec] |= 1 << i;
215 rte_intr_vec_list_index_set(intr_handle,
217 if (vec >= hw->nb_msix)
218 vec = IAVF_RX_VEC_START;
221 "%u vectors are mapping to %u Rx queues",
222 hw->nb_msix, dev->data->nb_rx_queues);
226 if (ice_dcf_config_irq_map(hw)) {
227 PMD_DRV_LOG(ERR, "config interrupt mapping failed");
234 alloc_rxq_mbufs(struct ice_rx_queue *rxq)
236 volatile union ice_rx_flex_desc *rxd;
237 struct rte_mbuf *mbuf = NULL;
241 for (i = 0; i < rxq->nb_rx_desc; i++) {
242 mbuf = rte_mbuf_raw_alloc(rxq->mp);
243 if (unlikely(!mbuf)) {
244 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
248 rte_mbuf_refcnt_set(mbuf, 1);
250 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
252 mbuf->port = rxq->port_id;
255 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
257 rxd = &rxq->rx_ring[i];
258 rxd->read.pkt_addr = dma_addr;
259 rxd->read.hdr_addr = 0;
260 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
265 rxq->sw_ring[i].mbuf = (void *)mbuf;
272 ice_dcf_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
274 struct ice_dcf_adapter *ad = dev->data->dev_private;
275 struct iavf_hw *hw = &ad->real_hw.avf;
276 struct ice_rx_queue *rxq;
279 if (rx_queue_id >= dev->data->nb_rx_queues)
282 rxq = dev->data->rx_queues[rx_queue_id];
284 err = alloc_rxq_mbufs(rxq);
286 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
292 /* Init the RX tail register. */
293 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
294 IAVF_WRITE_FLUSH(hw);
296 /* Ready to switch the queue on */
297 err = ice_dcf_switch_queue(&ad->real_hw, rx_queue_id, true, true);
299 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
304 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
310 reset_rx_queue(struct ice_rx_queue *rxq)
318 len = rxq->nb_rx_desc + ICE_RX_MAX_BURST;
320 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
321 ((volatile char *)rxq->rx_ring)[i] = 0;
323 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
325 for (i = 0; i < ICE_RX_MAX_BURST; i++)
326 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
329 rxq->rx_nb_avail = 0;
330 rxq->rx_next_avail = 0;
331 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
335 rxq->pkt_first_seg = NULL;
336 rxq->pkt_last_seg = NULL;
340 reset_tx_queue(struct ice_tx_queue *txq)
342 struct ice_tx_entry *txe;
347 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
352 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
353 for (i = 0; i < size; i++)
354 ((volatile char *)txq->tx_ring)[i] = 0;
356 prev = (uint16_t)(txq->nb_tx_desc - 1);
357 for (i = 0; i < txq->nb_tx_desc; i++) {
358 txq->tx_ring[i].cmd_type_offset_bsz =
359 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
362 txe[prev].next_id = i;
369 txq->last_desc_cleaned = txq->nb_tx_desc - 1;
370 txq->nb_tx_free = txq->nb_tx_desc - 1;
372 txq->tx_next_dd = txq->tx_rs_thresh - 1;
373 txq->tx_next_rs = txq->tx_rs_thresh - 1;
377 ice_dcf_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
379 struct ice_dcf_adapter *ad = dev->data->dev_private;
380 struct ice_dcf_hw *hw = &ad->real_hw;
381 struct ice_rx_queue *rxq;
384 if (rx_queue_id >= dev->data->nb_rx_queues)
387 err = ice_dcf_switch_queue(hw, rx_queue_id, true, false);
389 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
394 rxq = dev->data->rx_queues[rx_queue_id];
395 rxq->rx_rel_mbufs(rxq);
397 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
403 ice_dcf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
405 struct ice_dcf_adapter *ad = dev->data->dev_private;
406 struct iavf_hw *hw = &ad->real_hw.avf;
407 struct ice_tx_queue *txq;
410 if (tx_queue_id >= dev->data->nb_tx_queues)
413 txq = dev->data->tx_queues[tx_queue_id];
415 /* Init the RX tail register. */
416 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(tx_queue_id);
417 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
418 IAVF_WRITE_FLUSH(hw);
420 /* Ready to switch the queue on */
421 err = ice_dcf_switch_queue(&ad->real_hw, tx_queue_id, false, true);
424 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
429 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
435 ice_dcf_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
437 struct ice_dcf_adapter *ad = dev->data->dev_private;
438 struct ice_dcf_hw *hw = &ad->real_hw;
439 struct ice_tx_queue *txq;
442 if (tx_queue_id >= dev->data->nb_tx_queues)
445 err = ice_dcf_switch_queue(hw, tx_queue_id, false, false);
447 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
452 txq = dev->data->tx_queues[tx_queue_id];
453 txq->tx_rel_mbufs(txq);
455 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
461 ice_dcf_start_queues(struct rte_eth_dev *dev)
463 struct ice_rx_queue *rxq;
464 struct ice_tx_queue *txq;
468 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
469 txq = dev->data->tx_queues[nb_txq];
470 if (txq->tx_deferred_start)
472 if (ice_dcf_tx_queue_start(dev, nb_txq) != 0) {
473 PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_txq);
478 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
479 rxq = dev->data->rx_queues[nb_rxq];
480 if (rxq->rx_deferred_start)
482 if (ice_dcf_rx_queue_start(dev, nb_rxq) != 0) {
483 PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_rxq);
490 /* stop the started queues if failed to start all queues */
492 for (i = 0; i < nb_rxq; i++)
493 ice_dcf_rx_queue_stop(dev, i);
495 for (i = 0; i < nb_txq; i++)
496 ice_dcf_tx_queue_stop(dev, i);
502 ice_dcf_dev_start(struct rte_eth_dev *dev)
504 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
505 struct rte_intr_handle *intr_handle = dev->intr_handle;
506 struct ice_adapter *ad = &dcf_ad->parent;
507 struct ice_dcf_hw *hw = &dcf_ad->real_hw;
512 "The DCF has been reset by PF, please reinit first");
516 if (hw->tm_conf.root && !hw->tm_conf.committed) {
518 "please call hierarchy_commit() before starting the port");
522 ad->pf.adapter_stopped = 0;
524 hw->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
525 dev->data->nb_tx_queues);
527 ret = ice_dcf_init_rx_queues(dev);
529 PMD_DRV_LOG(ERR, "Fail to init queues");
533 if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF) {
534 ret = ice_dcf_init_rss(hw);
536 PMD_DRV_LOG(ERR, "Failed to configure RSS");
541 ret = ice_dcf_configure_queues(hw);
543 PMD_DRV_LOG(ERR, "Fail to config queues");
547 ret = ice_dcf_config_rx_queues_irqs(dev, intr_handle);
549 PMD_DRV_LOG(ERR, "Fail to config rx queues' irqs");
553 if (dev->data->dev_conf.intr_conf.rxq != 0) {
554 rte_intr_disable(intr_handle);
555 rte_intr_enable(intr_handle);
558 ret = ice_dcf_start_queues(dev);
560 PMD_DRV_LOG(ERR, "Failed to enable queues");
564 ret = ice_dcf_add_del_all_mac_addr(hw, true);
566 PMD_DRV_LOG(ERR, "Failed to add mac addr");
570 dev->data->dev_link.link_status = RTE_ETH_LINK_UP;
576 ice_dcf_stop_queues(struct rte_eth_dev *dev)
578 struct ice_dcf_adapter *ad = dev->data->dev_private;
579 struct ice_dcf_hw *hw = &ad->real_hw;
580 struct ice_rx_queue *rxq;
581 struct ice_tx_queue *txq;
584 /* Stop All queues */
585 ret = ice_dcf_disable_queues(hw);
587 PMD_DRV_LOG(WARNING, "Fail to stop queues");
589 for (i = 0; i < dev->data->nb_tx_queues; i++) {
590 txq = dev->data->tx_queues[i];
593 txq->tx_rel_mbufs(txq);
595 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
597 for (i = 0; i < dev->data->nb_rx_queues; i++) {
598 rxq = dev->data->rx_queues[i];
601 rxq->rx_rel_mbufs(rxq);
603 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
608 ice_dcf_dev_stop(struct rte_eth_dev *dev)
610 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
611 struct rte_intr_handle *intr_handle = dev->intr_handle;
612 struct ice_adapter *ad = &dcf_ad->parent;
613 struct ice_dcf_hw *hw = &dcf_ad->real_hw;
615 if (ad->pf.adapter_stopped == 1) {
616 PMD_DRV_LOG(DEBUG, "Port is already stopped");
620 /* Stop the VF representors for this device */
621 ice_dcf_vf_repr_stop_all(dcf_ad);
623 ice_dcf_stop_queues(dev);
625 rte_intr_efd_disable(intr_handle);
626 rte_intr_vec_list_free(intr_handle);
628 ice_dcf_add_del_all_mac_addr(&dcf_ad->real_hw, false);
629 dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN;
630 ad->pf.adapter_stopped = 1;
631 hw->tm_conf.committed = false;
637 ice_dcf_dev_configure(struct rte_eth_dev *dev)
639 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
640 struct ice_adapter *ad = &dcf_ad->parent;
642 ad->rx_bulk_alloc_allowed = true;
643 ad->tx_simple_allowed = true;
645 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
646 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
652 ice_dcf_dev_info_get(struct rte_eth_dev *dev,
653 struct rte_eth_dev_info *dev_info)
655 struct ice_dcf_adapter *adapter = dev->data->dev_private;
656 struct ice_dcf_hw *hw = &adapter->real_hw;
658 dev_info->max_mac_addrs = 1;
659 dev_info->max_rx_queues = hw->vsi_res->num_queue_pairs;
660 dev_info->max_tx_queues = hw->vsi_res->num_queue_pairs;
661 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
662 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
663 dev_info->hash_key_size = hw->vf_res->rss_key_size;
664 dev_info->reta_size = hw->vf_res->rss_lut_size;
665 dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL;
666 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
668 dev_info->rx_offload_capa =
669 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
670 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
671 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
672 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
673 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
674 RTE_ETH_RX_OFFLOAD_SCATTER |
675 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
676 RTE_ETH_RX_OFFLOAD_RSS_HASH;
677 dev_info->tx_offload_capa =
678 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
679 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
680 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
681 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
682 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
683 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
684 RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM |
685 RTE_ETH_TX_OFFLOAD_TCP_TSO |
686 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
687 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
688 RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO |
689 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
690 RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
692 dev_info->default_rxconf = (struct rte_eth_rxconf) {
694 .pthresh = ICE_DEFAULT_RX_PTHRESH,
695 .hthresh = ICE_DEFAULT_RX_HTHRESH,
696 .wthresh = ICE_DEFAULT_RX_WTHRESH,
698 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
703 dev_info->default_txconf = (struct rte_eth_txconf) {
705 .pthresh = ICE_DEFAULT_TX_PTHRESH,
706 .hthresh = ICE_DEFAULT_TX_HTHRESH,
707 .wthresh = ICE_DEFAULT_TX_WTHRESH,
709 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
710 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
714 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
715 .nb_max = ICE_MAX_RING_DESC,
716 .nb_min = ICE_MIN_RING_DESC,
717 .nb_align = ICE_ALIGN_RING_DESC,
720 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
721 .nb_max = ICE_MAX_RING_DESC,
722 .nb_min = ICE_MIN_RING_DESC,
723 .nb_align = ICE_ALIGN_RING_DESC,
730 ice_dcf_dev_promiscuous_enable(__rte_unused struct rte_eth_dev *dev)
736 ice_dcf_dev_promiscuous_disable(__rte_unused struct rte_eth_dev *dev)
742 ice_dcf_dev_allmulticast_enable(__rte_unused struct rte_eth_dev *dev)
748 ice_dcf_dev_allmulticast_disable(__rte_unused struct rte_eth_dev *dev)
754 ice_dcf_dev_flow_ops_get(struct rte_eth_dev *dev,
755 const struct rte_flow_ops **ops)
760 *ops = &ice_flow_ops;
765 ice_dcf_dev_rss_reta_update(struct rte_eth_dev *dev,
766 struct rte_eth_rss_reta_entry64 *reta_conf,
769 struct ice_dcf_adapter *adapter = dev->data->dev_private;
770 struct ice_dcf_hw *hw = &adapter->real_hw;
772 uint16_t i, idx, shift;
775 if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF))
778 if (reta_size != hw->vf_res->rss_lut_size) {
779 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
780 "(%d) doesn't match the number of hardware can "
781 "support (%d)", reta_size, hw->vf_res->rss_lut_size);
785 lut = rte_zmalloc("rss_lut", reta_size, 0);
787 PMD_DRV_LOG(ERR, "No memory can be allocated");
790 /* store the old lut table temporarily */
791 rte_memcpy(lut, hw->rss_lut, reta_size);
793 for (i = 0; i < reta_size; i++) {
794 idx = i / RTE_ETH_RETA_GROUP_SIZE;
795 shift = i % RTE_ETH_RETA_GROUP_SIZE;
796 if (reta_conf[idx].mask & (1ULL << shift))
797 lut[i] = reta_conf[idx].reta[shift];
800 rte_memcpy(hw->rss_lut, lut, reta_size);
801 /* send virtchnnl ops to configure rss*/
802 ret = ice_dcf_configure_rss_lut(hw);
803 if (ret) /* revert back */
804 rte_memcpy(hw->rss_lut, lut, reta_size);
811 ice_dcf_dev_rss_reta_query(struct rte_eth_dev *dev,
812 struct rte_eth_rss_reta_entry64 *reta_conf,
815 struct ice_dcf_adapter *adapter = dev->data->dev_private;
816 struct ice_dcf_hw *hw = &adapter->real_hw;
817 uint16_t i, idx, shift;
819 if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF))
822 if (reta_size != hw->vf_res->rss_lut_size) {
823 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
824 "(%d) doesn't match the number of hardware can "
825 "support (%d)", reta_size, hw->vf_res->rss_lut_size);
829 for (i = 0; i < reta_size; i++) {
830 idx = i / RTE_ETH_RETA_GROUP_SIZE;
831 shift = i % RTE_ETH_RETA_GROUP_SIZE;
832 if (reta_conf[idx].mask & (1ULL << shift))
833 reta_conf[idx].reta[shift] = hw->rss_lut[i];
839 #define ICE_DCF_32_BIT_WIDTH (CHAR_BIT * 4)
840 #define ICE_DCF_48_BIT_WIDTH (CHAR_BIT * 6)
841 #define ICE_DCF_48_BIT_MASK RTE_LEN2MASK(ICE_DCF_48_BIT_WIDTH, uint64_t)
844 ice_dcf_stat_update_48(uint64_t *offset, uint64_t *stat)
846 if (*stat >= *offset)
847 *stat = *stat - *offset;
849 *stat = (uint64_t)((*stat +
850 ((uint64_t)1 << ICE_DCF_48_BIT_WIDTH)) - *offset);
852 *stat &= ICE_DCF_48_BIT_MASK;
856 ice_dcf_stat_update_32(uint64_t *offset, uint64_t *stat)
858 if (*stat >= *offset)
859 *stat = (uint64_t)(*stat - *offset);
861 *stat = (uint64_t)((*stat +
862 ((uint64_t)1 << ICE_DCF_32_BIT_WIDTH)) - *offset);
866 ice_dcf_update_stats(struct virtchnl_eth_stats *oes,
867 struct virtchnl_eth_stats *nes)
869 ice_dcf_stat_update_48(&oes->rx_bytes, &nes->rx_bytes);
870 ice_dcf_stat_update_48(&oes->rx_unicast, &nes->rx_unicast);
871 ice_dcf_stat_update_48(&oes->rx_multicast, &nes->rx_multicast);
872 ice_dcf_stat_update_48(&oes->rx_broadcast, &nes->rx_broadcast);
873 ice_dcf_stat_update_32(&oes->rx_discards, &nes->rx_discards);
874 ice_dcf_stat_update_48(&oes->tx_bytes, &nes->tx_bytes);
875 ice_dcf_stat_update_48(&oes->tx_unicast, &nes->tx_unicast);
876 ice_dcf_stat_update_48(&oes->tx_multicast, &nes->tx_multicast);
877 ice_dcf_stat_update_48(&oes->tx_broadcast, &nes->tx_broadcast);
878 ice_dcf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
879 ice_dcf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
884 ice_dcf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
886 struct ice_dcf_adapter *ad = dev->data->dev_private;
887 struct ice_dcf_hw *hw = &ad->real_hw;
888 struct virtchnl_eth_stats pstats;
893 "The DCF has been reset by PF, please reinit first");
897 ret = ice_dcf_query_stats(hw, &pstats);
899 ice_dcf_update_stats(&hw->eth_stats_offset, &pstats);
900 stats->ipackets = pstats.rx_unicast + pstats.rx_multicast +
901 pstats.rx_broadcast - pstats.rx_discards;
902 stats->opackets = pstats.tx_broadcast + pstats.tx_multicast +
904 stats->imissed = pstats.rx_discards;
905 stats->oerrors = pstats.tx_errors + pstats.tx_discards;
906 stats->ibytes = pstats.rx_bytes;
907 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN;
908 stats->obytes = pstats.tx_bytes;
910 PMD_DRV_LOG(ERR, "Get statistics failed");
916 ice_dcf_stats_reset(struct rte_eth_dev *dev)
918 struct ice_dcf_adapter *ad = dev->data->dev_private;
919 struct ice_dcf_hw *hw = &ad->real_hw;
920 struct virtchnl_eth_stats pstats;
926 /* read stat values to clear hardware registers */
927 ret = ice_dcf_query_stats(hw, &pstats);
931 /* set stats offset base on current values */
932 hw->eth_stats_offset = pstats;
938 ice_dcf_free_repr_info(struct ice_dcf_adapter *dcf_adapter)
940 if (dcf_adapter->repr_infos) {
941 rte_free(dcf_adapter->repr_infos);
942 dcf_adapter->repr_infos = NULL;
947 ice_dcf_init_repr_info(struct ice_dcf_adapter *dcf_adapter)
949 dcf_adapter->repr_infos =
950 rte_calloc("ice_dcf_rep_info",
951 dcf_adapter->real_hw.num_vfs,
952 sizeof(dcf_adapter->repr_infos[0]), 0);
953 if (!dcf_adapter->repr_infos) {
954 PMD_DRV_LOG(ERR, "Failed to alloc memory for VF representors\n");
962 ice_dcf_dev_close(struct rte_eth_dev *dev)
964 struct ice_dcf_adapter *adapter = dev->data->dev_private;
966 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
969 (void)ice_dcf_dev_stop(dev);
971 ice_free_queues(dev);
973 ice_dcf_free_repr_info(adapter);
974 ice_dcf_uninit_parent_adapter(dev);
975 ice_dcf_uninit_hw(dev, &adapter->real_hw);
981 ice_dcf_link_update(struct rte_eth_dev *dev,
982 __rte_unused int wait_to_complete)
984 struct ice_dcf_adapter *ad = dev->data->dev_private;
985 struct ice_dcf_hw *hw = &ad->real_hw;
986 struct rte_eth_link new_link;
988 memset(&new_link, 0, sizeof(new_link));
990 /* Only read status info stored in VF, and the info is updated
991 * when receive LINK_CHANGE event from PF by virtchnl.
993 switch (hw->link_speed) {
995 new_link.link_speed = RTE_ETH_SPEED_NUM_10M;
998 new_link.link_speed = RTE_ETH_SPEED_NUM_100M;
1001 new_link.link_speed = RTE_ETH_SPEED_NUM_1G;
1004 new_link.link_speed = RTE_ETH_SPEED_NUM_10G;
1007 new_link.link_speed = RTE_ETH_SPEED_NUM_20G;
1010 new_link.link_speed = RTE_ETH_SPEED_NUM_25G;
1013 new_link.link_speed = RTE_ETH_SPEED_NUM_40G;
1016 new_link.link_speed = RTE_ETH_SPEED_NUM_50G;
1019 new_link.link_speed = RTE_ETH_SPEED_NUM_100G;
1022 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
1026 new_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1027 new_link.link_status = hw->link_up ? RTE_ETH_LINK_UP :
1029 new_link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1030 RTE_ETH_LINK_SPEED_FIXED);
1032 return rte_eth_linkstatus_set(dev, &new_link);
1036 ice_dcf_adminq_need_retry(struct ice_adapter *ad)
1038 return ad->hw.dcf_enabled &&
1039 !__atomic_load_n(&ad->dcf_state_on, __ATOMIC_RELAXED);
1042 /* Add UDP tunneling port */
1044 ice_dcf_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
1045 struct rte_eth_udp_tunnel *udp_tunnel)
1047 struct ice_dcf_adapter *adapter = dev->data->dev_private;
1048 struct ice_adapter *parent_adapter = &adapter->parent;
1049 struct ice_hw *parent_hw = &parent_adapter->hw;
1055 switch (udp_tunnel->prot_type) {
1056 case RTE_ETH_TUNNEL_TYPE_VXLAN:
1057 ret = ice_create_tunnel(parent_hw, TNL_VXLAN,
1058 udp_tunnel->udp_port);
1060 case RTE_ETH_TUNNEL_TYPE_ECPRI:
1061 ret = ice_create_tunnel(parent_hw, TNL_ECPRI,
1062 udp_tunnel->udp_port);
1065 PMD_DRV_LOG(ERR, "Invalid tunnel type");
1073 /* Delete UDP tunneling port */
1075 ice_dcf_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
1076 struct rte_eth_udp_tunnel *udp_tunnel)
1078 struct ice_dcf_adapter *adapter = dev->data->dev_private;
1079 struct ice_adapter *parent_adapter = &adapter->parent;
1080 struct ice_hw *parent_hw = &parent_adapter->hw;
1086 switch (udp_tunnel->prot_type) {
1087 case RTE_ETH_TUNNEL_TYPE_VXLAN:
1088 case RTE_ETH_TUNNEL_TYPE_ECPRI:
1089 ret = ice_destroy_tunnel(parent_hw, udp_tunnel->udp_port, 0);
1092 PMD_DRV_LOG(ERR, "Invalid tunnel type");
1101 ice_dcf_tm_ops_get(struct rte_eth_dev *dev __rte_unused,
1107 *(const void **)arg = &ice_dcf_tm_ops;
1113 ice_dcf_reset_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw)
1115 ice_dcf_uninit_hw(eth_dev, hw);
1116 ice_dcf_init_hw(eth_dev, hw);
1119 /* Check if reset has been triggered by PF */
1121 ice_dcf_is_reset(struct rte_eth_dev *dev)
1123 struct ice_dcf_adapter *ad = dev->data->dev_private;
1124 struct iavf_hw *hw = &ad->real_hw.avf;
1126 return !(IAVF_READ_REG(hw, IAVF_VF_ARQLEN1) &
1127 IAVF_VF_ARQLEN1_ARQENABLE_MASK);
1131 ice_dcf_dev_reset(struct rte_eth_dev *dev)
1133 struct ice_dcf_adapter *ad = dev->data->dev_private;
1134 struct ice_dcf_hw *hw = &ad->real_hw;
1137 if (ice_dcf_is_reset(dev)) {
1138 if (!ad->real_hw.resetting)
1139 ad->real_hw.resetting = true;
1140 PMD_DRV_LOG(ERR, "The DCF has been reset by PF");
1143 * Simply reset hw to trigger an additional DCF enable/disable
1144 * cycle which help to workaround the issue that kernel driver
1145 * may not clean up resource during previous reset.
1147 ice_dcf_reset_hw(dev, hw);
1150 ret = ice_dcf_dev_uninit(dev);
1154 ret = ice_dcf_dev_init(dev);
1159 static const struct eth_dev_ops ice_dcf_eth_dev_ops = {
1160 .dev_start = ice_dcf_dev_start,
1161 .dev_stop = ice_dcf_dev_stop,
1162 .dev_close = ice_dcf_dev_close,
1163 .dev_reset = ice_dcf_dev_reset,
1164 .dev_configure = ice_dcf_dev_configure,
1165 .dev_infos_get = ice_dcf_dev_info_get,
1166 .rx_queue_setup = ice_rx_queue_setup,
1167 .tx_queue_setup = ice_tx_queue_setup,
1168 .rx_queue_release = ice_dev_rx_queue_release,
1169 .tx_queue_release = ice_dev_tx_queue_release,
1170 .rx_queue_start = ice_dcf_rx_queue_start,
1171 .tx_queue_start = ice_dcf_tx_queue_start,
1172 .rx_queue_stop = ice_dcf_rx_queue_stop,
1173 .tx_queue_stop = ice_dcf_tx_queue_stop,
1174 .link_update = ice_dcf_link_update,
1175 .stats_get = ice_dcf_stats_get,
1176 .stats_reset = ice_dcf_stats_reset,
1177 .promiscuous_enable = ice_dcf_dev_promiscuous_enable,
1178 .promiscuous_disable = ice_dcf_dev_promiscuous_disable,
1179 .allmulticast_enable = ice_dcf_dev_allmulticast_enable,
1180 .allmulticast_disable = ice_dcf_dev_allmulticast_disable,
1181 .flow_ops_get = ice_dcf_dev_flow_ops_get,
1182 .udp_tunnel_port_add = ice_dcf_dev_udp_tunnel_port_add,
1183 .udp_tunnel_port_del = ice_dcf_dev_udp_tunnel_port_del,
1184 .tm_ops_get = ice_dcf_tm_ops_get,
1185 .reta_update = ice_dcf_dev_rss_reta_update,
1186 .reta_query = ice_dcf_dev_rss_reta_query,
1190 ice_dcf_dev_init(struct rte_eth_dev *eth_dev)
1192 struct ice_dcf_adapter *adapter = eth_dev->data->dev_private;
1193 struct ice_adapter *parent_adapter = &adapter->parent;
1195 eth_dev->dev_ops = &ice_dcf_eth_dev_ops;
1196 eth_dev->rx_pkt_burst = ice_dcf_recv_pkts;
1197 eth_dev->tx_pkt_burst = ice_dcf_xmit_pkts;
1199 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1202 adapter->real_hw.vc_event_msg_cb = ice_dcf_handle_pf_event_msg;
1203 if (ice_dcf_init_hw(eth_dev, &adapter->real_hw) != 0) {
1204 PMD_INIT_LOG(ERR, "Failed to init DCF hardware");
1205 __atomic_store_n(&parent_adapter->dcf_state_on, false,
1210 __atomic_store_n(&parent_adapter->dcf_state_on, true, __ATOMIC_RELAXED);
1212 if (ice_dcf_init_parent_adapter(eth_dev) != 0) {
1213 PMD_INIT_LOG(ERR, "Failed to init DCF parent adapter");
1214 ice_dcf_uninit_hw(eth_dev, &adapter->real_hw);
1222 ice_dcf_dev_uninit(struct rte_eth_dev *eth_dev)
1224 ice_dcf_dev_close(eth_dev);
1230 ice_dcf_cap_check_handler(__rte_unused const char *key,
1231 const char *value, __rte_unused void *opaque)
1233 if (strcmp(value, "dcf"))
1240 ice_dcf_cap_selected(struct rte_devargs *devargs)
1242 struct rte_kvargs *kvlist;
1243 const char *key = "cap";
1246 if (devargs == NULL)
1249 kvlist = rte_kvargs_parse(devargs->args, NULL);
1253 if (!rte_kvargs_count(kvlist, key))
1256 /* dcf capability selected when there's a key-value pair: cap=dcf */
1257 if (rte_kvargs_process(kvlist, key,
1258 ice_dcf_cap_check_handler, NULL) < 0)
1264 rte_kvargs_free(kvlist);
1269 eth_ice_dcf_pci_probe(__rte_unused struct rte_pci_driver *pci_drv,
1270 struct rte_pci_device *pci_dev)
1272 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
1273 struct ice_dcf_vf_repr_param repr_param;
1274 char repr_name[RTE_ETH_NAME_MAX_LEN];
1275 struct ice_dcf_adapter *dcf_adapter;
1276 struct rte_eth_dev *dcf_ethdev;
1277 uint16_t dcf_vsi_id;
1280 if (!ice_dcf_cap_selected(pci_dev->device.devargs))
1283 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, ð_da);
1287 ret = rte_eth_dev_pci_generic_probe(pci_dev,
1288 sizeof(struct ice_dcf_adapter),
1290 if (ret || !eth_da.nb_representor_ports)
1292 if (eth_da.type != RTE_ETH_REPRESENTOR_VF)
1295 dcf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1296 if (dcf_ethdev == NULL)
1299 dcf_adapter = dcf_ethdev->data->dev_private;
1300 ret = ice_dcf_init_repr_info(dcf_adapter);
1304 if (eth_da.nb_representor_ports > dcf_adapter->real_hw.num_vfs ||
1305 eth_da.nb_representor_ports >= RTE_MAX_ETHPORTS) {
1306 PMD_DRV_LOG(ERR, "the number of port representors is too large: %u",
1307 eth_da.nb_representor_ports);
1308 ice_dcf_free_repr_info(dcf_adapter);
1312 dcf_vsi_id = dcf_adapter->real_hw.vsi_id | VIRTCHNL_DCF_VF_VSI_VALID;
1314 repr_param.dcf_eth_dev = dcf_ethdev;
1315 repr_param.switch_domain_id = 0;
1317 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1318 uint16_t vf_id = eth_da.representor_ports[i];
1319 struct rte_eth_dev *vf_rep_eth_dev;
1321 if (vf_id >= dcf_adapter->real_hw.num_vfs) {
1322 PMD_DRV_LOG(ERR, "VF ID %u is out of range (0 ~ %u)",
1323 vf_id, dcf_adapter->real_hw.num_vfs - 1);
1328 if (dcf_adapter->real_hw.vf_vsi_map[vf_id] == dcf_vsi_id) {
1329 PMD_DRV_LOG(ERR, "VF ID %u is DCF's ID.\n", vf_id);
1334 repr_param.vf_id = vf_id;
1335 snprintf(repr_name, sizeof(repr_name), "net_%s_representor_%u",
1336 pci_dev->device.name, vf_id);
1337 ret = rte_eth_dev_create(&pci_dev->device, repr_name,
1338 sizeof(struct ice_dcf_vf_repr),
1339 NULL, NULL, ice_dcf_vf_repr_init,
1342 PMD_DRV_LOG(ERR, "failed to create DCF VF representor %s",
1347 vf_rep_eth_dev = rte_eth_dev_allocated(repr_name);
1348 if (!vf_rep_eth_dev) {
1350 "Failed to find the ethdev for DCF VF representor: %s",
1356 dcf_adapter->repr_infos[vf_id].vf_rep_eth_dev = vf_rep_eth_dev;
1357 dcf_adapter->num_reprs++;
1364 eth_ice_dcf_pci_remove(struct rte_pci_device *pci_dev)
1366 struct rte_eth_dev *eth_dev;
1368 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1372 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1373 return rte_eth_dev_pci_generic_remove(pci_dev,
1374 ice_dcf_vf_repr_uninit);
1376 return rte_eth_dev_pci_generic_remove(pci_dev,
1377 ice_dcf_dev_uninit);
1380 static const struct rte_pci_id pci_id_ice_dcf_map[] = {
1381 { RTE_PCI_DEVICE(IAVF_INTEL_VENDOR_ID, IAVF_DEV_ID_ADAPTIVE_VF) },
1382 { .vendor_id = 0, /* sentinel */ },
1385 static struct rte_pci_driver rte_ice_dcf_pmd = {
1386 .id_table = pci_id_ice_dcf_map,
1387 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1388 .probe = eth_ice_dcf_pci_probe,
1389 .remove = eth_ice_dcf_pci_remove,
1392 RTE_PMD_REGISTER_PCI(net_ice_dcf, rte_ice_dcf_pmd);
1393 RTE_PMD_REGISTER_PCI_TABLE(net_ice_dcf, pci_id_ice_dcf_map);
1394 RTE_PMD_REGISTER_KMOD_DEP(net_ice_dcf, "* igb_uio | vfio-pci");
1395 RTE_PMD_REGISTER_PARAM_STRING(net_ice_dcf, "cap=dcf");