1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
18 #include "rte_pmd_ice.h"
19 #include "ice_ethdev.h"
21 #include "ice_generic_flow.h"
24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
26 #define ICE_PROTO_XTR_ARG "proto_xtr"
28 static const char * const ice_valid_args[] = {
29 ICE_SAFE_MODE_SUPPORT_ARG,
30 ICE_PIPELINE_MODE_SUPPORT_ARG,
35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
36 .name = "intel_pmd_dynfield_proto_xtr_metadata",
37 .size = sizeof(uint32_t),
38 .align = __alignof__(uint32_t),
42 struct proto_xtr_ol_flag {
43 const struct rte_mbuf_dynflag param;
48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
52 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
55 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
58 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
60 [PROTO_XTR_IPV6_FLOW] = {
61 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
64 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
66 [PROTO_XTR_IP_OFFSET] = {
67 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
68 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
71 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
73 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
74 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
75 #define ICE_MAX_RES_DESC_NUM 1024
77 static int ice_dev_configure(struct rte_eth_dev *dev);
78 static int ice_dev_start(struct rte_eth_dev *dev);
79 static int ice_dev_stop(struct rte_eth_dev *dev);
80 static int ice_dev_close(struct rte_eth_dev *dev);
81 static int ice_dev_reset(struct rte_eth_dev *dev);
82 static int ice_dev_info_get(struct rte_eth_dev *dev,
83 struct rte_eth_dev_info *dev_info);
84 static int ice_link_update(struct rte_eth_dev *dev,
85 int wait_to_complete);
86 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
87 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
89 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
90 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
91 static int ice_rss_reta_update(struct rte_eth_dev *dev,
92 struct rte_eth_rss_reta_entry64 *reta_conf,
94 static int ice_rss_reta_query(struct rte_eth_dev *dev,
95 struct rte_eth_rss_reta_entry64 *reta_conf,
97 static int ice_rss_hash_update(struct rte_eth_dev *dev,
98 struct rte_eth_rss_conf *rss_conf);
99 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
100 struct rte_eth_rss_conf *rss_conf);
101 static int ice_promisc_enable(struct rte_eth_dev *dev);
102 static int ice_promisc_disable(struct rte_eth_dev *dev);
103 static int ice_allmulti_enable(struct rte_eth_dev *dev);
104 static int ice_allmulti_disable(struct rte_eth_dev *dev);
105 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
108 static int ice_macaddr_set(struct rte_eth_dev *dev,
109 struct rte_ether_addr *mac_addr);
110 static int ice_macaddr_add(struct rte_eth_dev *dev,
111 struct rte_ether_addr *mac_addr,
112 __rte_unused uint32_t index,
114 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
115 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
117 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
119 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
121 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
122 uint16_t pvid, int on);
123 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
124 static int ice_get_eeprom(struct rte_eth_dev *dev,
125 struct rte_dev_eeprom_info *eeprom);
126 static int ice_stats_get(struct rte_eth_dev *dev,
127 struct rte_eth_stats *stats);
128 static int ice_stats_reset(struct rte_eth_dev *dev);
129 static int ice_xstats_get(struct rte_eth_dev *dev,
130 struct rte_eth_xstat *xstats, unsigned int n);
131 static int ice_xstats_get_names(struct rte_eth_dev *dev,
132 struct rte_eth_xstat_name *xstats_names,
134 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
135 enum rte_filter_type filter_type,
136 enum rte_filter_op filter_op,
138 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
139 struct rte_eth_udp_tunnel *udp_tunnel);
140 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
141 struct rte_eth_udp_tunnel *udp_tunnel);
143 static const struct rte_pci_id pci_id_ice_map[] = {
144 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
145 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
146 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
147 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
148 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
149 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
150 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
157 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
159 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
164 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
165 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
166 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
167 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
168 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
169 { .vendor_id = 0, /* sentinel */ },
172 static const struct eth_dev_ops ice_eth_dev_ops = {
173 .dev_configure = ice_dev_configure,
174 .dev_start = ice_dev_start,
175 .dev_stop = ice_dev_stop,
176 .dev_close = ice_dev_close,
177 .dev_reset = ice_dev_reset,
178 .dev_set_link_up = ice_dev_set_link_up,
179 .dev_set_link_down = ice_dev_set_link_down,
180 .rx_queue_start = ice_rx_queue_start,
181 .rx_queue_stop = ice_rx_queue_stop,
182 .tx_queue_start = ice_tx_queue_start,
183 .tx_queue_stop = ice_tx_queue_stop,
184 .rx_queue_setup = ice_rx_queue_setup,
185 .rx_queue_release = ice_rx_queue_release,
186 .tx_queue_setup = ice_tx_queue_setup,
187 .tx_queue_release = ice_tx_queue_release,
188 .dev_infos_get = ice_dev_info_get,
189 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
190 .link_update = ice_link_update,
191 .mtu_set = ice_mtu_set,
192 .mac_addr_set = ice_macaddr_set,
193 .mac_addr_add = ice_macaddr_add,
194 .mac_addr_remove = ice_macaddr_remove,
195 .vlan_filter_set = ice_vlan_filter_set,
196 .vlan_offload_set = ice_vlan_offload_set,
197 .reta_update = ice_rss_reta_update,
198 .reta_query = ice_rss_reta_query,
199 .rss_hash_update = ice_rss_hash_update,
200 .rss_hash_conf_get = ice_rss_hash_conf_get,
201 .promiscuous_enable = ice_promisc_enable,
202 .promiscuous_disable = ice_promisc_disable,
203 .allmulticast_enable = ice_allmulti_enable,
204 .allmulticast_disable = ice_allmulti_disable,
205 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
206 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
207 .fw_version_get = ice_fw_version_get,
208 .vlan_pvid_set = ice_vlan_pvid_set,
209 .rxq_info_get = ice_rxq_info_get,
210 .txq_info_get = ice_txq_info_get,
211 .rx_burst_mode_get = ice_rx_burst_mode_get,
212 .tx_burst_mode_get = ice_tx_burst_mode_get,
213 .get_eeprom_length = ice_get_eeprom_length,
214 .get_eeprom = ice_get_eeprom,
215 .stats_get = ice_stats_get,
216 .stats_reset = ice_stats_reset,
217 .xstats_get = ice_xstats_get,
218 .xstats_get_names = ice_xstats_get_names,
219 .xstats_reset = ice_stats_reset,
220 .filter_ctrl = ice_dev_filter_ctrl,
221 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
222 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
223 .tx_done_cleanup = ice_tx_done_cleanup,
224 .get_monitor_addr = ice_get_monitor_addr,
227 /* store statistics names and its offset in stats structure */
228 struct ice_xstats_name_off {
229 char name[RTE_ETH_XSTATS_NAME_SIZE];
233 static const struct ice_xstats_name_off ice_stats_strings[] = {
234 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
235 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
236 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
237 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
238 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
239 rx_unknown_protocol)},
240 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
241 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
242 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
243 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
246 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
247 sizeof(ice_stats_strings[0]))
249 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
250 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
251 tx_dropped_link_down)},
252 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
253 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
255 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
256 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
258 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
260 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
262 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
263 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
264 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
265 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
266 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
267 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
269 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
271 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
273 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
275 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
277 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
279 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
281 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
283 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
284 mac_short_pkt_dropped)},
285 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
287 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
288 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
289 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
291 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
293 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
295 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
297 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
299 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
303 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
304 sizeof(ice_hw_port_strings[0]))
307 ice_init_controlq_parameter(struct ice_hw *hw)
309 /* fields for adminq */
310 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
311 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
312 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
313 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
315 /* fields for mailboxq, DPDK used as PF host */
316 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
317 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
318 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
319 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
323 lookup_proto_xtr_type(const char *xtr_name)
327 enum proto_xtr_type type;
329 { "vlan", PROTO_XTR_VLAN },
330 { "ipv4", PROTO_XTR_IPV4 },
331 { "ipv6", PROTO_XTR_IPV6 },
332 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
333 { "tcp", PROTO_XTR_TCP },
334 { "ip_offset", PROTO_XTR_IP_OFFSET },
338 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
339 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
340 return xtr_type_map[i].type;
347 * Parse elem, the elem could be single number/range or '(' ')' group
348 * 1) A single number elem, it's just a simple digit. e.g. 9
349 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
350 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
351 * Within group elem, '-' used for a range separator;
352 * ',' used for a single number.
355 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
357 const char *str = input;
362 while (isblank(*str))
365 if (!isdigit(*str) && *str != '(')
368 /* process single number or single range of number */
371 idx = strtoul(str, &end, 10);
372 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
375 while (isblank(*end))
381 /* process single <number>-<number> */
384 while (isblank(*end))
390 idx = strtoul(end, &end, 10);
391 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
395 while (isblank(*end))
402 for (idx = RTE_MIN(min, max);
403 idx <= RTE_MAX(min, max); idx++)
404 devargs->proto_xtr[idx] = xtr_type;
409 /* process set within bracket */
411 while (isblank(*str))
416 min = ICE_MAX_QUEUE_NUM;
418 /* go ahead to the first digit */
419 while (isblank(*str))
424 /* get the digit value */
426 idx = strtoul(str, &end, 10);
427 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
430 /* go ahead to separator '-',',' and ')' */
431 while (isblank(*end))
434 if (min == ICE_MAX_QUEUE_NUM)
436 else /* avoid continuous '-' */
438 } else if (*end == ',' || *end == ')') {
440 if (min == ICE_MAX_QUEUE_NUM)
443 for (idx = RTE_MIN(min, max);
444 idx <= RTE_MAX(min, max); idx++)
445 devargs->proto_xtr[idx] = xtr_type;
447 min = ICE_MAX_QUEUE_NUM;
453 } while (*end != ')' && *end != '\0');
459 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
461 const char *queue_start;
466 while (isblank(*queues))
469 if (*queues != '[') {
470 xtr_type = lookup_proto_xtr_type(queues);
474 devargs->proto_xtr_dflt = xtr_type;
481 while (isblank(*queues))
486 queue_start = queues;
488 /* go across a complete bracket */
489 if (*queue_start == '(') {
490 queues += strcspn(queues, ")");
495 /* scan the separator ':' */
496 queues += strcspn(queues, ":");
497 if (*queues++ != ':')
499 while (isblank(*queues))
502 for (idx = 0; ; idx++) {
503 if (isblank(queues[idx]) ||
504 queues[idx] == ',' ||
505 queues[idx] == ']' ||
509 if (idx > sizeof(xtr_name) - 2)
512 xtr_name[idx] = queues[idx];
514 xtr_name[idx] = '\0';
515 xtr_type = lookup_proto_xtr_type(xtr_name);
521 while (isblank(*queues) || *queues == ',' || *queues == ']')
524 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
526 } while (*queues != '\0');
532 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
535 struct ice_devargs *devargs = extra_args;
537 if (value == NULL || extra_args == NULL)
540 if (parse_queue_proto_xtr(value, devargs) < 0) {
542 "The protocol extraction parameter is wrong : '%s'",
551 ice_check_proto_xtr_support(struct ice_hw *hw)
553 #define FLX_REG(val, fld, idx) \
554 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
555 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
562 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
564 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
565 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
567 ICE_PROT_IPV4_OF_OR_S,
568 ICE_PROT_IPV4_OF_OR_S },
569 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
571 ICE_PROT_IPV6_OF_OR_S,
572 ICE_PROT_IPV6_OF_OR_S },
573 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
575 ICE_PROT_IPV6_OF_OR_S,
576 ICE_PROT_IPV6_OF_OR_S },
577 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
579 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
580 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
582 ICE_PROT_IPV4_OF_OR_S,
583 ICE_PROT_IPV6_OF_OR_S },
587 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
588 uint32_t rxdid = xtr_sets[i].rxdid;
591 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
592 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
594 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
595 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
596 ice_proto_xtr_hw_support[i] = true;
599 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
600 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
602 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
603 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
604 ice_proto_xtr_hw_support[i] = true;
610 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
613 struct pool_entry *entry;
618 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
621 "Failed to allocate memory for resource pool");
625 /* queue heap initialize */
626 pool->num_free = num;
629 LIST_INIT(&pool->alloc_list);
630 LIST_INIT(&pool->free_list);
632 /* Initialize element */
636 LIST_INSERT_HEAD(&pool->free_list, entry, next);
641 ice_res_pool_alloc(struct ice_res_pool_info *pool,
644 struct pool_entry *entry, *valid_entry;
647 PMD_INIT_LOG(ERR, "Invalid parameter");
651 if (pool->num_free < num) {
652 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
653 num, pool->num_free);
658 /* Lookup in free list and find most fit one */
659 LIST_FOREACH(entry, &pool->free_list, next) {
660 if (entry->len >= num) {
662 if (entry->len == num) {
667 valid_entry->len > entry->len)
672 /* Not find one to satisfy the request, return */
674 PMD_INIT_LOG(ERR, "No valid entry found");
678 * The entry have equal queue number as requested,
679 * remove it from alloc_list.
681 if (valid_entry->len == num) {
682 LIST_REMOVE(valid_entry, next);
685 * The entry have more numbers than requested,
686 * create a new entry for alloc_list and minus its
687 * queue base and number in free_list.
689 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
692 "Failed to allocate memory for "
696 entry->base = valid_entry->base;
698 valid_entry->base += num;
699 valid_entry->len -= num;
703 /* Insert it into alloc list, not sorted */
704 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
706 pool->num_free -= valid_entry->len;
707 pool->num_alloc += valid_entry->len;
709 return valid_entry->base + pool->base;
713 ice_res_pool_destroy(struct ice_res_pool_info *pool)
715 struct pool_entry *entry, *next_entry;
720 for (entry = LIST_FIRST(&pool->alloc_list);
721 entry && (next_entry = LIST_NEXT(entry, next), 1);
722 entry = next_entry) {
723 LIST_REMOVE(entry, next);
727 for (entry = LIST_FIRST(&pool->free_list);
728 entry && (next_entry = LIST_NEXT(entry, next), 1);
729 entry = next_entry) {
730 LIST_REMOVE(entry, next);
737 LIST_INIT(&pool->alloc_list);
738 LIST_INIT(&pool->free_list);
742 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
744 /* Set VSI LUT selection */
745 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
746 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
747 /* Set Hash scheme */
748 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
749 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
751 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
754 static enum ice_status
755 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
756 struct ice_aqc_vsi_props *info,
757 uint8_t enabled_tcmap)
759 uint16_t bsf, qp_idx;
761 /* default tc 0 now. Multi-TC supporting need to be done later.
762 * Configure TC and queue mapping parameters, for enabled TC,
763 * allocate qpnum_per_tc queues to this traffic.
765 if (enabled_tcmap != 0x01) {
766 PMD_INIT_LOG(ERR, "only TC0 is supported");
770 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
771 bsf = rte_bsf32(vsi->nb_qps);
772 /* Adjust the queue number to actual queues that can be applied */
773 vsi->nb_qps = 0x1 << bsf;
776 /* Set tc and queue mapping with VSI */
777 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
778 ICE_AQ_VSI_TC_Q_OFFSET_S) |
779 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
781 /* Associate queue number with VSI */
782 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
783 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
784 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
785 info->valid_sections |=
786 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
787 /* Set the info.ingress_table and info.egress_table
788 * for UP translate table. Now just set it to 1:1 map by default
789 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
791 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
792 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
793 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
794 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
799 ice_init_mac_address(struct rte_eth_dev *dev)
801 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
803 if (!rte_is_unicast_ether_addr
804 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
805 PMD_INIT_LOG(ERR, "Invalid MAC address");
810 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
811 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
813 dev->data->mac_addrs =
814 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
815 if (!dev->data->mac_addrs) {
817 "Failed to allocate memory to store mac address");
820 /* store it to dev data */
822 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
823 &dev->data->mac_addrs[0]);
827 /* Find out specific MAC filter */
828 static struct ice_mac_filter *
829 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
831 struct ice_mac_filter *f;
833 TAILQ_FOREACH(f, &vsi->mac_list, next) {
834 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
842 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
844 struct ice_fltr_list_entry *m_list_itr = NULL;
845 struct ice_mac_filter *f;
846 struct LIST_HEAD_TYPE list_head;
847 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
850 /* If it's added and configured, return */
851 f = ice_find_mac_filter(vsi, mac_addr);
853 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
857 INIT_LIST_HEAD(&list_head);
859 m_list_itr = (struct ice_fltr_list_entry *)
860 ice_malloc(hw, sizeof(*m_list_itr));
865 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
866 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
867 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
868 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
869 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
870 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
871 m_list_itr->fltr_info.vsi_handle = vsi->idx;
873 LIST_ADD(&m_list_itr->list_entry, &list_head);
876 ret = ice_add_mac(hw, &list_head);
877 if (ret != ICE_SUCCESS) {
878 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
882 /* Add the mac addr into mac list */
883 f = rte_zmalloc(NULL, sizeof(*f), 0);
885 PMD_DRV_LOG(ERR, "failed to allocate memory");
889 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
890 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
896 rte_free(m_list_itr);
901 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
903 struct ice_fltr_list_entry *m_list_itr = NULL;
904 struct ice_mac_filter *f;
905 struct LIST_HEAD_TYPE list_head;
906 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
909 /* Can't find it, return an error */
910 f = ice_find_mac_filter(vsi, mac_addr);
914 INIT_LIST_HEAD(&list_head);
916 m_list_itr = (struct ice_fltr_list_entry *)
917 ice_malloc(hw, sizeof(*m_list_itr));
922 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
923 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
924 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
925 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
926 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
927 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
928 m_list_itr->fltr_info.vsi_handle = vsi->idx;
930 LIST_ADD(&m_list_itr->list_entry, &list_head);
932 /* remove the mac filter */
933 ret = ice_remove_mac(hw, &list_head);
934 if (ret != ICE_SUCCESS) {
935 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
940 /* Remove the mac addr from mac list */
941 TAILQ_REMOVE(&vsi->mac_list, f, next);
947 rte_free(m_list_itr);
951 /* Find out specific VLAN filter */
952 static struct ice_vlan_filter *
953 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
955 struct ice_vlan_filter *f;
957 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
958 if (vlan_id == f->vlan_info.vlan_id)
966 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
968 struct ice_fltr_list_entry *v_list_itr = NULL;
969 struct ice_vlan_filter *f;
970 struct LIST_HEAD_TYPE list_head;
974 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
977 hw = ICE_VSI_TO_HW(vsi);
979 /* If it's added and configured, return. */
980 f = ice_find_vlan_filter(vsi, vlan_id);
982 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
986 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
989 INIT_LIST_HEAD(&list_head);
991 v_list_itr = (struct ice_fltr_list_entry *)
992 ice_malloc(hw, sizeof(*v_list_itr));
997 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
998 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
999 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1000 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1001 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1002 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1004 LIST_ADD(&v_list_itr->list_entry, &list_head);
1007 ret = ice_add_vlan(hw, &list_head);
1008 if (ret != ICE_SUCCESS) {
1009 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1014 /* Add vlan into vlan list */
1015 f = rte_zmalloc(NULL, sizeof(*f), 0);
1017 PMD_DRV_LOG(ERR, "failed to allocate memory");
1021 f->vlan_info.vlan_id = vlan_id;
1022 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1028 rte_free(v_list_itr);
1033 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1035 struct ice_fltr_list_entry *v_list_itr = NULL;
1036 struct ice_vlan_filter *f;
1037 struct LIST_HEAD_TYPE list_head;
1042 * Vlan 0 is the generic filter for untagged packets
1043 * and can't be removed.
1045 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1048 hw = ICE_VSI_TO_HW(vsi);
1050 /* Can't find it, return an error */
1051 f = ice_find_vlan_filter(vsi, vlan_id);
1055 INIT_LIST_HEAD(&list_head);
1057 v_list_itr = (struct ice_fltr_list_entry *)
1058 ice_malloc(hw, sizeof(*v_list_itr));
1064 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1065 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1066 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1067 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1068 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1069 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1071 LIST_ADD(&v_list_itr->list_entry, &list_head);
1073 /* remove the vlan filter */
1074 ret = ice_remove_vlan(hw, &list_head);
1075 if (ret != ICE_SUCCESS) {
1076 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1081 /* Remove the vlan id from vlan list */
1082 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1088 rte_free(v_list_itr);
1093 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1095 struct ice_mac_filter *m_f;
1096 struct ice_vlan_filter *v_f;
1099 if (!vsi || !vsi->mac_num)
1102 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1103 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1104 if (ret != ICE_SUCCESS) {
1110 if (vsi->vlan_num == 0)
1113 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1114 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1115 if (ret != ICE_SUCCESS) {
1126 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1128 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1129 struct ice_vsi_ctx ctxt;
1133 /* Check if it has been already on or off */
1134 if (vsi->info.valid_sections &
1135 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1137 if ((vsi->info.outer_vlan_flags &
1138 ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST) ==
1139 ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST)
1140 return 0; /* already on */
1142 if (!(vsi->info.outer_vlan_flags &
1143 ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST))
1144 return 0; /* already off */
1149 qinq_flags = ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST;
1152 /* clear global insertion and use per packet insertion */
1153 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT);
1154 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST);
1155 vsi->info.outer_vlan_flags |= qinq_flags;
1156 /* use default vlan type 0x8100 */
1157 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1158 vsi->info.outer_vlan_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1159 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1160 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1161 ctxt.info.valid_sections =
1162 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1163 ctxt.vsi_num = vsi->vsi_id;
1164 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1167 "Update VSI failed to %s qinq stripping",
1168 on ? "enable" : "disable");
1172 vsi->info.valid_sections |=
1173 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1179 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1181 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1182 struct ice_vsi_ctx ctxt;
1186 /* Check if it has been already on or off */
1187 if (vsi->info.valid_sections &
1188 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1190 if ((vsi->info.outer_vlan_flags &
1191 ICE_AQ_VSI_OUTER_VLAN_EMODE_M) ==
1192 ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW)
1193 return 0; /* already on */
1195 if ((vsi->info.outer_vlan_flags &
1196 ICE_AQ_VSI_OUTER_VLAN_EMODE_M) ==
1197 ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH)
1198 return 0; /* already off */
1203 qinq_flags = ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW;
1205 qinq_flags = ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH;
1206 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M);
1207 vsi->info.outer_vlan_flags |= qinq_flags;
1208 /* use default vlan type 0x8100 */
1209 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1210 vsi->info.outer_vlan_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1211 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1212 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1213 ctxt.info.valid_sections =
1214 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1215 ctxt.vsi_num = vsi->vsi_id;
1216 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1219 "Update VSI failed to %s qinq stripping",
1220 on ? "enable" : "disable");
1224 vsi->info.valid_sections |=
1225 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1231 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1235 ret = ice_vsi_config_qinq_stripping(vsi, on);
1237 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1239 ret = ice_vsi_config_qinq_insertion(vsi, on);
1241 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1248 ice_pf_enable_irq0(struct ice_hw *hw)
1250 /* reset the registers */
1251 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1252 ICE_READ_REG(hw, PFINT_OICR);
1255 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1256 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1257 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1259 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1260 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1261 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1262 PFINT_OICR_CTL_ITR_INDX_M) |
1263 PFINT_OICR_CTL_CAUSE_ENA_M);
1265 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1266 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1267 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1268 PFINT_FW_CTL_ITR_INDX_M) |
1269 PFINT_FW_CTL_CAUSE_ENA_M);
1271 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1274 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1275 GLINT_DYN_CTL_INTENA_M |
1276 GLINT_DYN_CTL_CLEARPBA_M |
1277 GLINT_DYN_CTL_ITR_INDX_M);
1284 ice_pf_disable_irq0(struct ice_hw *hw)
1286 /* Disable all interrupt types */
1287 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1293 ice_handle_aq_msg(struct rte_eth_dev *dev)
1295 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1296 struct ice_ctl_q_info *cq = &hw->adminq;
1297 struct ice_rq_event_info event;
1298 uint16_t pending, opcode;
1301 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1302 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1303 if (!event.msg_buf) {
1304 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1310 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1312 if (ret != ICE_SUCCESS) {
1314 "Failed to read msg from AdminQ, "
1316 hw->adminq.sq_last_status);
1319 opcode = rte_le_to_cpu_16(event.desc.opcode);
1322 case ice_aqc_opc_get_link_status:
1323 ret = ice_link_update(dev, 0);
1325 rte_eth_dev_callback_process
1326 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1329 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1334 rte_free(event.msg_buf);
1339 * Interrupt handler triggered by NIC for handling
1340 * specific interrupt.
1343 * Pointer to interrupt handle.
1345 * The address of parameter (struct rte_eth_dev *) regsitered before.
1351 ice_interrupt_handler(void *param)
1353 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1354 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1362 uint32_t int_fw_ctl;
1365 /* Disable interrupt */
1366 ice_pf_disable_irq0(hw);
1368 /* read out interrupt causes */
1369 oicr = ICE_READ_REG(hw, PFINT_OICR);
1371 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1374 /* No interrupt event indicated */
1375 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1376 PMD_DRV_LOG(INFO, "No interrupt event");
1381 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1382 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1383 ice_handle_aq_msg(dev);
1386 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1387 PMD_DRV_LOG(INFO, "OICR: link state change event");
1388 ret = ice_link_update(dev, 0);
1390 rte_eth_dev_callback_process
1391 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1395 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1396 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1397 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1398 if (reg & GL_MDET_TX_PQM_VALID_M) {
1399 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1400 GL_MDET_TX_PQM_PF_NUM_S;
1401 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1402 GL_MDET_TX_PQM_MAL_TYPE_S;
1403 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1404 GL_MDET_TX_PQM_QNUM_S;
1406 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1407 "%d by PQM on TX queue %d PF# %d",
1408 event, queue, pf_num);
1411 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1412 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1413 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1414 GL_MDET_TX_TCLAN_PF_NUM_S;
1415 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1416 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1417 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1418 GL_MDET_TX_TCLAN_QNUM_S;
1420 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1421 "%d by TCLAN on TX queue %d PF# %d",
1422 event, queue, pf_num);
1426 /* Enable interrupt */
1427 ice_pf_enable_irq0(hw);
1428 rte_intr_ack(dev->intr_handle);
1432 ice_init_proto_xtr(struct rte_eth_dev *dev)
1434 struct ice_adapter *ad =
1435 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1436 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1437 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1438 const struct proto_xtr_ol_flag *ol_flag;
1439 bool proto_xtr_enable = false;
1443 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1444 if (unlikely(pf->proto_xtr == NULL)) {
1445 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1449 for (i = 0; i < pf->lan_nb_qps; i++) {
1450 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1451 ad->devargs.proto_xtr[i] :
1452 ad->devargs.proto_xtr_dflt;
1454 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1455 uint8_t type = pf->proto_xtr[i];
1457 ice_proto_xtr_ol_flag_params[type].required = true;
1458 proto_xtr_enable = true;
1462 if (likely(!proto_xtr_enable))
1465 ice_check_proto_xtr_support(hw);
1467 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1468 if (unlikely(offset == -1)) {
1470 "Protocol extraction metadata is disabled in mbuf with error %d",
1476 "Protocol extraction metadata offset in mbuf is : %d",
1478 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1480 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1481 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1483 if (!ol_flag->required)
1486 if (!ice_proto_xtr_hw_support[i]) {
1488 "Protocol extraction type %u is not supported in hardware",
1490 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1494 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1495 if (unlikely(offset == -1)) {
1497 "Protocol extraction offload '%s' failed to register with error %d",
1498 ol_flag->param.name, -rte_errno);
1500 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1505 "Protocol extraction offload '%s' offset in mbuf is : %d",
1506 ol_flag->param.name, offset);
1507 *ol_flag->ol_flag = 1ULL << offset;
1511 /* Initialize SW parameters of PF */
1513 ice_pf_sw_init(struct rte_eth_dev *dev)
1515 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1516 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1519 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1520 hw->func_caps.common_cap.num_rxq);
1522 pf->lan_nb_qps = pf->lan_nb_qp_max;
1524 ice_init_proto_xtr(dev);
1526 if (hw->func_caps.fd_fltr_guar > 0 ||
1527 hw->func_caps.fd_fltr_best_effort > 0) {
1528 pf->flags |= ICE_FLAG_FDIR;
1529 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1530 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1532 pf->fdir_nb_qps = 0;
1534 pf->fdir_qp_offset = 0;
1540 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1542 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1543 struct ice_vsi *vsi = NULL;
1544 struct ice_vsi_ctx vsi_ctx;
1546 struct rte_ether_addr broadcast = {
1547 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1548 struct rte_ether_addr mac_addr;
1549 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1550 uint8_t tc_bitmap = 0x1;
1553 /* hw->num_lports = 1 in NIC mode */
1554 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1558 vsi->idx = pf->next_vsi_idx;
1561 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1562 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1563 vsi->vlan_anti_spoof_on = 0;
1564 vsi->vlan_filter_on = 1;
1565 TAILQ_INIT(&vsi->mac_list);
1566 TAILQ_INIT(&vsi->vlan_list);
1568 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1569 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1570 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1571 hw->func_caps.common_cap.rss_table_size;
1572 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1574 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1577 vsi->nb_qps = pf->lan_nb_qps;
1578 vsi->base_queue = 1;
1579 ice_vsi_config_default_rss(&vsi_ctx.info);
1580 vsi_ctx.alloc_from_pool = true;
1581 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1582 /* switch_id is queried by get_switch_config aq, which is done
1585 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1586 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1587 /* Allow all untagged or tagged packets */
1588 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1589 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1590 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1591 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1594 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1595 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1596 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1597 cfg = ICE_AQ_VSI_FD_ENABLE;
1598 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1599 vsi_ctx.info.max_fd_fltr_dedicated =
1600 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1601 vsi_ctx.info.max_fd_fltr_shared =
1602 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1604 /* Enable VLAN/UP trip */
1605 ret = ice_vsi_config_tc_queue_mapping(vsi,
1610 "tc queue mapping with vsi failed, "
1618 vsi->nb_qps = pf->fdir_nb_qps;
1619 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1620 vsi_ctx.alloc_from_pool = true;
1621 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1623 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1624 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1625 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1626 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1627 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1628 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1629 ret = ice_vsi_config_tc_queue_mapping(vsi,
1634 "tc queue mapping with vsi failed, "
1641 /* for other types of VSI */
1642 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1646 /* VF has MSIX interrupt in VF range, don't allocate here */
1647 if (type == ICE_VSI_PF) {
1648 ret = ice_res_pool_alloc(&pf->msix_pool,
1649 RTE_MIN(vsi->nb_qps,
1650 RTE_MAX_RXTX_INTR_VEC_ID));
1652 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1655 vsi->msix_intr = ret;
1656 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1657 } else if (type == ICE_VSI_CTRL) {
1658 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1660 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1663 vsi->msix_intr = ret;
1669 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1670 if (ret != ICE_SUCCESS) {
1671 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1674 /* store vsi information is SW structure */
1675 vsi->vsi_id = vsi_ctx.vsi_num;
1676 vsi->info = vsi_ctx.info;
1677 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1678 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1680 if (type == ICE_VSI_PF) {
1681 /* MAC configuration */
1682 rte_ether_addr_copy((struct rte_ether_addr *)
1683 hw->port_info->mac.perm_addr,
1686 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1687 ret = ice_add_mac_filter(vsi, &mac_addr);
1688 if (ret != ICE_SUCCESS)
1689 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1691 rte_ether_addr_copy(&broadcast, &mac_addr);
1692 ret = ice_add_mac_filter(vsi, &mac_addr);
1693 if (ret != ICE_SUCCESS)
1694 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1697 /* At the beginning, only TC0. */
1698 /* What we need here is the maximam number of the TX queues.
1699 * Currently vsi->nb_qps means it.
1700 * Correct it if any change.
1702 max_txqs[0] = vsi->nb_qps;
1703 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1704 tc_bitmap, max_txqs);
1705 if (ret != ICE_SUCCESS)
1706 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1716 ice_send_driver_ver(struct ice_hw *hw)
1718 struct ice_driver_ver dv;
1720 /* we don't have driver version use 0 for dummy */
1724 dv.subbuild_ver = 0;
1725 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1727 return ice_aq_send_driver_ver(hw, &dv, NULL);
1731 ice_pf_setup(struct ice_pf *pf)
1733 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1734 struct ice_vsi *vsi;
1737 /* Clear all stats counters */
1738 pf->offset_loaded = false;
1739 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1740 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1741 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1742 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1744 /* force guaranteed filter pool for PF */
1745 ice_alloc_fd_guar_item(hw, &unused,
1746 hw->func_caps.fd_fltr_guar);
1747 /* force shared filter pool for PF */
1748 ice_alloc_fd_shrd_item(hw, &unused,
1749 hw->func_caps.fd_fltr_best_effort);
1751 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1753 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1763 * Extract device serial number from PCIe Configuration Space and
1764 * determine the pkg file path according to the DSN.
1767 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1770 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1771 uint32_t dsn_low, dsn_high;
1772 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1774 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1777 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1778 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1779 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1780 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1782 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1786 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1787 ICE_MAX_PKG_FILENAME_SIZE);
1788 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1791 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1792 ICE_MAX_PKG_FILENAME_SIZE);
1793 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1797 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1798 if (!access(pkg_file, 0))
1800 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1805 ice_load_pkg_type(struct ice_hw *hw)
1807 enum ice_pkg_type package_type;
1809 /* store the activated package type (OS default or Comms) */
1810 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1812 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1813 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1815 package_type = ICE_PKG_TYPE_COMMS;
1817 package_type = ICE_PKG_TYPE_UNKNOWN;
1819 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1820 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1821 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1822 hw->active_pkg_name);
1824 return package_type;
1827 static int ice_load_pkg(struct rte_eth_dev *dev)
1829 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1830 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1836 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1837 struct ice_adapter *ad =
1838 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1840 ice_pkg_file_search_path(pci_dev, pkg_file);
1842 file = fopen(pkg_file, "rb");
1844 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1848 err = stat(pkg_file, &fstat);
1850 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1855 buf_len = fstat.st_size;
1856 buf = rte_malloc(NULL, buf_len, 0);
1859 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1865 err = fread(buf, buf_len, 1, file);
1867 PMD_INIT_LOG(ERR, "failed to read package data\n");
1875 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1877 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1881 /* store the loaded pkg type info */
1882 ad->active_pkg_type = ice_load_pkg_type(hw);
1884 err = ice_init_hw_tbls(hw);
1886 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1887 goto fail_init_tbls;
1893 rte_free(hw->pkg_copy);
1900 ice_base_queue_get(struct ice_pf *pf)
1903 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1905 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1906 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1907 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1909 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1915 parse_bool(const char *key, const char *value, void *args)
1917 int *i = (int *)args;
1921 num = strtoul(value, &end, 10);
1923 if (num != 0 && num != 1) {
1924 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1925 "value must be 0 or 1",
1934 static int ice_parse_devargs(struct rte_eth_dev *dev)
1936 struct ice_adapter *ad =
1937 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1938 struct rte_devargs *devargs = dev->device->devargs;
1939 struct rte_kvargs *kvlist;
1942 if (devargs == NULL)
1945 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1946 if (kvlist == NULL) {
1947 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1951 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1952 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1953 sizeof(ad->devargs.proto_xtr));
1955 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1956 &handle_proto_xtr_arg, &ad->devargs);
1960 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1961 &parse_bool, &ad->devargs.safe_mode_support);
1965 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1966 &parse_bool, &ad->devargs.pipe_mode_support);
1971 rte_kvargs_free(kvlist);
1975 /* Forward LLDP packets to default VSI by set switch rules */
1977 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1979 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1980 struct ice_fltr_list_entry *s_list_itr = NULL;
1981 struct LIST_HEAD_TYPE list_head;
1984 INIT_LIST_HEAD(&list_head);
1986 s_list_itr = (struct ice_fltr_list_entry *)
1987 ice_malloc(hw, sizeof(*s_list_itr));
1990 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1991 s_list_itr->fltr_info.vsi_handle = vsi->idx;
1992 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1993 RTE_ETHER_TYPE_LLDP;
1994 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1995 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1996 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1997 LIST_ADD(&s_list_itr->list_entry, &list_head);
1999 ret = ice_add_eth_mac(hw, &list_head);
2001 ret = ice_remove_eth_mac(hw, &list_head);
2003 rte_free(s_list_itr);
2007 static enum ice_status
2008 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2009 uint16_t num, uint16_t desc_id,
2010 uint16_t *prof_buf, uint16_t *num_prof)
2012 struct ice_aqc_res_elem *resp_buf;
2015 bool res_shared = 1;
2016 struct ice_aq_desc aq_desc;
2017 struct ice_sq_cd *cd = NULL;
2018 struct ice_aqc_get_allocd_res_desc *cmd =
2019 &aq_desc.params.get_res_desc;
2021 buf_len = sizeof(*resp_buf) * num;
2022 resp_buf = ice_malloc(hw, buf_len);
2026 ice_fill_dflt_direct_cmd_desc(&aq_desc,
2027 ice_aqc_opc_get_allocd_res_desc);
2029 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2030 ICE_AQC_RES_TYPE_M) | (res_shared ?
2031 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2032 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2034 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2036 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2040 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
2041 (*num_prof), ICE_NONDMA_TO_NONDMA);
2048 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2052 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2053 uint16_t first_desc = 1;
2054 uint16_t num_prof = 0;
2056 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2057 first_desc, prof_buf, &num_prof);
2059 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2063 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2064 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2066 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2074 ice_reset_fxp_resource(struct ice_hw *hw)
2078 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2080 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2084 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2086 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2094 ice_rss_ctx_init(struct ice_pf *pf)
2096 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
2100 ice_get_supported_rxdid(struct ice_hw *hw)
2102 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2106 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2108 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2109 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2110 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2111 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2112 supported_rxdid |= BIT(i);
2114 return supported_rxdid;
2118 ice_dev_init(struct rte_eth_dev *dev)
2120 struct rte_pci_device *pci_dev;
2121 struct rte_intr_handle *intr_handle;
2122 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2124 struct ice_adapter *ad =
2125 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2126 struct ice_vsi *vsi;
2129 dev->dev_ops = &ice_eth_dev_ops;
2130 dev->rx_queue_count = ice_rx_queue_count;
2131 dev->rx_descriptor_status = ice_rx_descriptor_status;
2132 dev->tx_descriptor_status = ice_tx_descriptor_status;
2133 dev->rx_pkt_burst = ice_recv_pkts;
2134 dev->tx_pkt_burst = ice_xmit_pkts;
2135 dev->tx_pkt_prepare = ice_prep_pkts;
2137 /* for secondary processes, we don't initialise any further as primary
2138 * has already done this work.
2140 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2141 ice_set_rx_function(dev);
2142 ice_set_tx_function(dev);
2146 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2148 ice_set_default_ptype_table(dev);
2149 pci_dev = RTE_DEV_TO_PCI(dev->device);
2150 intr_handle = &pci_dev->intr_handle;
2152 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2153 pf->adapter->eth_dev = dev;
2154 pf->dev_data = dev->data;
2155 hw->back = pf->adapter;
2156 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2157 hw->vendor_id = pci_dev->id.vendor_id;
2158 hw->device_id = pci_dev->id.device_id;
2159 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2160 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2161 hw->bus.device = pci_dev->addr.devid;
2162 hw->bus.func = pci_dev->addr.function;
2164 ret = ice_parse_devargs(dev);
2166 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2170 ice_init_controlq_parameter(hw);
2172 ret = ice_init_hw(hw);
2174 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2178 ret = ice_load_pkg(dev);
2180 if (ad->devargs.safe_mode_support == 0) {
2181 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2182 "Use safe-mode-support=1 to enter Safe Mode");
2186 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2187 "Entering Safe Mode");
2188 ad->is_safe_mode = 1;
2191 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2192 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2193 hw->api_maj_ver, hw->api_min_ver);
2195 ice_pf_sw_init(dev);
2196 ret = ice_init_mac_address(dev);
2198 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2202 ret = ice_res_pool_init(&pf->msix_pool, 1,
2203 hw->func_caps.common_cap.num_msix_vectors - 1);
2205 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2206 goto err_msix_pool_init;
2209 ret = ice_pf_setup(pf);
2211 PMD_INIT_LOG(ERR, "Failed to setup PF");
2215 ret = ice_send_driver_ver(hw);
2217 PMD_INIT_LOG(ERR, "Failed to send driver version");
2223 /* Disable double vlan by default */
2224 ice_vsi_config_double_vlan(vsi, false);
2226 ret = ice_aq_stop_lldp(hw, true, false, NULL);
2227 if (ret != ICE_SUCCESS)
2228 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2229 ret = ice_init_dcb(hw, true);
2230 if (ret != ICE_SUCCESS)
2231 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2232 /* Forward LLDP packets to default VSI */
2233 ret = ice_vsi_config_sw_lldp(vsi, true);
2234 if (ret != ICE_SUCCESS)
2235 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2236 /* register callback func to eal lib */
2237 rte_intr_callback_register(intr_handle,
2238 ice_interrupt_handler, dev);
2240 ice_pf_enable_irq0(hw);
2242 /* enable uio intr after callback register */
2243 rte_intr_enable(intr_handle);
2245 /* get base queue pairs index in the device */
2246 ice_base_queue_get(pf);
2248 /* Initialize RSS context for gtpu_eh */
2249 ice_rss_ctx_init(pf);
2251 if (!ad->is_safe_mode) {
2252 ret = ice_flow_init(ad);
2254 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2259 ret = ice_reset_fxp_resource(hw);
2261 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2265 pf->supported_rxdid = ice_get_supported_rxdid(hw);
2270 ice_res_pool_destroy(&pf->msix_pool);
2272 rte_free(dev->data->mac_addrs);
2273 dev->data->mac_addrs = NULL;
2275 ice_sched_cleanup_all(hw);
2276 rte_free(hw->port_info);
2277 ice_shutdown_all_ctrlq(hw);
2278 rte_free(pf->proto_xtr);
2284 ice_release_vsi(struct ice_vsi *vsi)
2287 struct ice_vsi_ctx vsi_ctx;
2288 enum ice_status ret;
2294 hw = ICE_VSI_TO_HW(vsi);
2296 ice_remove_all_mac_vlan_filters(vsi);
2298 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2300 vsi_ctx.vsi_num = vsi->vsi_id;
2301 vsi_ctx.info = vsi->info;
2302 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2303 if (ret != ICE_SUCCESS) {
2304 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2308 rte_free(vsi->rss_lut);
2309 rte_free(vsi->rss_key);
2315 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2317 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2318 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2319 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2320 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2321 uint16_t msix_intr, i;
2323 /* disable interrupt and also clear all the exist config */
2324 for (i = 0; i < vsi->nb_qps; i++) {
2325 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2326 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2330 if (rte_intr_allow_others(intr_handle))
2332 for (i = 0; i < vsi->nb_msix; i++) {
2333 msix_intr = vsi->msix_intr + i;
2334 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2335 GLINT_DYN_CTL_WB_ON_ITR_M);
2339 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2343 ice_dev_stop(struct rte_eth_dev *dev)
2345 struct rte_eth_dev_data *data = dev->data;
2346 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2347 struct ice_vsi *main_vsi = pf->main_vsi;
2348 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2349 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2352 /* avoid stopping again */
2353 if (pf->adapter_stopped)
2356 /* stop and clear all Rx queues */
2357 for (i = 0; i < data->nb_rx_queues; i++)
2358 ice_rx_queue_stop(dev, i);
2360 /* stop and clear all Tx queues */
2361 for (i = 0; i < data->nb_tx_queues; i++)
2362 ice_tx_queue_stop(dev, i);
2364 /* disable all queue interrupts */
2365 ice_vsi_disable_queues_intr(main_vsi);
2367 if (pf->init_link_up)
2368 ice_dev_set_link_up(dev);
2370 ice_dev_set_link_down(dev);
2372 /* Clean datapath event and queue/vec mapping */
2373 rte_intr_efd_disable(intr_handle);
2374 if (intr_handle->intr_vec) {
2375 rte_free(intr_handle->intr_vec);
2376 intr_handle->intr_vec = NULL;
2379 pf->adapter_stopped = true;
2380 dev->data->dev_started = 0;
2386 ice_dev_close(struct rte_eth_dev *dev)
2388 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2389 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2391 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2392 struct ice_adapter *ad =
2393 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2396 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2399 /* Since stop will make link down, then the link event will be
2400 * triggered, disable the irq firstly to avoid the port_infoe etc
2401 * resources deallocation causing the interrupt service thread
2404 ice_pf_disable_irq0(hw);
2406 ret = ice_dev_stop(dev);
2408 if (!ad->is_safe_mode)
2409 ice_flow_uninit(ad);
2411 /* release all queue resource */
2412 ice_free_queues(dev);
2414 ice_res_pool_destroy(&pf->msix_pool);
2415 ice_release_vsi(pf->main_vsi);
2416 ice_sched_cleanup_all(hw);
2417 ice_free_hw_tbls(hw);
2418 rte_free(hw->port_info);
2419 hw->port_info = NULL;
2420 ice_shutdown_all_ctrlq(hw);
2421 rte_free(pf->proto_xtr);
2422 pf->proto_xtr = NULL;
2424 /* disable uio intr before callback unregister */
2425 rte_intr_disable(intr_handle);
2427 /* unregister callback func from eal lib */
2428 rte_intr_callback_unregister(intr_handle,
2429 ice_interrupt_handler, dev);
2435 ice_dev_uninit(struct rte_eth_dev *dev)
2443 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2445 return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2449 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2454 cfg->hdr_type = ICE_RSS_ANY_HEADERS;
2458 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2460 enum ice_status status = ICE_SUCCESS;
2461 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2462 struct ice_vsi *vsi = pf->main_vsi;
2464 if (!is_hash_cfg_valid(cfg))
2467 status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2468 if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2470 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2479 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2481 enum ice_status status = ICE_SUCCESS;
2482 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2483 struct ice_vsi *vsi = pf->main_vsi;
2485 if (!is_hash_cfg_valid(cfg))
2488 status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2491 "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2500 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2504 ret = ice_hash_moveout(pf, cfg);
2505 if (ret && (ret != -ENOENT))
2508 hash_cfg_reset(cfg);
2514 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2520 case ICE_HASH_GTPU_CTX_EH_IP:
2521 ret = ice_hash_remove(pf,
2522 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2523 if (ret && (ret != -ENOENT))
2526 ret = ice_hash_remove(pf,
2527 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2528 if (ret && (ret != -ENOENT))
2531 ret = ice_hash_remove(pf,
2532 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2533 if (ret && (ret != -ENOENT))
2536 ret = ice_hash_remove(pf,
2537 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2538 if (ret && (ret != -ENOENT))
2541 ret = ice_hash_remove(pf,
2542 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2543 if (ret && (ret != -ENOENT))
2546 ret = ice_hash_remove(pf,
2547 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2548 if (ret && (ret != -ENOENT))
2551 ret = ice_hash_remove(pf,
2552 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2553 if (ret && (ret != -ENOENT))
2556 ret = ice_hash_remove(pf,
2557 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2558 if (ret && (ret != -ENOENT))
2562 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2563 ret = ice_hash_remove(pf,
2564 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2565 if (ret && (ret != -ENOENT))
2568 ret = ice_hash_remove(pf,
2569 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2570 if (ret && (ret != -ENOENT))
2573 ret = ice_hash_moveout(pf,
2574 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2575 if (ret && (ret != -ENOENT))
2578 ret = ice_hash_moveout(pf,
2579 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2580 if (ret && (ret != -ENOENT))
2583 ret = ice_hash_moveout(pf,
2584 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2585 if (ret && (ret != -ENOENT))
2588 ret = ice_hash_moveout(pf,
2589 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2590 if (ret && (ret != -ENOENT))
2594 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2595 ret = ice_hash_remove(pf,
2596 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2597 if (ret && (ret != -ENOENT))
2600 ret = ice_hash_remove(pf,
2601 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2602 if (ret && (ret != -ENOENT))
2605 ret = ice_hash_moveout(pf,
2606 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2607 if (ret && (ret != -ENOENT))
2610 ret = ice_hash_moveout(pf,
2611 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2612 if (ret && (ret != -ENOENT))
2615 ret = ice_hash_moveout(pf,
2616 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2617 if (ret && (ret != -ENOENT))
2620 ret = ice_hash_moveout(pf,
2621 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2622 if (ret && (ret != -ENOENT))
2626 case ICE_HASH_GTPU_CTX_UP_IP:
2627 ret = ice_hash_remove(pf,
2628 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2629 if (ret && (ret != -ENOENT))
2632 ret = ice_hash_remove(pf,
2633 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2634 if (ret && (ret != -ENOENT))
2637 ret = ice_hash_moveout(pf,
2638 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2639 if (ret && (ret != -ENOENT))
2642 ret = ice_hash_moveout(pf,
2643 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2644 if (ret && (ret != -ENOENT))
2647 ret = ice_hash_moveout(pf,
2648 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2649 if (ret && (ret != -ENOENT))
2653 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2654 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2655 ret = ice_hash_moveout(pf,
2656 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2657 if (ret && (ret != -ENOENT))
2660 ret = ice_hash_moveout(pf,
2661 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2662 if (ret && (ret != -ENOENT))
2665 ret = ice_hash_moveout(pf,
2666 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2667 if (ret && (ret != -ENOENT))
2671 case ICE_HASH_GTPU_CTX_DW_IP:
2672 ret = ice_hash_remove(pf,
2673 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2674 if (ret && (ret != -ENOENT))
2677 ret = ice_hash_remove(pf,
2678 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2679 if (ret && (ret != -ENOENT))
2682 ret = ice_hash_moveout(pf,
2683 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2684 if (ret && (ret != -ENOENT))
2687 ret = ice_hash_moveout(pf,
2688 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2689 if (ret && (ret != -ENOENT))
2692 ret = ice_hash_moveout(pf,
2693 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2694 if (ret && (ret != -ENOENT))
2698 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2699 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2700 ret = ice_hash_moveout(pf,
2701 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2702 if (ret && (ret != -ENOENT))
2705 ret = ice_hash_moveout(pf,
2706 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2707 if (ret && (ret != -ENOENT))
2710 ret = ice_hash_moveout(pf,
2711 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2712 if (ret && (ret != -ENOENT))
2723 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2727 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2729 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2731 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2734 return ICE_HASH_GTPU_CTX_MAX;
2737 if (hdr & ICE_FLOW_SEG_HDR_UDP)
2739 else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2742 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2743 return eh_idx * 3 + ip_idx;
2745 return ICE_HASH_GTPU_CTX_MAX;
2749 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2751 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2753 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2754 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2756 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2757 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2764 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2765 u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2769 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2770 ctx->ctx[ctx_idx] = *cfg;
2773 case ICE_HASH_GTPU_CTX_EH_IP:
2775 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2776 ret = ice_hash_moveback(pf,
2777 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2778 if (ret && (ret != -ENOENT))
2781 ret = ice_hash_moveback(pf,
2782 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2783 if (ret && (ret != -ENOENT))
2786 ret = ice_hash_moveback(pf,
2787 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2788 if (ret && (ret != -ENOENT))
2791 ret = ice_hash_moveback(pf,
2792 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2793 if (ret && (ret != -ENOENT))
2797 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2798 ret = ice_hash_moveback(pf,
2799 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2800 if (ret && (ret != -ENOENT))
2803 ret = ice_hash_moveback(pf,
2804 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2805 if (ret && (ret != -ENOENT))
2808 ret = ice_hash_moveback(pf,
2809 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2810 if (ret && (ret != -ENOENT))
2813 ret = ice_hash_moveback(pf,
2814 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2815 if (ret && (ret != -ENOENT))
2819 case ICE_HASH_GTPU_CTX_UP_IP:
2820 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2821 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2822 case ICE_HASH_GTPU_CTX_DW_IP:
2823 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2824 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2825 ret = ice_hash_moveback(pf,
2826 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2827 if (ret && (ret != -ENOENT))
2830 ret = ice_hash_moveback(pf,
2831 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2832 if (ret && (ret != -ENOENT))
2835 ret = ice_hash_moveback(pf,
2836 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2837 if (ret && (ret != -ENOENT))
2849 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2851 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2853 if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2854 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2856 else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2857 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2864 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2866 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2868 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2871 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2872 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2873 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2874 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2878 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2879 struct ice_rss_hash_cfg *cfg)
2881 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2884 ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2885 if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2886 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2888 ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2894 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2895 struct ice_rss_hash_cfg *cfg)
2897 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2900 ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2902 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2904 ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2906 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2908 ret = ice_add_rss_cfg_post(pf, cfg);
2910 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2916 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2918 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2919 struct ice_vsi *vsi = pf->main_vsi;
2920 struct ice_rss_hash_cfg cfg;
2923 #define ICE_RSS_HF_ALL ( \
2926 ETH_RSS_NONFRAG_IPV4_UDP | \
2927 ETH_RSS_NONFRAG_IPV6_UDP | \
2928 ETH_RSS_NONFRAG_IPV4_TCP | \
2929 ETH_RSS_NONFRAG_IPV6_TCP | \
2930 ETH_RSS_NONFRAG_IPV4_SCTP | \
2931 ETH_RSS_NONFRAG_IPV6_SCTP)
2933 ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2935 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2939 cfg.hdr_type = ICE_RSS_ANY_HEADERS;
2940 /* Configure RSS for IPv4 with src/dst addr as input set */
2941 if (rss_hf & ETH_RSS_IPV4) {
2942 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2943 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2944 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2946 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2950 /* Configure RSS for IPv6 with src/dst addr as input set */
2951 if (rss_hf & ETH_RSS_IPV6) {
2952 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2953 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2954 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2956 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2960 /* Configure RSS for udp4 with src/dst addr and port as input set */
2961 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2962 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2963 ICE_FLOW_SEG_HDR_IPV_OTHER;
2964 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2965 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2967 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2971 /* Configure RSS for udp6 with src/dst addr and port as input set */
2972 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2973 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
2974 ICE_FLOW_SEG_HDR_IPV_OTHER;
2975 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2976 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2978 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2982 /* Configure RSS for tcp4 with src/dst addr and port as input set */
2983 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2984 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
2985 ICE_FLOW_SEG_HDR_IPV_OTHER;
2986 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2987 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2989 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2993 /* Configure RSS for tcp6 with src/dst addr and port as input set */
2994 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2995 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
2996 ICE_FLOW_SEG_HDR_IPV_OTHER;
2997 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2998 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3000 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
3004 /* Configure RSS for sctp4 with src/dst addr and port as input set */
3005 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
3006 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
3007 ICE_FLOW_SEG_HDR_IPV_OTHER;
3008 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
3009 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3011 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
3015 /* Configure RSS for sctp6 with src/dst addr and port as input set */
3016 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
3017 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
3018 ICE_FLOW_SEG_HDR_IPV_OTHER;
3019 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
3020 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3022 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
3026 if (rss_hf & ETH_RSS_IPV4) {
3027 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV4 |
3028 ICE_FLOW_SEG_HDR_IPV_OTHER;
3029 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
3030 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3032 PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
3035 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV4 |
3036 ICE_FLOW_SEG_HDR_IPV_OTHER;
3037 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3039 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
3042 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
3043 ICE_FLOW_SEG_HDR_IPV_OTHER;
3044 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3046 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
3050 if (rss_hf & ETH_RSS_IPV6) {
3051 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV6 |
3052 ICE_FLOW_SEG_HDR_IPV_OTHER;
3053 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
3054 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3056 PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
3059 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV6 |
3060 ICE_FLOW_SEG_HDR_IPV_OTHER;
3061 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3063 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
3066 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
3067 ICE_FLOW_SEG_HDR_IPV_OTHER;
3068 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3070 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
3074 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
3075 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
3076 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3077 cfg.hash_flds = ICE_HASH_UDP_IPV4;
3078 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3080 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
3083 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
3084 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3085 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3087 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
3090 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3091 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3092 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3094 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
3098 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
3099 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
3100 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3101 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3102 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3104 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
3107 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
3108 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3109 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3111 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
3114 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3115 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3116 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3118 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3122 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3123 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3124 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3125 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3126 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3128 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
3131 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3132 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3133 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3135 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
3138 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3139 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3140 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3142 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3146 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3147 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3148 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3149 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3150 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3152 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
3155 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3156 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3157 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3159 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
3162 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3163 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3164 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3166 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3170 pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3173 static int ice_init_rss(struct ice_pf *pf)
3175 struct ice_hw *hw = ICE_PF_TO_HW(pf);
3176 struct ice_vsi *vsi = pf->main_vsi;
3177 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3178 struct ice_aq_get_set_rss_lut_params lut_params;
3179 struct rte_eth_rss_conf *rss_conf;
3180 struct ice_aqc_get_set_rss_keys key;
3183 bool is_safe_mode = pf->adapter->is_safe_mode;
3186 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3187 nb_q = dev->data->nb_rx_queues;
3188 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3189 vsi->rss_lut_size = pf->hash_lut_size;
3192 PMD_DRV_LOG(WARNING,
3193 "RSS is not supported as rx queues number is zero\n");
3198 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3202 if (!vsi->rss_key) {
3203 vsi->rss_key = rte_zmalloc(NULL,
3204 vsi->rss_key_size, 0);
3205 if (vsi->rss_key == NULL) {
3206 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3210 if (!vsi->rss_lut) {
3211 vsi->rss_lut = rte_zmalloc(NULL,
3212 vsi->rss_lut_size, 0);
3213 if (vsi->rss_lut == NULL) {
3214 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3215 rte_free(vsi->rss_key);
3216 vsi->rss_key = NULL;
3220 /* configure RSS key */
3221 if (!rss_conf->rss_key) {
3222 /* Calculate the default hash key */
3223 for (i = 0; i <= vsi->rss_key_size; i++)
3224 vsi->rss_key[i] = (uint8_t)rte_rand();
3226 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3227 RTE_MIN(rss_conf->rss_key_len,
3228 vsi->rss_key_size));
3230 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3231 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3235 /* init RSS LUT table */
3236 for (i = 0; i < vsi->rss_lut_size; i++)
3237 vsi->rss_lut[i] = i % nb_q;
3239 lut_params.vsi_handle = vsi->idx;
3240 lut_params.lut_size = vsi->rss_lut_size;
3241 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3242 lut_params.lut = vsi->rss_lut;
3243 lut_params.global_lut_id = 0;
3244 ret = ice_aq_set_rss_lut(hw, &lut_params);
3248 /* Enable registers for symmetric_toeplitz function. */
3249 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3250 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3251 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3252 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3254 /* RSS hash configuration */
3255 ice_rss_hash_set(pf, rss_conf->rss_hf);
3259 rte_free(vsi->rss_key);
3260 vsi->rss_key = NULL;
3261 rte_free(vsi->rss_lut);
3262 vsi->rss_lut = NULL;
3267 ice_dev_configure(struct rte_eth_dev *dev)
3269 struct ice_adapter *ad =
3270 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3271 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3274 /* Initialize to TRUE. If any of Rx queues doesn't meet the
3275 * bulk allocation or vector Rx preconditions we will reset it.
3277 ad->rx_bulk_alloc_allowed = true;
3278 ad->tx_simple_allowed = true;
3280 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3281 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3283 if (dev->data->nb_rx_queues) {
3284 ret = ice_init_rss(pf);
3286 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3295 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3296 int base_queue, int nb_queue)
3298 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3299 uint32_t val, val_tx;
3302 for (i = 0; i < nb_queue; i++) {
3304 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3305 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3306 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3307 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3309 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3310 base_queue + i, msix_vect);
3311 /* set ITR0 value */
3312 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3313 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3314 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3319 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3321 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3322 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3323 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3324 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3325 uint16_t msix_vect = vsi->msix_intr;
3326 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3327 uint16_t queue_idx = 0;
3331 /* clear Rx/Tx queue interrupt */
3332 for (i = 0; i < vsi->nb_used_qps; i++) {
3333 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3334 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3337 /* PF bind interrupt */
3338 if (rte_intr_dp_is_en(intr_handle)) {
3343 for (i = 0; i < vsi->nb_used_qps; i++) {
3345 if (!rte_intr_allow_others(intr_handle))
3346 msix_vect = ICE_MISC_VEC_ID;
3348 /* uio mapping all queue to one msix_vect */
3349 __vsi_queues_bind_intr(vsi, msix_vect,
3350 vsi->base_queue + i,
3351 vsi->nb_used_qps - i);
3353 for (; !!record && i < vsi->nb_used_qps; i++)
3354 intr_handle->intr_vec[queue_idx + i] =
3359 /* vfio 1:1 queue/msix_vect mapping */
3360 __vsi_queues_bind_intr(vsi, msix_vect,
3361 vsi->base_queue + i, 1);
3364 intr_handle->intr_vec[queue_idx + i] = msix_vect;
3372 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3374 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3375 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3376 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3377 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3378 uint16_t msix_intr, i;
3380 if (rte_intr_allow_others(intr_handle))
3381 for (i = 0; i < vsi->nb_used_qps; i++) {
3382 msix_intr = vsi->msix_intr + i;
3383 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3384 GLINT_DYN_CTL_INTENA_M |
3385 GLINT_DYN_CTL_CLEARPBA_M |
3386 GLINT_DYN_CTL_ITR_INDX_M |
3387 GLINT_DYN_CTL_WB_ON_ITR_M);
3390 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3391 GLINT_DYN_CTL_INTENA_M |
3392 GLINT_DYN_CTL_CLEARPBA_M |
3393 GLINT_DYN_CTL_ITR_INDX_M |
3394 GLINT_DYN_CTL_WB_ON_ITR_M);
3398 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3400 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3401 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3402 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3403 struct ice_vsi *vsi = pf->main_vsi;
3404 uint32_t intr_vector = 0;
3406 rte_intr_disable(intr_handle);
3408 /* check and configure queue intr-vector mapping */
3409 if ((rte_intr_cap_multiple(intr_handle) ||
3410 !RTE_ETH_DEV_SRIOV(dev).active) &&
3411 dev->data->dev_conf.intr_conf.rxq != 0) {
3412 intr_vector = dev->data->nb_rx_queues;
3413 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3414 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3415 ICE_MAX_INTR_QUEUE_NUM);
3418 if (rte_intr_efd_enable(intr_handle, intr_vector))
3422 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3423 intr_handle->intr_vec =
3424 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3426 if (!intr_handle->intr_vec) {
3428 "Failed to allocate %d rx_queues intr_vec",
3429 dev->data->nb_rx_queues);
3434 /* Map queues with MSIX interrupt */
3435 vsi->nb_used_qps = dev->data->nb_rx_queues;
3436 ice_vsi_queues_bind_intr(vsi);
3438 /* Enable interrupts for all the queues */
3439 ice_vsi_enable_queues_intr(vsi);
3441 rte_intr_enable(intr_handle);
3447 ice_get_init_link_status(struct rte_eth_dev *dev)
3449 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3450 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3451 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3452 struct ice_link_status link_status;
3455 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3456 &link_status, NULL);
3457 if (ret != ICE_SUCCESS) {
3458 PMD_DRV_LOG(ERR, "Failed to get link info");
3459 pf->init_link_up = false;
3463 if (link_status.link_info & ICE_AQ_LINK_UP)
3464 pf->init_link_up = true;
3468 ice_dev_start(struct rte_eth_dev *dev)
3470 struct rte_eth_dev_data *data = dev->data;
3471 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3472 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3473 struct ice_vsi *vsi = pf->main_vsi;
3474 uint16_t nb_rxq = 0;
3476 uint16_t max_frame_size;
3479 /* program Tx queues' context in hardware */
3480 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3481 ret = ice_tx_queue_start(dev, nb_txq);
3483 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3488 /* program Rx queues' context in hardware*/
3489 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3490 ret = ice_rx_queue_start(dev, nb_rxq);
3492 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3497 ice_set_rx_function(dev);
3498 ice_set_tx_function(dev);
3500 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3501 ETH_VLAN_EXTEND_MASK;
3502 ret = ice_vlan_offload_set(dev, mask);
3504 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3508 /* enable Rx interrput and mapping Rx queue to interrupt vector */
3509 if (ice_rxq_intr_setup(dev))
3512 /* Enable receiving broadcast packets and transmitting packets */
3513 ret = ice_set_vsi_promisc(hw, vsi->idx,
3514 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3515 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3517 if (ret != ICE_SUCCESS)
3518 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3520 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3521 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3522 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3523 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3524 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3525 ICE_AQ_LINK_EVENT_AN_COMPLETED |
3526 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3528 if (ret != ICE_SUCCESS)
3529 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3531 ice_get_init_link_status(dev);
3533 ice_dev_set_link_up(dev);
3535 /* Call get_link_info aq commond to enable/disable LSE */
3536 ice_link_update(dev, 0);
3538 pf->adapter_stopped = false;
3540 /* Set the max frame size to default value*/
3541 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3542 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3545 /* Set the max frame size to HW*/
3546 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3550 /* stop the started queues if failed to start all queues */
3552 for (i = 0; i < nb_rxq; i++)
3553 ice_rx_queue_stop(dev, i);
3555 for (i = 0; i < nb_txq; i++)
3556 ice_tx_queue_stop(dev, i);
3562 ice_dev_reset(struct rte_eth_dev *dev)
3566 if (dev->data->sriov.active)
3569 ret = ice_dev_uninit(dev);
3571 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3575 ret = ice_dev_init(dev);
3577 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3585 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3587 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3588 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3589 struct ice_vsi *vsi = pf->main_vsi;
3590 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3591 bool is_safe_mode = pf->adapter->is_safe_mode;
3595 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3596 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3597 dev_info->max_rx_queues = vsi->nb_qps;
3598 dev_info->max_tx_queues = vsi->nb_qps;
3599 dev_info->max_mac_addrs = vsi->max_macaddrs;
3600 dev_info->max_vfs = pci_dev->max_vfs;
3601 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3602 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3604 dev_info->rx_offload_capa =
3605 DEV_RX_OFFLOAD_VLAN_STRIP |
3606 DEV_RX_OFFLOAD_JUMBO_FRAME |
3607 DEV_RX_OFFLOAD_KEEP_CRC |
3608 DEV_RX_OFFLOAD_SCATTER |
3609 DEV_RX_OFFLOAD_VLAN_FILTER;
3610 dev_info->tx_offload_capa =
3611 DEV_TX_OFFLOAD_VLAN_INSERT |
3612 DEV_TX_OFFLOAD_TCP_TSO |
3613 DEV_TX_OFFLOAD_MULTI_SEGS |
3614 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3615 dev_info->flow_type_rss_offloads = 0;
3617 if (!is_safe_mode) {
3618 dev_info->rx_offload_capa |=
3619 DEV_RX_OFFLOAD_IPV4_CKSUM |
3620 DEV_RX_OFFLOAD_UDP_CKSUM |
3621 DEV_RX_OFFLOAD_TCP_CKSUM |
3622 DEV_RX_OFFLOAD_QINQ_STRIP |
3623 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3624 DEV_RX_OFFLOAD_VLAN_EXTEND |
3625 DEV_RX_OFFLOAD_RSS_HASH;
3626 dev_info->tx_offload_capa |=
3627 DEV_TX_OFFLOAD_QINQ_INSERT |
3628 DEV_TX_OFFLOAD_IPV4_CKSUM |
3629 DEV_TX_OFFLOAD_UDP_CKSUM |
3630 DEV_TX_OFFLOAD_TCP_CKSUM |
3631 DEV_TX_OFFLOAD_SCTP_CKSUM |
3632 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3633 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3634 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3637 dev_info->rx_queue_offload_capa = 0;
3638 dev_info->tx_queue_offload_capa = 0;
3640 dev_info->reta_size = pf->hash_lut_size;
3641 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3643 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3645 .pthresh = ICE_DEFAULT_RX_PTHRESH,
3646 .hthresh = ICE_DEFAULT_RX_HTHRESH,
3647 .wthresh = ICE_DEFAULT_RX_WTHRESH,
3649 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3654 dev_info->default_txconf = (struct rte_eth_txconf) {
3656 .pthresh = ICE_DEFAULT_TX_PTHRESH,
3657 .hthresh = ICE_DEFAULT_TX_HTHRESH,
3658 .wthresh = ICE_DEFAULT_TX_WTHRESH,
3660 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3661 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3665 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3666 .nb_max = ICE_MAX_RING_DESC,
3667 .nb_min = ICE_MIN_RING_DESC,
3668 .nb_align = ICE_ALIGN_RING_DESC,
3671 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3672 .nb_max = ICE_MAX_RING_DESC,
3673 .nb_min = ICE_MIN_RING_DESC,
3674 .nb_align = ICE_ALIGN_RING_DESC,
3677 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3678 ETH_LINK_SPEED_100M |
3680 ETH_LINK_SPEED_2_5G |
3682 ETH_LINK_SPEED_10G |
3683 ETH_LINK_SPEED_20G |
3686 phy_type_low = hw->port_info->phy.phy_type_low;
3687 phy_type_high = hw->port_info->phy.phy_type_high;
3689 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3690 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3692 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3693 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3694 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3696 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3697 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3699 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3700 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3701 dev_info->default_rxportconf.nb_queues = 1;
3702 dev_info->default_txportconf.nb_queues = 1;
3703 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3704 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3710 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3711 struct rte_eth_link *link)
3713 struct rte_eth_link *dst = link;
3714 struct rte_eth_link *src = &dev->data->dev_link;
3716 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3717 *(uint64_t *)src) == 0)
3724 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3725 struct rte_eth_link *link)
3727 struct rte_eth_link *dst = &dev->data->dev_link;
3728 struct rte_eth_link *src = link;
3730 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3731 *(uint64_t *)src) == 0)
3738 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3740 #define CHECK_INTERVAL 100 /* 100ms */
3741 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3742 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3743 struct ice_link_status link_status;
3744 struct rte_eth_link link, old;
3746 unsigned int rep_cnt = MAX_REPEAT_TIME;
3747 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3749 memset(&link, 0, sizeof(link));
3750 memset(&old, 0, sizeof(old));
3751 memset(&link_status, 0, sizeof(link_status));
3752 ice_atomic_read_link_status(dev, &old);
3755 /* Get link status information from hardware */
3756 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3757 &link_status, NULL);
3758 if (status != ICE_SUCCESS) {
3759 link.link_speed = ETH_SPEED_NUM_100M;
3760 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3761 PMD_DRV_LOG(ERR, "Failed to get link info");
3765 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3766 if (!wait_to_complete || link.link_status)
3769 rte_delay_ms(CHECK_INTERVAL);
3770 } while (--rep_cnt);
3772 if (!link.link_status)
3775 /* Full-duplex operation at all supported speeds */
3776 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3778 /* Parse the link status */
3779 switch (link_status.link_speed) {
3780 case ICE_AQ_LINK_SPEED_10MB:
3781 link.link_speed = ETH_SPEED_NUM_10M;
3783 case ICE_AQ_LINK_SPEED_100MB:
3784 link.link_speed = ETH_SPEED_NUM_100M;
3786 case ICE_AQ_LINK_SPEED_1000MB:
3787 link.link_speed = ETH_SPEED_NUM_1G;
3789 case ICE_AQ_LINK_SPEED_2500MB:
3790 link.link_speed = ETH_SPEED_NUM_2_5G;
3792 case ICE_AQ_LINK_SPEED_5GB:
3793 link.link_speed = ETH_SPEED_NUM_5G;
3795 case ICE_AQ_LINK_SPEED_10GB:
3796 link.link_speed = ETH_SPEED_NUM_10G;
3798 case ICE_AQ_LINK_SPEED_20GB:
3799 link.link_speed = ETH_SPEED_NUM_20G;
3801 case ICE_AQ_LINK_SPEED_25GB:
3802 link.link_speed = ETH_SPEED_NUM_25G;
3804 case ICE_AQ_LINK_SPEED_40GB:
3805 link.link_speed = ETH_SPEED_NUM_40G;
3807 case ICE_AQ_LINK_SPEED_50GB:
3808 link.link_speed = ETH_SPEED_NUM_50G;
3810 case ICE_AQ_LINK_SPEED_100GB:
3811 link.link_speed = ETH_SPEED_NUM_100G;
3813 case ICE_AQ_LINK_SPEED_UNKNOWN:
3814 PMD_DRV_LOG(ERR, "Unknown link speed");
3815 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3818 PMD_DRV_LOG(ERR, "None link speed");
3819 link.link_speed = ETH_SPEED_NUM_NONE;
3823 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3824 ETH_LINK_SPEED_FIXED);
3827 ice_atomic_write_link_status(dev, &link);
3828 if (link.link_status == old.link_status)
3834 /* Force the physical link state by getting the current PHY capabilities from
3835 * hardware and setting the PHY config based on the determined capabilities. If
3836 * link changes, link event will be triggered because both the Enable Automatic
3837 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3839 static enum ice_status
3840 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3842 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3843 struct ice_aqc_get_phy_caps_data *pcaps;
3844 struct ice_port_info *pi;
3845 enum ice_status status;
3847 if (!hw || !hw->port_info)
3848 return ICE_ERR_PARAM;
3852 pcaps = (struct ice_aqc_get_phy_caps_data *)
3853 ice_malloc(hw, sizeof(*pcaps));
3855 return ICE_ERR_NO_MEMORY;
3857 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3862 /* No change in link */
3863 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3864 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3867 cfg.phy_type_low = pcaps->phy_type_low;
3868 cfg.phy_type_high = pcaps->phy_type_high;
3869 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3870 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3871 cfg.eee_cap = pcaps->eee_cap;
3872 cfg.eeer_value = pcaps->eeer_value;
3873 cfg.link_fec_opt = pcaps->link_fec_options;
3875 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3877 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3879 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3882 ice_free(hw, pcaps);
3887 ice_dev_set_link_up(struct rte_eth_dev *dev)
3889 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3891 return ice_force_phys_link_state(hw, true);
3895 ice_dev_set_link_down(struct rte_eth_dev *dev)
3897 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3899 return ice_force_phys_link_state(hw, false);
3903 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3905 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3906 struct rte_eth_dev_data *dev_data = pf->dev_data;
3907 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3909 /* check if mtu is within the allowed range */
3910 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3913 /* mtu setting is forbidden if port is start */
3914 if (dev_data->dev_started) {
3916 "port %d must be stopped before configuration",
3921 if (frame_size > ICE_ETH_MAX_LEN)
3922 dev_data->dev_conf.rxmode.offloads |=
3923 DEV_RX_OFFLOAD_JUMBO_FRAME;
3925 dev_data->dev_conf.rxmode.offloads &=
3926 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3928 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3933 static int ice_macaddr_set(struct rte_eth_dev *dev,
3934 struct rte_ether_addr *mac_addr)
3936 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3937 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3938 struct ice_vsi *vsi = pf->main_vsi;
3939 struct ice_mac_filter *f;
3943 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3944 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3948 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3949 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3954 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3958 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3959 if (ret != ICE_SUCCESS) {
3960 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3963 ret = ice_add_mac_filter(vsi, mac_addr);
3964 if (ret != ICE_SUCCESS) {
3965 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3968 rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3970 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3971 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3972 if (ret != ICE_SUCCESS)
3973 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3978 /* Add a MAC address, and update filters */
3980 ice_macaddr_add(struct rte_eth_dev *dev,
3981 struct rte_ether_addr *mac_addr,
3982 __rte_unused uint32_t index,
3983 __rte_unused uint32_t pool)
3985 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3986 struct ice_vsi *vsi = pf->main_vsi;
3989 ret = ice_add_mac_filter(vsi, mac_addr);
3990 if (ret != ICE_SUCCESS) {
3991 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3998 /* Remove a MAC address, and update filters */
4000 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4002 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4003 struct ice_vsi *vsi = pf->main_vsi;
4004 struct rte_eth_dev_data *data = dev->data;
4005 struct rte_ether_addr *macaddr;
4008 macaddr = &data->mac_addrs[index];
4009 ret = ice_remove_mac_filter(vsi, macaddr);
4011 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
4017 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4019 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4020 struct ice_vsi *vsi = pf->main_vsi;
4023 PMD_INIT_FUNC_TRACE();
4026 ret = ice_add_vlan_filter(vsi, vlan_id);
4028 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
4032 ret = ice_remove_vlan_filter(vsi, vlan_id);
4034 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
4042 /* Configure vlan filter on or off */
4044 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4046 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4047 struct ice_vsi_ctx ctxt;
4048 uint8_t sec_flags, sw_flags2;
4051 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
4052 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
4053 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4056 vsi->info.sec_flags |= sec_flags;
4057 vsi->info.sw_flags2 |= sw_flags2;
4059 vsi->info.sec_flags &= ~sec_flags;
4060 vsi->info.sw_flags2 &= ~sw_flags2;
4062 vsi->info.sw_id = hw->port_info->sw_id;
4063 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4064 ctxt.info.valid_sections =
4065 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4066 ICE_AQ_VSI_PROP_SECURITY_VALID);
4067 ctxt.vsi_num = vsi->vsi_id;
4069 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4071 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4072 on ? "enable" : "disable");
4075 vsi->info.valid_sections |=
4076 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4077 ICE_AQ_VSI_PROP_SECURITY_VALID);
4080 /* consist with other drivers, allow untagged packet when vlan filter on */
4082 ret = ice_add_vlan_filter(vsi, 0);
4084 ret = ice_remove_vlan_filter(vsi, 0);
4090 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
4092 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4093 struct ice_vsi_ctx ctxt;
4097 /* Check if it has been already on or off */
4098 if (vsi->info.valid_sections &
4099 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
4101 if ((vsi->info.inner_vlan_flags &
4102 ICE_AQ_VSI_INNER_VLAN_EMODE_M) ==
4103 ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH)
4104 return 0; /* already on */
4106 if ((vsi->info.inner_vlan_flags &
4107 ICE_AQ_VSI_INNER_VLAN_EMODE_M) ==
4108 ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING)
4109 return 0; /* already off */
4114 vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4116 vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4117 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4118 vsi->info.inner_vlan_flags |= vlan_flags;
4119 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4120 ctxt.info.valid_sections =
4121 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4122 ctxt.vsi_num = vsi->vsi_id;
4123 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4125 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4126 on ? "enable" : "disable");
4130 vsi->info.valid_sections |=
4131 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4137 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4139 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4140 struct ice_vsi *vsi = pf->main_vsi;
4141 struct rte_eth_rxmode *rxmode;
4143 rxmode = &dev->data->dev_conf.rxmode;
4144 if (mask & ETH_VLAN_FILTER_MASK) {
4145 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4146 ice_vsi_config_vlan_filter(vsi, true);
4148 ice_vsi_config_vlan_filter(vsi, false);
4151 if (mask & ETH_VLAN_STRIP_MASK) {
4152 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4153 ice_vsi_config_vlan_stripping(vsi, true);
4155 ice_vsi_config_vlan_stripping(vsi, false);
4158 if (mask & ETH_VLAN_EXTEND_MASK) {
4159 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
4160 ice_vsi_config_double_vlan(vsi, true);
4162 ice_vsi_config_double_vlan(vsi, false);
4169 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4171 struct ice_aq_get_set_rss_lut_params lut_params;
4172 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4173 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4179 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4180 lut_params.vsi_handle = vsi->idx;
4181 lut_params.lut_size = lut_size;
4182 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4183 lut_params.lut = lut;
4184 lut_params.global_lut_id = 0;
4185 ret = ice_aq_get_rss_lut(hw, &lut_params);
4187 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4191 uint64_t *lut_dw = (uint64_t *)lut;
4192 uint16_t i, lut_size_dw = lut_size / 4;
4194 for (i = 0; i < lut_size_dw; i++)
4195 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4202 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4204 struct ice_aq_get_set_rss_lut_params lut_params;
4212 pf = ICE_VSI_TO_PF(vsi);
4213 hw = ICE_VSI_TO_HW(vsi);
4215 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4216 lut_params.vsi_handle = vsi->idx;
4217 lut_params.lut_size = lut_size;
4218 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4219 lut_params.lut = lut;
4220 lut_params.global_lut_id = 0;
4221 ret = ice_aq_set_rss_lut(hw, &lut_params);
4223 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4227 uint64_t *lut_dw = (uint64_t *)lut;
4228 uint16_t i, lut_size_dw = lut_size / 4;
4230 for (i = 0; i < lut_size_dw; i++)
4231 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4240 ice_rss_reta_update(struct rte_eth_dev *dev,
4241 struct rte_eth_rss_reta_entry64 *reta_conf,
4244 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4245 uint16_t i, lut_size = pf->hash_lut_size;
4246 uint16_t idx, shift;
4250 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4251 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4252 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4254 "The size of hash lookup table configured (%d)"
4255 "doesn't match the number hardware can "
4256 "supported (128, 512, 2048)",
4261 /* It MUST use the current LUT size to get the RSS lookup table,
4262 * otherwise if will fail with -100 error code.
4264 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
4266 PMD_DRV_LOG(ERR, "No memory can be allocated");
4269 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4273 for (i = 0; i < reta_size; i++) {
4274 idx = i / RTE_RETA_GROUP_SIZE;
4275 shift = i % RTE_RETA_GROUP_SIZE;
4276 if (reta_conf[idx].mask & (1ULL << shift))
4277 lut[i] = reta_conf[idx].reta[shift];
4279 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4280 if (ret == 0 && lut_size != reta_size) {
4282 "The size of hash lookup table is changed from (%d) to (%d)",
4283 lut_size, reta_size);
4284 pf->hash_lut_size = reta_size;
4294 ice_rss_reta_query(struct rte_eth_dev *dev,
4295 struct rte_eth_rss_reta_entry64 *reta_conf,
4298 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4299 uint16_t i, lut_size = pf->hash_lut_size;
4300 uint16_t idx, shift;
4304 if (reta_size != lut_size) {
4306 "The size of hash lookup table configured (%d)"
4307 "doesn't match the number hardware can "
4309 reta_size, lut_size);
4313 lut = rte_zmalloc(NULL, reta_size, 0);
4315 PMD_DRV_LOG(ERR, "No memory can be allocated");
4319 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4323 for (i = 0; i < reta_size; i++) {
4324 idx = i / RTE_RETA_GROUP_SIZE;
4325 shift = i % RTE_RETA_GROUP_SIZE;
4326 if (reta_conf[idx].mask & (1ULL << shift))
4327 reta_conf[idx].reta[shift] = lut[i];
4337 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4339 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4342 if (!key || key_len == 0) {
4343 PMD_DRV_LOG(DEBUG, "No key to be configured");
4345 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4347 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4351 struct ice_aqc_get_set_rss_keys *key_dw =
4352 (struct ice_aqc_get_set_rss_keys *)key;
4354 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4356 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4364 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4366 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4369 if (!key || !key_len)
4372 ret = ice_aq_get_rss_key
4374 (struct ice_aqc_get_set_rss_keys *)key);
4376 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4379 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4385 ice_rss_hash_update(struct rte_eth_dev *dev,
4386 struct rte_eth_rss_conf *rss_conf)
4388 enum ice_status status = ICE_SUCCESS;
4389 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4390 struct ice_vsi *vsi = pf->main_vsi;
4393 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4397 if (rss_conf->rss_hf == 0)
4400 /* RSS hash configuration */
4401 ice_rss_hash_set(pf, rss_conf->rss_hf);
4407 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4408 struct rte_eth_rss_conf *rss_conf)
4410 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4411 struct ice_vsi *vsi = pf->main_vsi;
4413 ice_get_rss_key(vsi, rss_conf->rss_key,
4414 &rss_conf->rss_key_len);
4416 rss_conf->rss_hf = pf->rss_hf;
4421 ice_promisc_enable(struct rte_eth_dev *dev)
4423 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4424 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4425 struct ice_vsi *vsi = pf->main_vsi;
4426 enum ice_status status;
4430 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4431 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4433 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4435 case ICE_ERR_ALREADY_EXISTS:
4436 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4440 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4448 ice_promisc_disable(struct rte_eth_dev *dev)
4450 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4451 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4452 struct ice_vsi *vsi = pf->main_vsi;
4453 enum ice_status status;
4457 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4458 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4460 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4461 if (status != ICE_SUCCESS) {
4462 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4470 ice_allmulti_enable(struct rte_eth_dev *dev)
4472 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4473 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4474 struct ice_vsi *vsi = pf->main_vsi;
4475 enum ice_status status;
4479 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4481 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4484 case ICE_ERR_ALREADY_EXISTS:
4485 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4489 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4497 ice_allmulti_disable(struct rte_eth_dev *dev)
4499 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4500 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4501 struct ice_vsi *vsi = pf->main_vsi;
4502 enum ice_status status;
4506 if (dev->data->promiscuous == 1)
4507 return 0; /* must remain in all_multicast mode */
4509 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4511 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4512 if (status != ICE_SUCCESS) {
4513 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4520 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4523 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4524 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4525 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4529 msix_intr = intr_handle->intr_vec[queue_id];
4531 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4532 GLINT_DYN_CTL_ITR_INDX_M;
4533 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4535 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4536 rte_intr_ack(&pci_dev->intr_handle);
4541 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4544 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4545 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4546 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4549 msix_intr = intr_handle->intr_vec[queue_id];
4551 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4557 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4559 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4564 ver = hw->flash.orom.major;
4565 patch = hw->flash.orom.patch;
4566 build = hw->flash.orom.build;
4568 ret = snprintf(fw_version, fw_size,
4569 "%x.%02x 0x%08x %d.%d.%d",
4570 hw->flash.nvm.major,
4571 hw->flash.nvm.minor,
4572 hw->flash.nvm.eetrack,
4575 /* add the size of '\0' */
4577 if (fw_size < (u32)ret)
4584 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4587 struct ice_vsi_ctx ctxt;
4588 uint8_t vlan_flags = 0;
4591 if (!vsi || !info) {
4592 PMD_DRV_LOG(ERR, "invalid parameters");
4597 vsi->info.port_based_inner_vlan = info->config.pvid;
4599 * If insert pvid is enabled, only tagged pkts are
4600 * allowed to be sent out.
4602 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4603 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4605 vsi->info.port_based_inner_vlan = 0;
4606 if (info->config.reject.tagged == 0)
4607 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4609 if (info->config.reject.untagged == 0)
4610 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4612 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4613 ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4614 vsi->info.inner_vlan_flags |= vlan_flags;
4615 memset(&ctxt, 0, sizeof(ctxt));
4616 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4617 ctxt.info.valid_sections =
4618 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4619 ctxt.vsi_num = vsi->vsi_id;
4621 hw = ICE_VSI_TO_HW(vsi);
4622 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4623 if (ret != ICE_SUCCESS) {
4625 "update VSI for VLAN insert failed, err %d",
4630 vsi->info.valid_sections |=
4631 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4637 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4639 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4640 struct ice_vsi *vsi = pf->main_vsi;
4641 struct rte_eth_dev_data *data = pf->dev_data;
4642 struct ice_vsi_vlan_pvid_info info;
4645 memset(&info, 0, sizeof(info));
4648 info.config.pvid = pvid;
4650 info.config.reject.tagged =
4651 data->dev_conf.txmode.hw_vlan_reject_tagged;
4652 info.config.reject.untagged =
4653 data->dev_conf.txmode.hw_vlan_reject_untagged;
4656 ret = ice_vsi_vlan_pvid_set(vsi, &info);
4658 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4666 ice_get_eeprom_length(struct rte_eth_dev *dev)
4668 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4670 return hw->flash.flash_size;
4674 ice_get_eeprom(struct rte_eth_dev *dev,
4675 struct rte_dev_eeprom_info *eeprom)
4677 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4678 enum ice_status status = ICE_SUCCESS;
4679 uint8_t *data = eeprom->data;
4681 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4683 status = ice_acquire_nvm(hw, ICE_RES_READ);
4685 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4689 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4692 ice_release_nvm(hw);
4695 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4703 ice_stat_update_32(struct ice_hw *hw,
4711 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4715 if (new_data >= *offset)
4716 *stat = (uint64_t)(new_data - *offset);
4718 *stat = (uint64_t)((new_data +
4719 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4724 ice_stat_update_40(struct ice_hw *hw,
4733 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4734 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4740 if (new_data >= *offset)
4741 *stat = new_data - *offset;
4743 *stat = (uint64_t)((new_data +
4744 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4747 *stat &= ICE_40_BIT_MASK;
4750 /* Get all the statistics of a VSI */
4752 ice_update_vsi_stats(struct ice_vsi *vsi)
4754 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4755 struct ice_eth_stats *nes = &vsi->eth_stats;
4756 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4757 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4759 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4760 vsi->offset_loaded, &oes->rx_bytes,
4762 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4763 vsi->offset_loaded, &oes->rx_unicast,
4765 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4766 vsi->offset_loaded, &oes->rx_multicast,
4767 &nes->rx_multicast);
4768 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4769 vsi->offset_loaded, &oes->rx_broadcast,
4770 &nes->rx_broadcast);
4771 /* enlarge the limitation when rx_bytes overflowed */
4772 if (vsi->offset_loaded) {
4773 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4774 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4775 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4777 vsi->old_rx_bytes = nes->rx_bytes;
4778 /* exclude CRC bytes */
4779 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4780 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4782 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4783 &oes->rx_discards, &nes->rx_discards);
4784 /* GLV_REPC not supported */
4785 /* GLV_RMPC not supported */
4786 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4787 &oes->rx_unknown_protocol,
4788 &nes->rx_unknown_protocol);
4789 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4790 vsi->offset_loaded, &oes->tx_bytes,
4792 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4793 vsi->offset_loaded, &oes->tx_unicast,
4795 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4796 vsi->offset_loaded, &oes->tx_multicast,
4797 &nes->tx_multicast);
4798 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4799 vsi->offset_loaded, &oes->tx_broadcast,
4800 &nes->tx_broadcast);
4801 /* GLV_TDPC not supported */
4802 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4803 &oes->tx_errors, &nes->tx_errors);
4804 /* enlarge the limitation when tx_bytes overflowed */
4805 if (vsi->offset_loaded) {
4806 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4807 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4808 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4810 vsi->old_tx_bytes = nes->tx_bytes;
4811 vsi->offset_loaded = true;
4813 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4815 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4816 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4817 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4818 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4819 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4820 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4821 nes->rx_unknown_protocol);
4822 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4823 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4824 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4825 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4826 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4827 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4828 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4833 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4835 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4836 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4838 /* Get statistics of struct ice_eth_stats */
4839 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4840 GLPRT_GORCL(hw->port_info->lport),
4841 pf->offset_loaded, &os->eth.rx_bytes,
4843 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4844 GLPRT_UPRCL(hw->port_info->lport),
4845 pf->offset_loaded, &os->eth.rx_unicast,
4846 &ns->eth.rx_unicast);
4847 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4848 GLPRT_MPRCL(hw->port_info->lport),
4849 pf->offset_loaded, &os->eth.rx_multicast,
4850 &ns->eth.rx_multicast);
4851 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4852 GLPRT_BPRCL(hw->port_info->lport),
4853 pf->offset_loaded, &os->eth.rx_broadcast,
4854 &ns->eth.rx_broadcast);
4855 ice_stat_update_32(hw, PRTRPB_RDPC,
4856 pf->offset_loaded, &os->eth.rx_discards,
4857 &ns->eth.rx_discards);
4858 /* enlarge the limitation when rx_bytes overflowed */
4859 if (pf->offset_loaded) {
4860 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4861 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4862 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4864 pf->old_rx_bytes = ns->eth.rx_bytes;
4866 /* Workaround: CRC size should not be included in byte statistics,
4867 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4870 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4871 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4873 /* GLPRT_REPC not supported */
4874 /* GLPRT_RMPC not supported */
4875 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4877 &os->eth.rx_unknown_protocol,
4878 &ns->eth.rx_unknown_protocol);
4879 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4880 GLPRT_GOTCL(hw->port_info->lport),
4881 pf->offset_loaded, &os->eth.tx_bytes,
4883 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4884 GLPRT_UPTCL(hw->port_info->lport),
4885 pf->offset_loaded, &os->eth.tx_unicast,
4886 &ns->eth.tx_unicast);
4887 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4888 GLPRT_MPTCL(hw->port_info->lport),
4889 pf->offset_loaded, &os->eth.tx_multicast,
4890 &ns->eth.tx_multicast);
4891 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4892 GLPRT_BPTCL(hw->port_info->lport),
4893 pf->offset_loaded, &os->eth.tx_broadcast,
4894 &ns->eth.tx_broadcast);
4895 /* enlarge the limitation when tx_bytes overflowed */
4896 if (pf->offset_loaded) {
4897 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4898 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4899 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4901 pf->old_tx_bytes = ns->eth.tx_bytes;
4902 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4903 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4905 /* GLPRT_TEPC not supported */
4907 /* additional port specific stats */
4908 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4909 pf->offset_loaded, &os->tx_dropped_link_down,
4910 &ns->tx_dropped_link_down);
4911 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4912 pf->offset_loaded, &os->crc_errors,
4914 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4915 pf->offset_loaded, &os->illegal_bytes,
4916 &ns->illegal_bytes);
4917 /* GLPRT_ERRBC not supported */
4918 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4919 pf->offset_loaded, &os->mac_local_faults,
4920 &ns->mac_local_faults);
4921 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4922 pf->offset_loaded, &os->mac_remote_faults,
4923 &ns->mac_remote_faults);
4925 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4926 pf->offset_loaded, &os->rx_len_errors,
4927 &ns->rx_len_errors);
4929 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4930 pf->offset_loaded, &os->link_xon_rx,
4932 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4933 pf->offset_loaded, &os->link_xoff_rx,
4935 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4936 pf->offset_loaded, &os->link_xon_tx,
4938 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4939 pf->offset_loaded, &os->link_xoff_tx,
4941 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4942 GLPRT_PRC64L(hw->port_info->lport),
4943 pf->offset_loaded, &os->rx_size_64,
4945 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4946 GLPRT_PRC127L(hw->port_info->lport),
4947 pf->offset_loaded, &os->rx_size_127,
4949 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4950 GLPRT_PRC255L(hw->port_info->lport),
4951 pf->offset_loaded, &os->rx_size_255,
4953 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4954 GLPRT_PRC511L(hw->port_info->lport),
4955 pf->offset_loaded, &os->rx_size_511,
4957 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4958 GLPRT_PRC1023L(hw->port_info->lport),
4959 pf->offset_loaded, &os->rx_size_1023,
4961 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4962 GLPRT_PRC1522L(hw->port_info->lport),
4963 pf->offset_loaded, &os->rx_size_1522,
4965 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4966 GLPRT_PRC9522L(hw->port_info->lport),
4967 pf->offset_loaded, &os->rx_size_big,
4969 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4970 pf->offset_loaded, &os->rx_undersize,
4972 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4973 pf->offset_loaded, &os->rx_fragments,
4975 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4976 pf->offset_loaded, &os->rx_oversize,
4978 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4979 pf->offset_loaded, &os->rx_jabber,
4981 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4982 GLPRT_PTC64L(hw->port_info->lport),
4983 pf->offset_loaded, &os->tx_size_64,
4985 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4986 GLPRT_PTC127L(hw->port_info->lport),
4987 pf->offset_loaded, &os->tx_size_127,
4989 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4990 GLPRT_PTC255L(hw->port_info->lport),
4991 pf->offset_loaded, &os->tx_size_255,
4993 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4994 GLPRT_PTC511L(hw->port_info->lport),
4995 pf->offset_loaded, &os->tx_size_511,
4997 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4998 GLPRT_PTC1023L(hw->port_info->lport),
4999 pf->offset_loaded, &os->tx_size_1023,
5001 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5002 GLPRT_PTC1522L(hw->port_info->lport),
5003 pf->offset_loaded, &os->tx_size_1522,
5005 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5006 GLPRT_PTC9522L(hw->port_info->lport),
5007 pf->offset_loaded, &os->tx_size_big,
5010 /* GLPRT_MSPDC not supported */
5011 /* GLPRT_XEC not supported */
5013 pf->offset_loaded = true;
5016 ice_update_vsi_stats(pf->main_vsi);
5019 /* Get all statistics of a port */
5021 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5023 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5024 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5025 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5027 /* call read registers - updates values, now write them to struct */
5028 ice_read_stats_registers(pf, hw);
5030 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5031 pf->main_vsi->eth_stats.rx_multicast +
5032 pf->main_vsi->eth_stats.rx_broadcast -
5033 pf->main_vsi->eth_stats.rx_discards;
5034 stats->opackets = ns->eth.tx_unicast +
5035 ns->eth.tx_multicast +
5036 ns->eth.tx_broadcast;
5037 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
5038 stats->obytes = ns->eth.tx_bytes;
5039 stats->oerrors = ns->eth.tx_errors +
5040 pf->main_vsi->eth_stats.tx_errors;
5043 stats->imissed = ns->eth.rx_discards +
5044 pf->main_vsi->eth_stats.rx_discards;
5045 stats->ierrors = ns->crc_errors +
5047 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5049 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5050 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
5051 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5052 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5053 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5054 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5055 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5056 pf->main_vsi->eth_stats.rx_discards);
5057 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5058 ns->eth.rx_unknown_protocol);
5059 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
5060 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5061 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5062 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5063 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5064 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5065 pf->main_vsi->eth_stats.tx_discards);
5066 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
5068 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
5069 ns->tx_dropped_link_down);
5070 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5071 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
5073 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
5074 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
5075 ns->mac_local_faults);
5076 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
5077 ns->mac_remote_faults);
5078 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
5079 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
5080 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
5081 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
5082 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
5083 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
5084 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
5085 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
5086 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
5087 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
5088 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
5089 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
5090 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
5091 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
5092 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
5093 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
5094 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
5095 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
5096 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
5097 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
5098 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
5099 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
5100 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
5101 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5105 /* Reset the statistics */
5107 ice_stats_reset(struct rte_eth_dev *dev)
5109 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5110 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5112 /* Mark PF and VSI stats to update the offset, aka "reset" */
5113 pf->offset_loaded = false;
5115 pf->main_vsi->offset_loaded = false;
5117 /* read the stats, reading current register values into offset */
5118 ice_read_stats_registers(pf, hw);
5124 ice_xstats_calc_num(void)
5128 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5134 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5137 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5138 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5141 struct ice_hw_port_stats *hw_stats = &pf->stats;
5143 count = ice_xstats_calc_num();
5147 ice_read_stats_registers(pf, hw);
5154 /* Get stats from ice_eth_stats struct */
5155 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5156 xstats[count].value =
5157 *(uint64_t *)((char *)&hw_stats->eth +
5158 ice_stats_strings[i].offset);
5159 xstats[count].id = count;
5163 /* Get individiual stats from ice_hw_port struct */
5164 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5165 xstats[count].value =
5166 *(uint64_t *)((char *)hw_stats +
5167 ice_hw_port_strings[i].offset);
5168 xstats[count].id = count;
5175 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5176 struct rte_eth_xstat_name *xstats_names,
5177 __rte_unused unsigned int limit)
5179 unsigned int count = 0;
5183 return ice_xstats_calc_num();
5185 /* Note: limit checked in rte_eth_xstats_names() */
5187 /* Get stats from ice_eth_stats struct */
5188 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5189 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5190 sizeof(xstats_names[count].name));
5194 /* Get individiual stats from ice_hw_port struct */
5195 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5196 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5197 sizeof(xstats_names[count].name));
5205 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
5206 enum rte_filter_type filter_type,
5207 enum rte_filter_op filter_op,
5215 switch (filter_type) {
5216 case RTE_ETH_FILTER_GENERIC:
5217 if (filter_op != RTE_ETH_FILTER_GET)
5219 *(const void **)arg = &ice_flow_ops;
5222 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5231 /* Add UDP tunneling port */
5233 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5234 struct rte_eth_udp_tunnel *udp_tunnel)
5237 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5239 if (udp_tunnel == NULL)
5242 switch (udp_tunnel->prot_type) {
5243 case RTE_TUNNEL_TYPE_VXLAN:
5244 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5247 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5255 /* Delete UDP tunneling port */
5257 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5258 struct rte_eth_udp_tunnel *udp_tunnel)
5261 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5263 if (udp_tunnel == NULL)
5266 switch (udp_tunnel->prot_type) {
5267 case RTE_TUNNEL_TYPE_VXLAN:
5268 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5271 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5280 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5281 struct rte_pci_device *pci_dev)
5283 return rte_eth_dev_pci_generic_probe(pci_dev,
5284 sizeof(struct ice_adapter),
5289 ice_pci_remove(struct rte_pci_device *pci_dev)
5291 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5294 static struct rte_pci_driver rte_ice_pmd = {
5295 .id_table = pci_id_ice_map,
5296 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5297 .probe = ice_pci_probe,
5298 .remove = ice_pci_remove,
5302 * Driver initialization routine.
5303 * Invoked once at EAL init time.
5304 * Register itself as the [Poll Mode] Driver of PCI devices.
5306 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5307 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5308 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5309 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5310 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5311 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5312 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5314 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5315 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5316 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5317 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5319 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5320 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5322 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5323 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);