1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "ice_ethdev.h"
18 #include "ice_switch_filter.h"
21 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
22 #define ICE_PROTO_XTR_ARG "proto_xtr"
24 static const char * const ice_valid_args[] = {
25 ICE_SAFE_MODE_SUPPORT_ARG,
30 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
32 /* DDP package search path */
33 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
34 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
35 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
36 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
38 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
39 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
40 #define ICE_MAX_PKG_FILENAME_SIZE 256
43 int ice_logtype_driver;
44 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
47 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
50 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
51 int ice_logtype_tx_free;
54 static int ice_dev_configure(struct rte_eth_dev *dev);
55 static int ice_dev_start(struct rte_eth_dev *dev);
56 static void ice_dev_stop(struct rte_eth_dev *dev);
57 static void ice_dev_close(struct rte_eth_dev *dev);
58 static int ice_dev_reset(struct rte_eth_dev *dev);
59 static int ice_dev_info_get(struct rte_eth_dev *dev,
60 struct rte_eth_dev_info *dev_info);
61 static int ice_link_update(struct rte_eth_dev *dev,
62 int wait_to_complete);
63 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
64 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
66 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
67 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
68 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
69 enum rte_vlan_type vlan_type,
71 static int ice_rss_reta_update(struct rte_eth_dev *dev,
72 struct rte_eth_rss_reta_entry64 *reta_conf,
74 static int ice_rss_reta_query(struct rte_eth_dev *dev,
75 struct rte_eth_rss_reta_entry64 *reta_conf,
77 static int ice_rss_hash_update(struct rte_eth_dev *dev,
78 struct rte_eth_rss_conf *rss_conf);
79 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
80 struct rte_eth_rss_conf *rss_conf);
81 static int ice_promisc_enable(struct rte_eth_dev *dev);
82 static int ice_promisc_disable(struct rte_eth_dev *dev);
83 static int ice_allmulti_enable(struct rte_eth_dev *dev);
84 static int ice_allmulti_disable(struct rte_eth_dev *dev);
85 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
88 static int ice_macaddr_set(struct rte_eth_dev *dev,
89 struct rte_ether_addr *mac_addr);
90 static int ice_macaddr_add(struct rte_eth_dev *dev,
91 struct rte_ether_addr *mac_addr,
92 __rte_unused uint32_t index,
94 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
95 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
97 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
99 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
101 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
102 uint16_t pvid, int on);
103 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
104 static int ice_get_eeprom(struct rte_eth_dev *dev,
105 struct rte_dev_eeprom_info *eeprom);
106 static int ice_stats_get(struct rte_eth_dev *dev,
107 struct rte_eth_stats *stats);
108 static int ice_stats_reset(struct rte_eth_dev *dev);
109 static int ice_xstats_get(struct rte_eth_dev *dev,
110 struct rte_eth_xstat *xstats, unsigned int n);
111 static int ice_xstats_get_names(struct rte_eth_dev *dev,
112 struct rte_eth_xstat_name *xstats_names,
114 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
115 enum rte_filter_type filter_type,
116 enum rte_filter_op filter_op,
118 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
119 struct rte_eth_udp_tunnel *udp_tunnel);
120 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
121 struct rte_eth_udp_tunnel *udp_tunnel);
123 static const struct rte_pci_id pci_id_ice_map[] = {
124 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
125 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
126 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
127 { .vendor_id = 0, /* sentinel */ },
130 static const struct eth_dev_ops ice_eth_dev_ops = {
131 .dev_configure = ice_dev_configure,
132 .dev_start = ice_dev_start,
133 .dev_stop = ice_dev_stop,
134 .dev_close = ice_dev_close,
135 .dev_reset = ice_dev_reset,
136 .dev_set_link_up = ice_dev_set_link_up,
137 .dev_set_link_down = ice_dev_set_link_down,
138 .rx_queue_start = ice_rx_queue_start,
139 .rx_queue_stop = ice_rx_queue_stop,
140 .tx_queue_start = ice_tx_queue_start,
141 .tx_queue_stop = ice_tx_queue_stop,
142 .rx_queue_setup = ice_rx_queue_setup,
143 .rx_queue_release = ice_rx_queue_release,
144 .tx_queue_setup = ice_tx_queue_setup,
145 .tx_queue_release = ice_tx_queue_release,
146 .dev_infos_get = ice_dev_info_get,
147 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
148 .link_update = ice_link_update,
149 .mtu_set = ice_mtu_set,
150 .mac_addr_set = ice_macaddr_set,
151 .mac_addr_add = ice_macaddr_add,
152 .mac_addr_remove = ice_macaddr_remove,
153 .vlan_filter_set = ice_vlan_filter_set,
154 .vlan_offload_set = ice_vlan_offload_set,
155 .vlan_tpid_set = ice_vlan_tpid_set,
156 .reta_update = ice_rss_reta_update,
157 .reta_query = ice_rss_reta_query,
158 .rss_hash_update = ice_rss_hash_update,
159 .rss_hash_conf_get = ice_rss_hash_conf_get,
160 .promiscuous_enable = ice_promisc_enable,
161 .promiscuous_disable = ice_promisc_disable,
162 .allmulticast_enable = ice_allmulti_enable,
163 .allmulticast_disable = ice_allmulti_disable,
164 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
165 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
166 .fw_version_get = ice_fw_version_get,
167 .vlan_pvid_set = ice_vlan_pvid_set,
168 .rxq_info_get = ice_rxq_info_get,
169 .txq_info_get = ice_txq_info_get,
170 .rx_burst_mode_get = ice_rx_burst_mode_get,
171 .tx_burst_mode_get = ice_tx_burst_mode_get,
172 .get_eeprom_length = ice_get_eeprom_length,
173 .get_eeprom = ice_get_eeprom,
174 .rx_queue_count = ice_rx_queue_count,
175 .rx_descriptor_status = ice_rx_descriptor_status,
176 .tx_descriptor_status = ice_tx_descriptor_status,
177 .stats_get = ice_stats_get,
178 .stats_reset = ice_stats_reset,
179 .xstats_get = ice_xstats_get,
180 .xstats_get_names = ice_xstats_get_names,
181 .xstats_reset = ice_stats_reset,
182 .filter_ctrl = ice_dev_filter_ctrl,
183 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
184 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
187 /* store statistics names and its offset in stats structure */
188 struct ice_xstats_name_off {
189 char name[RTE_ETH_XSTATS_NAME_SIZE];
193 static const struct ice_xstats_name_off ice_stats_strings[] = {
194 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
195 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
196 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
197 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
198 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
199 rx_unknown_protocol)},
200 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
201 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
202 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
203 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
206 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
207 sizeof(ice_stats_strings[0]))
209 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
210 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
211 tx_dropped_link_down)},
212 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
213 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
215 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
216 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
218 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
220 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
222 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
223 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
224 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
225 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
226 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
227 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
229 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
231 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
233 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
235 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
237 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
239 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
241 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
243 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
244 mac_short_pkt_dropped)},
245 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
247 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
248 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
249 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
251 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
253 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
255 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
257 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
259 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
263 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
264 sizeof(ice_hw_port_strings[0]))
267 ice_init_controlq_parameter(struct ice_hw *hw)
269 /* fields for adminq */
270 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
271 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
272 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
273 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
275 /* fields for mailboxq, DPDK used as PF host */
276 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
277 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
278 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
279 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
283 lookup_proto_xtr_type(const char *xtr_name)
287 enum proto_xtr_type type;
289 { "vlan", PROTO_XTR_VLAN },
290 { "ipv4", PROTO_XTR_IPV4 },
291 { "ipv6", PROTO_XTR_IPV6 },
292 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
293 { "tcp", PROTO_XTR_TCP },
297 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
298 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
299 return xtr_type_map[i].type;
306 * Parse elem, the elem could be single number/range or '(' ')' group
307 * 1) A single number elem, it's just a simple digit. e.g. 9
308 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
309 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
310 * Within group elem, '-' used for a range separator;
311 * ',' used for a single number.
314 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
316 const char *str = input;
321 while (isblank(*str))
324 if (!isdigit(*str) && *str != '(')
327 /* process single number or single range of number */
330 idx = strtoul(str, &end, 10);
331 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
334 while (isblank(*end))
340 /* process single <number>-<number> */
343 while (isblank(*end))
349 idx = strtoul(end, &end, 10);
350 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
354 while (isblank(*end))
361 for (idx = RTE_MIN(min, max);
362 idx <= RTE_MAX(min, max); idx++)
363 devargs->proto_xtr[idx] = xtr_type;
368 /* process set within bracket */
370 while (isblank(*str))
375 min = ICE_MAX_QUEUE_NUM;
377 /* go ahead to the first digit */
378 while (isblank(*str))
383 /* get the digit value */
385 idx = strtoul(str, &end, 10);
386 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
389 /* go ahead to separator '-',',' and ')' */
390 while (isblank(*end))
393 if (min == ICE_MAX_QUEUE_NUM)
395 else /* avoid continuous '-' */
397 } else if (*end == ',' || *end == ')') {
399 if (min == ICE_MAX_QUEUE_NUM)
402 for (idx = RTE_MIN(min, max);
403 idx <= RTE_MAX(min, max); idx++)
404 devargs->proto_xtr[idx] = xtr_type;
406 min = ICE_MAX_QUEUE_NUM;
412 } while (*end != ')' && *end != '\0');
418 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
420 const char *queue_start;
425 while (isblank(*queues))
428 if (*queues != '[') {
429 xtr_type = lookup_proto_xtr_type(queues);
433 devargs->proto_xtr_dflt = xtr_type;
440 while (isblank(*queues))
445 queue_start = queues;
447 /* go across a complete bracket */
448 if (*queue_start == '(') {
449 queues += strcspn(queues, ")");
454 /* scan the separator ':' */
455 queues += strcspn(queues, ":");
456 if (*queues++ != ':')
458 while (isblank(*queues))
461 for (idx = 0; ; idx++) {
462 if (isblank(queues[idx]) ||
463 queues[idx] == ',' ||
464 queues[idx] == ']' ||
468 if (idx > sizeof(xtr_name) - 2)
471 xtr_name[idx] = queues[idx];
473 xtr_name[idx] = '\0';
474 xtr_type = lookup_proto_xtr_type(xtr_name);
480 while (isblank(*queues) || *queues == ',' || *queues == ']')
483 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
485 } while (*queues != '\0');
491 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
494 struct ice_devargs *devargs = extra_args;
496 if (value == NULL || extra_args == NULL)
499 if (parse_queue_proto_xtr(value, devargs) < 0) {
501 "The protocol extraction parameter is wrong : '%s'",
510 ice_proto_xtr_support(struct ice_hw *hw)
512 #define FLX_REG(val, fld, idx) \
513 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
514 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
520 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
521 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
522 ICE_PROT_IPV4_OF_OR_S },
523 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
524 ICE_PROT_IPV6_OF_OR_S },
525 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
526 ICE_PROT_IPV6_OF_OR_S },
527 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
531 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
532 uint32_t rxdid = xtr_sets[i].rxdid;
535 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
536 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
538 if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
539 FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
543 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
544 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
546 if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
547 FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
556 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
559 struct pool_entry *entry;
564 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
567 "Failed to allocate memory for resource pool");
571 /* queue heap initialize */
572 pool->num_free = num;
575 LIST_INIT(&pool->alloc_list);
576 LIST_INIT(&pool->free_list);
578 /* Initialize element */
582 LIST_INSERT_HEAD(&pool->free_list, entry, next);
587 ice_res_pool_alloc(struct ice_res_pool_info *pool,
590 struct pool_entry *entry, *valid_entry;
593 PMD_INIT_LOG(ERR, "Invalid parameter");
597 if (pool->num_free < num) {
598 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
599 num, pool->num_free);
604 /* Lookup in free list and find most fit one */
605 LIST_FOREACH(entry, &pool->free_list, next) {
606 if (entry->len >= num) {
608 if (entry->len == num) {
613 valid_entry->len > entry->len)
618 /* Not find one to satisfy the request, return */
620 PMD_INIT_LOG(ERR, "No valid entry found");
624 * The entry have equal queue number as requested,
625 * remove it from alloc_list.
627 if (valid_entry->len == num) {
628 LIST_REMOVE(valid_entry, next);
631 * The entry have more numbers than requested,
632 * create a new entry for alloc_list and minus its
633 * queue base and number in free_list.
635 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
638 "Failed to allocate memory for "
642 entry->base = valid_entry->base;
644 valid_entry->base += num;
645 valid_entry->len -= num;
649 /* Insert it into alloc list, not sorted */
650 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
652 pool->num_free -= valid_entry->len;
653 pool->num_alloc += valid_entry->len;
655 return valid_entry->base + pool->base;
659 ice_res_pool_destroy(struct ice_res_pool_info *pool)
661 struct pool_entry *entry, *next_entry;
666 for (entry = LIST_FIRST(&pool->alloc_list);
667 entry && (next_entry = LIST_NEXT(entry, next), 1);
668 entry = next_entry) {
669 LIST_REMOVE(entry, next);
673 for (entry = LIST_FIRST(&pool->free_list);
674 entry && (next_entry = LIST_NEXT(entry, next), 1);
675 entry = next_entry) {
676 LIST_REMOVE(entry, next);
683 LIST_INIT(&pool->alloc_list);
684 LIST_INIT(&pool->free_list);
688 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
690 /* Set VSI LUT selection */
691 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
692 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
693 /* Set Hash scheme */
694 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
695 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
697 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
700 static enum ice_status
701 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
702 struct ice_aqc_vsi_props *info,
703 uint8_t enabled_tcmap)
705 uint16_t bsf, qp_idx;
707 /* default tc 0 now. Multi-TC supporting need to be done later.
708 * Configure TC and queue mapping parameters, for enabled TC,
709 * allocate qpnum_per_tc queues to this traffic.
711 if (enabled_tcmap != 0x01) {
712 PMD_INIT_LOG(ERR, "only TC0 is supported");
716 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
717 bsf = rte_bsf32(vsi->nb_qps);
718 /* Adjust the queue number to actual queues that can be applied */
719 vsi->nb_qps = 0x1 << bsf;
722 /* Set tc and queue mapping with VSI */
723 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
724 ICE_AQ_VSI_TC_Q_OFFSET_S) |
725 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
727 /* Associate queue number with VSI */
728 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
729 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
730 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
731 info->valid_sections |=
732 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
733 /* Set the info.ingress_table and info.egress_table
734 * for UP translate table. Now just set it to 1:1 map by default
735 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
737 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
738 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
739 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
740 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
745 ice_init_mac_address(struct rte_eth_dev *dev)
747 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
749 if (!rte_is_unicast_ether_addr
750 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
751 PMD_INIT_LOG(ERR, "Invalid MAC address");
756 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
757 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
759 dev->data->mac_addrs =
760 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
761 if (!dev->data->mac_addrs) {
763 "Failed to allocate memory to store mac address");
766 /* store it to dev data */
768 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
769 &dev->data->mac_addrs[0]);
773 /* Find out specific MAC filter */
774 static struct ice_mac_filter *
775 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
777 struct ice_mac_filter *f;
779 TAILQ_FOREACH(f, &vsi->mac_list, next) {
780 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
788 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
790 struct ice_fltr_list_entry *m_list_itr = NULL;
791 struct ice_mac_filter *f;
792 struct LIST_HEAD_TYPE list_head;
793 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
796 /* If it's added and configured, return */
797 f = ice_find_mac_filter(vsi, mac_addr);
799 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
803 INIT_LIST_HEAD(&list_head);
805 m_list_itr = (struct ice_fltr_list_entry *)
806 ice_malloc(hw, sizeof(*m_list_itr));
811 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
812 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
813 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
814 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
815 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
816 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
817 m_list_itr->fltr_info.vsi_handle = vsi->idx;
819 LIST_ADD(&m_list_itr->list_entry, &list_head);
822 ret = ice_add_mac(hw, &list_head);
823 if (ret != ICE_SUCCESS) {
824 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
828 /* Add the mac addr into mac list */
829 f = rte_zmalloc(NULL, sizeof(*f), 0);
831 PMD_DRV_LOG(ERR, "failed to allocate memory");
835 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
836 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
842 rte_free(m_list_itr);
847 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
849 struct ice_fltr_list_entry *m_list_itr = NULL;
850 struct ice_mac_filter *f;
851 struct LIST_HEAD_TYPE list_head;
852 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
855 /* Can't find it, return an error */
856 f = ice_find_mac_filter(vsi, mac_addr);
860 INIT_LIST_HEAD(&list_head);
862 m_list_itr = (struct ice_fltr_list_entry *)
863 ice_malloc(hw, sizeof(*m_list_itr));
868 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
869 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
870 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
871 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
872 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
873 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
874 m_list_itr->fltr_info.vsi_handle = vsi->idx;
876 LIST_ADD(&m_list_itr->list_entry, &list_head);
878 /* remove the mac filter */
879 ret = ice_remove_mac(hw, &list_head);
880 if (ret != ICE_SUCCESS) {
881 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
886 /* Remove the mac addr from mac list */
887 TAILQ_REMOVE(&vsi->mac_list, f, next);
893 rte_free(m_list_itr);
897 /* Find out specific VLAN filter */
898 static struct ice_vlan_filter *
899 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
901 struct ice_vlan_filter *f;
903 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
904 if (vlan_id == f->vlan_info.vlan_id)
912 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
914 struct ice_fltr_list_entry *v_list_itr = NULL;
915 struct ice_vlan_filter *f;
916 struct LIST_HEAD_TYPE list_head;
920 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
923 hw = ICE_VSI_TO_HW(vsi);
925 /* If it's added and configured, return. */
926 f = ice_find_vlan_filter(vsi, vlan_id);
928 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
932 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
935 INIT_LIST_HEAD(&list_head);
937 v_list_itr = (struct ice_fltr_list_entry *)
938 ice_malloc(hw, sizeof(*v_list_itr));
943 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
944 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
945 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
946 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
947 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
948 v_list_itr->fltr_info.vsi_handle = vsi->idx;
950 LIST_ADD(&v_list_itr->list_entry, &list_head);
953 ret = ice_add_vlan(hw, &list_head);
954 if (ret != ICE_SUCCESS) {
955 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
960 /* Add vlan into vlan list */
961 f = rte_zmalloc(NULL, sizeof(*f), 0);
963 PMD_DRV_LOG(ERR, "failed to allocate memory");
967 f->vlan_info.vlan_id = vlan_id;
968 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
974 rte_free(v_list_itr);
979 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
981 struct ice_fltr_list_entry *v_list_itr = NULL;
982 struct ice_vlan_filter *f;
983 struct LIST_HEAD_TYPE list_head;
988 * Vlan 0 is the generic filter for untagged packets
989 * and can't be removed.
991 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
994 hw = ICE_VSI_TO_HW(vsi);
996 /* Can't find it, return an error */
997 f = ice_find_vlan_filter(vsi, vlan_id);
1001 INIT_LIST_HEAD(&list_head);
1003 v_list_itr = (struct ice_fltr_list_entry *)
1004 ice_malloc(hw, sizeof(*v_list_itr));
1010 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1011 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1012 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1013 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1014 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1015 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1017 LIST_ADD(&v_list_itr->list_entry, &list_head);
1019 /* remove the vlan filter */
1020 ret = ice_remove_vlan(hw, &list_head);
1021 if (ret != ICE_SUCCESS) {
1022 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1027 /* Remove the vlan id from vlan list */
1028 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1034 rte_free(v_list_itr);
1039 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1041 struct ice_mac_filter *m_f;
1042 struct ice_vlan_filter *v_f;
1045 if (!vsi || !vsi->mac_num)
1048 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1049 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1050 if (ret != ICE_SUCCESS) {
1056 if (vsi->vlan_num == 0)
1059 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1060 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1061 if (ret != ICE_SUCCESS) {
1072 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1074 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1075 struct ice_vsi_ctx ctxt;
1079 /* Check if it has been already on or off */
1080 if (vsi->info.valid_sections &
1081 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1083 if ((vsi->info.outer_tag_flags &
1084 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1085 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1086 return 0; /* already on */
1088 if (!(vsi->info.outer_tag_flags &
1089 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1090 return 0; /* already off */
1095 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1098 /* clear global insertion and use per packet insertion */
1099 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1100 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1101 vsi->info.outer_tag_flags |= qinq_flags;
1102 /* use default vlan type 0x8100 */
1103 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1104 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1105 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1106 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1107 ctxt.info.valid_sections =
1108 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1109 ctxt.vsi_num = vsi->vsi_id;
1110 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1113 "Update VSI failed to %s qinq stripping",
1114 on ? "enable" : "disable");
1118 vsi->info.valid_sections |=
1119 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1125 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1127 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1128 struct ice_vsi_ctx ctxt;
1132 /* Check if it has been already on or off */
1133 if (vsi->info.valid_sections &
1134 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1136 if ((vsi->info.outer_tag_flags &
1137 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1138 ICE_AQ_VSI_OUTER_TAG_COPY)
1139 return 0; /* already on */
1141 if ((vsi->info.outer_tag_flags &
1142 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1143 ICE_AQ_VSI_OUTER_TAG_NOTHING)
1144 return 0; /* already off */
1149 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1151 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1152 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1153 vsi->info.outer_tag_flags |= qinq_flags;
1154 /* use default vlan type 0x8100 */
1155 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1156 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1157 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1158 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1159 ctxt.info.valid_sections =
1160 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1161 ctxt.vsi_num = vsi->vsi_id;
1162 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1165 "Update VSI failed to %s qinq stripping",
1166 on ? "enable" : "disable");
1170 vsi->info.valid_sections |=
1171 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1177 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1181 ret = ice_vsi_config_qinq_stripping(vsi, on);
1183 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1185 ret = ice_vsi_config_qinq_insertion(vsi, on);
1187 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1194 ice_pf_enable_irq0(struct ice_hw *hw)
1196 /* reset the registers */
1197 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1198 ICE_READ_REG(hw, PFINT_OICR);
1201 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1202 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1203 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1205 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1206 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1207 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1208 PFINT_OICR_CTL_ITR_INDX_M) |
1209 PFINT_OICR_CTL_CAUSE_ENA_M);
1211 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1212 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1213 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1214 PFINT_FW_CTL_ITR_INDX_M) |
1215 PFINT_FW_CTL_CAUSE_ENA_M);
1217 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1220 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1221 GLINT_DYN_CTL_INTENA_M |
1222 GLINT_DYN_CTL_CLEARPBA_M |
1223 GLINT_DYN_CTL_ITR_INDX_M);
1230 ice_pf_disable_irq0(struct ice_hw *hw)
1232 /* Disable all interrupt types */
1233 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1239 ice_handle_aq_msg(struct rte_eth_dev *dev)
1241 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1242 struct ice_ctl_q_info *cq = &hw->adminq;
1243 struct ice_rq_event_info event;
1244 uint16_t pending, opcode;
1247 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1248 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1249 if (!event.msg_buf) {
1250 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1256 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1258 if (ret != ICE_SUCCESS) {
1260 "Failed to read msg from AdminQ, "
1262 hw->adminq.sq_last_status);
1265 opcode = rte_le_to_cpu_16(event.desc.opcode);
1268 case ice_aqc_opc_get_link_status:
1269 ret = ice_link_update(dev, 0);
1271 _rte_eth_dev_callback_process
1272 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1275 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1280 rte_free(event.msg_buf);
1285 * Interrupt handler triggered by NIC for handling
1286 * specific interrupt.
1289 * Pointer to interrupt handle.
1291 * The address of parameter (struct rte_eth_dev *) regsitered before.
1297 ice_interrupt_handler(void *param)
1299 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1300 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307 uint32_t int_fw_ctl;
1310 /* Disable interrupt */
1311 ice_pf_disable_irq0(hw);
1313 /* read out interrupt causes */
1314 oicr = ICE_READ_REG(hw, PFINT_OICR);
1316 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1319 /* No interrupt event indicated */
1320 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1321 PMD_DRV_LOG(INFO, "No interrupt event");
1326 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1327 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1328 ice_handle_aq_msg(dev);
1331 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1332 PMD_DRV_LOG(INFO, "OICR: link state change event");
1333 ice_link_update(dev, 0);
1337 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1338 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1339 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1340 if (reg & GL_MDET_TX_PQM_VALID_M) {
1341 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1342 GL_MDET_TX_PQM_PF_NUM_S;
1343 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1344 GL_MDET_TX_PQM_MAL_TYPE_S;
1345 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1346 GL_MDET_TX_PQM_QNUM_S;
1348 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1349 "%d by PQM on TX queue %d PF# %d",
1350 event, queue, pf_num);
1353 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1354 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1355 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1356 GL_MDET_TX_TCLAN_PF_NUM_S;
1357 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1358 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1359 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1360 GL_MDET_TX_TCLAN_QNUM_S;
1362 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1363 "%d by TCLAN on TX queue %d PF# %d",
1364 event, queue, pf_num);
1368 /* Enable interrupt */
1369 ice_pf_enable_irq0(hw);
1370 rte_intr_ack(dev->intr_handle);
1374 ice_init_proto_xtr(struct rte_eth_dev *dev)
1376 struct ice_adapter *ad =
1377 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1378 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1379 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1382 if (!ice_proto_xtr_support(hw)) {
1383 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1387 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1388 if (unlikely(pf->proto_xtr == NULL)) {
1389 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1393 for (i = 0; i < pf->lan_nb_qps; i++)
1394 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1395 ad->devargs.proto_xtr[i] :
1396 ad->devargs.proto_xtr_dflt;
1399 /* Initialize SW parameters of PF */
1401 ice_pf_sw_init(struct rte_eth_dev *dev)
1403 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1404 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1407 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1408 hw->func_caps.common_cap.num_rxq);
1410 pf->lan_nb_qps = pf->lan_nb_qp_max;
1412 ice_init_proto_xtr(dev);
1417 static struct ice_vsi *
1418 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1420 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1421 struct ice_vsi *vsi = NULL;
1422 struct ice_vsi_ctx vsi_ctx;
1424 struct rte_ether_addr broadcast = {
1425 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1426 struct rte_ether_addr mac_addr;
1427 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1428 uint8_t tc_bitmap = 0x1;
1430 /* hw->num_lports = 1 in NIC mode */
1431 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1435 vsi->idx = pf->next_vsi_idx;
1438 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1439 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1440 vsi->vlan_anti_spoof_on = 0;
1441 vsi->vlan_filter_on = 1;
1442 TAILQ_INIT(&vsi->mac_list);
1443 TAILQ_INIT(&vsi->vlan_list);
1445 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1446 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1447 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1448 hw->func_caps.common_cap.rss_table_size;
1449 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1451 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1452 /* base_queue in used in queue mapping of VSI add/update command.
1453 * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1454 * cases in the first stage. Only Main VSI.
1456 vsi->base_queue = 0;
1459 vsi->nb_qps = pf->lan_nb_qps;
1460 ice_vsi_config_default_rss(&vsi_ctx.info);
1461 vsi_ctx.alloc_from_pool = true;
1462 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1463 /* switch_id is queried by get_switch_config aq, which is done
1466 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1467 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1468 /* Allow all untagged or tagged packets */
1469 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1470 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1471 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1472 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1473 /* Enable VLAN/UP trip */
1474 ret = ice_vsi_config_tc_queue_mapping(vsi,
1479 "tc queue mapping with vsi failed, "
1487 /* for other types of VSI */
1488 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1492 /* VF has MSIX interrupt in VF range, don't allocate here */
1493 if (type == ICE_VSI_PF) {
1494 ret = ice_res_pool_alloc(&pf->msix_pool,
1495 RTE_MIN(vsi->nb_qps,
1496 RTE_MAX_RXTX_INTR_VEC_ID));
1498 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1501 vsi->msix_intr = ret;
1502 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1507 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1508 if (ret != ICE_SUCCESS) {
1509 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1512 /* store vsi information is SW structure */
1513 vsi->vsi_id = vsi_ctx.vsi_num;
1514 vsi->info = vsi_ctx.info;
1515 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1516 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1518 /* MAC configuration */
1519 rte_memcpy(pf->dev_addr.addr_bytes,
1520 hw->port_info->mac.perm_addr,
1523 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1524 ret = ice_add_mac_filter(vsi, &mac_addr);
1525 if (ret != ICE_SUCCESS)
1526 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1528 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1529 ret = ice_add_mac_filter(vsi, &mac_addr);
1530 if (ret != ICE_SUCCESS)
1531 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1533 /* At the beginning, only TC0. */
1534 /* What we need here is the maximam number of the TX queues.
1535 * Currently vsi->nb_qps means it.
1536 * Correct it if any change.
1538 max_txqs[0] = vsi->nb_qps;
1539 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1540 tc_bitmap, max_txqs);
1541 if (ret != ICE_SUCCESS)
1542 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1552 ice_send_driver_ver(struct ice_hw *hw)
1554 struct ice_driver_ver dv;
1556 /* we don't have driver version use 0 for dummy */
1560 dv.subbuild_ver = 0;
1561 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1563 return ice_aq_send_driver_ver(hw, &dv, NULL);
1567 ice_pf_setup(struct ice_pf *pf)
1569 struct ice_vsi *vsi;
1571 /* Clear all stats counters */
1572 pf->offset_loaded = FALSE;
1573 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1574 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1575 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1576 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1578 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1580 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1589 /* PCIe configuration space setting */
1590 #define PCI_CFG_SPACE_SIZE 256
1591 #define PCI_CFG_SPACE_EXP_SIZE 4096
1592 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
1593 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
1594 #define PCI_EXT_CAP_ID_DSN 0x03
1597 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1601 int pos = PCI_CFG_SPACE_SIZE;
1603 /* minimum 8 bytes per capability */
1604 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1606 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1607 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1612 * If we have no capabilities, this is indicated by cap ID,
1613 * cap version and next pointer all being 0.
1619 if (PCI_EXT_CAP_ID(header) == cap)
1622 pos = PCI_EXT_CAP_NEXT(header);
1624 if (pos < PCI_CFG_SPACE_SIZE)
1627 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1628 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1637 * Extract device serial number from PCIe Configuration Space and
1638 * determine the pkg file path according to the DSN.
1641 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1644 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1645 uint32_t dsn_low, dsn_high;
1646 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1648 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1651 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1652 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1653 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1654 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1656 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1660 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1661 ICE_MAX_PKG_FILENAME_SIZE);
1662 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1665 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1666 ICE_MAX_PKG_FILENAME_SIZE);
1667 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1671 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1672 if (!access(pkg_file, 0))
1674 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1678 static enum ice_pkg_type
1679 ice_load_pkg_type(struct ice_hw *hw)
1681 enum ice_pkg_type package_type;
1683 /* store the activated package type (OS default or Comms) */
1684 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1686 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1687 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1689 package_type = ICE_PKG_TYPE_COMMS;
1691 package_type = ICE_PKG_TYPE_UNKNOWN;
1693 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1694 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1695 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1696 hw->active_pkg_name);
1698 return package_type;
1701 static int ice_load_pkg(struct rte_eth_dev *dev)
1703 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1710 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1711 struct ice_adapter *ad =
1712 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1714 ice_pkg_file_search_path(pci_dev, pkg_file);
1716 file = fopen(pkg_file, "rb");
1718 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1722 err = stat(pkg_file, &fstat);
1724 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1729 buf_len = fstat.st_size;
1730 buf = rte_malloc(NULL, buf_len, 0);
1733 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1739 err = fread(buf, buf_len, 1, file);
1741 PMD_INIT_LOG(ERR, "failed to read package data\n");
1749 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1751 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1755 /* store the loaded pkg type info */
1756 ad->active_pkg_type = ice_load_pkg_type(hw);
1758 err = ice_init_hw_tbls(hw);
1760 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1761 goto fail_init_tbls;
1767 rte_free(hw->pkg_copy);
1774 ice_base_queue_get(struct ice_pf *pf)
1777 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1779 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1780 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1781 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1783 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1789 parse_bool(const char *key, const char *value, void *args)
1791 int *i = (int *)args;
1795 num = strtoul(value, &end, 10);
1797 if (num != 0 && num != 1) {
1798 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1799 "value must be 0 or 1",
1808 static int ice_parse_devargs(struct rte_eth_dev *dev)
1810 struct ice_adapter *ad =
1811 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1812 struct rte_devargs *devargs = dev->device->devargs;
1813 struct rte_kvargs *kvlist;
1816 if (devargs == NULL)
1819 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1820 if (kvlist == NULL) {
1821 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1825 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1826 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1827 sizeof(ad->devargs.proto_xtr));
1829 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1830 &handle_proto_xtr_arg, &ad->devargs);
1834 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1835 &parse_bool, &ad->devargs.safe_mode_support);
1838 rte_kvargs_free(kvlist);
1842 /* Forward LLDP packets to default VSI by set switch rules */
1844 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1846 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1847 struct ice_fltr_list_entry *s_list_itr = NULL;
1848 struct LIST_HEAD_TYPE list_head;
1851 INIT_LIST_HEAD(&list_head);
1853 s_list_itr = (struct ice_fltr_list_entry *)
1854 ice_malloc(hw, sizeof(*s_list_itr));
1857 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1858 s_list_itr->fltr_info.vsi_handle = vsi->idx;
1859 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1860 RTE_ETHER_TYPE_LLDP;
1861 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1862 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1863 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1864 LIST_ADD(&s_list_itr->list_entry, &list_head);
1866 ret = ice_add_eth_mac(hw, &list_head);
1868 ret = ice_remove_eth_mac(hw, &list_head);
1870 rte_free(s_list_itr);
1875 ice_dev_init(struct rte_eth_dev *dev)
1877 struct rte_pci_device *pci_dev;
1878 struct rte_intr_handle *intr_handle;
1879 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1880 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1881 struct ice_adapter *ad =
1882 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1883 struct ice_vsi *vsi;
1886 dev->dev_ops = &ice_eth_dev_ops;
1887 dev->rx_pkt_burst = ice_recv_pkts;
1888 dev->tx_pkt_burst = ice_xmit_pkts;
1889 dev->tx_pkt_prepare = ice_prep_pkts;
1891 /* for secondary processes, we don't initialise any further as primary
1892 * has already done this work.
1894 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1895 ice_set_rx_function(dev);
1896 ice_set_tx_function(dev);
1900 ice_set_default_ptype_table(dev);
1901 pci_dev = RTE_DEV_TO_PCI(dev->device);
1902 intr_handle = &pci_dev->intr_handle;
1904 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1905 pf->adapter->eth_dev = dev;
1906 pf->dev_data = dev->data;
1907 hw->back = pf->adapter;
1908 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1909 hw->vendor_id = pci_dev->id.vendor_id;
1910 hw->device_id = pci_dev->id.device_id;
1911 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1912 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1913 hw->bus.device = pci_dev->addr.devid;
1914 hw->bus.func = pci_dev->addr.function;
1916 ret = ice_parse_devargs(dev);
1918 PMD_INIT_LOG(ERR, "Failed to parse devargs");
1922 ice_init_controlq_parameter(hw);
1924 ret = ice_init_hw(hw);
1926 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1930 ret = ice_load_pkg(dev);
1932 if (ad->devargs.safe_mode_support == 0) {
1933 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
1934 "Use safe-mode-support=1 to enter Safe Mode");
1938 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1939 "Entering Safe Mode");
1940 ad->is_safe_mode = 1;
1943 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1944 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1945 hw->api_maj_ver, hw->api_min_ver);
1947 ice_pf_sw_init(dev);
1948 ret = ice_init_mac_address(dev);
1950 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1954 /* Pass the information to the rte_eth_dev_close() that it should also
1955 * release the private port resources.
1957 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1959 ret = ice_res_pool_init(&pf->msix_pool, 1,
1960 hw->func_caps.common_cap.num_msix_vectors - 1);
1962 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1963 goto err_msix_pool_init;
1966 ret = ice_pf_setup(pf);
1968 PMD_INIT_LOG(ERR, "Failed to setup PF");
1972 ret = ice_send_driver_ver(hw);
1974 PMD_INIT_LOG(ERR, "Failed to send driver version");
1980 /* Disable double vlan by default */
1981 ice_vsi_config_double_vlan(vsi, FALSE);
1983 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1984 if (ret != ICE_SUCCESS)
1985 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1986 ret = ice_init_dcb(hw, TRUE);
1987 if (ret != ICE_SUCCESS)
1988 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
1989 /* Forward LLDP packets to default VSI */
1990 ret = ice_vsi_config_sw_lldp(vsi, TRUE);
1991 if (ret != ICE_SUCCESS)
1992 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
1993 /* register callback func to eal lib */
1994 rte_intr_callback_register(intr_handle,
1995 ice_interrupt_handler, dev);
1997 ice_pf_enable_irq0(hw);
1999 /* enable uio intr after callback register */
2000 rte_intr_enable(intr_handle);
2002 /* get base queue pairs index in the device */
2003 ice_base_queue_get(pf);
2005 TAILQ_INIT(&pf->flow_list);
2010 ice_res_pool_destroy(&pf->msix_pool);
2012 rte_free(dev->data->mac_addrs);
2013 dev->data->mac_addrs = NULL;
2015 ice_sched_cleanup_all(hw);
2016 rte_free(hw->port_info);
2017 ice_shutdown_all_ctrlq(hw);
2018 rte_free(pf->proto_xtr);
2024 ice_release_vsi(struct ice_vsi *vsi)
2027 struct ice_vsi_ctx vsi_ctx;
2028 enum ice_status ret;
2033 hw = ICE_VSI_TO_HW(vsi);
2035 ice_remove_all_mac_vlan_filters(vsi);
2037 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2039 vsi_ctx.vsi_num = vsi->vsi_id;
2040 vsi_ctx.info = vsi->info;
2041 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2042 if (ret != ICE_SUCCESS) {
2043 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2053 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2055 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2056 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2057 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2058 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2059 uint16_t msix_intr, i;
2061 /* disable interrupt and also clear all the exist config */
2062 for (i = 0; i < vsi->nb_qps; i++) {
2063 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2064 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2068 if (rte_intr_allow_others(intr_handle))
2070 for (i = 0; i < vsi->nb_msix; i++) {
2071 msix_intr = vsi->msix_intr + i;
2072 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2073 GLINT_DYN_CTL_WB_ON_ITR_M);
2077 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2081 ice_dev_stop(struct rte_eth_dev *dev)
2083 struct rte_eth_dev_data *data = dev->data;
2084 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2085 struct ice_vsi *main_vsi = pf->main_vsi;
2086 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2087 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2090 /* avoid stopping again */
2091 if (pf->adapter_stopped)
2094 /* stop and clear all Rx queues */
2095 for (i = 0; i < data->nb_rx_queues; i++)
2096 ice_rx_queue_stop(dev, i);
2098 /* stop and clear all Tx queues */
2099 for (i = 0; i < data->nb_tx_queues; i++)
2100 ice_tx_queue_stop(dev, i);
2102 /* disable all queue interrupts */
2103 ice_vsi_disable_queues_intr(main_vsi);
2105 /* Clear all queues and release mbufs */
2106 ice_clear_queues(dev);
2108 ice_dev_set_link_down(dev);
2110 /* Clean datapath event and queue/vec mapping */
2111 rte_intr_efd_disable(intr_handle);
2112 if (intr_handle->intr_vec) {
2113 rte_free(intr_handle->intr_vec);
2114 intr_handle->intr_vec = NULL;
2117 pf->adapter_stopped = true;
2121 ice_dev_close(struct rte_eth_dev *dev)
2123 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2124 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2126 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2127 struct rte_flow *p_flow;
2129 /* Since stop will make link down, then the link event will be
2130 * triggered, disable the irq firstly to avoid the port_infoe etc
2131 * resources deallocation causing the interrupt service thread
2134 ice_pf_disable_irq0(hw);
2138 /* release all queue resource */
2139 ice_free_queues(dev);
2141 ice_res_pool_destroy(&pf->msix_pool);
2142 ice_release_vsi(pf->main_vsi);
2143 ice_sched_cleanup_all(hw);
2144 rte_free(hw->port_info);
2145 hw->port_info = NULL;
2146 ice_shutdown_all_ctrlq(hw);
2147 rte_free(pf->proto_xtr);
2148 pf->proto_xtr = NULL;
2150 dev->dev_ops = NULL;
2151 dev->rx_pkt_burst = NULL;
2152 dev->tx_pkt_burst = NULL;
2154 rte_free(dev->data->mac_addrs);
2155 dev->data->mac_addrs = NULL;
2157 /* disable uio intr before callback unregister */
2158 rte_intr_disable(intr_handle);
2160 /* unregister callback func from eal lib */
2161 rte_intr_callback_unregister(intr_handle,
2162 ice_interrupt_handler, dev);
2164 /* Remove all flows */
2165 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2166 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2167 ice_free_switch_filter_rule(p_flow->rule);
2173 ice_dev_uninit(struct rte_eth_dev *dev)
2181 ice_dev_configure(struct rte_eth_dev *dev)
2183 struct ice_adapter *ad =
2184 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2186 /* Initialize to TRUE. If any of Rx queues doesn't meet the
2187 * bulk allocation or vector Rx preconditions we will reset it.
2189 ad->rx_bulk_alloc_allowed = true;
2190 ad->tx_simple_allowed = true;
2195 static int ice_init_rss(struct ice_pf *pf)
2197 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2198 struct ice_vsi *vsi = pf->main_vsi;
2199 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2200 struct rte_eth_rss_conf *rss_conf;
2201 struct ice_aqc_get_set_rss_keys key;
2204 bool is_safe_mode = pf->adapter->is_safe_mode;
2206 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2207 nb_q = dev->data->nb_rx_queues;
2208 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2209 vsi->rss_lut_size = pf->hash_lut_size;
2212 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2217 vsi->rss_key = rte_zmalloc(NULL,
2218 vsi->rss_key_size, 0);
2220 vsi->rss_lut = rte_zmalloc(NULL,
2221 vsi->rss_lut_size, 0);
2223 /* configure RSS key */
2224 if (!rss_conf->rss_key) {
2225 /* Calculate the default hash key */
2226 for (i = 0; i <= vsi->rss_key_size; i++)
2227 vsi->rss_key[i] = (uint8_t)rte_rand();
2229 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2230 RTE_MIN(rss_conf->rss_key_len,
2231 vsi->rss_key_size));
2233 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2234 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2238 /* init RSS LUT table */
2239 for (i = 0; i < vsi->rss_lut_size; i++)
2240 vsi->rss_lut[i] = i % nb_q;
2242 ret = ice_aq_set_rss_lut(hw, vsi->idx,
2243 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2244 vsi->rss_lut, vsi->rss_lut_size);
2248 /* configure RSS for IPv4 with input set IPv4 src/dst */
2249 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2250 ICE_FLOW_SEG_HDR_IPV4, 0);
2252 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2254 /* configure RSS for IPv6 with input set IPv6 src/dst */
2255 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2256 ICE_FLOW_SEG_HDR_IPV6, 0);
2258 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2260 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2261 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2262 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2264 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2266 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2267 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2268 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2270 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2272 /* configure RSS for sctp6 with input set IPv6 src/dst */
2273 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2274 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2276 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2279 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2280 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2281 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2283 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2285 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2286 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2287 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2289 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2291 /* configure RSS for sctp4 with input set IP src/dst */
2292 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2293 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2295 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2302 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2303 int base_queue, int nb_queue)
2305 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2306 uint32_t val, val_tx;
2309 for (i = 0; i < nb_queue; i++) {
2311 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2312 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2313 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2314 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2316 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2317 base_queue + i, msix_vect);
2318 /* set ITR0 value */
2319 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2320 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2321 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2326 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2328 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2329 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2330 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2331 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2332 uint16_t msix_vect = vsi->msix_intr;
2333 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2334 uint16_t queue_idx = 0;
2338 /* clear Rx/Tx queue interrupt */
2339 for (i = 0; i < vsi->nb_used_qps; i++) {
2340 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2341 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2344 /* PF bind interrupt */
2345 if (rte_intr_dp_is_en(intr_handle)) {
2350 for (i = 0; i < vsi->nb_used_qps; i++) {
2352 if (!rte_intr_allow_others(intr_handle))
2353 msix_vect = ICE_MISC_VEC_ID;
2355 /* uio mapping all queue to one msix_vect */
2356 __vsi_queues_bind_intr(vsi, msix_vect,
2357 vsi->base_queue + i,
2358 vsi->nb_used_qps - i);
2360 for (; !!record && i < vsi->nb_used_qps; i++)
2361 intr_handle->intr_vec[queue_idx + i] =
2366 /* vfio 1:1 queue/msix_vect mapping */
2367 __vsi_queues_bind_intr(vsi, msix_vect,
2368 vsi->base_queue + i, 1);
2371 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2379 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2381 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2382 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2383 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2384 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2385 uint16_t msix_intr, i;
2387 if (rte_intr_allow_others(intr_handle))
2388 for (i = 0; i < vsi->nb_used_qps; i++) {
2389 msix_intr = vsi->msix_intr + i;
2390 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2391 GLINT_DYN_CTL_INTENA_M |
2392 GLINT_DYN_CTL_CLEARPBA_M |
2393 GLINT_DYN_CTL_ITR_INDX_M |
2394 GLINT_DYN_CTL_WB_ON_ITR_M);
2397 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2398 GLINT_DYN_CTL_INTENA_M |
2399 GLINT_DYN_CTL_CLEARPBA_M |
2400 GLINT_DYN_CTL_ITR_INDX_M |
2401 GLINT_DYN_CTL_WB_ON_ITR_M);
2405 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2407 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2408 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2409 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2410 struct ice_vsi *vsi = pf->main_vsi;
2411 uint32_t intr_vector = 0;
2413 rte_intr_disable(intr_handle);
2415 /* check and configure queue intr-vector mapping */
2416 if ((rte_intr_cap_multiple(intr_handle) ||
2417 !RTE_ETH_DEV_SRIOV(dev).active) &&
2418 dev->data->dev_conf.intr_conf.rxq != 0) {
2419 intr_vector = dev->data->nb_rx_queues;
2420 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2421 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2422 ICE_MAX_INTR_QUEUE_NUM);
2425 if (rte_intr_efd_enable(intr_handle, intr_vector))
2429 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2430 intr_handle->intr_vec =
2431 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2433 if (!intr_handle->intr_vec) {
2435 "Failed to allocate %d rx_queues intr_vec",
2436 dev->data->nb_rx_queues);
2441 /* Map queues with MSIX interrupt */
2442 vsi->nb_used_qps = dev->data->nb_rx_queues;
2443 ice_vsi_queues_bind_intr(vsi);
2445 /* Enable interrupts for all the queues */
2446 ice_vsi_enable_queues_intr(vsi);
2448 rte_intr_enable(intr_handle);
2454 ice_dev_start(struct rte_eth_dev *dev)
2456 struct rte_eth_dev_data *data = dev->data;
2457 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2458 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2459 struct ice_vsi *vsi = pf->main_vsi;
2460 uint16_t nb_rxq = 0;
2464 /* program Tx queues' context in hardware */
2465 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2466 ret = ice_tx_queue_start(dev, nb_txq);
2468 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2473 /* program Rx queues' context in hardware*/
2474 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2475 ret = ice_rx_queue_start(dev, nb_rxq);
2477 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2482 ret = ice_init_rss(pf);
2484 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2488 ice_set_rx_function(dev);
2489 ice_set_tx_function(dev);
2491 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2492 ETH_VLAN_EXTEND_MASK;
2493 ret = ice_vlan_offload_set(dev, mask);
2495 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2499 /* enable Rx interrput and mapping Rx queue to interrupt vector */
2500 if (ice_rxq_intr_setup(dev))
2503 /* Enable receiving broadcast packets and transmitting packets */
2504 ret = ice_set_vsi_promisc(hw, vsi->idx,
2505 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2506 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2508 if (ret != ICE_SUCCESS)
2509 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2511 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2512 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2513 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2514 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2515 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2516 ICE_AQ_LINK_EVENT_AN_COMPLETED |
2517 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2519 if (ret != ICE_SUCCESS)
2520 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2522 ice_dev_set_link_up(dev);
2524 /* Call get_link_info aq commond to enable/disable LSE */
2525 ice_link_update(dev, 0);
2527 pf->adapter_stopped = false;
2531 /* stop the started queues if failed to start all queues */
2533 for (i = 0; i < nb_rxq; i++)
2534 ice_rx_queue_stop(dev, i);
2536 for (i = 0; i < nb_txq; i++)
2537 ice_tx_queue_stop(dev, i);
2543 ice_dev_reset(struct rte_eth_dev *dev)
2547 if (dev->data->sriov.active)
2550 ret = ice_dev_uninit(dev);
2552 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2556 ret = ice_dev_init(dev);
2558 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2566 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2568 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2569 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570 struct ice_vsi *vsi = pf->main_vsi;
2571 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2572 bool is_safe_mode = pf->adapter->is_safe_mode;
2576 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2577 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2578 dev_info->max_rx_queues = vsi->nb_qps;
2579 dev_info->max_tx_queues = vsi->nb_qps;
2580 dev_info->max_mac_addrs = vsi->max_macaddrs;
2581 dev_info->max_vfs = pci_dev->max_vfs;
2582 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2583 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2585 dev_info->rx_offload_capa =
2586 DEV_RX_OFFLOAD_VLAN_STRIP |
2587 DEV_RX_OFFLOAD_JUMBO_FRAME |
2588 DEV_RX_OFFLOAD_KEEP_CRC |
2589 DEV_RX_OFFLOAD_SCATTER |
2590 DEV_RX_OFFLOAD_VLAN_FILTER;
2591 dev_info->tx_offload_capa =
2592 DEV_TX_OFFLOAD_VLAN_INSERT |
2593 DEV_TX_OFFLOAD_TCP_TSO |
2594 DEV_TX_OFFLOAD_MULTI_SEGS |
2595 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2596 dev_info->flow_type_rss_offloads = 0;
2598 if (!is_safe_mode) {
2599 dev_info->rx_offload_capa |=
2600 DEV_RX_OFFLOAD_IPV4_CKSUM |
2601 DEV_RX_OFFLOAD_UDP_CKSUM |
2602 DEV_RX_OFFLOAD_TCP_CKSUM |
2603 DEV_RX_OFFLOAD_QINQ_STRIP |
2604 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2605 DEV_RX_OFFLOAD_VLAN_EXTEND;
2606 dev_info->tx_offload_capa |=
2607 DEV_TX_OFFLOAD_QINQ_INSERT |
2608 DEV_TX_OFFLOAD_IPV4_CKSUM |
2609 DEV_TX_OFFLOAD_UDP_CKSUM |
2610 DEV_TX_OFFLOAD_TCP_CKSUM |
2611 DEV_TX_OFFLOAD_SCTP_CKSUM |
2612 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2613 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2614 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2617 dev_info->rx_queue_offload_capa = 0;
2618 dev_info->tx_queue_offload_capa = 0;
2620 dev_info->reta_size = pf->hash_lut_size;
2621 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2623 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2625 .pthresh = ICE_DEFAULT_RX_PTHRESH,
2626 .hthresh = ICE_DEFAULT_RX_HTHRESH,
2627 .wthresh = ICE_DEFAULT_RX_WTHRESH,
2629 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2634 dev_info->default_txconf = (struct rte_eth_txconf) {
2636 .pthresh = ICE_DEFAULT_TX_PTHRESH,
2637 .hthresh = ICE_DEFAULT_TX_HTHRESH,
2638 .wthresh = ICE_DEFAULT_TX_WTHRESH,
2640 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2641 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2645 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2646 .nb_max = ICE_MAX_RING_DESC,
2647 .nb_min = ICE_MIN_RING_DESC,
2648 .nb_align = ICE_ALIGN_RING_DESC,
2651 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2652 .nb_max = ICE_MAX_RING_DESC,
2653 .nb_min = ICE_MIN_RING_DESC,
2654 .nb_align = ICE_ALIGN_RING_DESC,
2657 dev_info->speed_capa = ETH_LINK_SPEED_10M |
2658 ETH_LINK_SPEED_100M |
2660 ETH_LINK_SPEED_2_5G |
2662 ETH_LINK_SPEED_10G |
2663 ETH_LINK_SPEED_20G |
2666 phy_type_low = hw->port_info->phy.phy_type_low;
2667 phy_type_high = hw->port_info->phy.phy_type_high;
2669 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2670 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2672 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2673 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2674 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2676 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2677 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2679 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2680 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2681 dev_info->default_rxportconf.nb_queues = 1;
2682 dev_info->default_txportconf.nb_queues = 1;
2683 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2684 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2690 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2691 struct rte_eth_link *link)
2693 struct rte_eth_link *dst = link;
2694 struct rte_eth_link *src = &dev->data->dev_link;
2696 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2697 *(uint64_t *)src) == 0)
2704 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2705 struct rte_eth_link *link)
2707 struct rte_eth_link *dst = &dev->data->dev_link;
2708 struct rte_eth_link *src = link;
2710 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2711 *(uint64_t *)src) == 0)
2718 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2720 #define CHECK_INTERVAL 100 /* 100ms */
2721 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2722 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2723 struct ice_link_status link_status;
2724 struct rte_eth_link link, old;
2726 unsigned int rep_cnt = MAX_REPEAT_TIME;
2727 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2729 memset(&link, 0, sizeof(link));
2730 memset(&old, 0, sizeof(old));
2731 memset(&link_status, 0, sizeof(link_status));
2732 ice_atomic_read_link_status(dev, &old);
2735 /* Get link status information from hardware */
2736 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2737 &link_status, NULL);
2738 if (status != ICE_SUCCESS) {
2739 link.link_speed = ETH_SPEED_NUM_100M;
2740 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2741 PMD_DRV_LOG(ERR, "Failed to get link info");
2745 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2746 if (!wait_to_complete || link.link_status)
2749 rte_delay_ms(CHECK_INTERVAL);
2750 } while (--rep_cnt);
2752 if (!link.link_status)
2755 /* Full-duplex operation at all supported speeds */
2756 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2758 /* Parse the link status */
2759 switch (link_status.link_speed) {
2760 case ICE_AQ_LINK_SPEED_10MB:
2761 link.link_speed = ETH_SPEED_NUM_10M;
2763 case ICE_AQ_LINK_SPEED_100MB:
2764 link.link_speed = ETH_SPEED_NUM_100M;
2766 case ICE_AQ_LINK_SPEED_1000MB:
2767 link.link_speed = ETH_SPEED_NUM_1G;
2769 case ICE_AQ_LINK_SPEED_2500MB:
2770 link.link_speed = ETH_SPEED_NUM_2_5G;
2772 case ICE_AQ_LINK_SPEED_5GB:
2773 link.link_speed = ETH_SPEED_NUM_5G;
2775 case ICE_AQ_LINK_SPEED_10GB:
2776 link.link_speed = ETH_SPEED_NUM_10G;
2778 case ICE_AQ_LINK_SPEED_20GB:
2779 link.link_speed = ETH_SPEED_NUM_20G;
2781 case ICE_AQ_LINK_SPEED_25GB:
2782 link.link_speed = ETH_SPEED_NUM_25G;
2784 case ICE_AQ_LINK_SPEED_40GB:
2785 link.link_speed = ETH_SPEED_NUM_40G;
2787 case ICE_AQ_LINK_SPEED_50GB:
2788 link.link_speed = ETH_SPEED_NUM_50G;
2790 case ICE_AQ_LINK_SPEED_100GB:
2791 link.link_speed = ETH_SPEED_NUM_100G;
2793 case ICE_AQ_LINK_SPEED_UNKNOWN:
2795 PMD_DRV_LOG(ERR, "Unknown link speed");
2796 link.link_speed = ETH_SPEED_NUM_NONE;
2800 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2801 ETH_LINK_SPEED_FIXED);
2804 ice_atomic_write_link_status(dev, &link);
2805 if (link.link_status == old.link_status)
2811 /* Force the physical link state by getting the current PHY capabilities from
2812 * hardware and setting the PHY config based on the determined capabilities. If
2813 * link changes, link event will be triggered because both the Enable Automatic
2814 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2816 static enum ice_status
2817 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2819 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2820 struct ice_aqc_get_phy_caps_data *pcaps;
2821 struct ice_port_info *pi;
2822 enum ice_status status;
2824 if (!hw || !hw->port_info)
2825 return ICE_ERR_PARAM;
2829 pcaps = (struct ice_aqc_get_phy_caps_data *)
2830 ice_malloc(hw, sizeof(*pcaps));
2832 return ICE_ERR_NO_MEMORY;
2834 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2839 /* No change in link */
2840 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2841 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2844 cfg.phy_type_low = pcaps->phy_type_low;
2845 cfg.phy_type_high = pcaps->phy_type_high;
2846 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2847 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2848 cfg.eee_cap = pcaps->eee_cap;
2849 cfg.eeer_value = pcaps->eeer_value;
2850 cfg.link_fec_opt = pcaps->link_fec_options;
2852 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2854 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2856 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2859 ice_free(hw, pcaps);
2864 ice_dev_set_link_up(struct rte_eth_dev *dev)
2866 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2868 return ice_force_phys_link_state(hw, true);
2872 ice_dev_set_link_down(struct rte_eth_dev *dev)
2874 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876 return ice_force_phys_link_state(hw, false);
2880 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2882 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2883 struct rte_eth_dev_data *dev_data = pf->dev_data;
2884 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2886 /* check if mtu is within the allowed range */
2887 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2890 /* mtu setting is forbidden if port is start */
2891 if (dev_data->dev_started) {
2893 "port %d must be stopped before configuration",
2898 if (frame_size > RTE_ETHER_MAX_LEN)
2899 dev_data->dev_conf.rxmode.offloads |=
2900 DEV_RX_OFFLOAD_JUMBO_FRAME;
2902 dev_data->dev_conf.rxmode.offloads &=
2903 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2905 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2910 static int ice_macaddr_set(struct rte_eth_dev *dev,
2911 struct rte_ether_addr *mac_addr)
2913 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2914 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2915 struct ice_vsi *vsi = pf->main_vsi;
2916 struct ice_mac_filter *f;
2920 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2921 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2925 TAILQ_FOREACH(f, &vsi->mac_list, next) {
2926 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2931 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2935 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2936 if (ret != ICE_SUCCESS) {
2937 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2940 ret = ice_add_mac_filter(vsi, mac_addr);
2941 if (ret != ICE_SUCCESS) {
2942 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2945 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2947 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2948 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2949 if (ret != ICE_SUCCESS)
2950 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2955 /* Add a MAC address, and update filters */
2957 ice_macaddr_add(struct rte_eth_dev *dev,
2958 struct rte_ether_addr *mac_addr,
2959 __rte_unused uint32_t index,
2960 __rte_unused uint32_t pool)
2962 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2963 struct ice_vsi *vsi = pf->main_vsi;
2966 ret = ice_add_mac_filter(vsi, mac_addr);
2967 if (ret != ICE_SUCCESS) {
2968 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2975 /* Remove a MAC address, and update filters */
2977 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2979 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2980 struct ice_vsi *vsi = pf->main_vsi;
2981 struct rte_eth_dev_data *data = dev->data;
2982 struct rte_ether_addr *macaddr;
2985 macaddr = &data->mac_addrs[index];
2986 ret = ice_remove_mac_filter(vsi, macaddr);
2988 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2994 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2996 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2997 struct ice_vsi *vsi = pf->main_vsi;
3000 PMD_INIT_FUNC_TRACE();
3003 ret = ice_add_vlan_filter(vsi, vlan_id);
3005 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3009 ret = ice_remove_vlan_filter(vsi, vlan_id);
3011 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3019 /* Configure vlan filter on or off */
3021 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3023 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3024 struct ice_vsi_ctx ctxt;
3025 uint8_t sec_flags, sw_flags2;
3028 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3029 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3030 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3033 vsi->info.sec_flags |= sec_flags;
3034 vsi->info.sw_flags2 |= sw_flags2;
3036 vsi->info.sec_flags &= ~sec_flags;
3037 vsi->info.sw_flags2 &= ~sw_flags2;
3039 vsi->info.sw_id = hw->port_info->sw_id;
3040 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3041 ctxt.info.valid_sections =
3042 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3043 ICE_AQ_VSI_PROP_SECURITY_VALID);
3044 ctxt.vsi_num = vsi->vsi_id;
3046 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3048 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3049 on ? "enable" : "disable");
3052 vsi->info.valid_sections |=
3053 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3054 ICE_AQ_VSI_PROP_SECURITY_VALID);
3057 /* consist with other drivers, allow untagged packet when vlan filter on */
3059 ret = ice_add_vlan_filter(vsi, 0);
3061 ret = ice_remove_vlan_filter(vsi, 0);
3067 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3069 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3070 struct ice_vsi_ctx ctxt;
3074 /* Check if it has been already on or off */
3075 if (vsi->info.valid_sections &
3076 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3078 if ((vsi->info.vlan_flags &
3079 ICE_AQ_VSI_VLAN_EMOD_M) ==
3080 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3081 return 0; /* already on */
3083 if ((vsi->info.vlan_flags &
3084 ICE_AQ_VSI_VLAN_EMOD_M) ==
3085 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3086 return 0; /* already off */
3091 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3093 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3094 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3095 vsi->info.vlan_flags |= vlan_flags;
3096 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3097 ctxt.info.valid_sections =
3098 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3099 ctxt.vsi_num = vsi->vsi_id;
3100 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3102 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3103 on ? "enable" : "disable");
3107 vsi->info.valid_sections |=
3108 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3114 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3116 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3117 struct ice_vsi *vsi = pf->main_vsi;
3118 struct rte_eth_rxmode *rxmode;
3120 rxmode = &dev->data->dev_conf.rxmode;
3121 if (mask & ETH_VLAN_FILTER_MASK) {
3122 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3123 ice_vsi_config_vlan_filter(vsi, TRUE);
3125 ice_vsi_config_vlan_filter(vsi, FALSE);
3128 if (mask & ETH_VLAN_STRIP_MASK) {
3129 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3130 ice_vsi_config_vlan_stripping(vsi, TRUE);
3132 ice_vsi_config_vlan_stripping(vsi, FALSE);
3135 if (mask & ETH_VLAN_EXTEND_MASK) {
3136 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3137 ice_vsi_config_double_vlan(vsi, TRUE);
3139 ice_vsi_config_double_vlan(vsi, FALSE);
3146 ice_vlan_tpid_set(struct rte_eth_dev *dev,
3147 enum rte_vlan_type vlan_type,
3150 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3151 uint64_t reg_r = 0, reg_w = 0;
3152 uint16_t reg_id = 0;
3154 int qinq = dev->data->dev_conf.rxmode.offloads &
3155 DEV_RX_OFFLOAD_VLAN_EXTEND;
3157 switch (vlan_type) {
3158 case ETH_VLAN_TYPE_OUTER:
3164 case ETH_VLAN_TYPE_INNER:
3169 "Unsupported vlan type in single vlan.");
3174 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
3177 reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
3178 PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
3179 "0x%08"PRIx64"", reg_id, reg_r);
3181 reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
3182 reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
3183 if (reg_r == reg_w) {
3184 PMD_DRV_LOG(DEBUG, "No need to write");
3188 ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
3189 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3190 "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3196 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3198 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3199 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3205 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3206 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
3209 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3213 uint64_t *lut_dw = (uint64_t *)lut;
3214 uint16_t i, lut_size_dw = lut_size / 4;
3216 for (i = 0; i < lut_size_dw; i++)
3217 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3224 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3233 pf = ICE_VSI_TO_PF(vsi);
3234 hw = ICE_VSI_TO_HW(vsi);
3236 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3237 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
3240 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3244 uint64_t *lut_dw = (uint64_t *)lut;
3245 uint16_t i, lut_size_dw = lut_size / 4;
3247 for (i = 0; i < lut_size_dw; i++)
3248 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3257 ice_rss_reta_update(struct rte_eth_dev *dev,
3258 struct rte_eth_rss_reta_entry64 *reta_conf,
3261 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3262 uint16_t i, lut_size = pf->hash_lut_size;
3263 uint16_t idx, shift;
3267 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3268 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3269 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3271 "The size of hash lookup table configured (%d)"
3272 "doesn't match the number hardware can "
3273 "supported (128, 512, 2048)",
3278 /* It MUST use the current LUT size to get the RSS lookup table,
3279 * otherwise if will fail with -100 error code.
3281 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
3283 PMD_DRV_LOG(ERR, "No memory can be allocated");
3286 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3290 for (i = 0; i < reta_size; i++) {
3291 idx = i / RTE_RETA_GROUP_SIZE;
3292 shift = i % RTE_RETA_GROUP_SIZE;
3293 if (reta_conf[idx].mask & (1ULL << shift))
3294 lut[i] = reta_conf[idx].reta[shift];
3296 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3297 if (ret == 0 && lut_size != reta_size) {
3299 "The size of hash lookup table is changed from (%d) to (%d)",
3300 lut_size, reta_size);
3301 pf->hash_lut_size = reta_size;
3311 ice_rss_reta_query(struct rte_eth_dev *dev,
3312 struct rte_eth_rss_reta_entry64 *reta_conf,
3315 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3316 uint16_t i, lut_size = pf->hash_lut_size;
3317 uint16_t idx, shift;
3321 if (reta_size != lut_size) {
3323 "The size of hash lookup table configured (%d)"
3324 "doesn't match the number hardware can "
3326 reta_size, lut_size);
3330 lut = rte_zmalloc(NULL, reta_size, 0);
3332 PMD_DRV_LOG(ERR, "No memory can be allocated");
3336 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3340 for (i = 0; i < reta_size; i++) {
3341 idx = i / RTE_RETA_GROUP_SIZE;
3342 shift = i % RTE_RETA_GROUP_SIZE;
3343 if (reta_conf[idx].mask & (1ULL << shift))
3344 reta_conf[idx].reta[shift] = lut[i];
3354 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3356 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3359 if (!key || key_len == 0) {
3360 PMD_DRV_LOG(DEBUG, "No key to be configured");
3362 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3364 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3368 struct ice_aqc_get_set_rss_keys *key_dw =
3369 (struct ice_aqc_get_set_rss_keys *)key;
3371 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3373 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3381 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3383 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3386 if (!key || !key_len)
3389 ret = ice_aq_get_rss_key
3391 (struct ice_aqc_get_set_rss_keys *)key);
3393 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3396 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3402 ice_rss_hash_update(struct rte_eth_dev *dev,
3403 struct rte_eth_rss_conf *rss_conf)
3405 enum ice_status status = ICE_SUCCESS;
3406 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3407 struct ice_vsi *vsi = pf->main_vsi;
3410 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3414 /* TODO: hash enable config, ice_add_rss_cfg */
3419 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3420 struct rte_eth_rss_conf *rss_conf)
3422 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3423 struct ice_vsi *vsi = pf->main_vsi;
3425 ice_get_rss_key(vsi, rss_conf->rss_key,
3426 &rss_conf->rss_key_len);
3428 /* TODO: default set to 0 as hf config is not supported now */
3429 rss_conf->rss_hf = 0;
3434 ice_promisc_enable(struct rte_eth_dev *dev)
3436 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3437 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3438 struct ice_vsi *vsi = pf->main_vsi;
3439 enum ice_status status;
3443 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3444 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3446 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3448 case ICE_ERR_ALREADY_EXISTS:
3449 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3453 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3461 ice_promisc_disable(struct rte_eth_dev *dev)
3463 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3464 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3465 struct ice_vsi *vsi = pf->main_vsi;
3466 enum ice_status status;
3470 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3471 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3473 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3474 if (status != ICE_SUCCESS) {
3475 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3483 ice_allmulti_enable(struct rte_eth_dev *dev)
3485 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3486 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3487 struct ice_vsi *vsi = pf->main_vsi;
3488 enum ice_status status;
3492 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3494 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3497 case ICE_ERR_ALREADY_EXISTS:
3498 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3502 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3510 ice_allmulti_disable(struct rte_eth_dev *dev)
3512 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3513 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3514 struct ice_vsi *vsi = pf->main_vsi;
3515 enum ice_status status;
3519 if (dev->data->promiscuous == 1)
3520 return 0; /* must remain in all_multicast mode */
3522 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3524 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3525 if (status != ICE_SUCCESS) {
3526 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3533 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3536 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3537 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3538 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3542 msix_intr = intr_handle->intr_vec[queue_id];
3544 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3545 GLINT_DYN_CTL_ITR_INDX_M;
3546 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3548 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3549 rte_intr_ack(&pci_dev->intr_handle);
3554 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3557 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3558 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3559 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3562 msix_intr = intr_handle->intr_vec[queue_id];
3564 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3570 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3572 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578 full_ver = hw->nvm.oem_ver;
3579 ver = (u8)(full_ver >> 24);
3580 build = (u16)((full_ver >> 8) & 0xffff);
3581 patch = (u8)(full_ver & 0xff);
3583 ret = snprintf(fw_version, fw_size,
3584 "%d.%d%d 0x%08x %d.%d.%d",
3585 ((hw->nvm.ver >> 12) & 0xf),
3586 ((hw->nvm.ver >> 4) & 0xff),
3587 (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3590 /* add the size of '\0' */
3592 if (fw_size < (u32)ret)
3599 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3602 struct ice_vsi_ctx ctxt;
3603 uint8_t vlan_flags = 0;
3606 if (!vsi || !info) {
3607 PMD_DRV_LOG(ERR, "invalid parameters");
3612 vsi->info.pvid = info->config.pvid;
3614 * If insert pvid is enabled, only tagged pkts are
3615 * allowed to be sent out.
3617 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3618 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3621 if (info->config.reject.tagged == 0)
3622 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3624 if (info->config.reject.untagged == 0)
3625 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3627 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3628 ICE_AQ_VSI_VLAN_MODE_M);
3629 vsi->info.vlan_flags |= vlan_flags;
3630 memset(&ctxt, 0, sizeof(ctxt));
3631 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3632 ctxt.info.valid_sections =
3633 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3634 ctxt.vsi_num = vsi->vsi_id;
3636 hw = ICE_VSI_TO_HW(vsi);
3637 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3638 if (ret != ICE_SUCCESS) {
3640 "update VSI for VLAN insert failed, err %d",
3645 vsi->info.valid_sections |=
3646 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3652 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3654 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3655 struct ice_vsi *vsi = pf->main_vsi;
3656 struct rte_eth_dev_data *data = pf->dev_data;
3657 struct ice_vsi_vlan_pvid_info info;
3660 memset(&info, 0, sizeof(info));
3663 info.config.pvid = pvid;
3665 info.config.reject.tagged =
3666 data->dev_conf.txmode.hw_vlan_reject_tagged;
3667 info.config.reject.untagged =
3668 data->dev_conf.txmode.hw_vlan_reject_untagged;
3671 ret = ice_vsi_vlan_pvid_set(vsi, &info);
3673 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3681 ice_get_eeprom_length(struct rte_eth_dev *dev)
3683 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3685 /* Convert word count to byte count */
3686 return hw->nvm.sr_words << 1;
3690 ice_get_eeprom(struct rte_eth_dev *dev,
3691 struct rte_dev_eeprom_info *eeprom)
3693 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3694 uint16_t *data = eeprom->data;
3695 uint16_t first_word, last_word, nwords;
3696 enum ice_status status = ICE_SUCCESS;
3698 first_word = eeprom->offset >> 1;
3699 last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3700 nwords = last_word - first_word + 1;
3702 if (first_word >= hw->nvm.sr_words ||
3703 last_word >= hw->nvm.sr_words) {
3704 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3708 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3710 status = ice_read_sr_buf(hw, first_word, &nwords, data);
3712 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3713 eeprom->length = sizeof(uint16_t) * nwords;
3721 ice_stat_update_32(struct ice_hw *hw,
3729 new_data = (uint64_t)ICE_READ_REG(hw, reg);
3733 if (new_data >= *offset)
3734 *stat = (uint64_t)(new_data - *offset);
3736 *stat = (uint64_t)((new_data +
3737 ((uint64_t)1 << ICE_32_BIT_WIDTH))
3742 ice_stat_update_40(struct ice_hw *hw,
3751 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3752 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3758 if (new_data >= *offset)
3759 *stat = new_data - *offset;
3761 *stat = (uint64_t)((new_data +
3762 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3765 *stat &= ICE_40_BIT_MASK;
3768 /* Get all the statistics of a VSI */
3770 ice_update_vsi_stats(struct ice_vsi *vsi)
3772 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3773 struct ice_eth_stats *nes = &vsi->eth_stats;
3774 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3775 int idx = rte_le_to_cpu_16(vsi->vsi_id);
3777 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3778 vsi->offset_loaded, &oes->rx_bytes,
3780 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3781 vsi->offset_loaded, &oes->rx_unicast,
3783 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3784 vsi->offset_loaded, &oes->rx_multicast,
3785 &nes->rx_multicast);
3786 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3787 vsi->offset_loaded, &oes->rx_broadcast,
3788 &nes->rx_broadcast);
3789 /* exclude CRC bytes */
3790 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3791 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3793 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3794 &oes->rx_discards, &nes->rx_discards);
3795 /* GLV_REPC not supported */
3796 /* GLV_RMPC not supported */
3797 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3798 &oes->rx_unknown_protocol,
3799 &nes->rx_unknown_protocol);
3800 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3801 vsi->offset_loaded, &oes->tx_bytes,
3803 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3804 vsi->offset_loaded, &oes->tx_unicast,
3806 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3807 vsi->offset_loaded, &oes->tx_multicast,
3808 &nes->tx_multicast);
3809 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3810 vsi->offset_loaded, &oes->tx_broadcast,
3811 &nes->tx_broadcast);
3812 /* GLV_TDPC not supported */
3813 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3814 &oes->tx_errors, &nes->tx_errors);
3815 vsi->offset_loaded = true;
3817 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3819 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3820 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3821 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3822 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3823 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3824 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3825 nes->rx_unknown_protocol);
3826 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3827 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3828 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3829 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3830 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3831 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3832 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3837 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3839 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3840 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3842 /* Get statistics of struct ice_eth_stats */
3843 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3844 GLPRT_GORCL(hw->port_info->lport),
3845 pf->offset_loaded, &os->eth.rx_bytes,
3847 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3848 GLPRT_UPRCL(hw->port_info->lport),
3849 pf->offset_loaded, &os->eth.rx_unicast,
3850 &ns->eth.rx_unicast);
3851 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3852 GLPRT_MPRCL(hw->port_info->lport),
3853 pf->offset_loaded, &os->eth.rx_multicast,
3854 &ns->eth.rx_multicast);
3855 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3856 GLPRT_BPRCL(hw->port_info->lport),
3857 pf->offset_loaded, &os->eth.rx_broadcast,
3858 &ns->eth.rx_broadcast);
3859 ice_stat_update_32(hw, PRTRPB_RDPC,
3860 pf->offset_loaded, &os->eth.rx_discards,
3861 &ns->eth.rx_discards);
3863 /* Workaround: CRC size should not be included in byte statistics,
3864 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3867 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3868 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3870 /* GLPRT_REPC not supported */
3871 /* GLPRT_RMPC not supported */
3872 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3874 &os->eth.rx_unknown_protocol,
3875 &ns->eth.rx_unknown_protocol);
3876 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3877 GLPRT_GOTCL(hw->port_info->lport),
3878 pf->offset_loaded, &os->eth.tx_bytes,
3880 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3881 GLPRT_UPTCL(hw->port_info->lport),
3882 pf->offset_loaded, &os->eth.tx_unicast,
3883 &ns->eth.tx_unicast);
3884 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3885 GLPRT_MPTCL(hw->port_info->lport),
3886 pf->offset_loaded, &os->eth.tx_multicast,
3887 &ns->eth.tx_multicast);
3888 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3889 GLPRT_BPTCL(hw->port_info->lport),
3890 pf->offset_loaded, &os->eth.tx_broadcast,
3891 &ns->eth.tx_broadcast);
3892 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3893 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3895 /* GLPRT_TEPC not supported */
3897 /* additional port specific stats */
3898 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3899 pf->offset_loaded, &os->tx_dropped_link_down,
3900 &ns->tx_dropped_link_down);
3901 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3902 pf->offset_loaded, &os->crc_errors,
3904 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3905 pf->offset_loaded, &os->illegal_bytes,
3906 &ns->illegal_bytes);
3907 /* GLPRT_ERRBC not supported */
3908 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3909 pf->offset_loaded, &os->mac_local_faults,
3910 &ns->mac_local_faults);
3911 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3912 pf->offset_loaded, &os->mac_remote_faults,
3913 &ns->mac_remote_faults);
3915 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3916 pf->offset_loaded, &os->rx_len_errors,
3917 &ns->rx_len_errors);
3919 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3920 pf->offset_loaded, &os->link_xon_rx,
3922 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3923 pf->offset_loaded, &os->link_xoff_rx,
3925 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3926 pf->offset_loaded, &os->link_xon_tx,
3928 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3929 pf->offset_loaded, &os->link_xoff_tx,
3931 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3932 GLPRT_PRC64L(hw->port_info->lport),
3933 pf->offset_loaded, &os->rx_size_64,
3935 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3936 GLPRT_PRC127L(hw->port_info->lport),
3937 pf->offset_loaded, &os->rx_size_127,
3939 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3940 GLPRT_PRC255L(hw->port_info->lport),
3941 pf->offset_loaded, &os->rx_size_255,
3943 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3944 GLPRT_PRC511L(hw->port_info->lport),
3945 pf->offset_loaded, &os->rx_size_511,
3947 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3948 GLPRT_PRC1023L(hw->port_info->lport),
3949 pf->offset_loaded, &os->rx_size_1023,
3951 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3952 GLPRT_PRC1522L(hw->port_info->lport),
3953 pf->offset_loaded, &os->rx_size_1522,
3955 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3956 GLPRT_PRC9522L(hw->port_info->lport),
3957 pf->offset_loaded, &os->rx_size_big,
3959 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3960 pf->offset_loaded, &os->rx_undersize,
3962 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3963 pf->offset_loaded, &os->rx_fragments,
3965 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3966 pf->offset_loaded, &os->rx_oversize,
3968 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3969 pf->offset_loaded, &os->rx_jabber,
3971 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3972 GLPRT_PTC64L(hw->port_info->lport),
3973 pf->offset_loaded, &os->tx_size_64,
3975 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3976 GLPRT_PTC127L(hw->port_info->lport),
3977 pf->offset_loaded, &os->tx_size_127,
3979 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3980 GLPRT_PTC255L(hw->port_info->lport),
3981 pf->offset_loaded, &os->tx_size_255,
3983 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3984 GLPRT_PTC511L(hw->port_info->lport),
3985 pf->offset_loaded, &os->tx_size_511,
3987 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3988 GLPRT_PTC1023L(hw->port_info->lport),
3989 pf->offset_loaded, &os->tx_size_1023,
3991 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3992 GLPRT_PTC1522L(hw->port_info->lport),
3993 pf->offset_loaded, &os->tx_size_1522,
3995 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3996 GLPRT_PTC9522L(hw->port_info->lport),
3997 pf->offset_loaded, &os->tx_size_big,
4000 /* GLPRT_MSPDC not supported */
4001 /* GLPRT_XEC not supported */
4003 pf->offset_loaded = true;
4006 ice_update_vsi_stats(pf->main_vsi);
4009 /* Get all statistics of a port */
4011 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4013 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4014 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4015 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4017 /* call read registers - updates values, now write them to struct */
4018 ice_read_stats_registers(pf, hw);
4020 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4021 pf->main_vsi->eth_stats.rx_multicast +
4022 pf->main_vsi->eth_stats.rx_broadcast -
4023 pf->main_vsi->eth_stats.rx_discards;
4024 stats->opackets = ns->eth.tx_unicast +
4025 ns->eth.tx_multicast +
4026 ns->eth.tx_broadcast;
4027 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
4028 stats->obytes = ns->eth.tx_bytes;
4029 stats->oerrors = ns->eth.tx_errors +
4030 pf->main_vsi->eth_stats.tx_errors;
4033 stats->imissed = ns->eth.rx_discards +
4034 pf->main_vsi->eth_stats.rx_discards;
4035 stats->ierrors = ns->crc_errors +
4037 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4039 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4040 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
4041 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4042 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4043 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4044 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4045 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4046 pf->main_vsi->eth_stats.rx_discards);
4047 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4048 ns->eth.rx_unknown_protocol);
4049 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
4050 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4051 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4052 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4053 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4054 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4055 pf->main_vsi->eth_stats.tx_discards);
4056 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
4058 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
4059 ns->tx_dropped_link_down);
4060 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4061 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
4063 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
4064 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
4065 ns->mac_local_faults);
4066 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
4067 ns->mac_remote_faults);
4068 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
4069 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
4070 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
4071 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
4072 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
4073 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
4074 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
4075 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
4076 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
4077 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
4078 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
4079 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
4080 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
4081 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
4082 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
4083 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
4084 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
4085 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
4086 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
4087 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
4088 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
4089 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
4090 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
4091 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4095 /* Reset the statistics */
4097 ice_stats_reset(struct rte_eth_dev *dev)
4099 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4100 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4102 /* Mark PF and VSI stats to update the offset, aka "reset" */
4103 pf->offset_loaded = false;
4105 pf->main_vsi->offset_loaded = false;
4107 /* read the stats, reading current register values into offset */
4108 ice_read_stats_registers(pf, hw);
4114 ice_xstats_calc_num(void)
4118 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4124 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4127 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4128 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4131 struct ice_hw_port_stats *hw_stats = &pf->stats;
4133 count = ice_xstats_calc_num();
4137 ice_read_stats_registers(pf, hw);
4144 /* Get stats from ice_eth_stats struct */
4145 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4146 xstats[count].value =
4147 *(uint64_t *)((char *)&hw_stats->eth +
4148 ice_stats_strings[i].offset);
4149 xstats[count].id = count;
4153 /* Get individiual stats from ice_hw_port struct */
4154 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4155 xstats[count].value =
4156 *(uint64_t *)((char *)hw_stats +
4157 ice_hw_port_strings[i].offset);
4158 xstats[count].id = count;
4165 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4166 struct rte_eth_xstat_name *xstats_names,
4167 __rte_unused unsigned int limit)
4169 unsigned int count = 0;
4173 return ice_xstats_calc_num();
4175 /* Note: limit checked in rte_eth_xstats_names() */
4177 /* Get stats from ice_eth_stats struct */
4178 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4179 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4180 sizeof(xstats_names[count].name));
4184 /* Get individiual stats from ice_hw_port struct */
4185 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4186 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4187 sizeof(xstats_names[count].name));
4195 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4196 enum rte_filter_type filter_type,
4197 enum rte_filter_op filter_op,
4205 switch (filter_type) {
4206 case RTE_ETH_FILTER_GENERIC:
4207 if (filter_op != RTE_ETH_FILTER_GET)
4209 *(const void **)arg = &ice_flow_ops;
4212 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4221 /* Add UDP tunneling port */
4223 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4224 struct rte_eth_udp_tunnel *udp_tunnel)
4227 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4229 if (udp_tunnel == NULL)
4232 switch (udp_tunnel->prot_type) {
4233 case RTE_TUNNEL_TYPE_VXLAN:
4234 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4237 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4245 /* Delete UDP tunneling port */
4247 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4248 struct rte_eth_udp_tunnel *udp_tunnel)
4251 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4253 if (udp_tunnel == NULL)
4256 switch (udp_tunnel->prot_type) {
4257 case RTE_TUNNEL_TYPE_VXLAN:
4258 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4261 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4270 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4271 struct rte_pci_device *pci_dev)
4273 return rte_eth_dev_pci_generic_probe(pci_dev,
4274 sizeof(struct ice_adapter),
4279 ice_pci_remove(struct rte_pci_device *pci_dev)
4281 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4284 static struct rte_pci_driver rte_ice_pmd = {
4285 .id_table = pci_id_ice_map,
4286 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4287 .probe = ice_pci_probe,
4288 .remove = ice_pci_remove,
4292 * Driver initialization routine.
4293 * Invoked once at EAL init time.
4294 * Register itself as the [Poll Mode] Driver of PCI devices.
4296 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4297 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4298 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4299 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4300 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4301 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>");
4303 RTE_INIT(ice_init_log)
4305 ice_logtype_init = rte_log_register("pmd.net.ice.init");
4306 if (ice_logtype_init >= 0)
4307 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4308 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4309 if (ice_logtype_driver >= 0)
4310 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4312 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4313 ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4314 if (ice_logtype_rx >= 0)
4315 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4318 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4319 ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4320 if (ice_logtype_tx >= 0)
4321 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4324 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4325 ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4326 if (ice_logtype_tx_free >= 0)
4327 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);