1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
18 #include "rte_pmd_ice.h"
19 #include "ice_ethdev.h"
21 #include "ice_generic_flow.h"
24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
26 #define ICE_FLOW_MARK_SUPPORT_ARG "flow-mark-support"
27 #define ICE_PROTO_XTR_ARG "proto_xtr"
29 static const char * const ice_valid_args[] = {
30 ICE_SAFE_MODE_SUPPORT_ARG,
31 ICE_PIPELINE_MODE_SUPPORT_ARG,
32 ICE_FLOW_MARK_SUPPORT_ARG,
37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
38 .name = "ice_dynfield_proto_xtr_metadata",
39 .size = sizeof(uint32_t),
40 .align = __alignof__(uint32_t),
44 struct proto_xtr_ol_flag {
45 const struct rte_mbuf_dynflag param;
50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
52 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
55 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
58 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
60 [PROTO_XTR_IPV6_FLOW] = {
61 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
64 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
68 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
70 /* DDP package search path */
71 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
72 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
73 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
74 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
76 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
77 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
78 #define ICE_MAX_PKG_FILENAME_SIZE 256
79 #define ICE_MAX_RES_DESC_NUM 1024
82 int ice_logtype_driver;
83 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
86 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
89 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
90 int ice_logtype_tx_free;
93 static int ice_dev_configure(struct rte_eth_dev *dev);
94 static int ice_dev_start(struct rte_eth_dev *dev);
95 static void ice_dev_stop(struct rte_eth_dev *dev);
96 static void ice_dev_close(struct rte_eth_dev *dev);
97 static int ice_dev_reset(struct rte_eth_dev *dev);
98 static int ice_dev_info_get(struct rte_eth_dev *dev,
99 struct rte_eth_dev_info *dev_info);
100 static int ice_link_update(struct rte_eth_dev *dev,
101 int wait_to_complete);
102 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
103 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
105 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
106 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
107 static int ice_rss_reta_update(struct rte_eth_dev *dev,
108 struct rte_eth_rss_reta_entry64 *reta_conf,
110 static int ice_rss_reta_query(struct rte_eth_dev *dev,
111 struct rte_eth_rss_reta_entry64 *reta_conf,
113 static int ice_rss_hash_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_conf *rss_conf);
115 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
116 struct rte_eth_rss_conf *rss_conf);
117 static int ice_promisc_enable(struct rte_eth_dev *dev);
118 static int ice_promisc_disable(struct rte_eth_dev *dev);
119 static int ice_allmulti_enable(struct rte_eth_dev *dev);
120 static int ice_allmulti_disable(struct rte_eth_dev *dev);
121 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
124 static int ice_macaddr_set(struct rte_eth_dev *dev,
125 struct rte_ether_addr *mac_addr);
126 static int ice_macaddr_add(struct rte_eth_dev *dev,
127 struct rte_ether_addr *mac_addr,
128 __rte_unused uint32_t index,
130 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
131 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
133 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
135 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
137 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
138 uint16_t pvid, int on);
139 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
140 static int ice_get_eeprom(struct rte_eth_dev *dev,
141 struct rte_dev_eeprom_info *eeprom);
142 static int ice_stats_get(struct rte_eth_dev *dev,
143 struct rte_eth_stats *stats);
144 static int ice_stats_reset(struct rte_eth_dev *dev);
145 static int ice_xstats_get(struct rte_eth_dev *dev,
146 struct rte_eth_xstat *xstats, unsigned int n);
147 static int ice_xstats_get_names(struct rte_eth_dev *dev,
148 struct rte_eth_xstat_name *xstats_names,
150 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
151 enum rte_filter_type filter_type,
152 enum rte_filter_op filter_op,
154 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
155 struct rte_eth_udp_tunnel *udp_tunnel);
156 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
157 struct rte_eth_udp_tunnel *udp_tunnel);
159 static const struct rte_pci_id pci_id_ice_map[] = {
160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
164 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
165 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
166 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_BACKPLANE) },
167 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_QSFP) },
168 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_SFP) },
169 { .vendor_id = 0, /* sentinel */ },
172 static const struct eth_dev_ops ice_eth_dev_ops = {
173 .dev_configure = ice_dev_configure,
174 .dev_start = ice_dev_start,
175 .dev_stop = ice_dev_stop,
176 .dev_close = ice_dev_close,
177 .dev_reset = ice_dev_reset,
178 .dev_set_link_up = ice_dev_set_link_up,
179 .dev_set_link_down = ice_dev_set_link_down,
180 .rx_queue_start = ice_rx_queue_start,
181 .rx_queue_stop = ice_rx_queue_stop,
182 .tx_queue_start = ice_tx_queue_start,
183 .tx_queue_stop = ice_tx_queue_stop,
184 .rx_queue_setup = ice_rx_queue_setup,
185 .rx_queue_release = ice_rx_queue_release,
186 .tx_queue_setup = ice_tx_queue_setup,
187 .tx_queue_release = ice_tx_queue_release,
188 .dev_infos_get = ice_dev_info_get,
189 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
190 .link_update = ice_link_update,
191 .mtu_set = ice_mtu_set,
192 .mac_addr_set = ice_macaddr_set,
193 .mac_addr_add = ice_macaddr_add,
194 .mac_addr_remove = ice_macaddr_remove,
195 .vlan_filter_set = ice_vlan_filter_set,
196 .vlan_offload_set = ice_vlan_offload_set,
197 .reta_update = ice_rss_reta_update,
198 .reta_query = ice_rss_reta_query,
199 .rss_hash_update = ice_rss_hash_update,
200 .rss_hash_conf_get = ice_rss_hash_conf_get,
201 .promiscuous_enable = ice_promisc_enable,
202 .promiscuous_disable = ice_promisc_disable,
203 .allmulticast_enable = ice_allmulti_enable,
204 .allmulticast_disable = ice_allmulti_disable,
205 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
206 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
207 .fw_version_get = ice_fw_version_get,
208 .vlan_pvid_set = ice_vlan_pvid_set,
209 .rxq_info_get = ice_rxq_info_get,
210 .txq_info_get = ice_txq_info_get,
211 .rx_burst_mode_get = ice_rx_burst_mode_get,
212 .tx_burst_mode_get = ice_tx_burst_mode_get,
213 .get_eeprom_length = ice_get_eeprom_length,
214 .get_eeprom = ice_get_eeprom,
215 .rx_queue_count = ice_rx_queue_count,
216 .rx_descriptor_status = ice_rx_descriptor_status,
217 .tx_descriptor_status = ice_tx_descriptor_status,
218 .stats_get = ice_stats_get,
219 .stats_reset = ice_stats_reset,
220 .xstats_get = ice_xstats_get,
221 .xstats_get_names = ice_xstats_get_names,
222 .xstats_reset = ice_stats_reset,
223 .filter_ctrl = ice_dev_filter_ctrl,
224 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
225 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
228 /* store statistics names and its offset in stats structure */
229 struct ice_xstats_name_off {
230 char name[RTE_ETH_XSTATS_NAME_SIZE];
234 static const struct ice_xstats_name_off ice_stats_strings[] = {
235 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
236 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
237 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
238 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
239 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
240 rx_unknown_protocol)},
241 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
242 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
243 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
244 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
247 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
248 sizeof(ice_stats_strings[0]))
250 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
251 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
252 tx_dropped_link_down)},
253 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
254 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
256 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
257 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
259 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
261 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
263 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
264 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
265 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
266 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
267 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
268 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
270 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
272 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
274 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
276 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
278 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
280 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
282 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
284 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
285 mac_short_pkt_dropped)},
286 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
288 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
289 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
290 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
292 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
294 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
296 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
298 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
300 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
304 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
305 sizeof(ice_hw_port_strings[0]))
308 ice_init_controlq_parameter(struct ice_hw *hw)
310 /* fields for adminq */
311 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
312 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
313 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
314 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
316 /* fields for mailboxq, DPDK used as PF host */
317 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
318 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
319 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
320 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
324 lookup_proto_xtr_type(const char *xtr_name)
328 enum proto_xtr_type type;
330 { "vlan", PROTO_XTR_VLAN },
331 { "ipv4", PROTO_XTR_IPV4 },
332 { "ipv6", PROTO_XTR_IPV6 },
333 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
334 { "tcp", PROTO_XTR_TCP },
338 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
339 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
340 return xtr_type_map[i].type;
347 * Parse elem, the elem could be single number/range or '(' ')' group
348 * 1) A single number elem, it's just a simple digit. e.g. 9
349 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
350 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
351 * Within group elem, '-' used for a range separator;
352 * ',' used for a single number.
355 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
357 const char *str = input;
362 while (isblank(*str))
365 if (!isdigit(*str) && *str != '(')
368 /* process single number or single range of number */
371 idx = strtoul(str, &end, 10);
372 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
375 while (isblank(*end))
381 /* process single <number>-<number> */
384 while (isblank(*end))
390 idx = strtoul(end, &end, 10);
391 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
395 while (isblank(*end))
402 for (idx = RTE_MIN(min, max);
403 idx <= RTE_MAX(min, max); idx++)
404 devargs->proto_xtr[idx] = xtr_type;
409 /* process set within bracket */
411 while (isblank(*str))
416 min = ICE_MAX_QUEUE_NUM;
418 /* go ahead to the first digit */
419 while (isblank(*str))
424 /* get the digit value */
426 idx = strtoul(str, &end, 10);
427 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
430 /* go ahead to separator '-',',' and ')' */
431 while (isblank(*end))
434 if (min == ICE_MAX_QUEUE_NUM)
436 else /* avoid continuous '-' */
438 } else if (*end == ',' || *end == ')') {
440 if (min == ICE_MAX_QUEUE_NUM)
443 for (idx = RTE_MIN(min, max);
444 idx <= RTE_MAX(min, max); idx++)
445 devargs->proto_xtr[idx] = xtr_type;
447 min = ICE_MAX_QUEUE_NUM;
453 } while (*end != ')' && *end != '\0');
459 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
461 const char *queue_start;
466 while (isblank(*queues))
469 if (*queues != '[') {
470 xtr_type = lookup_proto_xtr_type(queues);
474 devargs->proto_xtr_dflt = xtr_type;
481 while (isblank(*queues))
486 queue_start = queues;
488 /* go across a complete bracket */
489 if (*queue_start == '(') {
490 queues += strcspn(queues, ")");
495 /* scan the separator ':' */
496 queues += strcspn(queues, ":");
497 if (*queues++ != ':')
499 while (isblank(*queues))
502 for (idx = 0; ; idx++) {
503 if (isblank(queues[idx]) ||
504 queues[idx] == ',' ||
505 queues[idx] == ']' ||
509 if (idx > sizeof(xtr_name) - 2)
512 xtr_name[idx] = queues[idx];
514 xtr_name[idx] = '\0';
515 xtr_type = lookup_proto_xtr_type(xtr_name);
521 while (isblank(*queues) || *queues == ',' || *queues == ']')
524 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
526 } while (*queues != '\0');
532 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
535 struct ice_devargs *devargs = extra_args;
537 if (value == NULL || extra_args == NULL)
540 if (parse_queue_proto_xtr(value, devargs) < 0) {
542 "The protocol extraction parameter is wrong : '%s'",
551 ice_proto_xtr_support(struct ice_hw *hw)
553 #define FLX_REG(val, fld, idx) \
554 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
555 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
561 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
562 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
563 ICE_PROT_IPV4_OF_OR_S },
564 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
565 ICE_PROT_IPV6_OF_OR_S },
566 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
567 ICE_PROT_IPV6_OF_OR_S },
568 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
572 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
573 uint32_t rxdid = xtr_sets[i].rxdid;
576 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
577 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
579 if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
580 FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
584 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
585 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
587 if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
588 FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
597 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
600 struct pool_entry *entry;
605 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
608 "Failed to allocate memory for resource pool");
612 /* queue heap initialize */
613 pool->num_free = num;
616 LIST_INIT(&pool->alloc_list);
617 LIST_INIT(&pool->free_list);
619 /* Initialize element */
623 LIST_INSERT_HEAD(&pool->free_list, entry, next);
628 ice_res_pool_alloc(struct ice_res_pool_info *pool,
631 struct pool_entry *entry, *valid_entry;
634 PMD_INIT_LOG(ERR, "Invalid parameter");
638 if (pool->num_free < num) {
639 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
640 num, pool->num_free);
645 /* Lookup in free list and find most fit one */
646 LIST_FOREACH(entry, &pool->free_list, next) {
647 if (entry->len >= num) {
649 if (entry->len == num) {
654 valid_entry->len > entry->len)
659 /* Not find one to satisfy the request, return */
661 PMD_INIT_LOG(ERR, "No valid entry found");
665 * The entry have equal queue number as requested,
666 * remove it from alloc_list.
668 if (valid_entry->len == num) {
669 LIST_REMOVE(valid_entry, next);
672 * The entry have more numbers than requested,
673 * create a new entry for alloc_list and minus its
674 * queue base and number in free_list.
676 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
679 "Failed to allocate memory for "
683 entry->base = valid_entry->base;
685 valid_entry->base += num;
686 valid_entry->len -= num;
690 /* Insert it into alloc list, not sorted */
691 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
693 pool->num_free -= valid_entry->len;
694 pool->num_alloc += valid_entry->len;
696 return valid_entry->base + pool->base;
700 ice_res_pool_destroy(struct ice_res_pool_info *pool)
702 struct pool_entry *entry, *next_entry;
707 for (entry = LIST_FIRST(&pool->alloc_list);
708 entry && (next_entry = LIST_NEXT(entry, next), 1);
709 entry = next_entry) {
710 LIST_REMOVE(entry, next);
714 for (entry = LIST_FIRST(&pool->free_list);
715 entry && (next_entry = LIST_NEXT(entry, next), 1);
716 entry = next_entry) {
717 LIST_REMOVE(entry, next);
724 LIST_INIT(&pool->alloc_list);
725 LIST_INIT(&pool->free_list);
729 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
731 /* Set VSI LUT selection */
732 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
733 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
734 /* Set Hash scheme */
735 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
736 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
738 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
741 static enum ice_status
742 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
743 struct ice_aqc_vsi_props *info,
744 uint8_t enabled_tcmap)
746 uint16_t bsf, qp_idx;
748 /* default tc 0 now. Multi-TC supporting need to be done later.
749 * Configure TC and queue mapping parameters, for enabled TC,
750 * allocate qpnum_per_tc queues to this traffic.
752 if (enabled_tcmap != 0x01) {
753 PMD_INIT_LOG(ERR, "only TC0 is supported");
757 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
758 bsf = rte_bsf32(vsi->nb_qps);
759 /* Adjust the queue number to actual queues that can be applied */
760 vsi->nb_qps = 0x1 << bsf;
763 /* Set tc and queue mapping with VSI */
764 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
765 ICE_AQ_VSI_TC_Q_OFFSET_S) |
766 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
768 /* Associate queue number with VSI */
769 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
770 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
771 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
772 info->valid_sections |=
773 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
774 /* Set the info.ingress_table and info.egress_table
775 * for UP translate table. Now just set it to 1:1 map by default
776 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
778 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
779 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
780 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
781 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
786 ice_init_mac_address(struct rte_eth_dev *dev)
788 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
790 if (!rte_is_unicast_ether_addr
791 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
792 PMD_INIT_LOG(ERR, "Invalid MAC address");
797 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
798 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
800 dev->data->mac_addrs =
801 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
802 if (!dev->data->mac_addrs) {
804 "Failed to allocate memory to store mac address");
807 /* store it to dev data */
809 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
810 &dev->data->mac_addrs[0]);
814 /* Find out specific MAC filter */
815 static struct ice_mac_filter *
816 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
818 struct ice_mac_filter *f;
820 TAILQ_FOREACH(f, &vsi->mac_list, next) {
821 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
829 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
831 struct ice_fltr_list_entry *m_list_itr = NULL;
832 struct ice_mac_filter *f;
833 struct LIST_HEAD_TYPE list_head;
834 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
837 /* If it's added and configured, return */
838 f = ice_find_mac_filter(vsi, mac_addr);
840 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
844 INIT_LIST_HEAD(&list_head);
846 m_list_itr = (struct ice_fltr_list_entry *)
847 ice_malloc(hw, sizeof(*m_list_itr));
852 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
853 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
854 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
855 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
856 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
857 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
858 m_list_itr->fltr_info.vsi_handle = vsi->idx;
860 LIST_ADD(&m_list_itr->list_entry, &list_head);
863 ret = ice_add_mac(hw, &list_head);
864 if (ret != ICE_SUCCESS) {
865 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
869 /* Add the mac addr into mac list */
870 f = rte_zmalloc(NULL, sizeof(*f), 0);
872 PMD_DRV_LOG(ERR, "failed to allocate memory");
876 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
877 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
883 rte_free(m_list_itr);
888 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
890 struct ice_fltr_list_entry *m_list_itr = NULL;
891 struct ice_mac_filter *f;
892 struct LIST_HEAD_TYPE list_head;
893 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
896 /* Can't find it, return an error */
897 f = ice_find_mac_filter(vsi, mac_addr);
901 INIT_LIST_HEAD(&list_head);
903 m_list_itr = (struct ice_fltr_list_entry *)
904 ice_malloc(hw, sizeof(*m_list_itr));
909 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
910 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
911 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
912 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
913 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
914 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
915 m_list_itr->fltr_info.vsi_handle = vsi->idx;
917 LIST_ADD(&m_list_itr->list_entry, &list_head);
919 /* remove the mac filter */
920 ret = ice_remove_mac(hw, &list_head);
921 if (ret != ICE_SUCCESS) {
922 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
927 /* Remove the mac addr from mac list */
928 TAILQ_REMOVE(&vsi->mac_list, f, next);
934 rte_free(m_list_itr);
938 /* Find out specific VLAN filter */
939 static struct ice_vlan_filter *
940 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
942 struct ice_vlan_filter *f;
944 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
945 if (vlan_id == f->vlan_info.vlan_id)
953 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
955 struct ice_fltr_list_entry *v_list_itr = NULL;
956 struct ice_vlan_filter *f;
957 struct LIST_HEAD_TYPE list_head;
961 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
964 hw = ICE_VSI_TO_HW(vsi);
966 /* If it's added and configured, return. */
967 f = ice_find_vlan_filter(vsi, vlan_id);
969 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
973 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
976 INIT_LIST_HEAD(&list_head);
978 v_list_itr = (struct ice_fltr_list_entry *)
979 ice_malloc(hw, sizeof(*v_list_itr));
984 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
985 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
986 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
987 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
988 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
989 v_list_itr->fltr_info.vsi_handle = vsi->idx;
991 LIST_ADD(&v_list_itr->list_entry, &list_head);
994 ret = ice_add_vlan(hw, &list_head);
995 if (ret != ICE_SUCCESS) {
996 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1001 /* Add vlan into vlan list */
1002 f = rte_zmalloc(NULL, sizeof(*f), 0);
1004 PMD_DRV_LOG(ERR, "failed to allocate memory");
1008 f->vlan_info.vlan_id = vlan_id;
1009 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1015 rte_free(v_list_itr);
1020 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1022 struct ice_fltr_list_entry *v_list_itr = NULL;
1023 struct ice_vlan_filter *f;
1024 struct LIST_HEAD_TYPE list_head;
1029 * Vlan 0 is the generic filter for untagged packets
1030 * and can't be removed.
1032 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1035 hw = ICE_VSI_TO_HW(vsi);
1037 /* Can't find it, return an error */
1038 f = ice_find_vlan_filter(vsi, vlan_id);
1042 INIT_LIST_HEAD(&list_head);
1044 v_list_itr = (struct ice_fltr_list_entry *)
1045 ice_malloc(hw, sizeof(*v_list_itr));
1051 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1052 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1053 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1054 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1055 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1056 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1058 LIST_ADD(&v_list_itr->list_entry, &list_head);
1060 /* remove the vlan filter */
1061 ret = ice_remove_vlan(hw, &list_head);
1062 if (ret != ICE_SUCCESS) {
1063 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1068 /* Remove the vlan id from vlan list */
1069 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1075 rte_free(v_list_itr);
1080 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1082 struct ice_mac_filter *m_f;
1083 struct ice_vlan_filter *v_f;
1086 if (!vsi || !vsi->mac_num)
1089 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1090 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1091 if (ret != ICE_SUCCESS) {
1097 if (vsi->vlan_num == 0)
1100 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1101 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1102 if (ret != ICE_SUCCESS) {
1113 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1115 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1116 struct ice_vsi_ctx ctxt;
1120 /* Check if it has been already on or off */
1121 if (vsi->info.valid_sections &
1122 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1124 if ((vsi->info.outer_tag_flags &
1125 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1126 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1127 return 0; /* already on */
1129 if (!(vsi->info.outer_tag_flags &
1130 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1131 return 0; /* already off */
1136 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1139 /* clear global insertion and use per packet insertion */
1140 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1141 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1142 vsi->info.outer_tag_flags |= qinq_flags;
1143 /* use default vlan type 0x8100 */
1144 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1145 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1146 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1147 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1148 ctxt.info.valid_sections =
1149 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1150 ctxt.vsi_num = vsi->vsi_id;
1151 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1154 "Update VSI failed to %s qinq stripping",
1155 on ? "enable" : "disable");
1159 vsi->info.valid_sections |=
1160 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1166 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1168 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1169 struct ice_vsi_ctx ctxt;
1173 /* Check if it has been already on or off */
1174 if (vsi->info.valid_sections &
1175 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1177 if ((vsi->info.outer_tag_flags &
1178 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1179 ICE_AQ_VSI_OUTER_TAG_COPY)
1180 return 0; /* already on */
1182 if ((vsi->info.outer_tag_flags &
1183 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1184 ICE_AQ_VSI_OUTER_TAG_NOTHING)
1185 return 0; /* already off */
1190 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1192 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1193 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1194 vsi->info.outer_tag_flags |= qinq_flags;
1195 /* use default vlan type 0x8100 */
1196 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1197 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1198 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1199 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1200 ctxt.info.valid_sections =
1201 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1202 ctxt.vsi_num = vsi->vsi_id;
1203 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1206 "Update VSI failed to %s qinq stripping",
1207 on ? "enable" : "disable");
1211 vsi->info.valid_sections |=
1212 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1218 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1222 ret = ice_vsi_config_qinq_stripping(vsi, on);
1224 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1226 ret = ice_vsi_config_qinq_insertion(vsi, on);
1228 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1235 ice_pf_enable_irq0(struct ice_hw *hw)
1237 /* reset the registers */
1238 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1239 ICE_READ_REG(hw, PFINT_OICR);
1242 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1243 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1244 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1246 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1247 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1248 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1249 PFINT_OICR_CTL_ITR_INDX_M) |
1250 PFINT_OICR_CTL_CAUSE_ENA_M);
1252 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1253 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1254 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1255 PFINT_FW_CTL_ITR_INDX_M) |
1256 PFINT_FW_CTL_CAUSE_ENA_M);
1258 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1261 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1262 GLINT_DYN_CTL_INTENA_M |
1263 GLINT_DYN_CTL_CLEARPBA_M |
1264 GLINT_DYN_CTL_ITR_INDX_M);
1271 ice_pf_disable_irq0(struct ice_hw *hw)
1273 /* Disable all interrupt types */
1274 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1280 ice_handle_aq_msg(struct rte_eth_dev *dev)
1282 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1283 struct ice_ctl_q_info *cq = &hw->adminq;
1284 struct ice_rq_event_info event;
1285 uint16_t pending, opcode;
1288 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1289 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1290 if (!event.msg_buf) {
1291 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1297 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1299 if (ret != ICE_SUCCESS) {
1301 "Failed to read msg from AdminQ, "
1303 hw->adminq.sq_last_status);
1306 opcode = rte_le_to_cpu_16(event.desc.opcode);
1309 case ice_aqc_opc_get_link_status:
1310 ret = ice_link_update(dev, 0);
1312 _rte_eth_dev_callback_process
1313 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1316 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1321 rte_free(event.msg_buf);
1326 * Interrupt handler triggered by NIC for handling
1327 * specific interrupt.
1330 * Pointer to interrupt handle.
1332 * The address of parameter (struct rte_eth_dev *) regsitered before.
1338 ice_interrupt_handler(void *param)
1340 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1341 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349 uint32_t int_fw_ctl;
1352 /* Disable interrupt */
1353 ice_pf_disable_irq0(hw);
1355 /* read out interrupt causes */
1356 oicr = ICE_READ_REG(hw, PFINT_OICR);
1358 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1361 /* No interrupt event indicated */
1362 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1363 PMD_DRV_LOG(INFO, "No interrupt event");
1368 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1369 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1370 ice_handle_aq_msg(dev);
1373 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1374 PMD_DRV_LOG(INFO, "OICR: link state change event");
1375 ret = ice_link_update(dev, 0);
1377 _rte_eth_dev_callback_process
1378 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1382 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1383 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1384 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1385 if (reg & GL_MDET_TX_PQM_VALID_M) {
1386 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1387 GL_MDET_TX_PQM_PF_NUM_S;
1388 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1389 GL_MDET_TX_PQM_MAL_TYPE_S;
1390 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1391 GL_MDET_TX_PQM_QNUM_S;
1393 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1394 "%d by PQM on TX queue %d PF# %d",
1395 event, queue, pf_num);
1398 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1399 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1400 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1401 GL_MDET_TX_TCLAN_PF_NUM_S;
1402 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1403 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1404 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1405 GL_MDET_TX_TCLAN_QNUM_S;
1407 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1408 "%d by TCLAN on TX queue %d PF# %d",
1409 event, queue, pf_num);
1413 /* Enable interrupt */
1414 ice_pf_enable_irq0(hw);
1415 rte_intr_ack(dev->intr_handle);
1419 ice_init_proto_xtr(struct rte_eth_dev *dev)
1421 struct ice_adapter *ad =
1422 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1423 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1424 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1425 const struct proto_xtr_ol_flag *ol_flag;
1426 bool proto_xtr_enable = false;
1430 if (!ice_proto_xtr_support(hw)) {
1431 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1435 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1436 if (unlikely(pf->proto_xtr == NULL)) {
1437 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1441 for (i = 0; i < pf->lan_nb_qps; i++) {
1442 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1443 ad->devargs.proto_xtr[i] :
1444 ad->devargs.proto_xtr_dflt;
1446 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1447 uint8_t type = pf->proto_xtr[i];
1449 ice_proto_xtr_ol_flag_params[type].required = true;
1450 proto_xtr_enable = true;
1454 if (likely(!proto_xtr_enable))
1457 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1458 if (unlikely(offset == -1)) {
1460 "Protocol extraction metadata is disabled in mbuf with error %d",
1466 "Protocol extraction metadata offset in mbuf is : %d",
1468 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1470 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1471 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1473 if (!ol_flag->required)
1476 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1477 if (unlikely(offset == -1)) {
1479 "Protocol extraction offload '%s' failed to register with error %d",
1480 ol_flag->param.name, -rte_errno);
1482 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1487 "Protocol extraction offload '%s' offset in mbuf is : %d",
1488 ol_flag->param.name, offset);
1489 *ol_flag->ol_flag = 1ULL << offset;
1493 /* Initialize SW parameters of PF */
1495 ice_pf_sw_init(struct rte_eth_dev *dev)
1497 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1498 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1501 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1502 hw->func_caps.common_cap.num_rxq);
1504 pf->lan_nb_qps = pf->lan_nb_qp_max;
1506 ice_init_proto_xtr(dev);
1508 if (hw->func_caps.fd_fltr_guar > 0 ||
1509 hw->func_caps.fd_fltr_best_effort > 0) {
1510 pf->flags |= ICE_FLAG_FDIR;
1511 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1512 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1514 pf->fdir_nb_qps = 0;
1516 pf->fdir_qp_offset = 0;
1522 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1524 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1525 struct ice_vsi *vsi = NULL;
1526 struct ice_vsi_ctx vsi_ctx;
1528 struct rte_ether_addr broadcast = {
1529 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1530 struct rte_ether_addr mac_addr;
1531 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1532 uint8_t tc_bitmap = 0x1;
1535 /* hw->num_lports = 1 in NIC mode */
1536 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1540 vsi->idx = pf->next_vsi_idx;
1543 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1544 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1545 vsi->vlan_anti_spoof_on = 0;
1546 vsi->vlan_filter_on = 1;
1547 TAILQ_INIT(&vsi->mac_list);
1548 TAILQ_INIT(&vsi->vlan_list);
1550 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1551 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1552 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1553 hw->func_caps.common_cap.rss_table_size;
1554 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1556 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1559 vsi->nb_qps = pf->lan_nb_qps;
1560 vsi->base_queue = 1;
1561 ice_vsi_config_default_rss(&vsi_ctx.info);
1562 vsi_ctx.alloc_from_pool = true;
1563 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1564 /* switch_id is queried by get_switch_config aq, which is done
1567 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1568 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1569 /* Allow all untagged or tagged packets */
1570 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1571 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1572 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1573 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1576 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1577 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1578 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1579 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1580 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1581 vsi_ctx.info.max_fd_fltr_dedicated =
1582 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1583 vsi_ctx.info.max_fd_fltr_shared =
1584 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1586 /* Enable VLAN/UP trip */
1587 ret = ice_vsi_config_tc_queue_mapping(vsi,
1592 "tc queue mapping with vsi failed, "
1600 vsi->nb_qps = pf->fdir_nb_qps;
1601 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1602 vsi_ctx.alloc_from_pool = true;
1603 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1605 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1606 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1607 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1608 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1609 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1610 ret = ice_vsi_config_tc_queue_mapping(vsi,
1615 "tc queue mapping with vsi failed, "
1622 /* for other types of VSI */
1623 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1627 /* VF has MSIX interrupt in VF range, don't allocate here */
1628 if (type == ICE_VSI_PF) {
1629 ret = ice_res_pool_alloc(&pf->msix_pool,
1630 RTE_MIN(vsi->nb_qps,
1631 RTE_MAX_RXTX_INTR_VEC_ID));
1633 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1636 vsi->msix_intr = ret;
1637 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1638 } else if (type == ICE_VSI_CTRL) {
1639 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1641 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1644 vsi->msix_intr = ret;
1650 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1651 if (ret != ICE_SUCCESS) {
1652 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1655 /* store vsi information is SW structure */
1656 vsi->vsi_id = vsi_ctx.vsi_num;
1657 vsi->info = vsi_ctx.info;
1658 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1659 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1661 if (type == ICE_VSI_PF) {
1662 /* MAC configuration */
1663 rte_memcpy(pf->dev_addr.addr_bytes,
1664 hw->port_info->mac.perm_addr,
1667 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1668 ret = ice_add_mac_filter(vsi, &mac_addr);
1669 if (ret != ICE_SUCCESS)
1670 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1672 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1673 ret = ice_add_mac_filter(vsi, &mac_addr);
1674 if (ret != ICE_SUCCESS)
1675 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1678 /* At the beginning, only TC0. */
1679 /* What we need here is the maximam number of the TX queues.
1680 * Currently vsi->nb_qps means it.
1681 * Correct it if any change.
1683 max_txqs[0] = vsi->nb_qps;
1684 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1685 tc_bitmap, max_txqs);
1686 if (ret != ICE_SUCCESS)
1687 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1697 ice_send_driver_ver(struct ice_hw *hw)
1699 struct ice_driver_ver dv;
1701 /* we don't have driver version use 0 for dummy */
1705 dv.subbuild_ver = 0;
1706 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1708 return ice_aq_send_driver_ver(hw, &dv, NULL);
1712 ice_pf_setup(struct ice_pf *pf)
1714 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1715 struct ice_vsi *vsi;
1718 /* Clear all stats counters */
1719 pf->offset_loaded = FALSE;
1720 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1721 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1722 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1723 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1725 /* force guaranteed filter pool for PF */
1726 ice_alloc_fd_guar_item(hw, &unused,
1727 hw->func_caps.fd_fltr_guar);
1728 /* force shared filter pool for PF */
1729 ice_alloc_fd_shrd_item(hw, &unused,
1730 hw->func_caps.fd_fltr_best_effort);
1732 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1734 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1743 /* PCIe configuration space setting */
1744 #define PCI_CFG_SPACE_SIZE 256
1745 #define PCI_CFG_SPACE_EXP_SIZE 4096
1746 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
1747 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
1748 #define PCI_EXT_CAP_ID_DSN 0x03
1751 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1755 int pos = PCI_CFG_SPACE_SIZE;
1757 /* minimum 8 bytes per capability */
1758 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1760 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1761 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1766 * If we have no capabilities, this is indicated by cap ID,
1767 * cap version and next pointer all being 0.
1773 if (PCI_EXT_CAP_ID(header) == cap)
1776 pos = PCI_EXT_CAP_NEXT(header);
1778 if (pos < PCI_CFG_SPACE_SIZE)
1781 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1782 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1791 * Extract device serial number from PCIe Configuration Space and
1792 * determine the pkg file path according to the DSN.
1795 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1798 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1799 uint32_t dsn_low, dsn_high;
1800 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1802 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1805 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1806 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1807 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1808 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1810 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1814 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1815 ICE_MAX_PKG_FILENAME_SIZE);
1816 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1819 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1820 ICE_MAX_PKG_FILENAME_SIZE);
1821 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1825 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1826 if (!access(pkg_file, 0))
1828 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1832 static enum ice_pkg_type
1833 ice_load_pkg_type(struct ice_hw *hw)
1835 enum ice_pkg_type package_type;
1837 /* store the activated package type (OS default or Comms) */
1838 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1840 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1841 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1843 package_type = ICE_PKG_TYPE_COMMS;
1845 package_type = ICE_PKG_TYPE_UNKNOWN;
1847 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1848 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1849 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1850 hw->active_pkg_name);
1852 return package_type;
1855 static int ice_load_pkg(struct rte_eth_dev *dev)
1857 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1864 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1865 struct ice_adapter *ad =
1866 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1868 ice_pkg_file_search_path(pci_dev, pkg_file);
1870 file = fopen(pkg_file, "rb");
1872 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1876 err = stat(pkg_file, &fstat);
1878 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1883 buf_len = fstat.st_size;
1884 buf = rte_malloc(NULL, buf_len, 0);
1887 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1893 err = fread(buf, buf_len, 1, file);
1895 PMD_INIT_LOG(ERR, "failed to read package data\n");
1903 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1905 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1909 /* store the loaded pkg type info */
1910 ad->active_pkg_type = ice_load_pkg_type(hw);
1912 err = ice_init_hw_tbls(hw);
1914 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1915 goto fail_init_tbls;
1921 rte_free(hw->pkg_copy);
1928 ice_base_queue_get(struct ice_pf *pf)
1931 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1933 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1934 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1935 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1937 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1943 parse_bool(const char *key, const char *value, void *args)
1945 int *i = (int *)args;
1949 num = strtoul(value, &end, 10);
1951 if (num != 0 && num != 1) {
1952 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1953 "value must be 0 or 1",
1962 static int ice_parse_devargs(struct rte_eth_dev *dev)
1964 struct ice_adapter *ad =
1965 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1966 struct rte_devargs *devargs = dev->device->devargs;
1967 struct rte_kvargs *kvlist;
1970 if (devargs == NULL)
1973 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1974 if (kvlist == NULL) {
1975 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1979 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1980 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1981 sizeof(ad->devargs.proto_xtr));
1983 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1984 &handle_proto_xtr_arg, &ad->devargs);
1988 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1989 &parse_bool, &ad->devargs.safe_mode_support);
1993 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1994 &parse_bool, &ad->devargs.pipe_mode_support);
1998 ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
1999 &parse_bool, &ad->devargs.flow_mark_support);
2004 rte_kvargs_free(kvlist);
2008 /* Forward LLDP packets to default VSI by set switch rules */
2010 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
2012 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2013 struct ice_fltr_list_entry *s_list_itr = NULL;
2014 struct LIST_HEAD_TYPE list_head;
2017 INIT_LIST_HEAD(&list_head);
2019 s_list_itr = (struct ice_fltr_list_entry *)
2020 ice_malloc(hw, sizeof(*s_list_itr));
2023 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2024 s_list_itr->fltr_info.vsi_handle = vsi->idx;
2025 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2026 RTE_ETHER_TYPE_LLDP;
2027 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2028 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2029 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2030 LIST_ADD(&s_list_itr->list_entry, &list_head);
2032 ret = ice_add_eth_mac(hw, &list_head);
2034 ret = ice_remove_eth_mac(hw, &list_head);
2036 rte_free(s_list_itr);
2040 static enum ice_status
2041 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2042 uint16_t num, uint16_t desc_id,
2043 uint16_t *prof_buf, uint16_t *num_prof)
2045 struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2048 bool res_shared = 1;
2049 struct ice_aq_desc aq_desc;
2050 struct ice_sq_cd *cd = NULL;
2051 struct ice_aqc_get_allocd_res_desc *cmd =
2052 &aq_desc.params.get_res_desc;
2054 buf_len = sizeof(resp_buf->elem) * num;
2055 resp_buf = ice_malloc(hw, buf_len);
2059 ice_fill_dflt_direct_cmd_desc(&aq_desc,
2060 ice_aqc_opc_get_allocd_res_desc);
2062 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2063 ICE_AQC_RES_TYPE_M) | (res_shared ?
2064 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2065 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2067 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2069 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2073 ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2074 (*num_prof), ICE_NONDMA_TO_NONDMA);
2081 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2085 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2086 uint16_t first_desc = 1;
2087 uint16_t num_prof = 0;
2089 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2090 first_desc, prof_buf, &num_prof);
2092 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2096 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2097 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2099 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2107 ice_reset_fxp_resource(struct ice_hw *hw)
2111 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2113 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2117 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2119 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2127 ice_dev_init(struct rte_eth_dev *dev)
2129 struct rte_pci_device *pci_dev;
2130 struct rte_intr_handle *intr_handle;
2131 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2133 struct ice_adapter *ad =
2134 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2135 struct ice_vsi *vsi;
2138 dev->dev_ops = &ice_eth_dev_ops;
2139 dev->rx_pkt_burst = ice_recv_pkts;
2140 dev->tx_pkt_burst = ice_xmit_pkts;
2141 dev->tx_pkt_prepare = ice_prep_pkts;
2143 /* for secondary processes, we don't initialise any further as primary
2144 * has already done this work.
2146 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2147 ice_set_rx_function(dev);
2148 ice_set_tx_function(dev);
2152 ice_set_default_ptype_table(dev);
2153 pci_dev = RTE_DEV_TO_PCI(dev->device);
2154 intr_handle = &pci_dev->intr_handle;
2156 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2157 pf->adapter->eth_dev = dev;
2158 pf->dev_data = dev->data;
2159 hw->back = pf->adapter;
2160 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2161 hw->vendor_id = pci_dev->id.vendor_id;
2162 hw->device_id = pci_dev->id.device_id;
2163 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2164 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2165 hw->bus.device = pci_dev->addr.devid;
2166 hw->bus.func = pci_dev->addr.function;
2168 ret = ice_parse_devargs(dev);
2170 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2174 ice_init_controlq_parameter(hw);
2176 ret = ice_init_hw(hw);
2178 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2182 ret = ice_load_pkg(dev);
2184 if (ad->devargs.safe_mode_support == 0) {
2185 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2186 "Use safe-mode-support=1 to enter Safe Mode");
2190 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2191 "Entering Safe Mode");
2192 ad->is_safe_mode = 1;
2195 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2196 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2197 hw->api_maj_ver, hw->api_min_ver);
2199 ice_pf_sw_init(dev);
2200 ret = ice_init_mac_address(dev);
2202 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2206 /* Pass the information to the rte_eth_dev_close() that it should also
2207 * release the private port resources.
2209 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2211 ret = ice_res_pool_init(&pf->msix_pool, 1,
2212 hw->func_caps.common_cap.num_msix_vectors - 1);
2214 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2215 goto err_msix_pool_init;
2218 ret = ice_pf_setup(pf);
2220 PMD_INIT_LOG(ERR, "Failed to setup PF");
2224 ret = ice_send_driver_ver(hw);
2226 PMD_INIT_LOG(ERR, "Failed to send driver version");
2232 /* Disable double vlan by default */
2233 ice_vsi_config_double_vlan(vsi, FALSE);
2235 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
2236 if (ret != ICE_SUCCESS)
2237 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2238 ret = ice_init_dcb(hw, TRUE);
2239 if (ret != ICE_SUCCESS)
2240 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2241 /* Forward LLDP packets to default VSI */
2242 ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2243 if (ret != ICE_SUCCESS)
2244 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2245 /* register callback func to eal lib */
2246 rte_intr_callback_register(intr_handle,
2247 ice_interrupt_handler, dev);
2249 ice_pf_enable_irq0(hw);
2251 /* enable uio intr after callback register */
2252 rte_intr_enable(intr_handle);
2254 /* get base queue pairs index in the device */
2255 ice_base_queue_get(pf);
2257 if (!ad->is_safe_mode) {
2258 ret = ice_flow_init(ad);
2260 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2265 ret = ice_reset_fxp_resource(hw);
2267 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2274 ice_res_pool_destroy(&pf->msix_pool);
2276 rte_free(dev->data->mac_addrs);
2277 dev->data->mac_addrs = NULL;
2279 ice_sched_cleanup_all(hw);
2280 rte_free(hw->port_info);
2281 ice_shutdown_all_ctrlq(hw);
2282 rte_free(pf->proto_xtr);
2288 ice_release_vsi(struct ice_vsi *vsi)
2291 struct ice_vsi_ctx vsi_ctx;
2292 enum ice_status ret;
2297 hw = ICE_VSI_TO_HW(vsi);
2299 ice_remove_all_mac_vlan_filters(vsi);
2301 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2303 vsi_ctx.vsi_num = vsi->vsi_id;
2304 vsi_ctx.info = vsi->info;
2305 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2306 if (ret != ICE_SUCCESS) {
2307 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2317 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2319 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2320 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2321 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2322 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2323 uint16_t msix_intr, i;
2325 /* disable interrupt and also clear all the exist config */
2326 for (i = 0; i < vsi->nb_qps; i++) {
2327 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2328 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2332 if (rte_intr_allow_others(intr_handle))
2334 for (i = 0; i < vsi->nb_msix; i++) {
2335 msix_intr = vsi->msix_intr + i;
2336 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2337 GLINT_DYN_CTL_WB_ON_ITR_M);
2341 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2345 ice_dev_stop(struct rte_eth_dev *dev)
2347 struct rte_eth_dev_data *data = dev->data;
2348 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2349 struct ice_vsi *main_vsi = pf->main_vsi;
2350 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2351 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2354 /* avoid stopping again */
2355 if (pf->adapter_stopped)
2358 /* stop and clear all Rx queues */
2359 for (i = 0; i < data->nb_rx_queues; i++)
2360 ice_rx_queue_stop(dev, i);
2362 /* stop and clear all Tx queues */
2363 for (i = 0; i < data->nb_tx_queues; i++)
2364 ice_tx_queue_stop(dev, i);
2366 /* disable all queue interrupts */
2367 ice_vsi_disable_queues_intr(main_vsi);
2369 /* Clear all queues and release mbufs */
2370 ice_clear_queues(dev);
2372 if (pf->init_link_up)
2373 ice_dev_set_link_up(dev);
2375 ice_dev_set_link_down(dev);
2377 /* Clean datapath event and queue/vec mapping */
2378 rte_intr_efd_disable(intr_handle);
2379 if (intr_handle->intr_vec) {
2380 rte_free(intr_handle->intr_vec);
2381 intr_handle->intr_vec = NULL;
2384 pf->adapter_stopped = true;
2388 ice_dev_close(struct rte_eth_dev *dev)
2390 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2391 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2393 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2394 struct ice_adapter *ad =
2395 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2397 /* Since stop will make link down, then the link event will be
2398 * triggered, disable the irq firstly to avoid the port_infoe etc
2399 * resources deallocation causing the interrupt service thread
2402 ice_pf_disable_irq0(hw);
2406 if (!ad->is_safe_mode)
2407 ice_flow_uninit(ad);
2409 /* release all queue resource */
2410 ice_free_queues(dev);
2412 ice_res_pool_destroy(&pf->msix_pool);
2413 ice_release_vsi(pf->main_vsi);
2414 ice_sched_cleanup_all(hw);
2415 ice_free_hw_tbls(hw);
2416 rte_free(hw->port_info);
2417 hw->port_info = NULL;
2418 ice_shutdown_all_ctrlq(hw);
2419 rte_free(pf->proto_xtr);
2420 pf->proto_xtr = NULL;
2422 dev->dev_ops = NULL;
2423 dev->rx_pkt_burst = NULL;
2424 dev->tx_pkt_burst = NULL;
2426 rte_free(dev->data->mac_addrs);
2427 dev->data->mac_addrs = NULL;
2429 /* disable uio intr before callback unregister */
2430 rte_intr_disable(intr_handle);
2432 /* unregister callback func from eal lib */
2433 rte_intr_callback_unregister(intr_handle,
2434 ice_interrupt_handler, dev);
2438 ice_dev_uninit(struct rte_eth_dev *dev)
2446 ice_dev_configure(struct rte_eth_dev *dev)
2448 struct ice_adapter *ad =
2449 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2451 /* Initialize to TRUE. If any of Rx queues doesn't meet the
2452 * bulk allocation or vector Rx preconditions we will reset it.
2454 ad->rx_bulk_alloc_allowed = true;
2455 ad->tx_simple_allowed = true;
2457 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2458 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2463 static int ice_init_rss(struct ice_pf *pf)
2465 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2466 struct ice_vsi *vsi = pf->main_vsi;
2467 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2468 struct rte_eth_rss_conf *rss_conf;
2469 struct ice_aqc_get_set_rss_keys key;
2472 bool is_safe_mode = pf->adapter->is_safe_mode;
2475 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2476 nb_q = dev->data->nb_rx_queues;
2477 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2478 vsi->rss_lut_size = pf->hash_lut_size;
2481 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2486 vsi->rss_key = rte_zmalloc(NULL,
2487 vsi->rss_key_size, 0);
2489 vsi->rss_lut = rte_zmalloc(NULL,
2490 vsi->rss_lut_size, 0);
2492 /* configure RSS key */
2493 if (!rss_conf->rss_key) {
2494 /* Calculate the default hash key */
2495 for (i = 0; i <= vsi->rss_key_size; i++)
2496 vsi->rss_key[i] = (uint8_t)rte_rand();
2498 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2499 RTE_MIN(rss_conf->rss_key_len,
2500 vsi->rss_key_size));
2502 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2503 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2507 /* init RSS LUT table */
2508 for (i = 0; i < vsi->rss_lut_size; i++)
2509 vsi->rss_lut[i] = i % nb_q;
2511 ret = ice_aq_set_rss_lut(hw, vsi->idx,
2512 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2513 vsi->rss_lut, vsi->rss_lut_size);
2517 /* Enable registers for symmetric_toeplitz function. */
2518 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2519 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2520 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2521 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2523 /* configure RSS for IPv4 with input set IPv4 src/dst */
2524 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2525 ICE_FLOW_SEG_HDR_IPV4, 0);
2527 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2529 /* configure RSS for IPv6 with input set IPv6 src/dst */
2530 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2531 ICE_FLOW_SEG_HDR_IPV6, 0);
2533 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2535 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2536 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2537 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2539 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2541 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2542 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2543 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2545 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2547 /* configure RSS for sctp6 with input set IPv6 src/dst */
2548 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2549 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2551 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2554 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2555 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2556 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2558 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2560 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2561 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2562 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2564 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2566 /* configure RSS for sctp4 with input set IP src/dst */
2567 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2568 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2570 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2573 /* configure RSS for gtpu with input set TEID */
2574 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2575 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2577 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2581 * configure RSS for pppoe/pppod with input set
2582 * Source MAC and Session ID
2584 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2585 ICE_FLOW_SEG_HDR_PPPOE, 0);
2587 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2594 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2595 int base_queue, int nb_queue)
2597 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2598 uint32_t val, val_tx;
2601 for (i = 0; i < nb_queue; i++) {
2603 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2604 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2605 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2606 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2608 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2609 base_queue + i, msix_vect);
2610 /* set ITR0 value */
2611 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2612 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2613 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2618 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2620 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2621 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2622 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2623 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2624 uint16_t msix_vect = vsi->msix_intr;
2625 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2626 uint16_t queue_idx = 0;
2630 /* clear Rx/Tx queue interrupt */
2631 for (i = 0; i < vsi->nb_used_qps; i++) {
2632 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2633 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2636 /* PF bind interrupt */
2637 if (rte_intr_dp_is_en(intr_handle)) {
2642 for (i = 0; i < vsi->nb_used_qps; i++) {
2644 if (!rte_intr_allow_others(intr_handle))
2645 msix_vect = ICE_MISC_VEC_ID;
2647 /* uio mapping all queue to one msix_vect */
2648 __vsi_queues_bind_intr(vsi, msix_vect,
2649 vsi->base_queue + i,
2650 vsi->nb_used_qps - i);
2652 for (; !!record && i < vsi->nb_used_qps; i++)
2653 intr_handle->intr_vec[queue_idx + i] =
2658 /* vfio 1:1 queue/msix_vect mapping */
2659 __vsi_queues_bind_intr(vsi, msix_vect,
2660 vsi->base_queue + i, 1);
2663 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2671 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2673 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2674 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2675 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2676 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2677 uint16_t msix_intr, i;
2679 if (rte_intr_allow_others(intr_handle))
2680 for (i = 0; i < vsi->nb_used_qps; i++) {
2681 msix_intr = vsi->msix_intr + i;
2682 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2683 GLINT_DYN_CTL_INTENA_M |
2684 GLINT_DYN_CTL_CLEARPBA_M |
2685 GLINT_DYN_CTL_ITR_INDX_M |
2686 GLINT_DYN_CTL_WB_ON_ITR_M);
2689 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2690 GLINT_DYN_CTL_INTENA_M |
2691 GLINT_DYN_CTL_CLEARPBA_M |
2692 GLINT_DYN_CTL_ITR_INDX_M |
2693 GLINT_DYN_CTL_WB_ON_ITR_M);
2697 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2699 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2700 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2701 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2702 struct ice_vsi *vsi = pf->main_vsi;
2703 uint32_t intr_vector = 0;
2705 rte_intr_disable(intr_handle);
2707 /* check and configure queue intr-vector mapping */
2708 if ((rte_intr_cap_multiple(intr_handle) ||
2709 !RTE_ETH_DEV_SRIOV(dev).active) &&
2710 dev->data->dev_conf.intr_conf.rxq != 0) {
2711 intr_vector = dev->data->nb_rx_queues;
2712 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2713 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2714 ICE_MAX_INTR_QUEUE_NUM);
2717 if (rte_intr_efd_enable(intr_handle, intr_vector))
2721 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2722 intr_handle->intr_vec =
2723 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2725 if (!intr_handle->intr_vec) {
2727 "Failed to allocate %d rx_queues intr_vec",
2728 dev->data->nb_rx_queues);
2733 /* Map queues with MSIX interrupt */
2734 vsi->nb_used_qps = dev->data->nb_rx_queues;
2735 ice_vsi_queues_bind_intr(vsi);
2737 /* Enable interrupts for all the queues */
2738 ice_vsi_enable_queues_intr(vsi);
2740 rte_intr_enable(intr_handle);
2746 ice_get_init_link_status(struct rte_eth_dev *dev)
2748 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2749 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2750 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2751 struct ice_link_status link_status;
2754 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
2755 &link_status, NULL);
2756 if (ret != ICE_SUCCESS) {
2757 PMD_DRV_LOG(ERR, "Failed to get link info");
2758 pf->init_link_up = false;
2762 if (link_status.link_info & ICE_AQ_LINK_UP)
2763 pf->init_link_up = true;
2767 ice_dev_start(struct rte_eth_dev *dev)
2769 struct rte_eth_dev_data *data = dev->data;
2770 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2771 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2772 struct ice_vsi *vsi = pf->main_vsi;
2773 uint16_t nb_rxq = 0;
2775 uint16_t max_frame_size;
2778 /* program Tx queues' context in hardware */
2779 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2780 ret = ice_tx_queue_start(dev, nb_txq);
2782 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2787 /* program Rx queues' context in hardware*/
2788 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2789 ret = ice_rx_queue_start(dev, nb_rxq);
2791 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2796 ret = ice_init_rss(pf);
2798 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2802 ice_set_rx_function(dev);
2803 ice_set_tx_function(dev);
2805 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2806 ETH_VLAN_EXTEND_MASK;
2807 ret = ice_vlan_offload_set(dev, mask);
2809 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2813 /* enable Rx interrput and mapping Rx queue to interrupt vector */
2814 if (ice_rxq_intr_setup(dev))
2817 /* Enable receiving broadcast packets and transmitting packets */
2818 ret = ice_set_vsi_promisc(hw, vsi->idx,
2819 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2820 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2822 if (ret != ICE_SUCCESS)
2823 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2825 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2826 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2827 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2828 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2829 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2830 ICE_AQ_LINK_EVENT_AN_COMPLETED |
2831 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2833 if (ret != ICE_SUCCESS)
2834 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2836 ice_get_init_link_status(dev);
2838 ice_dev_set_link_up(dev);
2840 /* Call get_link_info aq commond to enable/disable LSE */
2841 ice_link_update(dev, 0);
2843 pf->adapter_stopped = false;
2845 /* Set the max frame size to default value*/
2846 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2847 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2850 /* Set the max frame size to HW*/
2851 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2855 /* stop the started queues if failed to start all queues */
2857 for (i = 0; i < nb_rxq; i++)
2858 ice_rx_queue_stop(dev, i);
2860 for (i = 0; i < nb_txq; i++)
2861 ice_tx_queue_stop(dev, i);
2867 ice_dev_reset(struct rte_eth_dev *dev)
2871 if (dev->data->sriov.active)
2874 ret = ice_dev_uninit(dev);
2876 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2880 ret = ice_dev_init(dev);
2882 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2890 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2892 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2893 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2894 struct ice_vsi *vsi = pf->main_vsi;
2895 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2896 bool is_safe_mode = pf->adapter->is_safe_mode;
2900 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2901 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2902 dev_info->max_rx_queues = vsi->nb_qps;
2903 dev_info->max_tx_queues = vsi->nb_qps;
2904 dev_info->max_mac_addrs = vsi->max_macaddrs;
2905 dev_info->max_vfs = pci_dev->max_vfs;
2906 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2907 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2909 dev_info->rx_offload_capa =
2910 DEV_RX_OFFLOAD_VLAN_STRIP |
2911 DEV_RX_OFFLOAD_JUMBO_FRAME |
2912 DEV_RX_OFFLOAD_KEEP_CRC |
2913 DEV_RX_OFFLOAD_SCATTER |
2914 DEV_RX_OFFLOAD_VLAN_FILTER;
2915 dev_info->tx_offload_capa =
2916 DEV_TX_OFFLOAD_VLAN_INSERT |
2917 DEV_TX_OFFLOAD_TCP_TSO |
2918 DEV_TX_OFFLOAD_MULTI_SEGS |
2919 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2920 dev_info->flow_type_rss_offloads = 0;
2922 if (!is_safe_mode) {
2923 dev_info->rx_offload_capa |=
2924 DEV_RX_OFFLOAD_IPV4_CKSUM |
2925 DEV_RX_OFFLOAD_UDP_CKSUM |
2926 DEV_RX_OFFLOAD_TCP_CKSUM |
2927 DEV_RX_OFFLOAD_QINQ_STRIP |
2928 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2929 DEV_RX_OFFLOAD_VLAN_EXTEND |
2930 DEV_RX_OFFLOAD_RSS_HASH;
2931 dev_info->tx_offload_capa |=
2932 DEV_TX_OFFLOAD_QINQ_INSERT |
2933 DEV_TX_OFFLOAD_IPV4_CKSUM |
2934 DEV_TX_OFFLOAD_UDP_CKSUM |
2935 DEV_TX_OFFLOAD_TCP_CKSUM |
2936 DEV_TX_OFFLOAD_SCTP_CKSUM |
2937 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2938 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2939 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2942 dev_info->rx_queue_offload_capa = 0;
2943 dev_info->tx_queue_offload_capa = 0;
2945 dev_info->reta_size = pf->hash_lut_size;
2946 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2948 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2950 .pthresh = ICE_DEFAULT_RX_PTHRESH,
2951 .hthresh = ICE_DEFAULT_RX_HTHRESH,
2952 .wthresh = ICE_DEFAULT_RX_WTHRESH,
2954 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2959 dev_info->default_txconf = (struct rte_eth_txconf) {
2961 .pthresh = ICE_DEFAULT_TX_PTHRESH,
2962 .hthresh = ICE_DEFAULT_TX_HTHRESH,
2963 .wthresh = ICE_DEFAULT_TX_WTHRESH,
2965 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2966 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2970 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2971 .nb_max = ICE_MAX_RING_DESC,
2972 .nb_min = ICE_MIN_RING_DESC,
2973 .nb_align = ICE_ALIGN_RING_DESC,
2976 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2977 .nb_max = ICE_MAX_RING_DESC,
2978 .nb_min = ICE_MIN_RING_DESC,
2979 .nb_align = ICE_ALIGN_RING_DESC,
2982 dev_info->speed_capa = ETH_LINK_SPEED_10M |
2983 ETH_LINK_SPEED_100M |
2985 ETH_LINK_SPEED_2_5G |
2987 ETH_LINK_SPEED_10G |
2988 ETH_LINK_SPEED_20G |
2991 phy_type_low = hw->port_info->phy.phy_type_low;
2992 phy_type_high = hw->port_info->phy.phy_type_high;
2994 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2995 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2997 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2998 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2999 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3001 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3002 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3004 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3005 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3006 dev_info->default_rxportconf.nb_queues = 1;
3007 dev_info->default_txportconf.nb_queues = 1;
3008 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3009 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3015 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3016 struct rte_eth_link *link)
3018 struct rte_eth_link *dst = link;
3019 struct rte_eth_link *src = &dev->data->dev_link;
3021 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3022 *(uint64_t *)src) == 0)
3029 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3030 struct rte_eth_link *link)
3032 struct rte_eth_link *dst = &dev->data->dev_link;
3033 struct rte_eth_link *src = link;
3035 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3036 *(uint64_t *)src) == 0)
3043 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3045 #define CHECK_INTERVAL 100 /* 100ms */
3046 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3047 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3048 struct ice_link_status link_status;
3049 struct rte_eth_link link, old;
3051 unsigned int rep_cnt = MAX_REPEAT_TIME;
3052 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3054 memset(&link, 0, sizeof(link));
3055 memset(&old, 0, sizeof(old));
3056 memset(&link_status, 0, sizeof(link_status));
3057 ice_atomic_read_link_status(dev, &old);
3060 /* Get link status information from hardware */
3061 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3062 &link_status, NULL);
3063 if (status != ICE_SUCCESS) {
3064 link.link_speed = ETH_SPEED_NUM_100M;
3065 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3066 PMD_DRV_LOG(ERR, "Failed to get link info");
3070 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3071 if (!wait_to_complete || link.link_status)
3074 rte_delay_ms(CHECK_INTERVAL);
3075 } while (--rep_cnt);
3077 if (!link.link_status)
3080 /* Full-duplex operation at all supported speeds */
3081 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3083 /* Parse the link status */
3084 switch (link_status.link_speed) {
3085 case ICE_AQ_LINK_SPEED_10MB:
3086 link.link_speed = ETH_SPEED_NUM_10M;
3088 case ICE_AQ_LINK_SPEED_100MB:
3089 link.link_speed = ETH_SPEED_NUM_100M;
3091 case ICE_AQ_LINK_SPEED_1000MB:
3092 link.link_speed = ETH_SPEED_NUM_1G;
3094 case ICE_AQ_LINK_SPEED_2500MB:
3095 link.link_speed = ETH_SPEED_NUM_2_5G;
3097 case ICE_AQ_LINK_SPEED_5GB:
3098 link.link_speed = ETH_SPEED_NUM_5G;
3100 case ICE_AQ_LINK_SPEED_10GB:
3101 link.link_speed = ETH_SPEED_NUM_10G;
3103 case ICE_AQ_LINK_SPEED_20GB:
3104 link.link_speed = ETH_SPEED_NUM_20G;
3106 case ICE_AQ_LINK_SPEED_25GB:
3107 link.link_speed = ETH_SPEED_NUM_25G;
3109 case ICE_AQ_LINK_SPEED_40GB:
3110 link.link_speed = ETH_SPEED_NUM_40G;
3112 case ICE_AQ_LINK_SPEED_50GB:
3113 link.link_speed = ETH_SPEED_NUM_50G;
3115 case ICE_AQ_LINK_SPEED_100GB:
3116 link.link_speed = ETH_SPEED_NUM_100G;
3118 case ICE_AQ_LINK_SPEED_UNKNOWN:
3120 PMD_DRV_LOG(ERR, "Unknown link speed");
3121 link.link_speed = ETH_SPEED_NUM_NONE;
3125 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3126 ETH_LINK_SPEED_FIXED);
3129 ice_atomic_write_link_status(dev, &link);
3130 if (link.link_status == old.link_status)
3136 /* Force the physical link state by getting the current PHY capabilities from
3137 * hardware and setting the PHY config based on the determined capabilities. If
3138 * link changes, link event will be triggered because both the Enable Automatic
3139 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3141 static enum ice_status
3142 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3144 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3145 struct ice_aqc_get_phy_caps_data *pcaps;
3146 struct ice_port_info *pi;
3147 enum ice_status status;
3149 if (!hw || !hw->port_info)
3150 return ICE_ERR_PARAM;
3154 pcaps = (struct ice_aqc_get_phy_caps_data *)
3155 ice_malloc(hw, sizeof(*pcaps));
3157 return ICE_ERR_NO_MEMORY;
3159 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3164 /* No change in link */
3165 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3166 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3169 cfg.phy_type_low = pcaps->phy_type_low;
3170 cfg.phy_type_high = pcaps->phy_type_high;
3171 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3172 cfg.low_power_ctrl = pcaps->low_power_ctrl;
3173 cfg.eee_cap = pcaps->eee_cap;
3174 cfg.eeer_value = pcaps->eeer_value;
3175 cfg.link_fec_opt = pcaps->link_fec_options;
3177 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3179 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3181 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3184 ice_free(hw, pcaps);
3189 ice_dev_set_link_up(struct rte_eth_dev *dev)
3191 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3193 return ice_force_phys_link_state(hw, true);
3197 ice_dev_set_link_down(struct rte_eth_dev *dev)
3199 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3201 return ice_force_phys_link_state(hw, false);
3205 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3207 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3208 struct rte_eth_dev_data *dev_data = pf->dev_data;
3209 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3211 /* check if mtu is within the allowed range */
3212 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3215 /* mtu setting is forbidden if port is start */
3216 if (dev_data->dev_started) {
3218 "port %d must be stopped before configuration",
3223 if (frame_size > RTE_ETHER_MAX_LEN)
3224 dev_data->dev_conf.rxmode.offloads |=
3225 DEV_RX_OFFLOAD_JUMBO_FRAME;
3227 dev_data->dev_conf.rxmode.offloads &=
3228 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3230 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3235 static int ice_macaddr_set(struct rte_eth_dev *dev,
3236 struct rte_ether_addr *mac_addr)
3238 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3239 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3240 struct ice_vsi *vsi = pf->main_vsi;
3241 struct ice_mac_filter *f;
3245 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3246 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3250 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3251 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3256 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3260 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3261 if (ret != ICE_SUCCESS) {
3262 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3265 ret = ice_add_mac_filter(vsi, mac_addr);
3266 if (ret != ICE_SUCCESS) {
3267 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3270 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
3272 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3273 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3274 if (ret != ICE_SUCCESS)
3275 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3280 /* Add a MAC address, and update filters */
3282 ice_macaddr_add(struct rte_eth_dev *dev,
3283 struct rte_ether_addr *mac_addr,
3284 __rte_unused uint32_t index,
3285 __rte_unused uint32_t pool)
3287 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3288 struct ice_vsi *vsi = pf->main_vsi;
3291 ret = ice_add_mac_filter(vsi, mac_addr);
3292 if (ret != ICE_SUCCESS) {
3293 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3300 /* Remove a MAC address, and update filters */
3302 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3304 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3305 struct ice_vsi *vsi = pf->main_vsi;
3306 struct rte_eth_dev_data *data = dev->data;
3307 struct rte_ether_addr *macaddr;
3310 macaddr = &data->mac_addrs[index];
3311 ret = ice_remove_mac_filter(vsi, macaddr);
3313 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3319 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3321 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3322 struct ice_vsi *vsi = pf->main_vsi;
3325 PMD_INIT_FUNC_TRACE();
3328 ret = ice_add_vlan_filter(vsi, vlan_id);
3330 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3334 ret = ice_remove_vlan_filter(vsi, vlan_id);
3336 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3344 /* Configure vlan filter on or off */
3346 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3348 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3349 struct ice_vsi_ctx ctxt;
3350 uint8_t sec_flags, sw_flags2;
3353 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3354 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3355 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3358 vsi->info.sec_flags |= sec_flags;
3359 vsi->info.sw_flags2 |= sw_flags2;
3361 vsi->info.sec_flags &= ~sec_flags;
3362 vsi->info.sw_flags2 &= ~sw_flags2;
3364 vsi->info.sw_id = hw->port_info->sw_id;
3365 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3366 ctxt.info.valid_sections =
3367 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3368 ICE_AQ_VSI_PROP_SECURITY_VALID);
3369 ctxt.vsi_num = vsi->vsi_id;
3371 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3373 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3374 on ? "enable" : "disable");
3377 vsi->info.valid_sections |=
3378 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3379 ICE_AQ_VSI_PROP_SECURITY_VALID);
3382 /* consist with other drivers, allow untagged packet when vlan filter on */
3384 ret = ice_add_vlan_filter(vsi, 0);
3386 ret = ice_remove_vlan_filter(vsi, 0);
3392 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3394 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3395 struct ice_vsi_ctx ctxt;
3399 /* Check if it has been already on or off */
3400 if (vsi->info.valid_sections &
3401 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3403 if ((vsi->info.vlan_flags &
3404 ICE_AQ_VSI_VLAN_EMOD_M) ==
3405 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3406 return 0; /* already on */
3408 if ((vsi->info.vlan_flags &
3409 ICE_AQ_VSI_VLAN_EMOD_M) ==
3410 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3411 return 0; /* already off */
3416 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3418 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3419 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3420 vsi->info.vlan_flags |= vlan_flags;
3421 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3422 ctxt.info.valid_sections =
3423 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3424 ctxt.vsi_num = vsi->vsi_id;
3425 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3427 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3428 on ? "enable" : "disable");
3432 vsi->info.valid_sections |=
3433 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3439 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3441 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3442 struct ice_vsi *vsi = pf->main_vsi;
3443 struct rte_eth_rxmode *rxmode;
3445 rxmode = &dev->data->dev_conf.rxmode;
3446 if (mask & ETH_VLAN_FILTER_MASK) {
3447 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3448 ice_vsi_config_vlan_filter(vsi, TRUE);
3450 ice_vsi_config_vlan_filter(vsi, FALSE);
3453 if (mask & ETH_VLAN_STRIP_MASK) {
3454 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3455 ice_vsi_config_vlan_stripping(vsi, TRUE);
3457 ice_vsi_config_vlan_stripping(vsi, FALSE);
3460 if (mask & ETH_VLAN_EXTEND_MASK) {
3461 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3462 ice_vsi_config_double_vlan(vsi, TRUE);
3464 ice_vsi_config_double_vlan(vsi, FALSE);
3471 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3473 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3474 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3480 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3481 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3482 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3484 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3488 uint64_t *lut_dw = (uint64_t *)lut;
3489 uint16_t i, lut_size_dw = lut_size / 4;
3491 for (i = 0; i < lut_size_dw; i++)
3492 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3499 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3508 pf = ICE_VSI_TO_PF(vsi);
3509 hw = ICE_VSI_TO_HW(vsi);
3511 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3512 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3513 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3515 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3519 uint64_t *lut_dw = (uint64_t *)lut;
3520 uint16_t i, lut_size_dw = lut_size / 4;
3522 for (i = 0; i < lut_size_dw; i++)
3523 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3532 ice_rss_reta_update(struct rte_eth_dev *dev,
3533 struct rte_eth_rss_reta_entry64 *reta_conf,
3536 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3537 uint16_t i, lut_size = pf->hash_lut_size;
3538 uint16_t idx, shift;
3542 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3543 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3544 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3546 "The size of hash lookup table configured (%d)"
3547 "doesn't match the number hardware can "
3548 "supported (128, 512, 2048)",
3553 /* It MUST use the current LUT size to get the RSS lookup table,
3554 * otherwise if will fail with -100 error code.
3556 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
3558 PMD_DRV_LOG(ERR, "No memory can be allocated");
3561 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3565 for (i = 0; i < reta_size; i++) {
3566 idx = i / RTE_RETA_GROUP_SIZE;
3567 shift = i % RTE_RETA_GROUP_SIZE;
3568 if (reta_conf[idx].mask & (1ULL << shift))
3569 lut[i] = reta_conf[idx].reta[shift];
3571 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3572 if (ret == 0 && lut_size != reta_size) {
3574 "The size of hash lookup table is changed from (%d) to (%d)",
3575 lut_size, reta_size);
3576 pf->hash_lut_size = reta_size;
3586 ice_rss_reta_query(struct rte_eth_dev *dev,
3587 struct rte_eth_rss_reta_entry64 *reta_conf,
3590 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3591 uint16_t i, lut_size = pf->hash_lut_size;
3592 uint16_t idx, shift;
3596 if (reta_size != lut_size) {
3598 "The size of hash lookup table configured (%d)"
3599 "doesn't match the number hardware can "
3601 reta_size, lut_size);
3605 lut = rte_zmalloc(NULL, reta_size, 0);
3607 PMD_DRV_LOG(ERR, "No memory can be allocated");
3611 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3615 for (i = 0; i < reta_size; i++) {
3616 idx = i / RTE_RETA_GROUP_SIZE;
3617 shift = i % RTE_RETA_GROUP_SIZE;
3618 if (reta_conf[idx].mask & (1ULL << shift))
3619 reta_conf[idx].reta[shift] = lut[i];
3629 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3631 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3634 if (!key || key_len == 0) {
3635 PMD_DRV_LOG(DEBUG, "No key to be configured");
3637 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3639 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3643 struct ice_aqc_get_set_rss_keys *key_dw =
3644 (struct ice_aqc_get_set_rss_keys *)key;
3646 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3648 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3656 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3658 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3661 if (!key || !key_len)
3664 ret = ice_aq_get_rss_key
3666 (struct ice_aqc_get_set_rss_keys *)key);
3668 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3671 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3677 ice_rss_hash_update(struct rte_eth_dev *dev,
3678 struct rte_eth_rss_conf *rss_conf)
3680 enum ice_status status = ICE_SUCCESS;
3681 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3682 struct ice_vsi *vsi = pf->main_vsi;
3685 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3689 /* TODO: hash enable config, ice_add_rss_cfg */
3694 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3695 struct rte_eth_rss_conf *rss_conf)
3697 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3698 struct ice_vsi *vsi = pf->main_vsi;
3700 ice_get_rss_key(vsi, rss_conf->rss_key,
3701 &rss_conf->rss_key_len);
3703 /* TODO: default set to 0 as hf config is not supported now */
3704 rss_conf->rss_hf = 0;
3709 ice_promisc_enable(struct rte_eth_dev *dev)
3711 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3712 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3713 struct ice_vsi *vsi = pf->main_vsi;
3714 enum ice_status status;
3718 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3719 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3721 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3723 case ICE_ERR_ALREADY_EXISTS:
3724 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3728 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3736 ice_promisc_disable(struct rte_eth_dev *dev)
3738 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3739 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3740 struct ice_vsi *vsi = pf->main_vsi;
3741 enum ice_status status;
3745 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3746 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3748 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3749 if (status != ICE_SUCCESS) {
3750 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3758 ice_allmulti_enable(struct rte_eth_dev *dev)
3760 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3761 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3762 struct ice_vsi *vsi = pf->main_vsi;
3763 enum ice_status status;
3767 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3769 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3772 case ICE_ERR_ALREADY_EXISTS:
3773 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3777 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3785 ice_allmulti_disable(struct rte_eth_dev *dev)
3787 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3788 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3789 struct ice_vsi *vsi = pf->main_vsi;
3790 enum ice_status status;
3794 if (dev->data->promiscuous == 1)
3795 return 0; /* must remain in all_multicast mode */
3797 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3799 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3800 if (status != ICE_SUCCESS) {
3801 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3808 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3811 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3812 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3813 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3817 msix_intr = intr_handle->intr_vec[queue_id];
3819 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3820 GLINT_DYN_CTL_ITR_INDX_M;
3821 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3823 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3824 rte_intr_ack(&pci_dev->intr_handle);
3829 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3832 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3833 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3834 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3837 msix_intr = intr_handle->intr_vec[queue_id];
3839 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3845 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3847 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3853 full_ver = hw->nvm.oem_ver;
3854 ver = (u8)(full_ver >> 24);
3855 build = (u16)((full_ver >> 8) & 0xffff);
3856 patch = (u8)(full_ver & 0xff);
3858 ret = snprintf(fw_version, fw_size,
3859 "%d.%d%d 0x%08x %d.%d.%d",
3860 ((hw->nvm.ver >> 12) & 0xf),
3861 ((hw->nvm.ver >> 4) & 0xff),
3862 (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3865 /* add the size of '\0' */
3867 if (fw_size < (u32)ret)
3874 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3877 struct ice_vsi_ctx ctxt;
3878 uint8_t vlan_flags = 0;
3881 if (!vsi || !info) {
3882 PMD_DRV_LOG(ERR, "invalid parameters");
3887 vsi->info.pvid = info->config.pvid;
3889 * If insert pvid is enabled, only tagged pkts are
3890 * allowed to be sent out.
3892 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3893 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3896 if (info->config.reject.tagged == 0)
3897 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3899 if (info->config.reject.untagged == 0)
3900 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3902 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3903 ICE_AQ_VSI_VLAN_MODE_M);
3904 vsi->info.vlan_flags |= vlan_flags;
3905 memset(&ctxt, 0, sizeof(ctxt));
3906 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3907 ctxt.info.valid_sections =
3908 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3909 ctxt.vsi_num = vsi->vsi_id;
3911 hw = ICE_VSI_TO_HW(vsi);
3912 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3913 if (ret != ICE_SUCCESS) {
3915 "update VSI for VLAN insert failed, err %d",
3920 vsi->info.valid_sections |=
3921 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3927 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3929 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3930 struct ice_vsi *vsi = pf->main_vsi;
3931 struct rte_eth_dev_data *data = pf->dev_data;
3932 struct ice_vsi_vlan_pvid_info info;
3935 memset(&info, 0, sizeof(info));
3938 info.config.pvid = pvid;
3940 info.config.reject.tagged =
3941 data->dev_conf.txmode.hw_vlan_reject_tagged;
3942 info.config.reject.untagged =
3943 data->dev_conf.txmode.hw_vlan_reject_untagged;
3946 ret = ice_vsi_vlan_pvid_set(vsi, &info);
3948 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3956 ice_get_eeprom_length(struct rte_eth_dev *dev)
3958 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3960 /* Convert word count to byte count */
3961 return hw->nvm.sr_words << 1;
3965 ice_get_eeprom(struct rte_eth_dev *dev,
3966 struct rte_dev_eeprom_info *eeprom)
3968 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3969 uint16_t *data = eeprom->data;
3970 uint16_t first_word, last_word, nwords;
3971 enum ice_status status = ICE_SUCCESS;
3973 first_word = eeprom->offset >> 1;
3974 last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3975 nwords = last_word - first_word + 1;
3977 if (first_word >= hw->nvm.sr_words ||
3978 last_word >= hw->nvm.sr_words) {
3979 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3983 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3985 status = ice_read_sr_buf(hw, first_word, &nwords, data);
3987 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3988 eeprom->length = sizeof(uint16_t) * nwords;
3996 ice_stat_update_32(struct ice_hw *hw,
4004 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4008 if (new_data >= *offset)
4009 *stat = (uint64_t)(new_data - *offset);
4011 *stat = (uint64_t)((new_data +
4012 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4017 ice_stat_update_40(struct ice_hw *hw,
4026 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4027 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4033 if (new_data >= *offset)
4034 *stat = new_data - *offset;
4036 *stat = (uint64_t)((new_data +
4037 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4040 *stat &= ICE_40_BIT_MASK;
4043 /* Get all the statistics of a VSI */
4045 ice_update_vsi_stats(struct ice_vsi *vsi)
4047 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4048 struct ice_eth_stats *nes = &vsi->eth_stats;
4049 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4050 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4052 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4053 vsi->offset_loaded, &oes->rx_bytes,
4055 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4056 vsi->offset_loaded, &oes->rx_unicast,
4058 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4059 vsi->offset_loaded, &oes->rx_multicast,
4060 &nes->rx_multicast);
4061 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4062 vsi->offset_loaded, &oes->rx_broadcast,
4063 &nes->rx_broadcast);
4064 /* exclude CRC bytes */
4065 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4066 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4068 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4069 &oes->rx_discards, &nes->rx_discards);
4070 /* GLV_REPC not supported */
4071 /* GLV_RMPC not supported */
4072 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4073 &oes->rx_unknown_protocol,
4074 &nes->rx_unknown_protocol);
4075 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4076 vsi->offset_loaded, &oes->tx_bytes,
4078 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4079 vsi->offset_loaded, &oes->tx_unicast,
4081 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4082 vsi->offset_loaded, &oes->tx_multicast,
4083 &nes->tx_multicast);
4084 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4085 vsi->offset_loaded, &oes->tx_broadcast,
4086 &nes->tx_broadcast);
4087 /* GLV_TDPC not supported */
4088 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4089 &oes->tx_errors, &nes->tx_errors);
4090 vsi->offset_loaded = true;
4092 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4094 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4095 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4096 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4097 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4098 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4099 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4100 nes->rx_unknown_protocol);
4101 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4102 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4103 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4104 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4105 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4106 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4107 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4112 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4114 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4115 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4117 /* Get statistics of struct ice_eth_stats */
4118 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4119 GLPRT_GORCL(hw->port_info->lport),
4120 pf->offset_loaded, &os->eth.rx_bytes,
4122 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4123 GLPRT_UPRCL(hw->port_info->lport),
4124 pf->offset_loaded, &os->eth.rx_unicast,
4125 &ns->eth.rx_unicast);
4126 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4127 GLPRT_MPRCL(hw->port_info->lport),
4128 pf->offset_loaded, &os->eth.rx_multicast,
4129 &ns->eth.rx_multicast);
4130 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4131 GLPRT_BPRCL(hw->port_info->lport),
4132 pf->offset_loaded, &os->eth.rx_broadcast,
4133 &ns->eth.rx_broadcast);
4134 ice_stat_update_32(hw, PRTRPB_RDPC,
4135 pf->offset_loaded, &os->eth.rx_discards,
4136 &ns->eth.rx_discards);
4138 /* Workaround: CRC size should not be included in byte statistics,
4139 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4142 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4143 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4145 /* GLPRT_REPC not supported */
4146 /* GLPRT_RMPC not supported */
4147 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4149 &os->eth.rx_unknown_protocol,
4150 &ns->eth.rx_unknown_protocol);
4151 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4152 GLPRT_GOTCL(hw->port_info->lport),
4153 pf->offset_loaded, &os->eth.tx_bytes,
4155 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4156 GLPRT_UPTCL(hw->port_info->lport),
4157 pf->offset_loaded, &os->eth.tx_unicast,
4158 &ns->eth.tx_unicast);
4159 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4160 GLPRT_MPTCL(hw->port_info->lport),
4161 pf->offset_loaded, &os->eth.tx_multicast,
4162 &ns->eth.tx_multicast);
4163 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4164 GLPRT_BPTCL(hw->port_info->lport),
4165 pf->offset_loaded, &os->eth.tx_broadcast,
4166 &ns->eth.tx_broadcast);
4167 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4168 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4170 /* GLPRT_TEPC not supported */
4172 /* additional port specific stats */
4173 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4174 pf->offset_loaded, &os->tx_dropped_link_down,
4175 &ns->tx_dropped_link_down);
4176 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4177 pf->offset_loaded, &os->crc_errors,
4179 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4180 pf->offset_loaded, &os->illegal_bytes,
4181 &ns->illegal_bytes);
4182 /* GLPRT_ERRBC not supported */
4183 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4184 pf->offset_loaded, &os->mac_local_faults,
4185 &ns->mac_local_faults);
4186 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4187 pf->offset_loaded, &os->mac_remote_faults,
4188 &ns->mac_remote_faults);
4190 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4191 pf->offset_loaded, &os->rx_len_errors,
4192 &ns->rx_len_errors);
4194 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4195 pf->offset_loaded, &os->link_xon_rx,
4197 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4198 pf->offset_loaded, &os->link_xoff_rx,
4200 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4201 pf->offset_loaded, &os->link_xon_tx,
4203 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4204 pf->offset_loaded, &os->link_xoff_tx,
4206 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4207 GLPRT_PRC64L(hw->port_info->lport),
4208 pf->offset_loaded, &os->rx_size_64,
4210 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4211 GLPRT_PRC127L(hw->port_info->lport),
4212 pf->offset_loaded, &os->rx_size_127,
4214 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4215 GLPRT_PRC255L(hw->port_info->lport),
4216 pf->offset_loaded, &os->rx_size_255,
4218 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4219 GLPRT_PRC511L(hw->port_info->lport),
4220 pf->offset_loaded, &os->rx_size_511,
4222 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4223 GLPRT_PRC1023L(hw->port_info->lport),
4224 pf->offset_loaded, &os->rx_size_1023,
4226 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4227 GLPRT_PRC1522L(hw->port_info->lport),
4228 pf->offset_loaded, &os->rx_size_1522,
4230 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4231 GLPRT_PRC9522L(hw->port_info->lport),
4232 pf->offset_loaded, &os->rx_size_big,
4234 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4235 pf->offset_loaded, &os->rx_undersize,
4237 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4238 pf->offset_loaded, &os->rx_fragments,
4240 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4241 pf->offset_loaded, &os->rx_oversize,
4243 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4244 pf->offset_loaded, &os->rx_jabber,
4246 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4247 GLPRT_PTC64L(hw->port_info->lport),
4248 pf->offset_loaded, &os->tx_size_64,
4250 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4251 GLPRT_PTC127L(hw->port_info->lport),
4252 pf->offset_loaded, &os->tx_size_127,
4254 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4255 GLPRT_PTC255L(hw->port_info->lport),
4256 pf->offset_loaded, &os->tx_size_255,
4258 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4259 GLPRT_PTC511L(hw->port_info->lport),
4260 pf->offset_loaded, &os->tx_size_511,
4262 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4263 GLPRT_PTC1023L(hw->port_info->lport),
4264 pf->offset_loaded, &os->tx_size_1023,
4266 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4267 GLPRT_PTC1522L(hw->port_info->lport),
4268 pf->offset_loaded, &os->tx_size_1522,
4270 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4271 GLPRT_PTC9522L(hw->port_info->lport),
4272 pf->offset_loaded, &os->tx_size_big,
4275 /* GLPRT_MSPDC not supported */
4276 /* GLPRT_XEC not supported */
4278 pf->offset_loaded = true;
4281 ice_update_vsi_stats(pf->main_vsi);
4284 /* Get all statistics of a port */
4286 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4288 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4289 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4290 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4292 /* call read registers - updates values, now write them to struct */
4293 ice_read_stats_registers(pf, hw);
4295 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4296 pf->main_vsi->eth_stats.rx_multicast +
4297 pf->main_vsi->eth_stats.rx_broadcast -
4298 pf->main_vsi->eth_stats.rx_discards;
4299 stats->opackets = ns->eth.tx_unicast +
4300 ns->eth.tx_multicast +
4301 ns->eth.tx_broadcast;
4302 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
4303 stats->obytes = ns->eth.tx_bytes;
4304 stats->oerrors = ns->eth.tx_errors +
4305 pf->main_vsi->eth_stats.tx_errors;
4308 stats->imissed = ns->eth.rx_discards +
4309 pf->main_vsi->eth_stats.rx_discards;
4310 stats->ierrors = ns->crc_errors +
4312 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4314 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4315 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
4316 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4317 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4318 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4319 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4320 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4321 pf->main_vsi->eth_stats.rx_discards);
4322 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4323 ns->eth.rx_unknown_protocol);
4324 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
4325 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4326 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4327 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4328 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4329 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4330 pf->main_vsi->eth_stats.tx_discards);
4331 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
4333 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
4334 ns->tx_dropped_link_down);
4335 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4336 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
4338 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
4339 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
4340 ns->mac_local_faults);
4341 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
4342 ns->mac_remote_faults);
4343 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
4344 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
4345 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
4346 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
4347 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
4348 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
4349 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
4350 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
4351 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
4352 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
4353 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
4354 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
4355 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
4356 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
4357 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
4358 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
4359 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
4360 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
4361 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
4362 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
4363 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
4364 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
4365 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
4366 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4370 /* Reset the statistics */
4372 ice_stats_reset(struct rte_eth_dev *dev)
4374 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4375 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4377 /* Mark PF and VSI stats to update the offset, aka "reset" */
4378 pf->offset_loaded = false;
4380 pf->main_vsi->offset_loaded = false;
4382 /* read the stats, reading current register values into offset */
4383 ice_read_stats_registers(pf, hw);
4389 ice_xstats_calc_num(void)
4393 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4399 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4402 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4403 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4406 struct ice_hw_port_stats *hw_stats = &pf->stats;
4408 count = ice_xstats_calc_num();
4412 ice_read_stats_registers(pf, hw);
4419 /* Get stats from ice_eth_stats struct */
4420 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4421 xstats[count].value =
4422 *(uint64_t *)((char *)&hw_stats->eth +
4423 ice_stats_strings[i].offset);
4424 xstats[count].id = count;
4428 /* Get individiual stats from ice_hw_port struct */
4429 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4430 xstats[count].value =
4431 *(uint64_t *)((char *)hw_stats +
4432 ice_hw_port_strings[i].offset);
4433 xstats[count].id = count;
4440 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4441 struct rte_eth_xstat_name *xstats_names,
4442 __rte_unused unsigned int limit)
4444 unsigned int count = 0;
4448 return ice_xstats_calc_num();
4450 /* Note: limit checked in rte_eth_xstats_names() */
4452 /* Get stats from ice_eth_stats struct */
4453 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4454 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4455 sizeof(xstats_names[count].name));
4459 /* Get individiual stats from ice_hw_port struct */
4460 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4461 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4462 sizeof(xstats_names[count].name));
4470 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4471 enum rte_filter_type filter_type,
4472 enum rte_filter_op filter_op,
4480 switch (filter_type) {
4481 case RTE_ETH_FILTER_GENERIC:
4482 if (filter_op != RTE_ETH_FILTER_GET)
4484 *(const void **)arg = &ice_flow_ops;
4487 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4496 /* Add UDP tunneling port */
4498 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4499 struct rte_eth_udp_tunnel *udp_tunnel)
4502 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4504 if (udp_tunnel == NULL)
4507 switch (udp_tunnel->prot_type) {
4508 case RTE_TUNNEL_TYPE_VXLAN:
4509 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4512 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4520 /* Delete UDP tunneling port */
4522 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4523 struct rte_eth_udp_tunnel *udp_tunnel)
4526 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4528 if (udp_tunnel == NULL)
4531 switch (udp_tunnel->prot_type) {
4532 case RTE_TUNNEL_TYPE_VXLAN:
4533 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4536 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4545 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4546 struct rte_pci_device *pci_dev)
4548 return rte_eth_dev_pci_generic_probe(pci_dev,
4549 sizeof(struct ice_adapter),
4554 ice_pci_remove(struct rte_pci_device *pci_dev)
4556 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4559 static struct rte_pci_driver rte_ice_pmd = {
4560 .id_table = pci_id_ice_map,
4561 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4562 .probe = ice_pci_probe,
4563 .remove = ice_pci_remove,
4567 * Driver initialization routine.
4568 * Invoked once at EAL init time.
4569 * Register itself as the [Poll Mode] Driver of PCI devices.
4571 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4572 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4573 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4574 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4575 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4576 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4577 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
4578 ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
4580 RTE_INIT(ice_init_log)
4582 ice_logtype_init = rte_log_register("pmd.net.ice.init");
4583 if (ice_logtype_init >= 0)
4584 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4585 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4586 if (ice_logtype_driver >= 0)
4587 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4589 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4590 ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4591 if (ice_logtype_rx >= 0)
4592 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4595 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4596 ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4597 if (ice_logtype_tx >= 0)
4598 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4601 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4602 ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4603 if (ice_logtype_tx_free >= 0)
4604 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);