1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
17 #include "ice_ethdev.h"
19 #include "ice_generic_flow.h"
22 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
23 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
24 #define ICE_PROTO_XTR_ARG "proto_xtr"
26 static const char * const ice_valid_args[] = {
27 ICE_SAFE_MODE_SUPPORT_ARG,
28 ICE_PIPELINE_MODE_SUPPORT_ARG,
33 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
35 /* DDP package search path */
36 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
37 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
38 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
39 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
41 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
42 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
43 #define ICE_MAX_PKG_FILENAME_SIZE 256
44 #define ICE_MAX_RES_DESC_NUM 1024
47 int ice_logtype_driver;
48 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
51 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
54 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
55 int ice_logtype_tx_free;
58 static int ice_dev_configure(struct rte_eth_dev *dev);
59 static int ice_dev_start(struct rte_eth_dev *dev);
60 static void ice_dev_stop(struct rte_eth_dev *dev);
61 static void ice_dev_close(struct rte_eth_dev *dev);
62 static int ice_dev_reset(struct rte_eth_dev *dev);
63 static int ice_dev_info_get(struct rte_eth_dev *dev,
64 struct rte_eth_dev_info *dev_info);
65 static int ice_link_update(struct rte_eth_dev *dev,
66 int wait_to_complete);
67 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
68 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
70 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
71 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
72 static int ice_rss_reta_update(struct rte_eth_dev *dev,
73 struct rte_eth_rss_reta_entry64 *reta_conf,
75 static int ice_rss_reta_query(struct rte_eth_dev *dev,
76 struct rte_eth_rss_reta_entry64 *reta_conf,
78 static int ice_rss_hash_update(struct rte_eth_dev *dev,
79 struct rte_eth_rss_conf *rss_conf);
80 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
81 struct rte_eth_rss_conf *rss_conf);
82 static int ice_promisc_enable(struct rte_eth_dev *dev);
83 static int ice_promisc_disable(struct rte_eth_dev *dev);
84 static int ice_allmulti_enable(struct rte_eth_dev *dev);
85 static int ice_allmulti_disable(struct rte_eth_dev *dev);
86 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
89 static int ice_macaddr_set(struct rte_eth_dev *dev,
90 struct rte_ether_addr *mac_addr);
91 static int ice_macaddr_add(struct rte_eth_dev *dev,
92 struct rte_ether_addr *mac_addr,
93 __rte_unused uint32_t index,
95 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
96 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
98 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
100 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
102 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
103 uint16_t pvid, int on);
104 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
105 static int ice_get_eeprom(struct rte_eth_dev *dev,
106 struct rte_dev_eeprom_info *eeprom);
107 static int ice_stats_get(struct rte_eth_dev *dev,
108 struct rte_eth_stats *stats);
109 static int ice_stats_reset(struct rte_eth_dev *dev);
110 static int ice_xstats_get(struct rte_eth_dev *dev,
111 struct rte_eth_xstat *xstats, unsigned int n);
112 static int ice_xstats_get_names(struct rte_eth_dev *dev,
113 struct rte_eth_xstat_name *xstats_names,
115 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
116 enum rte_filter_type filter_type,
117 enum rte_filter_op filter_op,
119 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
120 struct rte_eth_udp_tunnel *udp_tunnel);
121 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
122 struct rte_eth_udp_tunnel *udp_tunnel);
124 static const struct rte_pci_id pci_id_ice_map[] = {
125 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
126 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
127 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
128 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
129 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
130 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
131 { .vendor_id = 0, /* sentinel */ },
134 static const struct eth_dev_ops ice_eth_dev_ops = {
135 .dev_configure = ice_dev_configure,
136 .dev_start = ice_dev_start,
137 .dev_stop = ice_dev_stop,
138 .dev_close = ice_dev_close,
139 .dev_reset = ice_dev_reset,
140 .dev_set_link_up = ice_dev_set_link_up,
141 .dev_set_link_down = ice_dev_set_link_down,
142 .rx_queue_start = ice_rx_queue_start,
143 .rx_queue_stop = ice_rx_queue_stop,
144 .tx_queue_start = ice_tx_queue_start,
145 .tx_queue_stop = ice_tx_queue_stop,
146 .rx_queue_setup = ice_rx_queue_setup,
147 .rx_queue_release = ice_rx_queue_release,
148 .tx_queue_setup = ice_tx_queue_setup,
149 .tx_queue_release = ice_tx_queue_release,
150 .dev_infos_get = ice_dev_info_get,
151 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
152 .link_update = ice_link_update,
153 .mtu_set = ice_mtu_set,
154 .mac_addr_set = ice_macaddr_set,
155 .mac_addr_add = ice_macaddr_add,
156 .mac_addr_remove = ice_macaddr_remove,
157 .vlan_filter_set = ice_vlan_filter_set,
158 .vlan_offload_set = ice_vlan_offload_set,
159 .reta_update = ice_rss_reta_update,
160 .reta_query = ice_rss_reta_query,
161 .rss_hash_update = ice_rss_hash_update,
162 .rss_hash_conf_get = ice_rss_hash_conf_get,
163 .promiscuous_enable = ice_promisc_enable,
164 .promiscuous_disable = ice_promisc_disable,
165 .allmulticast_enable = ice_allmulti_enable,
166 .allmulticast_disable = ice_allmulti_disable,
167 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
168 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
169 .fw_version_get = ice_fw_version_get,
170 .vlan_pvid_set = ice_vlan_pvid_set,
171 .rxq_info_get = ice_rxq_info_get,
172 .txq_info_get = ice_txq_info_get,
173 .rx_burst_mode_get = ice_rx_burst_mode_get,
174 .tx_burst_mode_get = ice_tx_burst_mode_get,
175 .get_eeprom_length = ice_get_eeprom_length,
176 .get_eeprom = ice_get_eeprom,
177 .rx_queue_count = ice_rx_queue_count,
178 .rx_descriptor_status = ice_rx_descriptor_status,
179 .tx_descriptor_status = ice_tx_descriptor_status,
180 .stats_get = ice_stats_get,
181 .stats_reset = ice_stats_reset,
182 .xstats_get = ice_xstats_get,
183 .xstats_get_names = ice_xstats_get_names,
184 .xstats_reset = ice_stats_reset,
185 .filter_ctrl = ice_dev_filter_ctrl,
186 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
187 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
190 /* store statistics names and its offset in stats structure */
191 struct ice_xstats_name_off {
192 char name[RTE_ETH_XSTATS_NAME_SIZE];
196 static const struct ice_xstats_name_off ice_stats_strings[] = {
197 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
198 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
199 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
200 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
201 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
202 rx_unknown_protocol)},
203 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
204 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
205 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
206 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
209 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
210 sizeof(ice_stats_strings[0]))
212 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
213 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
214 tx_dropped_link_down)},
215 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
216 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
218 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
219 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
221 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
223 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
225 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
226 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
227 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
228 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
229 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
230 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
232 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
234 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
236 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
238 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
240 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
242 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
244 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
246 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
247 mac_short_pkt_dropped)},
248 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
250 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
251 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
252 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
254 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
256 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
258 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
260 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
262 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
266 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
267 sizeof(ice_hw_port_strings[0]))
270 ice_init_controlq_parameter(struct ice_hw *hw)
272 /* fields for adminq */
273 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
274 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
275 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
276 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
278 /* fields for mailboxq, DPDK used as PF host */
279 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
280 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
281 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
282 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
286 lookup_proto_xtr_type(const char *xtr_name)
290 enum proto_xtr_type type;
292 { "vlan", PROTO_XTR_VLAN },
293 { "ipv4", PROTO_XTR_IPV4 },
294 { "ipv6", PROTO_XTR_IPV6 },
295 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
296 { "tcp", PROTO_XTR_TCP },
300 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
301 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
302 return xtr_type_map[i].type;
309 * Parse elem, the elem could be single number/range or '(' ')' group
310 * 1) A single number elem, it's just a simple digit. e.g. 9
311 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
312 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
313 * Within group elem, '-' used for a range separator;
314 * ',' used for a single number.
317 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
319 const char *str = input;
324 while (isblank(*str))
327 if (!isdigit(*str) && *str != '(')
330 /* process single number or single range of number */
333 idx = strtoul(str, &end, 10);
334 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
337 while (isblank(*end))
343 /* process single <number>-<number> */
346 while (isblank(*end))
352 idx = strtoul(end, &end, 10);
353 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
357 while (isblank(*end))
364 for (idx = RTE_MIN(min, max);
365 idx <= RTE_MAX(min, max); idx++)
366 devargs->proto_xtr[idx] = xtr_type;
371 /* process set within bracket */
373 while (isblank(*str))
378 min = ICE_MAX_QUEUE_NUM;
380 /* go ahead to the first digit */
381 while (isblank(*str))
386 /* get the digit value */
388 idx = strtoul(str, &end, 10);
389 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
392 /* go ahead to separator '-',',' and ')' */
393 while (isblank(*end))
396 if (min == ICE_MAX_QUEUE_NUM)
398 else /* avoid continuous '-' */
400 } else if (*end == ',' || *end == ')') {
402 if (min == ICE_MAX_QUEUE_NUM)
405 for (idx = RTE_MIN(min, max);
406 idx <= RTE_MAX(min, max); idx++)
407 devargs->proto_xtr[idx] = xtr_type;
409 min = ICE_MAX_QUEUE_NUM;
415 } while (*end != ')' && *end != '\0');
421 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
423 const char *queue_start;
428 while (isblank(*queues))
431 if (*queues != '[') {
432 xtr_type = lookup_proto_xtr_type(queues);
436 devargs->proto_xtr_dflt = xtr_type;
443 while (isblank(*queues))
448 queue_start = queues;
450 /* go across a complete bracket */
451 if (*queue_start == '(') {
452 queues += strcspn(queues, ")");
457 /* scan the separator ':' */
458 queues += strcspn(queues, ":");
459 if (*queues++ != ':')
461 while (isblank(*queues))
464 for (idx = 0; ; idx++) {
465 if (isblank(queues[idx]) ||
466 queues[idx] == ',' ||
467 queues[idx] == ']' ||
471 if (idx > sizeof(xtr_name) - 2)
474 xtr_name[idx] = queues[idx];
476 xtr_name[idx] = '\0';
477 xtr_type = lookup_proto_xtr_type(xtr_name);
483 while (isblank(*queues) || *queues == ',' || *queues == ']')
486 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
488 } while (*queues != '\0');
494 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
497 struct ice_devargs *devargs = extra_args;
499 if (value == NULL || extra_args == NULL)
502 if (parse_queue_proto_xtr(value, devargs) < 0) {
504 "The protocol extraction parameter is wrong : '%s'",
513 ice_proto_xtr_support(struct ice_hw *hw)
515 #define FLX_REG(val, fld, idx) \
516 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
517 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
523 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
524 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
525 ICE_PROT_IPV4_OF_OR_S },
526 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
527 ICE_PROT_IPV6_OF_OR_S },
528 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
529 ICE_PROT_IPV6_OF_OR_S },
530 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
534 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
535 uint32_t rxdid = xtr_sets[i].rxdid;
538 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
539 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
541 if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
542 FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
546 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
547 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
549 if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
550 FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
559 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
562 struct pool_entry *entry;
567 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
570 "Failed to allocate memory for resource pool");
574 /* queue heap initialize */
575 pool->num_free = num;
578 LIST_INIT(&pool->alloc_list);
579 LIST_INIT(&pool->free_list);
581 /* Initialize element */
585 LIST_INSERT_HEAD(&pool->free_list, entry, next);
590 ice_res_pool_alloc(struct ice_res_pool_info *pool,
593 struct pool_entry *entry, *valid_entry;
596 PMD_INIT_LOG(ERR, "Invalid parameter");
600 if (pool->num_free < num) {
601 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
602 num, pool->num_free);
607 /* Lookup in free list and find most fit one */
608 LIST_FOREACH(entry, &pool->free_list, next) {
609 if (entry->len >= num) {
611 if (entry->len == num) {
616 valid_entry->len > entry->len)
621 /* Not find one to satisfy the request, return */
623 PMD_INIT_LOG(ERR, "No valid entry found");
627 * The entry have equal queue number as requested,
628 * remove it from alloc_list.
630 if (valid_entry->len == num) {
631 LIST_REMOVE(valid_entry, next);
634 * The entry have more numbers than requested,
635 * create a new entry for alloc_list and minus its
636 * queue base and number in free_list.
638 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
641 "Failed to allocate memory for "
645 entry->base = valid_entry->base;
647 valid_entry->base += num;
648 valid_entry->len -= num;
652 /* Insert it into alloc list, not sorted */
653 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
655 pool->num_free -= valid_entry->len;
656 pool->num_alloc += valid_entry->len;
658 return valid_entry->base + pool->base;
662 ice_res_pool_destroy(struct ice_res_pool_info *pool)
664 struct pool_entry *entry, *next_entry;
669 for (entry = LIST_FIRST(&pool->alloc_list);
670 entry && (next_entry = LIST_NEXT(entry, next), 1);
671 entry = next_entry) {
672 LIST_REMOVE(entry, next);
676 for (entry = LIST_FIRST(&pool->free_list);
677 entry && (next_entry = LIST_NEXT(entry, next), 1);
678 entry = next_entry) {
679 LIST_REMOVE(entry, next);
686 LIST_INIT(&pool->alloc_list);
687 LIST_INIT(&pool->free_list);
691 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
693 /* Set VSI LUT selection */
694 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
695 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
696 /* Set Hash scheme */
697 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
698 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
700 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
703 static enum ice_status
704 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
705 struct ice_aqc_vsi_props *info,
706 uint8_t enabled_tcmap)
708 uint16_t bsf, qp_idx;
710 /* default tc 0 now. Multi-TC supporting need to be done later.
711 * Configure TC and queue mapping parameters, for enabled TC,
712 * allocate qpnum_per_tc queues to this traffic.
714 if (enabled_tcmap != 0x01) {
715 PMD_INIT_LOG(ERR, "only TC0 is supported");
719 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
720 bsf = rte_bsf32(vsi->nb_qps);
721 /* Adjust the queue number to actual queues that can be applied */
722 vsi->nb_qps = 0x1 << bsf;
725 /* Set tc and queue mapping with VSI */
726 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
727 ICE_AQ_VSI_TC_Q_OFFSET_S) |
728 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
730 /* Associate queue number with VSI */
731 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
732 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
733 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
734 info->valid_sections |=
735 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
736 /* Set the info.ingress_table and info.egress_table
737 * for UP translate table. Now just set it to 1:1 map by default
738 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
740 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
741 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
742 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
743 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
748 ice_init_mac_address(struct rte_eth_dev *dev)
750 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
752 if (!rte_is_unicast_ether_addr
753 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
754 PMD_INIT_LOG(ERR, "Invalid MAC address");
759 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
760 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
762 dev->data->mac_addrs =
763 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
764 if (!dev->data->mac_addrs) {
766 "Failed to allocate memory to store mac address");
769 /* store it to dev data */
771 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
772 &dev->data->mac_addrs[0]);
776 /* Find out specific MAC filter */
777 static struct ice_mac_filter *
778 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
780 struct ice_mac_filter *f;
782 TAILQ_FOREACH(f, &vsi->mac_list, next) {
783 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
791 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
793 struct ice_fltr_list_entry *m_list_itr = NULL;
794 struct ice_mac_filter *f;
795 struct LIST_HEAD_TYPE list_head;
796 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
799 /* If it's added and configured, return */
800 f = ice_find_mac_filter(vsi, mac_addr);
802 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
806 INIT_LIST_HEAD(&list_head);
808 m_list_itr = (struct ice_fltr_list_entry *)
809 ice_malloc(hw, sizeof(*m_list_itr));
814 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
815 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
816 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
817 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
818 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
819 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
820 m_list_itr->fltr_info.vsi_handle = vsi->idx;
822 LIST_ADD(&m_list_itr->list_entry, &list_head);
825 ret = ice_add_mac(hw, &list_head);
826 if (ret != ICE_SUCCESS) {
827 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
831 /* Add the mac addr into mac list */
832 f = rte_zmalloc(NULL, sizeof(*f), 0);
834 PMD_DRV_LOG(ERR, "failed to allocate memory");
838 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
839 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
845 rte_free(m_list_itr);
850 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
852 struct ice_fltr_list_entry *m_list_itr = NULL;
853 struct ice_mac_filter *f;
854 struct LIST_HEAD_TYPE list_head;
855 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
858 /* Can't find it, return an error */
859 f = ice_find_mac_filter(vsi, mac_addr);
863 INIT_LIST_HEAD(&list_head);
865 m_list_itr = (struct ice_fltr_list_entry *)
866 ice_malloc(hw, sizeof(*m_list_itr));
871 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
872 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
873 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
874 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
875 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
876 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
877 m_list_itr->fltr_info.vsi_handle = vsi->idx;
879 LIST_ADD(&m_list_itr->list_entry, &list_head);
881 /* remove the mac filter */
882 ret = ice_remove_mac(hw, &list_head);
883 if (ret != ICE_SUCCESS) {
884 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
889 /* Remove the mac addr from mac list */
890 TAILQ_REMOVE(&vsi->mac_list, f, next);
896 rte_free(m_list_itr);
900 /* Find out specific VLAN filter */
901 static struct ice_vlan_filter *
902 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
904 struct ice_vlan_filter *f;
906 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
907 if (vlan_id == f->vlan_info.vlan_id)
915 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
917 struct ice_fltr_list_entry *v_list_itr = NULL;
918 struct ice_vlan_filter *f;
919 struct LIST_HEAD_TYPE list_head;
923 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
926 hw = ICE_VSI_TO_HW(vsi);
928 /* If it's added and configured, return. */
929 f = ice_find_vlan_filter(vsi, vlan_id);
931 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
935 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
938 INIT_LIST_HEAD(&list_head);
940 v_list_itr = (struct ice_fltr_list_entry *)
941 ice_malloc(hw, sizeof(*v_list_itr));
946 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
947 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
948 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
949 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
950 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
951 v_list_itr->fltr_info.vsi_handle = vsi->idx;
953 LIST_ADD(&v_list_itr->list_entry, &list_head);
956 ret = ice_add_vlan(hw, &list_head);
957 if (ret != ICE_SUCCESS) {
958 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
963 /* Add vlan into vlan list */
964 f = rte_zmalloc(NULL, sizeof(*f), 0);
966 PMD_DRV_LOG(ERR, "failed to allocate memory");
970 f->vlan_info.vlan_id = vlan_id;
971 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
977 rte_free(v_list_itr);
982 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
984 struct ice_fltr_list_entry *v_list_itr = NULL;
985 struct ice_vlan_filter *f;
986 struct LIST_HEAD_TYPE list_head;
991 * Vlan 0 is the generic filter for untagged packets
992 * and can't be removed.
994 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
997 hw = ICE_VSI_TO_HW(vsi);
999 /* Can't find it, return an error */
1000 f = ice_find_vlan_filter(vsi, vlan_id);
1004 INIT_LIST_HEAD(&list_head);
1006 v_list_itr = (struct ice_fltr_list_entry *)
1007 ice_malloc(hw, sizeof(*v_list_itr));
1013 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1014 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1015 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1016 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1017 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1018 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1020 LIST_ADD(&v_list_itr->list_entry, &list_head);
1022 /* remove the vlan filter */
1023 ret = ice_remove_vlan(hw, &list_head);
1024 if (ret != ICE_SUCCESS) {
1025 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1030 /* Remove the vlan id from vlan list */
1031 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1037 rte_free(v_list_itr);
1042 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1044 struct ice_mac_filter *m_f;
1045 struct ice_vlan_filter *v_f;
1048 if (!vsi || !vsi->mac_num)
1051 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1052 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1053 if (ret != ICE_SUCCESS) {
1059 if (vsi->vlan_num == 0)
1062 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1063 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1064 if (ret != ICE_SUCCESS) {
1075 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1077 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1078 struct ice_vsi_ctx ctxt;
1082 /* Check if it has been already on or off */
1083 if (vsi->info.valid_sections &
1084 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1086 if ((vsi->info.outer_tag_flags &
1087 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1088 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1089 return 0; /* already on */
1091 if (!(vsi->info.outer_tag_flags &
1092 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1093 return 0; /* already off */
1098 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1101 /* clear global insertion and use per packet insertion */
1102 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1103 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1104 vsi->info.outer_tag_flags |= qinq_flags;
1105 /* use default vlan type 0x8100 */
1106 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1107 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1108 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1109 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1110 ctxt.info.valid_sections =
1111 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1112 ctxt.vsi_num = vsi->vsi_id;
1113 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1116 "Update VSI failed to %s qinq stripping",
1117 on ? "enable" : "disable");
1121 vsi->info.valid_sections |=
1122 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1128 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1130 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1131 struct ice_vsi_ctx ctxt;
1135 /* Check if it has been already on or off */
1136 if (vsi->info.valid_sections &
1137 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1139 if ((vsi->info.outer_tag_flags &
1140 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1141 ICE_AQ_VSI_OUTER_TAG_COPY)
1142 return 0; /* already on */
1144 if ((vsi->info.outer_tag_flags &
1145 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1146 ICE_AQ_VSI_OUTER_TAG_NOTHING)
1147 return 0; /* already off */
1152 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1154 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1155 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1156 vsi->info.outer_tag_flags |= qinq_flags;
1157 /* use default vlan type 0x8100 */
1158 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1159 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1160 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1161 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1162 ctxt.info.valid_sections =
1163 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1164 ctxt.vsi_num = vsi->vsi_id;
1165 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1168 "Update VSI failed to %s qinq stripping",
1169 on ? "enable" : "disable");
1173 vsi->info.valid_sections |=
1174 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1180 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1184 ret = ice_vsi_config_qinq_stripping(vsi, on);
1186 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1188 ret = ice_vsi_config_qinq_insertion(vsi, on);
1190 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1197 ice_pf_enable_irq0(struct ice_hw *hw)
1199 /* reset the registers */
1200 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1201 ICE_READ_REG(hw, PFINT_OICR);
1204 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1205 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1206 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1208 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1209 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1210 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1211 PFINT_OICR_CTL_ITR_INDX_M) |
1212 PFINT_OICR_CTL_CAUSE_ENA_M);
1214 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1215 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1216 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1217 PFINT_FW_CTL_ITR_INDX_M) |
1218 PFINT_FW_CTL_CAUSE_ENA_M);
1220 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1223 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1224 GLINT_DYN_CTL_INTENA_M |
1225 GLINT_DYN_CTL_CLEARPBA_M |
1226 GLINT_DYN_CTL_ITR_INDX_M);
1233 ice_pf_disable_irq0(struct ice_hw *hw)
1235 /* Disable all interrupt types */
1236 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1242 ice_handle_aq_msg(struct rte_eth_dev *dev)
1244 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245 struct ice_ctl_q_info *cq = &hw->adminq;
1246 struct ice_rq_event_info event;
1247 uint16_t pending, opcode;
1250 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1251 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1252 if (!event.msg_buf) {
1253 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1259 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1261 if (ret != ICE_SUCCESS) {
1263 "Failed to read msg from AdminQ, "
1265 hw->adminq.sq_last_status);
1268 opcode = rte_le_to_cpu_16(event.desc.opcode);
1271 case ice_aqc_opc_get_link_status:
1272 ret = ice_link_update(dev, 0);
1274 _rte_eth_dev_callback_process
1275 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1278 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1283 rte_free(event.msg_buf);
1288 * Interrupt handler triggered by NIC for handling
1289 * specific interrupt.
1292 * Pointer to interrupt handle.
1294 * The address of parameter (struct rte_eth_dev *) regsitered before.
1300 ice_interrupt_handler(void *param)
1302 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1303 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1311 uint32_t int_fw_ctl;
1314 /* Disable interrupt */
1315 ice_pf_disable_irq0(hw);
1317 /* read out interrupt causes */
1318 oicr = ICE_READ_REG(hw, PFINT_OICR);
1320 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1323 /* No interrupt event indicated */
1324 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1325 PMD_DRV_LOG(INFO, "No interrupt event");
1330 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1331 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1332 ice_handle_aq_msg(dev);
1335 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1336 PMD_DRV_LOG(INFO, "OICR: link state change event");
1337 ret = ice_link_update(dev, 0);
1339 _rte_eth_dev_callback_process
1340 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1344 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1345 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1346 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1347 if (reg & GL_MDET_TX_PQM_VALID_M) {
1348 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1349 GL_MDET_TX_PQM_PF_NUM_S;
1350 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1351 GL_MDET_TX_PQM_MAL_TYPE_S;
1352 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1353 GL_MDET_TX_PQM_QNUM_S;
1355 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1356 "%d by PQM on TX queue %d PF# %d",
1357 event, queue, pf_num);
1360 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1361 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1362 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1363 GL_MDET_TX_TCLAN_PF_NUM_S;
1364 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1365 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1366 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1367 GL_MDET_TX_TCLAN_QNUM_S;
1369 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1370 "%d by TCLAN on TX queue %d PF# %d",
1371 event, queue, pf_num);
1375 /* Enable interrupt */
1376 ice_pf_enable_irq0(hw);
1377 rte_intr_ack(dev->intr_handle);
1381 ice_init_proto_xtr(struct rte_eth_dev *dev)
1383 struct ice_adapter *ad =
1384 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1385 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1386 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1389 if (!ice_proto_xtr_support(hw)) {
1390 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1394 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1395 if (unlikely(pf->proto_xtr == NULL)) {
1396 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1400 for (i = 0; i < pf->lan_nb_qps; i++)
1401 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1402 ad->devargs.proto_xtr[i] :
1403 ad->devargs.proto_xtr_dflt;
1406 /* Initialize SW parameters of PF */
1408 ice_pf_sw_init(struct rte_eth_dev *dev)
1410 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1411 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1414 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1415 hw->func_caps.common_cap.num_rxq);
1417 pf->lan_nb_qps = pf->lan_nb_qp_max;
1419 ice_init_proto_xtr(dev);
1421 if (hw->func_caps.fd_fltr_guar > 0 ||
1422 hw->func_caps.fd_fltr_best_effort > 0) {
1423 pf->flags |= ICE_FLAG_FDIR;
1424 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1425 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1427 pf->fdir_nb_qps = 0;
1429 pf->fdir_qp_offset = 0;
1435 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1437 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1438 struct ice_vsi *vsi = NULL;
1439 struct ice_vsi_ctx vsi_ctx;
1441 struct rte_ether_addr broadcast = {
1442 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1443 struct rte_ether_addr mac_addr;
1444 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1445 uint8_t tc_bitmap = 0x1;
1448 /* hw->num_lports = 1 in NIC mode */
1449 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1453 vsi->idx = pf->next_vsi_idx;
1456 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1457 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1458 vsi->vlan_anti_spoof_on = 0;
1459 vsi->vlan_filter_on = 1;
1460 TAILQ_INIT(&vsi->mac_list);
1461 TAILQ_INIT(&vsi->vlan_list);
1463 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1464 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1465 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1466 hw->func_caps.common_cap.rss_table_size;
1467 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1469 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1472 vsi->nb_qps = pf->lan_nb_qps;
1473 vsi->base_queue = 1;
1474 ice_vsi_config_default_rss(&vsi_ctx.info);
1475 vsi_ctx.alloc_from_pool = true;
1476 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1477 /* switch_id is queried by get_switch_config aq, which is done
1480 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1481 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1482 /* Allow all untagged or tagged packets */
1483 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1484 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1485 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1486 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1489 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1490 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1491 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1492 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1493 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1494 vsi_ctx.info.max_fd_fltr_dedicated =
1495 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1496 vsi_ctx.info.max_fd_fltr_shared =
1497 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1499 /* Enable VLAN/UP trip */
1500 ret = ice_vsi_config_tc_queue_mapping(vsi,
1505 "tc queue mapping with vsi failed, "
1513 vsi->nb_qps = pf->fdir_nb_qps;
1514 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1515 vsi_ctx.alloc_from_pool = true;
1516 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1518 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1519 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1520 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1521 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1522 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1523 ret = ice_vsi_config_tc_queue_mapping(vsi,
1528 "tc queue mapping with vsi failed, "
1535 /* for other types of VSI */
1536 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1540 /* VF has MSIX interrupt in VF range, don't allocate here */
1541 if (type == ICE_VSI_PF) {
1542 ret = ice_res_pool_alloc(&pf->msix_pool,
1543 RTE_MIN(vsi->nb_qps,
1544 RTE_MAX_RXTX_INTR_VEC_ID));
1546 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1549 vsi->msix_intr = ret;
1550 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1551 } else if (type == ICE_VSI_CTRL) {
1552 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1554 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1557 vsi->msix_intr = ret;
1563 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1564 if (ret != ICE_SUCCESS) {
1565 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1568 /* store vsi information is SW structure */
1569 vsi->vsi_id = vsi_ctx.vsi_num;
1570 vsi->info = vsi_ctx.info;
1571 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1572 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1574 if (type == ICE_VSI_PF) {
1575 /* MAC configuration */
1576 rte_memcpy(pf->dev_addr.addr_bytes,
1577 hw->port_info->mac.perm_addr,
1580 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1581 ret = ice_add_mac_filter(vsi, &mac_addr);
1582 if (ret != ICE_SUCCESS)
1583 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1585 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1586 ret = ice_add_mac_filter(vsi, &mac_addr);
1587 if (ret != ICE_SUCCESS)
1588 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1591 /* At the beginning, only TC0. */
1592 /* What we need here is the maximam number of the TX queues.
1593 * Currently vsi->nb_qps means it.
1594 * Correct it if any change.
1596 max_txqs[0] = vsi->nb_qps;
1597 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1598 tc_bitmap, max_txqs);
1599 if (ret != ICE_SUCCESS)
1600 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1610 ice_send_driver_ver(struct ice_hw *hw)
1612 struct ice_driver_ver dv;
1614 /* we don't have driver version use 0 for dummy */
1618 dv.subbuild_ver = 0;
1619 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1621 return ice_aq_send_driver_ver(hw, &dv, NULL);
1625 ice_pf_setup(struct ice_pf *pf)
1627 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1628 struct ice_vsi *vsi;
1631 /* Clear all stats counters */
1632 pf->offset_loaded = FALSE;
1633 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1634 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1635 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1636 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1638 /* force guaranteed filter pool for PF */
1639 ice_alloc_fd_guar_item(hw, &unused,
1640 hw->func_caps.fd_fltr_guar);
1641 /* force shared filter pool for PF */
1642 ice_alloc_fd_shrd_item(hw, &unused,
1643 hw->func_caps.fd_fltr_best_effort);
1645 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1647 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1656 /* PCIe configuration space setting */
1657 #define PCI_CFG_SPACE_SIZE 256
1658 #define PCI_CFG_SPACE_EXP_SIZE 4096
1659 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
1660 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
1661 #define PCI_EXT_CAP_ID_DSN 0x03
1664 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1668 int pos = PCI_CFG_SPACE_SIZE;
1670 /* minimum 8 bytes per capability */
1671 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1673 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1674 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1679 * If we have no capabilities, this is indicated by cap ID,
1680 * cap version and next pointer all being 0.
1686 if (PCI_EXT_CAP_ID(header) == cap)
1689 pos = PCI_EXT_CAP_NEXT(header);
1691 if (pos < PCI_CFG_SPACE_SIZE)
1694 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1695 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1704 * Extract device serial number from PCIe Configuration Space and
1705 * determine the pkg file path according to the DSN.
1708 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1711 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1712 uint32_t dsn_low, dsn_high;
1713 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1715 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1718 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1719 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1720 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1721 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1723 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1727 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1728 ICE_MAX_PKG_FILENAME_SIZE);
1729 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1732 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1733 ICE_MAX_PKG_FILENAME_SIZE);
1734 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1738 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1739 if (!access(pkg_file, 0))
1741 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1745 static enum ice_pkg_type
1746 ice_load_pkg_type(struct ice_hw *hw)
1748 enum ice_pkg_type package_type;
1750 /* store the activated package type (OS default or Comms) */
1751 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1753 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1754 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1756 package_type = ICE_PKG_TYPE_COMMS;
1758 package_type = ICE_PKG_TYPE_UNKNOWN;
1760 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1761 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1762 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1763 hw->active_pkg_name);
1765 return package_type;
1768 static int ice_load_pkg(struct rte_eth_dev *dev)
1770 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1777 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1778 struct ice_adapter *ad =
1779 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1781 ice_pkg_file_search_path(pci_dev, pkg_file);
1783 file = fopen(pkg_file, "rb");
1785 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1789 err = stat(pkg_file, &fstat);
1791 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1796 buf_len = fstat.st_size;
1797 buf = rte_malloc(NULL, buf_len, 0);
1800 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1806 err = fread(buf, buf_len, 1, file);
1808 PMD_INIT_LOG(ERR, "failed to read package data\n");
1816 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1818 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1822 /* store the loaded pkg type info */
1823 ad->active_pkg_type = ice_load_pkg_type(hw);
1825 err = ice_init_hw_tbls(hw);
1827 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1828 goto fail_init_tbls;
1834 rte_free(hw->pkg_copy);
1841 ice_base_queue_get(struct ice_pf *pf)
1844 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1846 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1847 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1848 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1850 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1856 parse_bool(const char *key, const char *value, void *args)
1858 int *i = (int *)args;
1862 num = strtoul(value, &end, 10);
1864 if (num != 0 && num != 1) {
1865 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1866 "value must be 0 or 1",
1875 static int ice_parse_devargs(struct rte_eth_dev *dev)
1877 struct ice_adapter *ad =
1878 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1879 struct rte_devargs *devargs = dev->device->devargs;
1880 struct rte_kvargs *kvlist;
1883 if (devargs == NULL)
1886 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1887 if (kvlist == NULL) {
1888 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1892 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1893 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1894 sizeof(ad->devargs.proto_xtr));
1896 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1897 &handle_proto_xtr_arg, &ad->devargs);
1901 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1902 &parse_bool, &ad->devargs.safe_mode_support);
1906 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1907 &parse_bool, &ad->devargs.pipe_mode_support);
1910 rte_kvargs_free(kvlist);
1914 /* Forward LLDP packets to default VSI by set switch rules */
1916 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1918 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1919 struct ice_fltr_list_entry *s_list_itr = NULL;
1920 struct LIST_HEAD_TYPE list_head;
1923 INIT_LIST_HEAD(&list_head);
1925 s_list_itr = (struct ice_fltr_list_entry *)
1926 ice_malloc(hw, sizeof(*s_list_itr));
1929 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1930 s_list_itr->fltr_info.vsi_handle = vsi->idx;
1931 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1932 RTE_ETHER_TYPE_LLDP;
1933 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1934 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1935 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1936 LIST_ADD(&s_list_itr->list_entry, &list_head);
1938 ret = ice_add_eth_mac(hw, &list_head);
1940 ret = ice_remove_eth_mac(hw, &list_head);
1942 rte_free(s_list_itr);
1946 static enum ice_status
1947 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1948 uint16_t num, uint16_t desc_id,
1949 uint16_t *prof_buf, uint16_t *num_prof)
1951 struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
1954 bool res_shared = 1;
1955 struct ice_aq_desc aq_desc;
1956 struct ice_sq_cd *cd = NULL;
1957 struct ice_aqc_get_allocd_res_desc *cmd =
1958 &aq_desc.params.get_res_desc;
1960 buf_len = sizeof(resp_buf->elem) * num;
1961 resp_buf = ice_malloc(hw, buf_len);
1965 ice_fill_dflt_direct_cmd_desc(&aq_desc,
1966 ice_aqc_opc_get_allocd_res_desc);
1968 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1969 ICE_AQC_RES_TYPE_M) | (res_shared ?
1970 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1971 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1973 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1975 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1979 ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
1980 (*num_prof), ICE_NONDMA_TO_NONDMA);
1987 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1991 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1992 uint16_t first_desc = 1;
1993 uint16_t num_prof = 0;
1995 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1996 first_desc, prof_buf, &num_prof);
1998 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2002 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2003 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2005 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2013 ice_reset_fxp_resource(struct ice_hw *hw)
2017 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2019 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2023 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2025 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2033 ice_dev_init(struct rte_eth_dev *dev)
2035 struct rte_pci_device *pci_dev;
2036 struct rte_intr_handle *intr_handle;
2037 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2038 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2039 struct ice_adapter *ad =
2040 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2041 struct ice_vsi *vsi;
2044 dev->dev_ops = &ice_eth_dev_ops;
2045 dev->rx_pkt_burst = ice_recv_pkts;
2046 dev->tx_pkt_burst = ice_xmit_pkts;
2047 dev->tx_pkt_prepare = ice_prep_pkts;
2049 /* for secondary processes, we don't initialise any further as primary
2050 * has already done this work.
2052 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2053 ice_set_rx_function(dev);
2054 ice_set_tx_function(dev);
2058 ice_set_default_ptype_table(dev);
2059 pci_dev = RTE_DEV_TO_PCI(dev->device);
2060 intr_handle = &pci_dev->intr_handle;
2062 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2063 pf->adapter->eth_dev = dev;
2064 pf->dev_data = dev->data;
2065 hw->back = pf->adapter;
2066 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2067 hw->vendor_id = pci_dev->id.vendor_id;
2068 hw->device_id = pci_dev->id.device_id;
2069 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2070 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2071 hw->bus.device = pci_dev->addr.devid;
2072 hw->bus.func = pci_dev->addr.function;
2074 ret = ice_parse_devargs(dev);
2076 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2080 ice_init_controlq_parameter(hw);
2082 ret = ice_init_hw(hw);
2084 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2088 ret = ice_load_pkg(dev);
2090 if (ad->devargs.safe_mode_support == 0) {
2091 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2092 "Use safe-mode-support=1 to enter Safe Mode");
2096 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2097 "Entering Safe Mode");
2098 ad->is_safe_mode = 1;
2101 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2102 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2103 hw->api_maj_ver, hw->api_min_ver);
2105 ice_pf_sw_init(dev);
2106 ret = ice_init_mac_address(dev);
2108 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2112 /* Pass the information to the rte_eth_dev_close() that it should also
2113 * release the private port resources.
2115 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2117 ret = ice_res_pool_init(&pf->msix_pool, 1,
2118 hw->func_caps.common_cap.num_msix_vectors - 1);
2120 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2121 goto err_msix_pool_init;
2124 ret = ice_pf_setup(pf);
2126 PMD_INIT_LOG(ERR, "Failed to setup PF");
2130 ret = ice_send_driver_ver(hw);
2132 PMD_INIT_LOG(ERR, "Failed to send driver version");
2138 /* Disable double vlan by default */
2139 ice_vsi_config_double_vlan(vsi, FALSE);
2141 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
2142 if (ret != ICE_SUCCESS)
2143 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2144 ret = ice_init_dcb(hw, TRUE);
2145 if (ret != ICE_SUCCESS)
2146 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2147 /* Forward LLDP packets to default VSI */
2148 ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2149 if (ret != ICE_SUCCESS)
2150 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2151 /* register callback func to eal lib */
2152 rte_intr_callback_register(intr_handle,
2153 ice_interrupt_handler, dev);
2155 ice_pf_enable_irq0(hw);
2157 /* enable uio intr after callback register */
2158 rte_intr_enable(intr_handle);
2160 /* get base queue pairs index in the device */
2161 ice_base_queue_get(pf);
2163 ret = ice_flow_init(ad);
2165 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2169 ret = ice_reset_fxp_resource(hw);
2171 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2178 ice_res_pool_destroy(&pf->msix_pool);
2180 rte_free(dev->data->mac_addrs);
2181 dev->data->mac_addrs = NULL;
2183 ice_sched_cleanup_all(hw);
2184 rte_free(hw->port_info);
2185 ice_shutdown_all_ctrlq(hw);
2186 rte_free(pf->proto_xtr);
2192 ice_release_vsi(struct ice_vsi *vsi)
2195 struct ice_vsi_ctx vsi_ctx;
2196 enum ice_status ret;
2201 hw = ICE_VSI_TO_HW(vsi);
2203 ice_remove_all_mac_vlan_filters(vsi);
2205 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2207 vsi_ctx.vsi_num = vsi->vsi_id;
2208 vsi_ctx.info = vsi->info;
2209 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2210 if (ret != ICE_SUCCESS) {
2211 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2221 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2223 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2224 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2225 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2226 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2227 uint16_t msix_intr, i;
2229 /* disable interrupt and also clear all the exist config */
2230 for (i = 0; i < vsi->nb_qps; i++) {
2231 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2232 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2236 if (rte_intr_allow_others(intr_handle))
2238 for (i = 0; i < vsi->nb_msix; i++) {
2239 msix_intr = vsi->msix_intr + i;
2240 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2241 GLINT_DYN_CTL_WB_ON_ITR_M);
2245 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2249 ice_dev_stop(struct rte_eth_dev *dev)
2251 struct rte_eth_dev_data *data = dev->data;
2252 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2253 struct ice_vsi *main_vsi = pf->main_vsi;
2254 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2255 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2258 /* avoid stopping again */
2259 if (pf->adapter_stopped)
2262 /* stop and clear all Rx queues */
2263 for (i = 0; i < data->nb_rx_queues; i++)
2264 ice_rx_queue_stop(dev, i);
2266 /* stop and clear all Tx queues */
2267 for (i = 0; i < data->nb_tx_queues; i++)
2268 ice_tx_queue_stop(dev, i);
2270 /* disable all queue interrupts */
2271 ice_vsi_disable_queues_intr(main_vsi);
2273 if (pf->fdir.fdir_vsi)
2274 ice_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2276 /* Clear all queues and release mbufs */
2277 ice_clear_queues(dev);
2279 ice_dev_set_link_down(dev);
2281 /* Clean datapath event and queue/vec mapping */
2282 rte_intr_efd_disable(intr_handle);
2283 if (intr_handle->intr_vec) {
2284 rte_free(intr_handle->intr_vec);
2285 intr_handle->intr_vec = NULL;
2288 pf->adapter_stopped = true;
2292 ice_dev_close(struct rte_eth_dev *dev)
2294 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2295 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2297 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2298 struct ice_adapter *ad =
2299 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2301 /* Since stop will make link down, then the link event will be
2302 * triggered, disable the irq firstly to avoid the port_infoe etc
2303 * resources deallocation causing the interrupt service thread
2306 ice_pf_disable_irq0(hw);
2310 ice_flow_uninit(ad);
2312 /* release all queue resource */
2313 ice_free_queues(dev);
2315 ice_res_pool_destroy(&pf->msix_pool);
2316 ice_release_vsi(pf->main_vsi);
2317 ice_sched_cleanup_all(hw);
2318 ice_free_hw_tbls(hw);
2319 rte_free(hw->port_info);
2320 hw->port_info = NULL;
2321 ice_shutdown_all_ctrlq(hw);
2322 rte_free(pf->proto_xtr);
2323 pf->proto_xtr = NULL;
2325 dev->dev_ops = NULL;
2326 dev->rx_pkt_burst = NULL;
2327 dev->tx_pkt_burst = NULL;
2329 rte_free(dev->data->mac_addrs);
2330 dev->data->mac_addrs = NULL;
2332 /* disable uio intr before callback unregister */
2333 rte_intr_disable(intr_handle);
2335 /* unregister callback func from eal lib */
2336 rte_intr_callback_unregister(intr_handle,
2337 ice_interrupt_handler, dev);
2341 ice_dev_uninit(struct rte_eth_dev *dev)
2349 ice_dev_configure(struct rte_eth_dev *dev)
2351 struct ice_adapter *ad =
2352 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2354 /* Initialize to TRUE. If any of Rx queues doesn't meet the
2355 * bulk allocation or vector Rx preconditions we will reset it.
2357 ad->rx_bulk_alloc_allowed = true;
2358 ad->tx_simple_allowed = true;
2363 static int ice_init_rss(struct ice_pf *pf)
2365 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2366 struct ice_vsi *vsi = pf->main_vsi;
2367 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2368 struct rte_eth_rss_conf *rss_conf;
2369 struct ice_aqc_get_set_rss_keys key;
2372 bool is_safe_mode = pf->adapter->is_safe_mode;
2375 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2376 nb_q = dev->data->nb_rx_queues;
2377 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2378 vsi->rss_lut_size = pf->hash_lut_size;
2381 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2386 vsi->rss_key = rte_zmalloc(NULL,
2387 vsi->rss_key_size, 0);
2389 vsi->rss_lut = rte_zmalloc(NULL,
2390 vsi->rss_lut_size, 0);
2392 /* configure RSS key */
2393 if (!rss_conf->rss_key) {
2394 /* Calculate the default hash key */
2395 for (i = 0; i <= vsi->rss_key_size; i++)
2396 vsi->rss_key[i] = (uint8_t)rte_rand();
2398 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2399 RTE_MIN(rss_conf->rss_key_len,
2400 vsi->rss_key_size));
2402 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2403 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2407 /* init RSS LUT table */
2408 for (i = 0; i < vsi->rss_lut_size; i++)
2409 vsi->rss_lut[i] = i % nb_q;
2411 ret = ice_aq_set_rss_lut(hw, vsi->idx,
2412 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2413 vsi->rss_lut, vsi->rss_lut_size);
2417 /* Enable registers for symmetric_toeplitz function. */
2418 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2419 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2420 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2421 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2423 /* configure RSS for IPv4 with input set IPv4 src/dst */
2424 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2425 ICE_FLOW_SEG_HDR_IPV4, 0);
2427 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2429 /* configure RSS for IPv6 with input set IPv6 src/dst */
2430 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2431 ICE_FLOW_SEG_HDR_IPV6, 0);
2433 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2435 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2436 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2437 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2439 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2441 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2442 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2443 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2445 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2447 /* configure RSS for sctp6 with input set IPv6 src/dst */
2448 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2449 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2451 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2454 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2455 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2456 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2458 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2460 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2461 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2462 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2464 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2466 /* configure RSS for sctp4 with input set IP src/dst */
2467 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2468 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2470 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2473 /* configure RSS for gtpu with input set TEID */
2474 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2475 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2477 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2481 * configure RSS for pppoe/pppod with input set
2482 * Source MAC and Session ID
2484 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2485 ICE_FLOW_SEG_HDR_PPPOE, 0);
2487 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2494 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2495 int base_queue, int nb_queue)
2497 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2498 uint32_t val, val_tx;
2501 for (i = 0; i < nb_queue; i++) {
2503 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2504 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2505 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2506 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2508 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2509 base_queue + i, msix_vect);
2510 /* set ITR0 value */
2511 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2512 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2513 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2518 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2520 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2521 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2522 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2523 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2524 uint16_t msix_vect = vsi->msix_intr;
2525 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2526 uint16_t queue_idx = 0;
2530 /* clear Rx/Tx queue interrupt */
2531 for (i = 0; i < vsi->nb_used_qps; i++) {
2532 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2533 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2536 /* PF bind interrupt */
2537 if (rte_intr_dp_is_en(intr_handle)) {
2542 for (i = 0; i < vsi->nb_used_qps; i++) {
2544 if (!rte_intr_allow_others(intr_handle))
2545 msix_vect = ICE_MISC_VEC_ID;
2547 /* uio mapping all queue to one msix_vect */
2548 __vsi_queues_bind_intr(vsi, msix_vect,
2549 vsi->base_queue + i,
2550 vsi->nb_used_qps - i);
2552 for (; !!record && i < vsi->nb_used_qps; i++)
2553 intr_handle->intr_vec[queue_idx + i] =
2558 /* vfio 1:1 queue/msix_vect mapping */
2559 __vsi_queues_bind_intr(vsi, msix_vect,
2560 vsi->base_queue + i, 1);
2563 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2571 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2573 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2574 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2575 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2576 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2577 uint16_t msix_intr, i;
2579 if (rte_intr_allow_others(intr_handle))
2580 for (i = 0; i < vsi->nb_used_qps; i++) {
2581 msix_intr = vsi->msix_intr + i;
2582 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2583 GLINT_DYN_CTL_INTENA_M |
2584 GLINT_DYN_CTL_CLEARPBA_M |
2585 GLINT_DYN_CTL_ITR_INDX_M |
2586 GLINT_DYN_CTL_WB_ON_ITR_M);
2589 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2590 GLINT_DYN_CTL_INTENA_M |
2591 GLINT_DYN_CTL_CLEARPBA_M |
2592 GLINT_DYN_CTL_ITR_INDX_M |
2593 GLINT_DYN_CTL_WB_ON_ITR_M);
2597 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2599 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2600 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2601 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2602 struct ice_vsi *vsi = pf->main_vsi;
2603 uint32_t intr_vector = 0;
2605 rte_intr_disable(intr_handle);
2607 /* check and configure queue intr-vector mapping */
2608 if ((rte_intr_cap_multiple(intr_handle) ||
2609 !RTE_ETH_DEV_SRIOV(dev).active) &&
2610 dev->data->dev_conf.intr_conf.rxq != 0) {
2611 intr_vector = dev->data->nb_rx_queues;
2612 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2613 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2614 ICE_MAX_INTR_QUEUE_NUM);
2617 if (rte_intr_efd_enable(intr_handle, intr_vector))
2621 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2622 intr_handle->intr_vec =
2623 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2625 if (!intr_handle->intr_vec) {
2627 "Failed to allocate %d rx_queues intr_vec",
2628 dev->data->nb_rx_queues);
2633 /* Map queues with MSIX interrupt */
2634 vsi->nb_used_qps = dev->data->nb_rx_queues;
2635 ice_vsi_queues_bind_intr(vsi);
2637 /* Enable interrupts for all the queues */
2638 ice_vsi_enable_queues_intr(vsi);
2640 /* Enable FDIR MSIX interrupt */
2641 if (pf->fdir.fdir_vsi) {
2642 ice_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
2643 ice_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2646 rte_intr_enable(intr_handle);
2652 ice_dev_start(struct rte_eth_dev *dev)
2654 struct rte_eth_dev_data *data = dev->data;
2655 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2656 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2657 struct ice_vsi *vsi = pf->main_vsi;
2658 uint16_t nb_rxq = 0;
2660 uint16_t max_frame_size;
2663 /* program Tx queues' context in hardware */
2664 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2665 ret = ice_tx_queue_start(dev, nb_txq);
2667 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2672 /* program Rx queues' context in hardware*/
2673 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2674 ret = ice_rx_queue_start(dev, nb_rxq);
2676 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2681 ret = ice_init_rss(pf);
2683 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2687 ice_set_rx_function(dev);
2688 ice_set_tx_function(dev);
2690 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2691 ETH_VLAN_EXTEND_MASK;
2692 ret = ice_vlan_offload_set(dev, mask);
2694 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2698 /* enable Rx interrput and mapping Rx queue to interrupt vector */
2699 if (ice_rxq_intr_setup(dev))
2702 /* Enable receiving broadcast packets and transmitting packets */
2703 ret = ice_set_vsi_promisc(hw, vsi->idx,
2704 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2705 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2707 if (ret != ICE_SUCCESS)
2708 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2710 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2711 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2712 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2713 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2714 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2715 ICE_AQ_LINK_EVENT_AN_COMPLETED |
2716 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2718 if (ret != ICE_SUCCESS)
2719 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2721 ice_dev_set_link_up(dev);
2723 /* Call get_link_info aq commond to enable/disable LSE */
2724 ice_link_update(dev, 0);
2726 pf->adapter_stopped = false;
2728 /* Set the max frame size to default value*/
2729 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2730 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2733 /* Set the max frame size to HW*/
2734 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2738 /* stop the started queues if failed to start all queues */
2740 for (i = 0; i < nb_rxq; i++)
2741 ice_rx_queue_stop(dev, i);
2743 for (i = 0; i < nb_txq; i++)
2744 ice_tx_queue_stop(dev, i);
2750 ice_dev_reset(struct rte_eth_dev *dev)
2754 if (dev->data->sriov.active)
2757 ret = ice_dev_uninit(dev);
2759 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2763 ret = ice_dev_init(dev);
2765 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2773 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2775 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2776 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2777 struct ice_vsi *vsi = pf->main_vsi;
2778 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2779 bool is_safe_mode = pf->adapter->is_safe_mode;
2783 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2784 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2785 dev_info->max_rx_queues = vsi->nb_qps;
2786 dev_info->max_tx_queues = vsi->nb_qps;
2787 dev_info->max_mac_addrs = vsi->max_macaddrs;
2788 dev_info->max_vfs = pci_dev->max_vfs;
2789 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2790 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2792 dev_info->rx_offload_capa =
2793 DEV_RX_OFFLOAD_VLAN_STRIP |
2794 DEV_RX_OFFLOAD_JUMBO_FRAME |
2795 DEV_RX_OFFLOAD_KEEP_CRC |
2796 DEV_RX_OFFLOAD_SCATTER |
2797 DEV_RX_OFFLOAD_VLAN_FILTER;
2798 dev_info->tx_offload_capa =
2799 DEV_TX_OFFLOAD_VLAN_INSERT |
2800 DEV_TX_OFFLOAD_TCP_TSO |
2801 DEV_TX_OFFLOAD_MULTI_SEGS |
2802 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2803 dev_info->flow_type_rss_offloads = 0;
2805 if (!is_safe_mode) {
2806 dev_info->rx_offload_capa |=
2807 DEV_RX_OFFLOAD_IPV4_CKSUM |
2808 DEV_RX_OFFLOAD_UDP_CKSUM |
2809 DEV_RX_OFFLOAD_TCP_CKSUM |
2810 DEV_RX_OFFLOAD_QINQ_STRIP |
2811 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2812 DEV_RX_OFFLOAD_VLAN_EXTEND;
2813 dev_info->tx_offload_capa |=
2814 DEV_TX_OFFLOAD_QINQ_INSERT |
2815 DEV_TX_OFFLOAD_IPV4_CKSUM |
2816 DEV_TX_OFFLOAD_UDP_CKSUM |
2817 DEV_TX_OFFLOAD_TCP_CKSUM |
2818 DEV_TX_OFFLOAD_SCTP_CKSUM |
2819 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2820 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2821 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2824 dev_info->rx_queue_offload_capa = 0;
2825 dev_info->tx_queue_offload_capa = 0;
2827 dev_info->reta_size = pf->hash_lut_size;
2828 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2830 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2832 .pthresh = ICE_DEFAULT_RX_PTHRESH,
2833 .hthresh = ICE_DEFAULT_RX_HTHRESH,
2834 .wthresh = ICE_DEFAULT_RX_WTHRESH,
2836 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2841 dev_info->default_txconf = (struct rte_eth_txconf) {
2843 .pthresh = ICE_DEFAULT_TX_PTHRESH,
2844 .hthresh = ICE_DEFAULT_TX_HTHRESH,
2845 .wthresh = ICE_DEFAULT_TX_WTHRESH,
2847 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2848 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2852 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2853 .nb_max = ICE_MAX_RING_DESC,
2854 .nb_min = ICE_MIN_RING_DESC,
2855 .nb_align = ICE_ALIGN_RING_DESC,
2858 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2859 .nb_max = ICE_MAX_RING_DESC,
2860 .nb_min = ICE_MIN_RING_DESC,
2861 .nb_align = ICE_ALIGN_RING_DESC,
2864 dev_info->speed_capa = ETH_LINK_SPEED_10M |
2865 ETH_LINK_SPEED_100M |
2867 ETH_LINK_SPEED_2_5G |
2869 ETH_LINK_SPEED_10G |
2870 ETH_LINK_SPEED_20G |
2873 phy_type_low = hw->port_info->phy.phy_type_low;
2874 phy_type_high = hw->port_info->phy.phy_type_high;
2876 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2877 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2879 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2880 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2881 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2883 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2884 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2886 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2887 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2888 dev_info->default_rxportconf.nb_queues = 1;
2889 dev_info->default_txportconf.nb_queues = 1;
2890 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2891 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2897 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2898 struct rte_eth_link *link)
2900 struct rte_eth_link *dst = link;
2901 struct rte_eth_link *src = &dev->data->dev_link;
2903 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2904 *(uint64_t *)src) == 0)
2911 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2912 struct rte_eth_link *link)
2914 struct rte_eth_link *dst = &dev->data->dev_link;
2915 struct rte_eth_link *src = link;
2917 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2918 *(uint64_t *)src) == 0)
2925 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2927 #define CHECK_INTERVAL 100 /* 100ms */
2928 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2929 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2930 struct ice_link_status link_status;
2931 struct rte_eth_link link, old;
2933 unsigned int rep_cnt = MAX_REPEAT_TIME;
2934 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2936 memset(&link, 0, sizeof(link));
2937 memset(&old, 0, sizeof(old));
2938 memset(&link_status, 0, sizeof(link_status));
2939 ice_atomic_read_link_status(dev, &old);
2942 /* Get link status information from hardware */
2943 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2944 &link_status, NULL);
2945 if (status != ICE_SUCCESS) {
2946 link.link_speed = ETH_SPEED_NUM_100M;
2947 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2948 PMD_DRV_LOG(ERR, "Failed to get link info");
2952 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2953 if (!wait_to_complete || link.link_status)
2956 rte_delay_ms(CHECK_INTERVAL);
2957 } while (--rep_cnt);
2959 if (!link.link_status)
2962 /* Full-duplex operation at all supported speeds */
2963 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2965 /* Parse the link status */
2966 switch (link_status.link_speed) {
2967 case ICE_AQ_LINK_SPEED_10MB:
2968 link.link_speed = ETH_SPEED_NUM_10M;
2970 case ICE_AQ_LINK_SPEED_100MB:
2971 link.link_speed = ETH_SPEED_NUM_100M;
2973 case ICE_AQ_LINK_SPEED_1000MB:
2974 link.link_speed = ETH_SPEED_NUM_1G;
2976 case ICE_AQ_LINK_SPEED_2500MB:
2977 link.link_speed = ETH_SPEED_NUM_2_5G;
2979 case ICE_AQ_LINK_SPEED_5GB:
2980 link.link_speed = ETH_SPEED_NUM_5G;
2982 case ICE_AQ_LINK_SPEED_10GB:
2983 link.link_speed = ETH_SPEED_NUM_10G;
2985 case ICE_AQ_LINK_SPEED_20GB:
2986 link.link_speed = ETH_SPEED_NUM_20G;
2988 case ICE_AQ_LINK_SPEED_25GB:
2989 link.link_speed = ETH_SPEED_NUM_25G;
2991 case ICE_AQ_LINK_SPEED_40GB:
2992 link.link_speed = ETH_SPEED_NUM_40G;
2994 case ICE_AQ_LINK_SPEED_50GB:
2995 link.link_speed = ETH_SPEED_NUM_50G;
2997 case ICE_AQ_LINK_SPEED_100GB:
2998 link.link_speed = ETH_SPEED_NUM_100G;
3000 case ICE_AQ_LINK_SPEED_UNKNOWN:
3002 PMD_DRV_LOG(ERR, "Unknown link speed");
3003 link.link_speed = ETH_SPEED_NUM_NONE;
3007 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3008 ETH_LINK_SPEED_FIXED);
3011 ice_atomic_write_link_status(dev, &link);
3012 if (link.link_status == old.link_status)
3018 /* Force the physical link state by getting the current PHY capabilities from
3019 * hardware and setting the PHY config based on the determined capabilities. If
3020 * link changes, link event will be triggered because both the Enable Automatic
3021 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3023 static enum ice_status
3024 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3026 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3027 struct ice_aqc_get_phy_caps_data *pcaps;
3028 struct ice_port_info *pi;
3029 enum ice_status status;
3031 if (!hw || !hw->port_info)
3032 return ICE_ERR_PARAM;
3036 pcaps = (struct ice_aqc_get_phy_caps_data *)
3037 ice_malloc(hw, sizeof(*pcaps));
3039 return ICE_ERR_NO_MEMORY;
3041 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3046 /* No change in link */
3047 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3048 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3051 cfg.phy_type_low = pcaps->phy_type_low;
3052 cfg.phy_type_high = pcaps->phy_type_high;
3053 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3054 cfg.low_power_ctrl = pcaps->low_power_ctrl;
3055 cfg.eee_cap = pcaps->eee_cap;
3056 cfg.eeer_value = pcaps->eeer_value;
3057 cfg.link_fec_opt = pcaps->link_fec_options;
3059 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3061 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3063 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3066 ice_free(hw, pcaps);
3071 ice_dev_set_link_up(struct rte_eth_dev *dev)
3073 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3075 return ice_force_phys_link_state(hw, true);
3079 ice_dev_set_link_down(struct rte_eth_dev *dev)
3081 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3083 return ice_force_phys_link_state(hw, false);
3087 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3089 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3090 struct rte_eth_dev_data *dev_data = pf->dev_data;
3091 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3093 /* check if mtu is within the allowed range */
3094 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3097 /* mtu setting is forbidden if port is start */
3098 if (dev_data->dev_started) {
3100 "port %d must be stopped before configuration",
3105 if (frame_size > RTE_ETHER_MAX_LEN)
3106 dev_data->dev_conf.rxmode.offloads |=
3107 DEV_RX_OFFLOAD_JUMBO_FRAME;
3109 dev_data->dev_conf.rxmode.offloads &=
3110 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3112 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3117 static int ice_macaddr_set(struct rte_eth_dev *dev,
3118 struct rte_ether_addr *mac_addr)
3120 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3121 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3122 struct ice_vsi *vsi = pf->main_vsi;
3123 struct ice_mac_filter *f;
3127 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3128 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3132 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3133 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3138 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3142 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3143 if (ret != ICE_SUCCESS) {
3144 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3147 ret = ice_add_mac_filter(vsi, mac_addr);
3148 if (ret != ICE_SUCCESS) {
3149 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3152 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
3154 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3155 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3156 if (ret != ICE_SUCCESS)
3157 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3162 /* Add a MAC address, and update filters */
3164 ice_macaddr_add(struct rte_eth_dev *dev,
3165 struct rte_ether_addr *mac_addr,
3166 __rte_unused uint32_t index,
3167 __rte_unused uint32_t pool)
3169 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3170 struct ice_vsi *vsi = pf->main_vsi;
3173 ret = ice_add_mac_filter(vsi, mac_addr);
3174 if (ret != ICE_SUCCESS) {
3175 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3182 /* Remove a MAC address, and update filters */
3184 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3186 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3187 struct ice_vsi *vsi = pf->main_vsi;
3188 struct rte_eth_dev_data *data = dev->data;
3189 struct rte_ether_addr *macaddr;
3192 macaddr = &data->mac_addrs[index];
3193 ret = ice_remove_mac_filter(vsi, macaddr);
3195 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3201 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3203 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3204 struct ice_vsi *vsi = pf->main_vsi;
3207 PMD_INIT_FUNC_TRACE();
3210 ret = ice_add_vlan_filter(vsi, vlan_id);
3212 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3216 ret = ice_remove_vlan_filter(vsi, vlan_id);
3218 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3226 /* Configure vlan filter on or off */
3228 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3230 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3231 struct ice_vsi_ctx ctxt;
3232 uint8_t sec_flags, sw_flags2;
3235 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3236 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3237 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3240 vsi->info.sec_flags |= sec_flags;
3241 vsi->info.sw_flags2 |= sw_flags2;
3243 vsi->info.sec_flags &= ~sec_flags;
3244 vsi->info.sw_flags2 &= ~sw_flags2;
3246 vsi->info.sw_id = hw->port_info->sw_id;
3247 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3248 ctxt.info.valid_sections =
3249 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3250 ICE_AQ_VSI_PROP_SECURITY_VALID);
3251 ctxt.vsi_num = vsi->vsi_id;
3253 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3255 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3256 on ? "enable" : "disable");
3259 vsi->info.valid_sections |=
3260 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3261 ICE_AQ_VSI_PROP_SECURITY_VALID);
3264 /* consist with other drivers, allow untagged packet when vlan filter on */
3266 ret = ice_add_vlan_filter(vsi, 0);
3268 ret = ice_remove_vlan_filter(vsi, 0);
3274 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3276 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3277 struct ice_vsi_ctx ctxt;
3281 /* Check if it has been already on or off */
3282 if (vsi->info.valid_sections &
3283 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3285 if ((vsi->info.vlan_flags &
3286 ICE_AQ_VSI_VLAN_EMOD_M) ==
3287 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3288 return 0; /* already on */
3290 if ((vsi->info.vlan_flags &
3291 ICE_AQ_VSI_VLAN_EMOD_M) ==
3292 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3293 return 0; /* already off */
3298 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3300 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3301 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3302 vsi->info.vlan_flags |= vlan_flags;
3303 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3304 ctxt.info.valid_sections =
3305 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3306 ctxt.vsi_num = vsi->vsi_id;
3307 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3309 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3310 on ? "enable" : "disable");
3314 vsi->info.valid_sections |=
3315 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3321 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3323 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3324 struct ice_vsi *vsi = pf->main_vsi;
3325 struct rte_eth_rxmode *rxmode;
3327 rxmode = &dev->data->dev_conf.rxmode;
3328 if (mask & ETH_VLAN_FILTER_MASK) {
3329 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3330 ice_vsi_config_vlan_filter(vsi, TRUE);
3332 ice_vsi_config_vlan_filter(vsi, FALSE);
3335 if (mask & ETH_VLAN_STRIP_MASK) {
3336 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3337 ice_vsi_config_vlan_stripping(vsi, TRUE);
3339 ice_vsi_config_vlan_stripping(vsi, FALSE);
3342 if (mask & ETH_VLAN_EXTEND_MASK) {
3343 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3344 ice_vsi_config_double_vlan(vsi, TRUE);
3346 ice_vsi_config_double_vlan(vsi, FALSE);
3353 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3355 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3356 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3362 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3363 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3364 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3366 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3370 uint64_t *lut_dw = (uint64_t *)lut;
3371 uint16_t i, lut_size_dw = lut_size / 4;
3373 for (i = 0; i < lut_size_dw; i++)
3374 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3381 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3390 pf = ICE_VSI_TO_PF(vsi);
3391 hw = ICE_VSI_TO_HW(vsi);
3393 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3394 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3395 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3397 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3401 uint64_t *lut_dw = (uint64_t *)lut;
3402 uint16_t i, lut_size_dw = lut_size / 4;
3404 for (i = 0; i < lut_size_dw; i++)
3405 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3414 ice_rss_reta_update(struct rte_eth_dev *dev,
3415 struct rte_eth_rss_reta_entry64 *reta_conf,
3418 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3419 uint16_t i, lut_size = pf->hash_lut_size;
3420 uint16_t idx, shift;
3424 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3425 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3426 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3428 "The size of hash lookup table configured (%d)"
3429 "doesn't match the number hardware can "
3430 "supported (128, 512, 2048)",
3435 /* It MUST use the current LUT size to get the RSS lookup table,
3436 * otherwise if will fail with -100 error code.
3438 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
3440 PMD_DRV_LOG(ERR, "No memory can be allocated");
3443 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3447 for (i = 0; i < reta_size; i++) {
3448 idx = i / RTE_RETA_GROUP_SIZE;
3449 shift = i % RTE_RETA_GROUP_SIZE;
3450 if (reta_conf[idx].mask & (1ULL << shift))
3451 lut[i] = reta_conf[idx].reta[shift];
3453 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3454 if (ret == 0 && lut_size != reta_size) {
3456 "The size of hash lookup table is changed from (%d) to (%d)",
3457 lut_size, reta_size);
3458 pf->hash_lut_size = reta_size;
3468 ice_rss_reta_query(struct rte_eth_dev *dev,
3469 struct rte_eth_rss_reta_entry64 *reta_conf,
3472 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3473 uint16_t i, lut_size = pf->hash_lut_size;
3474 uint16_t idx, shift;
3478 if (reta_size != lut_size) {
3480 "The size of hash lookup table configured (%d)"
3481 "doesn't match the number hardware can "
3483 reta_size, lut_size);
3487 lut = rte_zmalloc(NULL, reta_size, 0);
3489 PMD_DRV_LOG(ERR, "No memory can be allocated");
3493 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3497 for (i = 0; i < reta_size; i++) {
3498 idx = i / RTE_RETA_GROUP_SIZE;
3499 shift = i % RTE_RETA_GROUP_SIZE;
3500 if (reta_conf[idx].mask & (1ULL << shift))
3501 reta_conf[idx].reta[shift] = lut[i];
3511 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3513 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3516 if (!key || key_len == 0) {
3517 PMD_DRV_LOG(DEBUG, "No key to be configured");
3519 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3521 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3525 struct ice_aqc_get_set_rss_keys *key_dw =
3526 (struct ice_aqc_get_set_rss_keys *)key;
3528 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3530 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3538 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3540 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3543 if (!key || !key_len)
3546 ret = ice_aq_get_rss_key
3548 (struct ice_aqc_get_set_rss_keys *)key);
3550 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3553 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3559 ice_rss_hash_update(struct rte_eth_dev *dev,
3560 struct rte_eth_rss_conf *rss_conf)
3562 enum ice_status status = ICE_SUCCESS;
3563 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3564 struct ice_vsi *vsi = pf->main_vsi;
3567 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3571 /* TODO: hash enable config, ice_add_rss_cfg */
3576 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3577 struct rte_eth_rss_conf *rss_conf)
3579 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3580 struct ice_vsi *vsi = pf->main_vsi;
3582 ice_get_rss_key(vsi, rss_conf->rss_key,
3583 &rss_conf->rss_key_len);
3585 /* TODO: default set to 0 as hf config is not supported now */
3586 rss_conf->rss_hf = 0;
3591 ice_promisc_enable(struct rte_eth_dev *dev)
3593 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3594 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3595 struct ice_vsi *vsi = pf->main_vsi;
3596 enum ice_status status;
3600 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3601 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3603 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3605 case ICE_ERR_ALREADY_EXISTS:
3606 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3610 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3618 ice_promisc_disable(struct rte_eth_dev *dev)
3620 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3621 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3622 struct ice_vsi *vsi = pf->main_vsi;
3623 enum ice_status status;
3627 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3628 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3630 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3631 if (status != ICE_SUCCESS) {
3632 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3640 ice_allmulti_enable(struct rte_eth_dev *dev)
3642 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3643 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3644 struct ice_vsi *vsi = pf->main_vsi;
3645 enum ice_status status;
3649 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3651 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3654 case ICE_ERR_ALREADY_EXISTS:
3655 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3659 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3667 ice_allmulti_disable(struct rte_eth_dev *dev)
3669 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3670 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3671 struct ice_vsi *vsi = pf->main_vsi;
3672 enum ice_status status;
3676 if (dev->data->promiscuous == 1)
3677 return 0; /* must remain in all_multicast mode */
3679 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3681 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3682 if (status != ICE_SUCCESS) {
3683 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3690 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3693 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3694 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3695 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3699 msix_intr = intr_handle->intr_vec[queue_id];
3701 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3702 GLINT_DYN_CTL_ITR_INDX_M;
3703 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3705 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3706 rte_intr_ack(&pci_dev->intr_handle);
3711 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3714 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3715 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3716 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3719 msix_intr = intr_handle->intr_vec[queue_id];
3721 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3727 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3729 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3735 full_ver = hw->nvm.oem_ver;
3736 ver = (u8)(full_ver >> 24);
3737 build = (u16)((full_ver >> 8) & 0xffff);
3738 patch = (u8)(full_ver & 0xff);
3740 ret = snprintf(fw_version, fw_size,
3741 "%d.%d%d 0x%08x %d.%d.%d",
3742 ((hw->nvm.ver >> 12) & 0xf),
3743 ((hw->nvm.ver >> 4) & 0xff),
3744 (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3747 /* add the size of '\0' */
3749 if (fw_size < (u32)ret)
3756 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3759 struct ice_vsi_ctx ctxt;
3760 uint8_t vlan_flags = 0;
3763 if (!vsi || !info) {
3764 PMD_DRV_LOG(ERR, "invalid parameters");
3769 vsi->info.pvid = info->config.pvid;
3771 * If insert pvid is enabled, only tagged pkts are
3772 * allowed to be sent out.
3774 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3775 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3778 if (info->config.reject.tagged == 0)
3779 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3781 if (info->config.reject.untagged == 0)
3782 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3784 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3785 ICE_AQ_VSI_VLAN_MODE_M);
3786 vsi->info.vlan_flags |= vlan_flags;
3787 memset(&ctxt, 0, sizeof(ctxt));
3788 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3789 ctxt.info.valid_sections =
3790 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3791 ctxt.vsi_num = vsi->vsi_id;
3793 hw = ICE_VSI_TO_HW(vsi);
3794 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3795 if (ret != ICE_SUCCESS) {
3797 "update VSI for VLAN insert failed, err %d",
3802 vsi->info.valid_sections |=
3803 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3809 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3811 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3812 struct ice_vsi *vsi = pf->main_vsi;
3813 struct rte_eth_dev_data *data = pf->dev_data;
3814 struct ice_vsi_vlan_pvid_info info;
3817 memset(&info, 0, sizeof(info));
3820 info.config.pvid = pvid;
3822 info.config.reject.tagged =
3823 data->dev_conf.txmode.hw_vlan_reject_tagged;
3824 info.config.reject.untagged =
3825 data->dev_conf.txmode.hw_vlan_reject_untagged;
3828 ret = ice_vsi_vlan_pvid_set(vsi, &info);
3830 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3838 ice_get_eeprom_length(struct rte_eth_dev *dev)
3840 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3842 /* Convert word count to byte count */
3843 return hw->nvm.sr_words << 1;
3847 ice_get_eeprom(struct rte_eth_dev *dev,
3848 struct rte_dev_eeprom_info *eeprom)
3850 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3851 uint16_t *data = eeprom->data;
3852 uint16_t first_word, last_word, nwords;
3853 enum ice_status status = ICE_SUCCESS;
3855 first_word = eeprom->offset >> 1;
3856 last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3857 nwords = last_word - first_word + 1;
3859 if (first_word >= hw->nvm.sr_words ||
3860 last_word >= hw->nvm.sr_words) {
3861 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3865 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3867 status = ice_read_sr_buf(hw, first_word, &nwords, data);
3869 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3870 eeprom->length = sizeof(uint16_t) * nwords;
3878 ice_stat_update_32(struct ice_hw *hw,
3886 new_data = (uint64_t)ICE_READ_REG(hw, reg);
3890 if (new_data >= *offset)
3891 *stat = (uint64_t)(new_data - *offset);
3893 *stat = (uint64_t)((new_data +
3894 ((uint64_t)1 << ICE_32_BIT_WIDTH))
3899 ice_stat_update_40(struct ice_hw *hw,
3908 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3909 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3915 if (new_data >= *offset)
3916 *stat = new_data - *offset;
3918 *stat = (uint64_t)((new_data +
3919 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3922 *stat &= ICE_40_BIT_MASK;
3925 /* Get all the statistics of a VSI */
3927 ice_update_vsi_stats(struct ice_vsi *vsi)
3929 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3930 struct ice_eth_stats *nes = &vsi->eth_stats;
3931 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3932 int idx = rte_le_to_cpu_16(vsi->vsi_id);
3934 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3935 vsi->offset_loaded, &oes->rx_bytes,
3937 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3938 vsi->offset_loaded, &oes->rx_unicast,
3940 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3941 vsi->offset_loaded, &oes->rx_multicast,
3942 &nes->rx_multicast);
3943 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3944 vsi->offset_loaded, &oes->rx_broadcast,
3945 &nes->rx_broadcast);
3946 /* exclude CRC bytes */
3947 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3948 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3950 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3951 &oes->rx_discards, &nes->rx_discards);
3952 /* GLV_REPC not supported */
3953 /* GLV_RMPC not supported */
3954 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3955 &oes->rx_unknown_protocol,
3956 &nes->rx_unknown_protocol);
3957 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3958 vsi->offset_loaded, &oes->tx_bytes,
3960 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3961 vsi->offset_loaded, &oes->tx_unicast,
3963 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3964 vsi->offset_loaded, &oes->tx_multicast,
3965 &nes->tx_multicast);
3966 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3967 vsi->offset_loaded, &oes->tx_broadcast,
3968 &nes->tx_broadcast);
3969 /* GLV_TDPC not supported */
3970 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3971 &oes->tx_errors, &nes->tx_errors);
3972 vsi->offset_loaded = true;
3974 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3976 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3977 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3978 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3979 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3980 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3981 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3982 nes->rx_unknown_protocol);
3983 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3984 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3985 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3986 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3987 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3988 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3989 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3994 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3996 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3997 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3999 /* Get statistics of struct ice_eth_stats */
4000 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4001 GLPRT_GORCL(hw->port_info->lport),
4002 pf->offset_loaded, &os->eth.rx_bytes,
4004 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4005 GLPRT_UPRCL(hw->port_info->lport),
4006 pf->offset_loaded, &os->eth.rx_unicast,
4007 &ns->eth.rx_unicast);
4008 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4009 GLPRT_MPRCL(hw->port_info->lport),
4010 pf->offset_loaded, &os->eth.rx_multicast,
4011 &ns->eth.rx_multicast);
4012 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4013 GLPRT_BPRCL(hw->port_info->lport),
4014 pf->offset_loaded, &os->eth.rx_broadcast,
4015 &ns->eth.rx_broadcast);
4016 ice_stat_update_32(hw, PRTRPB_RDPC,
4017 pf->offset_loaded, &os->eth.rx_discards,
4018 &ns->eth.rx_discards);
4020 /* Workaround: CRC size should not be included in byte statistics,
4021 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4024 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4025 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4027 /* GLPRT_REPC not supported */
4028 /* GLPRT_RMPC not supported */
4029 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4031 &os->eth.rx_unknown_protocol,
4032 &ns->eth.rx_unknown_protocol);
4033 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4034 GLPRT_GOTCL(hw->port_info->lport),
4035 pf->offset_loaded, &os->eth.tx_bytes,
4037 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4038 GLPRT_UPTCL(hw->port_info->lport),
4039 pf->offset_loaded, &os->eth.tx_unicast,
4040 &ns->eth.tx_unicast);
4041 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4042 GLPRT_MPTCL(hw->port_info->lport),
4043 pf->offset_loaded, &os->eth.tx_multicast,
4044 &ns->eth.tx_multicast);
4045 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4046 GLPRT_BPTCL(hw->port_info->lport),
4047 pf->offset_loaded, &os->eth.tx_broadcast,
4048 &ns->eth.tx_broadcast);
4049 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4050 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4052 /* GLPRT_TEPC not supported */
4054 /* additional port specific stats */
4055 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4056 pf->offset_loaded, &os->tx_dropped_link_down,
4057 &ns->tx_dropped_link_down);
4058 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4059 pf->offset_loaded, &os->crc_errors,
4061 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4062 pf->offset_loaded, &os->illegal_bytes,
4063 &ns->illegal_bytes);
4064 /* GLPRT_ERRBC not supported */
4065 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4066 pf->offset_loaded, &os->mac_local_faults,
4067 &ns->mac_local_faults);
4068 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4069 pf->offset_loaded, &os->mac_remote_faults,
4070 &ns->mac_remote_faults);
4072 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4073 pf->offset_loaded, &os->rx_len_errors,
4074 &ns->rx_len_errors);
4076 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4077 pf->offset_loaded, &os->link_xon_rx,
4079 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4080 pf->offset_loaded, &os->link_xoff_rx,
4082 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4083 pf->offset_loaded, &os->link_xon_tx,
4085 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4086 pf->offset_loaded, &os->link_xoff_tx,
4088 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4089 GLPRT_PRC64L(hw->port_info->lport),
4090 pf->offset_loaded, &os->rx_size_64,
4092 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4093 GLPRT_PRC127L(hw->port_info->lport),
4094 pf->offset_loaded, &os->rx_size_127,
4096 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4097 GLPRT_PRC255L(hw->port_info->lport),
4098 pf->offset_loaded, &os->rx_size_255,
4100 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4101 GLPRT_PRC511L(hw->port_info->lport),
4102 pf->offset_loaded, &os->rx_size_511,
4104 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4105 GLPRT_PRC1023L(hw->port_info->lport),
4106 pf->offset_loaded, &os->rx_size_1023,
4108 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4109 GLPRT_PRC1522L(hw->port_info->lport),
4110 pf->offset_loaded, &os->rx_size_1522,
4112 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4113 GLPRT_PRC9522L(hw->port_info->lport),
4114 pf->offset_loaded, &os->rx_size_big,
4116 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4117 pf->offset_loaded, &os->rx_undersize,
4119 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4120 pf->offset_loaded, &os->rx_fragments,
4122 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4123 pf->offset_loaded, &os->rx_oversize,
4125 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4126 pf->offset_loaded, &os->rx_jabber,
4128 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4129 GLPRT_PTC64L(hw->port_info->lport),
4130 pf->offset_loaded, &os->tx_size_64,
4132 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4133 GLPRT_PTC127L(hw->port_info->lport),
4134 pf->offset_loaded, &os->tx_size_127,
4136 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4137 GLPRT_PTC255L(hw->port_info->lport),
4138 pf->offset_loaded, &os->tx_size_255,
4140 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4141 GLPRT_PTC511L(hw->port_info->lport),
4142 pf->offset_loaded, &os->tx_size_511,
4144 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4145 GLPRT_PTC1023L(hw->port_info->lport),
4146 pf->offset_loaded, &os->tx_size_1023,
4148 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4149 GLPRT_PTC1522L(hw->port_info->lport),
4150 pf->offset_loaded, &os->tx_size_1522,
4152 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4153 GLPRT_PTC9522L(hw->port_info->lport),
4154 pf->offset_loaded, &os->tx_size_big,
4157 /* GLPRT_MSPDC not supported */
4158 /* GLPRT_XEC not supported */
4160 pf->offset_loaded = true;
4163 ice_update_vsi_stats(pf->main_vsi);
4166 /* Get all statistics of a port */
4168 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4170 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4171 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4172 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4174 /* call read registers - updates values, now write them to struct */
4175 ice_read_stats_registers(pf, hw);
4177 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4178 pf->main_vsi->eth_stats.rx_multicast +
4179 pf->main_vsi->eth_stats.rx_broadcast -
4180 pf->main_vsi->eth_stats.rx_discards;
4181 stats->opackets = ns->eth.tx_unicast +
4182 ns->eth.tx_multicast +
4183 ns->eth.tx_broadcast;
4184 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
4185 stats->obytes = ns->eth.tx_bytes;
4186 stats->oerrors = ns->eth.tx_errors +
4187 pf->main_vsi->eth_stats.tx_errors;
4190 stats->imissed = ns->eth.rx_discards +
4191 pf->main_vsi->eth_stats.rx_discards;
4192 stats->ierrors = ns->crc_errors +
4194 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4196 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4197 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
4198 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4199 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4200 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4201 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4202 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4203 pf->main_vsi->eth_stats.rx_discards);
4204 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4205 ns->eth.rx_unknown_protocol);
4206 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
4207 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4208 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4209 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4210 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4211 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4212 pf->main_vsi->eth_stats.tx_discards);
4213 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
4215 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
4216 ns->tx_dropped_link_down);
4217 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4218 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
4220 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
4221 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
4222 ns->mac_local_faults);
4223 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
4224 ns->mac_remote_faults);
4225 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
4226 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
4227 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
4228 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
4229 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
4230 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
4231 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
4232 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
4233 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
4234 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
4235 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
4236 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
4237 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
4238 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
4239 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
4240 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
4241 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
4242 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
4243 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
4244 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
4245 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
4246 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
4247 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
4248 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4252 /* Reset the statistics */
4254 ice_stats_reset(struct rte_eth_dev *dev)
4256 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4257 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4259 /* Mark PF and VSI stats to update the offset, aka "reset" */
4260 pf->offset_loaded = false;
4262 pf->main_vsi->offset_loaded = false;
4264 /* read the stats, reading current register values into offset */
4265 ice_read_stats_registers(pf, hw);
4271 ice_xstats_calc_num(void)
4275 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4281 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4284 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4285 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4288 struct ice_hw_port_stats *hw_stats = &pf->stats;
4290 count = ice_xstats_calc_num();
4294 ice_read_stats_registers(pf, hw);
4301 /* Get stats from ice_eth_stats struct */
4302 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4303 xstats[count].value =
4304 *(uint64_t *)((char *)&hw_stats->eth +
4305 ice_stats_strings[i].offset);
4306 xstats[count].id = count;
4310 /* Get individiual stats from ice_hw_port struct */
4311 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4312 xstats[count].value =
4313 *(uint64_t *)((char *)hw_stats +
4314 ice_hw_port_strings[i].offset);
4315 xstats[count].id = count;
4322 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4323 struct rte_eth_xstat_name *xstats_names,
4324 __rte_unused unsigned int limit)
4326 unsigned int count = 0;
4330 return ice_xstats_calc_num();
4332 /* Note: limit checked in rte_eth_xstats_names() */
4334 /* Get stats from ice_eth_stats struct */
4335 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4336 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4337 sizeof(xstats_names[count].name));
4341 /* Get individiual stats from ice_hw_port struct */
4342 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4343 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4344 sizeof(xstats_names[count].name));
4352 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4353 enum rte_filter_type filter_type,
4354 enum rte_filter_op filter_op,
4362 switch (filter_type) {
4363 case RTE_ETH_FILTER_GENERIC:
4364 if (filter_op != RTE_ETH_FILTER_GET)
4366 *(const void **)arg = &ice_flow_ops;
4369 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4378 /* Add UDP tunneling port */
4380 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4381 struct rte_eth_udp_tunnel *udp_tunnel)
4384 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4386 if (udp_tunnel == NULL)
4389 switch (udp_tunnel->prot_type) {
4390 case RTE_TUNNEL_TYPE_VXLAN:
4391 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4394 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4402 /* Delete UDP tunneling port */
4404 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4405 struct rte_eth_udp_tunnel *udp_tunnel)
4408 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4410 if (udp_tunnel == NULL)
4413 switch (udp_tunnel->prot_type) {
4414 case RTE_TUNNEL_TYPE_VXLAN:
4415 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4418 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4427 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4428 struct rte_pci_device *pci_dev)
4430 return rte_eth_dev_pci_generic_probe(pci_dev,
4431 sizeof(struct ice_adapter),
4436 ice_pci_remove(struct rte_pci_device *pci_dev)
4438 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4441 static struct rte_pci_driver rte_ice_pmd = {
4442 .id_table = pci_id_ice_map,
4443 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4444 .probe = ice_pci_probe,
4445 .remove = ice_pci_remove,
4449 * Driver initialization routine.
4450 * Invoked once at EAL init time.
4451 * Register itself as the [Poll Mode] Driver of PCI devices.
4453 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4454 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4455 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4456 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4457 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4458 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4459 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
4461 RTE_INIT(ice_init_log)
4463 ice_logtype_init = rte_log_register("pmd.net.ice.init");
4464 if (ice_logtype_init >= 0)
4465 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4466 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4467 if (ice_logtype_driver >= 0)
4468 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4470 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4471 ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4472 if (ice_logtype_rx >= 0)
4473 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4476 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4477 ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4478 if (ice_logtype_tx >= 0)
4479 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4482 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4483 ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4484 if (ice_logtype_tx_free >= 0)
4485 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);