1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <ethdev_pci.h>
13 #include <rte_tailq.h>
15 #include "eal_firmware.h"
17 #include "base/ice_sched.h"
18 #include "base/ice_flow.h"
19 #include "base/ice_dcb.h"
20 #include "base/ice_common.h"
21 #include "base/ice_ptp_hw.h"
23 #include "rte_pmd_ice.h"
24 #include "ice_ethdev.h"
26 #include "ice_generic_flow.h"
29 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
30 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
31 #define ICE_PROTO_XTR_ARG "proto_xtr"
32 #define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask"
33 #define ICE_ONE_PPS_OUT_ARG "pps_out"
34 #define ICE_RX_LOW_LATENCY_ARG "rx_low_latency"
36 #define ICE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
38 uint64_t ice_timestamp_dynflag;
39 int ice_timestamp_dynfield_offset = -1;
41 static const char * const ice_valid_args[] = {
42 ICE_SAFE_MODE_SUPPORT_ARG,
43 ICE_PIPELINE_MODE_SUPPORT_ARG,
45 ICE_HW_DEBUG_MASK_ARG,
47 ICE_RX_LOW_LATENCY_ARG,
51 #define PPS_OUT_DELAY_NS 1
53 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
54 .name = "intel_pmd_dynfield_proto_xtr_metadata",
55 .size = sizeof(uint32_t),
56 .align = __alignof__(uint32_t),
60 struct proto_xtr_ol_flag {
61 const struct rte_mbuf_dynflag param;
66 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
68 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
70 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
71 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
73 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
74 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
76 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
77 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
78 [PROTO_XTR_IPV6_FLOW] = {
79 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
80 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
82 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
83 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
84 [PROTO_XTR_IP_OFFSET] = {
85 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
86 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
89 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
90 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
91 #define ICE_MAX_RES_DESC_NUM 1024
93 static int ice_dev_configure(struct rte_eth_dev *dev);
94 static int ice_dev_start(struct rte_eth_dev *dev);
95 static int ice_dev_stop(struct rte_eth_dev *dev);
96 static int ice_dev_close(struct rte_eth_dev *dev);
97 static int ice_dev_reset(struct rte_eth_dev *dev);
98 static int ice_dev_info_get(struct rte_eth_dev *dev,
99 struct rte_eth_dev_info *dev_info);
100 static int ice_link_update(struct rte_eth_dev *dev,
101 int wait_to_complete);
102 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
103 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
105 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
106 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
107 static int ice_rss_reta_update(struct rte_eth_dev *dev,
108 struct rte_eth_rss_reta_entry64 *reta_conf,
110 static int ice_rss_reta_query(struct rte_eth_dev *dev,
111 struct rte_eth_rss_reta_entry64 *reta_conf,
113 static int ice_rss_hash_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_conf *rss_conf);
115 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
116 struct rte_eth_rss_conf *rss_conf);
117 static int ice_promisc_enable(struct rte_eth_dev *dev);
118 static int ice_promisc_disable(struct rte_eth_dev *dev);
119 static int ice_allmulti_enable(struct rte_eth_dev *dev);
120 static int ice_allmulti_disable(struct rte_eth_dev *dev);
121 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
124 static int ice_macaddr_set(struct rte_eth_dev *dev,
125 struct rte_ether_addr *mac_addr);
126 static int ice_macaddr_add(struct rte_eth_dev *dev,
127 struct rte_ether_addr *mac_addr,
128 __rte_unused uint32_t index,
130 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
131 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
133 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
135 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
137 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
138 uint16_t pvid, int on);
139 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
140 static int ice_get_eeprom(struct rte_eth_dev *dev,
141 struct rte_dev_eeprom_info *eeprom);
142 static int ice_stats_get(struct rte_eth_dev *dev,
143 struct rte_eth_stats *stats);
144 static int ice_stats_reset(struct rte_eth_dev *dev);
145 static int ice_xstats_get(struct rte_eth_dev *dev,
146 struct rte_eth_xstat *xstats, unsigned int n);
147 static int ice_xstats_get_names(struct rte_eth_dev *dev,
148 struct rte_eth_xstat_name *xstats_names,
150 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev,
151 const struct rte_flow_ops **ops);
152 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
153 struct rte_eth_udp_tunnel *udp_tunnel);
154 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
155 struct rte_eth_udp_tunnel *udp_tunnel);
156 static int ice_timesync_enable(struct rte_eth_dev *dev);
157 static int ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
158 struct timespec *timestamp,
160 static int ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
161 struct timespec *timestamp);
162 static int ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
163 static int ice_timesync_read_time(struct rte_eth_dev *dev,
164 struct timespec *timestamp);
165 static int ice_timesync_write_time(struct rte_eth_dev *dev,
166 const struct timespec *timestamp);
167 static int ice_timesync_disable(struct rte_eth_dev *dev);
169 static const struct rte_pci_id pci_id_ice_map[] = {
170 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
171 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
172 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
173 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
174 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
175 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
176 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
177 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
178 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
179 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
180 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
181 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
182 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
183 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
184 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
185 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
186 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
187 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
188 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
189 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
190 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
191 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
192 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
193 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
194 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
195 { .vendor_id = 0, /* sentinel */ },
198 static const struct eth_dev_ops ice_eth_dev_ops = {
199 .dev_configure = ice_dev_configure,
200 .dev_start = ice_dev_start,
201 .dev_stop = ice_dev_stop,
202 .dev_close = ice_dev_close,
203 .dev_reset = ice_dev_reset,
204 .dev_set_link_up = ice_dev_set_link_up,
205 .dev_set_link_down = ice_dev_set_link_down,
206 .rx_queue_start = ice_rx_queue_start,
207 .rx_queue_stop = ice_rx_queue_stop,
208 .tx_queue_start = ice_tx_queue_start,
209 .tx_queue_stop = ice_tx_queue_stop,
210 .rx_queue_setup = ice_rx_queue_setup,
211 .rx_queue_release = ice_dev_rx_queue_release,
212 .tx_queue_setup = ice_tx_queue_setup,
213 .tx_queue_release = ice_dev_tx_queue_release,
214 .dev_infos_get = ice_dev_info_get,
215 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
216 .link_update = ice_link_update,
217 .mtu_set = ice_mtu_set,
218 .mac_addr_set = ice_macaddr_set,
219 .mac_addr_add = ice_macaddr_add,
220 .mac_addr_remove = ice_macaddr_remove,
221 .vlan_filter_set = ice_vlan_filter_set,
222 .vlan_offload_set = ice_vlan_offload_set,
223 .reta_update = ice_rss_reta_update,
224 .reta_query = ice_rss_reta_query,
225 .rss_hash_update = ice_rss_hash_update,
226 .rss_hash_conf_get = ice_rss_hash_conf_get,
227 .promiscuous_enable = ice_promisc_enable,
228 .promiscuous_disable = ice_promisc_disable,
229 .allmulticast_enable = ice_allmulti_enable,
230 .allmulticast_disable = ice_allmulti_disable,
231 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
232 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
233 .fw_version_get = ice_fw_version_get,
234 .vlan_pvid_set = ice_vlan_pvid_set,
235 .rxq_info_get = ice_rxq_info_get,
236 .txq_info_get = ice_txq_info_get,
237 .rx_burst_mode_get = ice_rx_burst_mode_get,
238 .tx_burst_mode_get = ice_tx_burst_mode_get,
239 .get_eeprom_length = ice_get_eeprom_length,
240 .get_eeprom = ice_get_eeprom,
241 .stats_get = ice_stats_get,
242 .stats_reset = ice_stats_reset,
243 .xstats_get = ice_xstats_get,
244 .xstats_get_names = ice_xstats_get_names,
245 .xstats_reset = ice_stats_reset,
246 .flow_ops_get = ice_dev_flow_ops_get,
247 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
248 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
249 .tx_done_cleanup = ice_tx_done_cleanup,
250 .get_monitor_addr = ice_get_monitor_addr,
251 .timesync_enable = ice_timesync_enable,
252 .timesync_read_rx_timestamp = ice_timesync_read_rx_timestamp,
253 .timesync_read_tx_timestamp = ice_timesync_read_tx_timestamp,
254 .timesync_adjust_time = ice_timesync_adjust_time,
255 .timesync_read_time = ice_timesync_read_time,
256 .timesync_write_time = ice_timesync_write_time,
257 .timesync_disable = ice_timesync_disable,
260 /* store statistics names and its offset in stats structure */
261 struct ice_xstats_name_off {
262 char name[RTE_ETH_XSTATS_NAME_SIZE];
266 static const struct ice_xstats_name_off ice_stats_strings[] = {
267 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
268 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
269 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
270 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
271 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
272 rx_unknown_protocol)},
273 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
274 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
275 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
276 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
279 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
280 sizeof(ice_stats_strings[0]))
282 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
283 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
284 tx_dropped_link_down)},
285 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
286 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
288 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
289 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
291 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
293 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
295 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
296 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
297 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
298 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
299 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
300 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
302 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
304 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
306 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
308 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
310 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
312 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
314 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
316 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
317 mac_short_pkt_dropped)},
318 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
320 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
321 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
322 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
324 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
326 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
328 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
330 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
332 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
336 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
337 sizeof(ice_hw_port_strings[0]))
340 ice_init_controlq_parameter(struct ice_hw *hw)
342 /* fields for adminq */
343 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
344 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
345 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
346 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
348 /* fields for mailboxq, DPDK used as PF host */
349 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
350 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
351 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
352 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
356 lookup_proto_xtr_type(const char *xtr_name)
360 enum proto_xtr_type type;
362 { "vlan", PROTO_XTR_VLAN },
363 { "ipv4", PROTO_XTR_IPV4 },
364 { "ipv6", PROTO_XTR_IPV6 },
365 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
366 { "tcp", PROTO_XTR_TCP },
367 { "ip_offset", PROTO_XTR_IP_OFFSET },
371 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
372 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
373 return xtr_type_map[i].type;
380 * Parse elem, the elem could be single number/range or '(' ')' group
381 * 1) A single number elem, it's just a simple digit. e.g. 9
382 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
383 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
384 * Within group elem, '-' used for a range separator;
385 * ',' used for a single number.
388 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
390 const char *str = input;
395 while (isblank(*str))
398 if (!isdigit(*str) && *str != '(')
401 /* process single number or single range of number */
404 idx = strtoul(str, &end, 10);
405 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
408 while (isblank(*end))
414 /* process single <number>-<number> */
417 while (isblank(*end))
423 idx = strtoul(end, &end, 10);
424 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
428 while (isblank(*end))
435 for (idx = RTE_MIN(min, max);
436 idx <= RTE_MAX(min, max); idx++)
437 devargs->proto_xtr[idx] = xtr_type;
442 /* process set within bracket */
444 while (isblank(*str))
449 min = ICE_MAX_QUEUE_NUM;
451 /* go ahead to the first digit */
452 while (isblank(*str))
457 /* get the digit value */
459 idx = strtoul(str, &end, 10);
460 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
463 /* go ahead to separator '-',',' and ')' */
464 while (isblank(*end))
467 if (min == ICE_MAX_QUEUE_NUM)
469 else /* avoid continuous '-' */
471 } else if (*end == ',' || *end == ')') {
473 if (min == ICE_MAX_QUEUE_NUM)
476 for (idx = RTE_MIN(min, max);
477 idx <= RTE_MAX(min, max); idx++)
478 devargs->proto_xtr[idx] = xtr_type;
480 min = ICE_MAX_QUEUE_NUM;
486 } while (*end != ')' && *end != '\0');
492 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
494 const char *queue_start;
499 while (isblank(*queues))
502 if (*queues != '[') {
503 xtr_type = lookup_proto_xtr_type(queues);
507 devargs->proto_xtr_dflt = xtr_type;
514 while (isblank(*queues))
519 queue_start = queues;
521 /* go across a complete bracket */
522 if (*queue_start == '(') {
523 queues += strcspn(queues, ")");
528 /* scan the separator ':' */
529 queues += strcspn(queues, ":");
530 if (*queues++ != ':')
532 while (isblank(*queues))
535 for (idx = 0; ; idx++) {
536 if (isblank(queues[idx]) ||
537 queues[idx] == ',' ||
538 queues[idx] == ']' ||
542 if (idx > sizeof(xtr_name) - 2)
545 xtr_name[idx] = queues[idx];
547 xtr_name[idx] = '\0';
548 xtr_type = lookup_proto_xtr_type(xtr_name);
554 while (isblank(*queues) || *queues == ',' || *queues == ']')
557 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
559 } while (*queues != '\0');
565 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
568 struct ice_devargs *devargs = extra_args;
570 if (value == NULL || extra_args == NULL)
573 if (parse_queue_proto_xtr(value, devargs) < 0) {
575 "The protocol extraction parameter is wrong : '%s'",
584 ice_check_proto_xtr_support(struct ice_hw *hw)
586 #define FLX_REG(val, fld, idx) \
587 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
588 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
595 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
597 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
598 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
600 ICE_PROT_IPV4_OF_OR_S,
601 ICE_PROT_IPV4_OF_OR_S },
602 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
604 ICE_PROT_IPV6_OF_OR_S,
605 ICE_PROT_IPV6_OF_OR_S },
606 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
608 ICE_PROT_IPV6_OF_OR_S,
609 ICE_PROT_IPV6_OF_OR_S },
610 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
612 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
613 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
615 ICE_PROT_IPV4_OF_OR_S,
616 ICE_PROT_IPV6_OF_OR_S },
620 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
621 uint32_t rxdid = xtr_sets[i].rxdid;
624 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
625 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
627 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
628 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
629 ice_proto_xtr_hw_support[i] = true;
632 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
633 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
635 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
636 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
637 ice_proto_xtr_hw_support[i] = true;
643 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
646 struct pool_entry *entry;
651 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
654 "Failed to allocate memory for resource pool");
658 /* queue heap initialize */
659 pool->num_free = num;
662 LIST_INIT(&pool->alloc_list);
663 LIST_INIT(&pool->free_list);
665 /* Initialize element */
669 LIST_INSERT_HEAD(&pool->free_list, entry, next);
674 ice_res_pool_alloc(struct ice_res_pool_info *pool,
677 struct pool_entry *entry, *valid_entry;
680 PMD_INIT_LOG(ERR, "Invalid parameter");
684 if (pool->num_free < num) {
685 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
686 num, pool->num_free);
691 /* Lookup in free list and find most fit one */
692 LIST_FOREACH(entry, &pool->free_list, next) {
693 if (entry->len >= num) {
695 if (entry->len == num) {
700 valid_entry->len > entry->len)
705 /* Not find one to satisfy the request, return */
707 PMD_INIT_LOG(ERR, "No valid entry found");
711 * The entry have equal queue number as requested,
712 * remove it from alloc_list.
714 if (valid_entry->len == num) {
715 LIST_REMOVE(valid_entry, next);
718 * The entry have more numbers than requested,
719 * create a new entry for alloc_list and minus its
720 * queue base and number in free_list.
722 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
725 "Failed to allocate memory for "
729 entry->base = valid_entry->base;
731 valid_entry->base += num;
732 valid_entry->len -= num;
736 /* Insert it into alloc list, not sorted */
737 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
739 pool->num_free -= valid_entry->len;
740 pool->num_alloc += valid_entry->len;
742 return valid_entry->base + pool->base;
746 ice_res_pool_destroy(struct ice_res_pool_info *pool)
748 struct pool_entry *entry, *next_entry;
753 for (entry = LIST_FIRST(&pool->alloc_list);
754 entry && (next_entry = LIST_NEXT(entry, next), 1);
755 entry = next_entry) {
756 LIST_REMOVE(entry, next);
760 for (entry = LIST_FIRST(&pool->free_list);
761 entry && (next_entry = LIST_NEXT(entry, next), 1);
762 entry = next_entry) {
763 LIST_REMOVE(entry, next);
770 LIST_INIT(&pool->alloc_list);
771 LIST_INIT(&pool->free_list);
775 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
777 /* Set VSI LUT selection */
778 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
779 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
780 /* Set Hash scheme */
781 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
782 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
784 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
787 static enum ice_status
788 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
789 struct ice_aqc_vsi_props *info,
790 uint8_t enabled_tcmap)
792 uint16_t bsf, qp_idx;
794 /* default tc 0 now. Multi-TC supporting need to be done later.
795 * Configure TC and queue mapping parameters, for enabled TC,
796 * allocate qpnum_per_tc queues to this traffic.
798 if (enabled_tcmap != 0x01) {
799 PMD_INIT_LOG(ERR, "only TC0 is supported");
803 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
804 bsf = rte_bsf32(vsi->nb_qps);
805 /* Adjust the queue number to actual queues that can be applied */
806 vsi->nb_qps = 0x1 << bsf;
809 /* Set tc and queue mapping with VSI */
810 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
811 ICE_AQ_VSI_TC_Q_OFFSET_S) |
812 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
814 /* Associate queue number with VSI */
815 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
816 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
817 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
818 info->valid_sections |=
819 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
820 /* Set the info.ingress_table and info.egress_table
821 * for UP translate table. Now just set it to 1:1 map by default
822 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
824 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
825 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
826 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
827 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
832 ice_init_mac_address(struct rte_eth_dev *dev)
834 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
836 if (!rte_is_unicast_ether_addr
837 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
838 PMD_INIT_LOG(ERR, "Invalid MAC address");
843 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
844 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
846 dev->data->mac_addrs =
847 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0);
848 if (!dev->data->mac_addrs) {
850 "Failed to allocate memory to store mac address");
853 /* store it to dev data */
855 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
856 &dev->data->mac_addrs[0]);
860 /* Find out specific MAC filter */
861 static struct ice_mac_filter *
862 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
864 struct ice_mac_filter *f;
866 TAILQ_FOREACH(f, &vsi->mac_list, next) {
867 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
875 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
877 struct ice_fltr_list_entry *m_list_itr = NULL;
878 struct ice_mac_filter *f;
879 struct LIST_HEAD_TYPE list_head;
880 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
883 /* If it's added and configured, return */
884 f = ice_find_mac_filter(vsi, mac_addr);
886 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
890 INIT_LIST_HEAD(&list_head);
892 m_list_itr = (struct ice_fltr_list_entry *)
893 ice_malloc(hw, sizeof(*m_list_itr));
898 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
899 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
900 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
901 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
902 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
903 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
904 m_list_itr->fltr_info.vsi_handle = vsi->idx;
906 LIST_ADD(&m_list_itr->list_entry, &list_head);
909 ret = ice_add_mac(hw, &list_head);
910 if (ret != ICE_SUCCESS) {
911 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
915 /* Add the mac addr into mac list */
916 f = rte_zmalloc(NULL, sizeof(*f), 0);
918 PMD_DRV_LOG(ERR, "failed to allocate memory");
922 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
923 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
929 rte_free(m_list_itr);
934 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
936 struct ice_fltr_list_entry *m_list_itr = NULL;
937 struct ice_mac_filter *f;
938 struct LIST_HEAD_TYPE list_head;
939 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
942 /* Can't find it, return an error */
943 f = ice_find_mac_filter(vsi, mac_addr);
947 INIT_LIST_HEAD(&list_head);
949 m_list_itr = (struct ice_fltr_list_entry *)
950 ice_malloc(hw, sizeof(*m_list_itr));
955 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
956 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
957 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
958 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
959 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
960 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
961 m_list_itr->fltr_info.vsi_handle = vsi->idx;
963 LIST_ADD(&m_list_itr->list_entry, &list_head);
965 /* remove the mac filter */
966 ret = ice_remove_mac(hw, &list_head);
967 if (ret != ICE_SUCCESS) {
968 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
973 /* Remove the mac addr from mac list */
974 TAILQ_REMOVE(&vsi->mac_list, f, next);
980 rte_free(m_list_itr);
984 /* Find out specific VLAN filter */
985 static struct ice_vlan_filter *
986 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
988 struct ice_vlan_filter *f;
990 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
991 if (vlan->tpid == f->vlan_info.vlan.tpid &&
992 vlan->vid == f->vlan_info.vlan.vid)
1000 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1002 struct ice_fltr_list_entry *v_list_itr = NULL;
1003 struct ice_vlan_filter *f;
1004 struct LIST_HEAD_TYPE list_head;
1008 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1011 hw = ICE_VSI_TO_HW(vsi);
1013 /* If it's added and configured, return. */
1014 f = ice_find_vlan_filter(vsi, vlan);
1016 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
1020 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
1023 INIT_LIST_HEAD(&list_head);
1025 v_list_itr = (struct ice_fltr_list_entry *)
1026 ice_malloc(hw, sizeof(*v_list_itr));
1031 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1032 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1033 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1034 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1035 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1036 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1037 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1038 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1040 LIST_ADD(&v_list_itr->list_entry, &list_head);
1043 ret = ice_add_vlan(hw, &list_head);
1044 if (ret != ICE_SUCCESS) {
1045 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1050 /* Add vlan into vlan list */
1051 f = rte_zmalloc(NULL, sizeof(*f), 0);
1053 PMD_DRV_LOG(ERR, "failed to allocate memory");
1057 f->vlan_info.vlan.tpid = vlan->tpid;
1058 f->vlan_info.vlan.vid = vlan->vid;
1059 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1065 rte_free(v_list_itr);
1070 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1072 struct ice_fltr_list_entry *v_list_itr = NULL;
1073 struct ice_vlan_filter *f;
1074 struct LIST_HEAD_TYPE list_head;
1078 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1081 hw = ICE_VSI_TO_HW(vsi);
1083 /* Can't find it, return an error */
1084 f = ice_find_vlan_filter(vsi, vlan);
1088 INIT_LIST_HEAD(&list_head);
1090 v_list_itr = (struct ice_fltr_list_entry *)
1091 ice_malloc(hw, sizeof(*v_list_itr));
1097 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1098 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1099 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1100 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1101 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1102 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1103 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1104 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1106 LIST_ADD(&v_list_itr->list_entry, &list_head);
1108 /* remove the vlan filter */
1109 ret = ice_remove_vlan(hw, &list_head);
1110 if (ret != ICE_SUCCESS) {
1111 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1116 /* Remove the vlan id from vlan list */
1117 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1123 rte_free(v_list_itr);
1128 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1130 struct ice_mac_filter *m_f;
1131 struct ice_vlan_filter *v_f;
1135 if (!vsi || !vsi->mac_num)
1138 RTE_TAILQ_FOREACH_SAFE(m_f, &vsi->mac_list, next, temp) {
1139 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1140 if (ret != ICE_SUCCESS) {
1146 if (vsi->vlan_num == 0)
1149 RTE_TAILQ_FOREACH_SAFE(v_f, &vsi->vlan_list, next, temp) {
1150 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1151 if (ret != ICE_SUCCESS) {
1163 ice_pf_enable_irq0(struct ice_hw *hw)
1165 /* reset the registers */
1166 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1167 ICE_READ_REG(hw, PFINT_OICR);
1170 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1171 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1172 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1174 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1175 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1176 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1177 PFINT_OICR_CTL_ITR_INDX_M) |
1178 PFINT_OICR_CTL_CAUSE_ENA_M);
1180 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1181 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1182 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1183 PFINT_FW_CTL_ITR_INDX_M) |
1184 PFINT_FW_CTL_CAUSE_ENA_M);
1186 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1189 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1190 GLINT_DYN_CTL_INTENA_M |
1191 GLINT_DYN_CTL_CLEARPBA_M |
1192 GLINT_DYN_CTL_ITR_INDX_M);
1199 ice_pf_disable_irq0(struct ice_hw *hw)
1201 /* Disable all interrupt types */
1202 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1208 ice_handle_aq_msg(struct rte_eth_dev *dev)
1210 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1211 struct ice_ctl_q_info *cq = &hw->adminq;
1212 struct ice_rq_event_info event;
1213 uint16_t pending, opcode;
1216 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1217 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1218 if (!event.msg_buf) {
1219 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1225 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1227 if (ret != ICE_SUCCESS) {
1229 "Failed to read msg from AdminQ, "
1231 hw->adminq.sq_last_status);
1234 opcode = rte_le_to_cpu_16(event.desc.opcode);
1237 case ice_aqc_opc_get_link_status:
1238 ret = ice_link_update(dev, 0);
1240 rte_eth_dev_callback_process
1241 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1244 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1249 rte_free(event.msg_buf);
1254 * Interrupt handler triggered by NIC for handling
1255 * specific interrupt.
1258 * Pointer to interrupt handle.
1260 * The address of parameter (struct rte_eth_dev *) regsitered before.
1266 ice_interrupt_handler(void *param)
1268 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1269 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1277 uint32_t int_fw_ctl;
1280 /* Disable interrupt */
1281 ice_pf_disable_irq0(hw);
1283 /* read out interrupt causes */
1284 oicr = ICE_READ_REG(hw, PFINT_OICR);
1286 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1289 /* No interrupt event indicated */
1290 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1291 PMD_DRV_LOG(INFO, "No interrupt event");
1296 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1297 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1298 ice_handle_aq_msg(dev);
1301 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1302 PMD_DRV_LOG(INFO, "OICR: link state change event");
1303 ret = ice_link_update(dev, 0);
1305 rte_eth_dev_callback_process
1306 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1310 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1311 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1312 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1313 if (reg & GL_MDET_TX_PQM_VALID_M) {
1314 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1315 GL_MDET_TX_PQM_PF_NUM_S;
1316 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1317 GL_MDET_TX_PQM_MAL_TYPE_S;
1318 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1319 GL_MDET_TX_PQM_QNUM_S;
1321 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1322 "%d by PQM on TX queue %d PF# %d",
1323 event, queue, pf_num);
1326 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1327 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1328 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1329 GL_MDET_TX_TCLAN_PF_NUM_S;
1330 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1331 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1332 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1333 GL_MDET_TX_TCLAN_QNUM_S;
1335 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1336 "%d by TCLAN on TX queue %d PF# %d",
1337 event, queue, pf_num);
1341 /* Enable interrupt */
1342 ice_pf_enable_irq0(hw);
1343 rte_intr_ack(dev->intr_handle);
1347 ice_init_proto_xtr(struct rte_eth_dev *dev)
1349 struct ice_adapter *ad =
1350 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1351 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1352 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1353 const struct proto_xtr_ol_flag *ol_flag;
1354 bool proto_xtr_enable = false;
1358 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1359 if (unlikely(pf->proto_xtr == NULL)) {
1360 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1364 for (i = 0; i < pf->lan_nb_qps; i++) {
1365 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1366 ad->devargs.proto_xtr[i] :
1367 ad->devargs.proto_xtr_dflt;
1369 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1370 uint8_t type = pf->proto_xtr[i];
1372 ice_proto_xtr_ol_flag_params[type].required = true;
1373 proto_xtr_enable = true;
1377 if (likely(!proto_xtr_enable))
1380 ice_check_proto_xtr_support(hw);
1382 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1383 if (unlikely(offset == -1)) {
1385 "Protocol extraction metadata is disabled in mbuf with error %d",
1391 "Protocol extraction metadata offset in mbuf is : %d",
1393 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1395 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1396 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1398 if (!ol_flag->required)
1401 if (!ice_proto_xtr_hw_support[i]) {
1403 "Protocol extraction type %u is not supported in hardware",
1405 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1409 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1410 if (unlikely(offset == -1)) {
1412 "Protocol extraction offload '%s' failed to register with error %d",
1413 ol_flag->param.name, -rte_errno);
1415 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1420 "Protocol extraction offload '%s' offset in mbuf is : %d",
1421 ol_flag->param.name, offset);
1422 *ol_flag->ol_flag = 1ULL << offset;
1426 /* Initialize SW parameters of PF */
1428 ice_pf_sw_init(struct rte_eth_dev *dev)
1430 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1431 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1434 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1435 hw->func_caps.common_cap.num_rxq);
1437 pf->lan_nb_qps = pf->lan_nb_qp_max;
1439 ice_init_proto_xtr(dev);
1441 if (hw->func_caps.fd_fltr_guar > 0 ||
1442 hw->func_caps.fd_fltr_best_effort > 0) {
1443 pf->flags |= ICE_FLAG_FDIR;
1444 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1445 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1447 pf->fdir_nb_qps = 0;
1449 pf->fdir_qp_offset = 0;
1455 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1457 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1458 struct ice_vsi *vsi = NULL;
1459 struct ice_vsi_ctx vsi_ctx;
1461 struct rte_ether_addr broadcast = {
1462 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1463 struct rte_ether_addr mac_addr;
1464 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1465 uint8_t tc_bitmap = 0x1;
1468 /* hw->num_lports = 1 in NIC mode */
1469 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1473 vsi->idx = pf->next_vsi_idx;
1476 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1477 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1478 vsi->vlan_anti_spoof_on = 0;
1479 vsi->vlan_filter_on = 1;
1480 TAILQ_INIT(&vsi->mac_list);
1481 TAILQ_INIT(&vsi->vlan_list);
1483 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1484 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1485 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1486 hw->func_caps.common_cap.rss_table_size;
1487 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1489 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1492 vsi->nb_qps = pf->lan_nb_qps;
1493 vsi->base_queue = 1;
1494 ice_vsi_config_default_rss(&vsi_ctx.info);
1495 vsi_ctx.alloc_from_pool = true;
1496 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1497 /* switch_id is queried by get_switch_config aq, which is done
1500 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1501 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1502 /* Allow all untagged or tagged packets */
1503 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1504 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1505 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1506 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1507 if (ice_is_dvm_ena(hw)) {
1508 vsi_ctx.info.outer_vlan_flags =
1509 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1510 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1511 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1512 vsi_ctx.info.outer_vlan_flags |=
1513 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1514 ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1515 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1519 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1520 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1521 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1522 cfg = ICE_AQ_VSI_FD_ENABLE;
1523 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1524 vsi_ctx.info.max_fd_fltr_dedicated =
1525 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1526 vsi_ctx.info.max_fd_fltr_shared =
1527 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1529 /* Enable VLAN/UP trip */
1530 ret = ice_vsi_config_tc_queue_mapping(vsi,
1535 "tc queue mapping with vsi failed, "
1543 vsi->nb_qps = pf->fdir_nb_qps;
1544 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1545 vsi_ctx.alloc_from_pool = true;
1546 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1548 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1549 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1550 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1551 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1552 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1553 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1554 ret = ice_vsi_config_tc_queue_mapping(vsi,
1559 "tc queue mapping with vsi failed, "
1566 /* for other types of VSI */
1567 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1571 /* VF has MSIX interrupt in VF range, don't allocate here */
1572 if (type == ICE_VSI_PF) {
1573 ret = ice_res_pool_alloc(&pf->msix_pool,
1574 RTE_MIN(vsi->nb_qps,
1575 RTE_MAX_RXTX_INTR_VEC_ID));
1577 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1580 vsi->msix_intr = ret;
1581 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1582 } else if (type == ICE_VSI_CTRL) {
1583 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1585 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1588 vsi->msix_intr = ret;
1594 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1595 if (ret != ICE_SUCCESS) {
1596 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1599 /* store vsi information is SW structure */
1600 vsi->vsi_id = vsi_ctx.vsi_num;
1601 vsi->info = vsi_ctx.info;
1602 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1603 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1605 if (type == ICE_VSI_PF) {
1606 /* MAC configuration */
1607 rte_ether_addr_copy((struct rte_ether_addr *)
1608 hw->port_info->mac.perm_addr,
1611 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1612 ret = ice_add_mac_filter(vsi, &mac_addr);
1613 if (ret != ICE_SUCCESS)
1614 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1616 rte_ether_addr_copy(&broadcast, &mac_addr);
1617 ret = ice_add_mac_filter(vsi, &mac_addr);
1618 if (ret != ICE_SUCCESS)
1619 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1622 /* At the beginning, only TC0. */
1623 /* What we need here is the maximam number of the TX queues.
1624 * Currently vsi->nb_qps means it.
1625 * Correct it if any change.
1627 max_txqs[0] = vsi->nb_qps;
1628 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1629 tc_bitmap, max_txqs);
1630 if (ret != ICE_SUCCESS)
1631 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1641 ice_send_driver_ver(struct ice_hw *hw)
1643 struct ice_driver_ver dv;
1645 /* we don't have driver version use 0 for dummy */
1649 dv.subbuild_ver = 0;
1650 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1652 return ice_aq_send_driver_ver(hw, &dv, NULL);
1656 ice_pf_setup(struct ice_pf *pf)
1658 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1659 struct ice_vsi *vsi;
1662 /* Clear all stats counters */
1663 pf->offset_loaded = false;
1664 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1665 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1666 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1667 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1669 /* force guaranteed filter pool for PF */
1670 ice_alloc_fd_guar_item(hw, &unused,
1671 hw->func_caps.fd_fltr_guar);
1672 /* force shared filter pool for PF */
1673 ice_alloc_fd_shrd_item(hw, &unused,
1674 hw->func_caps.fd_fltr_best_effort);
1676 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1678 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1687 static enum ice_pkg_type
1688 ice_load_pkg_type(struct ice_hw *hw)
1690 enum ice_pkg_type package_type;
1692 /* store the activated package type (OS default or Comms) */
1693 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1695 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1696 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1698 package_type = ICE_PKG_TYPE_COMMS;
1700 package_type = ICE_PKG_TYPE_UNKNOWN;
1702 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1703 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1704 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1705 hw->active_pkg_name,
1706 ice_is_dvm_ena(hw) ? "double" : "single");
1708 return package_type;
1711 int ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn)
1713 struct ice_hw *hw = &adapter->hw;
1714 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1715 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1723 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1724 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1725 "ice-%016" PRIx64 ".pkg", dsn);
1726 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1727 ICE_MAX_PKG_FILENAME_SIZE);
1728 strcat(pkg_file, opt_ddp_filename);
1729 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1732 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1733 ICE_MAX_PKG_FILENAME_SIZE);
1734 strcat(pkg_file, opt_ddp_filename);
1735 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1739 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1740 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1743 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1744 if (rte_firmware_read(pkg_file, &buf, &bufsz) < 0) {
1745 PMD_INIT_LOG(ERR, "failed to search file path\n");
1750 PMD_INIT_LOG(DEBUG, "DDP package name: %s", pkg_file);
1752 err = ice_copy_and_init_pkg(hw, buf, bufsz);
1754 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1758 /* store the loaded pkg type info */
1759 adapter->active_pkg_type = ice_load_pkg_type(hw);
1767 ice_base_queue_get(struct ice_pf *pf)
1770 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1772 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1773 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1774 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1776 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1782 parse_bool(const char *key, const char *value, void *args)
1784 int *i = (int *)args;
1788 num = strtoul(value, &end, 10);
1790 if (num != 0 && num != 1) {
1791 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1792 "value must be 0 or 1",
1802 parse_u64(const char *key, const char *value, void *args)
1804 u64 *num = (u64 *)args;
1808 tmp = strtoull(value, NULL, 16);
1810 PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u64",
1821 lookup_pps_type(const char *pps_name)
1826 } pps_type_map[] = {
1832 for (i = 0; i < RTE_DIM(pps_type_map); i++) {
1833 if (strcmp(pps_name, pps_type_map[i].name) == 0)
1834 return pps_type_map[i].type;
1841 parse_pin_set(const char *input, int pps_type, struct ice_devargs *devargs)
1843 const char *str = input;
1847 while (isblank(*str))
1853 if (pps_type == PPS_PIN) {
1854 idx = strtoul(str, &end, 10);
1855 if (end == NULL || idx >= ICE_MAX_PIN_NUM)
1857 while (isblank(*end))
1862 devargs->pin_idx = idx;
1863 devargs->pps_out_ena = 1;
1872 parse_pps_out_parameter(const char *pins, struct ice_devargs *devargs)
1874 const char *pin_start;
1879 while (isblank(*pins))
1883 while (isblank(*pins))
1888 for (idx = 0; ; idx++) {
1889 if (isblank(pins[idx]) ||
1894 pps_name[idx] = pins[idx];
1896 pps_name[idx] = '\0';
1897 pps_type = lookup_pps_type(pps_name);
1903 pins += strcspn(pins, ":");
1906 while (isblank(*pins))
1911 while (isblank(*pins))
1914 if (parse_pin_set(pin_start, pps_type, devargs) < 0)
1921 handle_pps_out_arg(__rte_unused const char *key, const char *value,
1924 struct ice_devargs *devargs = extra_args;
1926 if (value == NULL || extra_args == NULL)
1929 if (parse_pps_out_parameter(value, devargs) < 0) {
1931 "The GPIO pin parameter is wrong : '%s'",
1939 static int ice_parse_devargs(struct rte_eth_dev *dev)
1941 struct ice_adapter *ad =
1942 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1943 struct rte_devargs *devargs = dev->device->devargs;
1944 struct rte_kvargs *kvlist;
1947 if (devargs == NULL)
1950 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1951 if (kvlist == NULL) {
1952 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1956 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1957 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1958 sizeof(ad->devargs.proto_xtr));
1960 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1961 &handle_proto_xtr_arg, &ad->devargs);
1965 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1966 &parse_bool, &ad->devargs.safe_mode_support);
1970 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1971 &parse_bool, &ad->devargs.pipe_mode_support);
1975 ret = rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG,
1976 &parse_u64, &ad->hw.debug_mask);
1980 ret = rte_kvargs_process(kvlist, ICE_ONE_PPS_OUT_ARG,
1981 &handle_pps_out_arg, &ad->devargs);
1985 ret = rte_kvargs_process(kvlist, ICE_RX_LOW_LATENCY_ARG,
1986 &parse_bool, &ad->devargs.rx_low_latency);
1989 rte_kvargs_free(kvlist);
1993 /* Forward LLDP packets to default VSI by set switch rules */
1995 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1997 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1998 struct ice_fltr_list_entry *s_list_itr = NULL;
1999 struct LIST_HEAD_TYPE list_head;
2002 INIT_LIST_HEAD(&list_head);
2004 s_list_itr = (struct ice_fltr_list_entry *)
2005 ice_malloc(hw, sizeof(*s_list_itr));
2008 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2009 s_list_itr->fltr_info.vsi_handle = vsi->idx;
2010 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2011 RTE_ETHER_TYPE_LLDP;
2012 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2013 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2014 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2015 LIST_ADD(&s_list_itr->list_entry, &list_head);
2017 ret = ice_add_eth_mac(hw, &list_head);
2019 ret = ice_remove_eth_mac(hw, &list_head);
2021 rte_free(s_list_itr);
2025 static enum ice_status
2026 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2027 uint16_t num, uint16_t desc_id,
2028 uint16_t *prof_buf, uint16_t *num_prof)
2030 struct ice_aqc_res_elem *resp_buf;
2033 bool res_shared = 1;
2034 struct ice_aq_desc aq_desc;
2035 struct ice_sq_cd *cd = NULL;
2036 struct ice_aqc_get_allocd_res_desc *cmd =
2037 &aq_desc.params.get_res_desc;
2039 buf_len = sizeof(*resp_buf) * num;
2040 resp_buf = ice_malloc(hw, buf_len);
2044 ice_fill_dflt_direct_cmd_desc(&aq_desc,
2045 ice_aqc_opc_get_allocd_res_desc);
2047 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2048 ICE_AQC_RES_TYPE_M) | (res_shared ?
2049 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2050 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2052 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2054 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2058 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
2059 (*num_prof), ICE_NONDMA_TO_NONDMA);
2066 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2070 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2071 uint16_t first_desc = 1;
2072 uint16_t num_prof = 0;
2074 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2075 first_desc, prof_buf, &num_prof);
2077 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2081 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2082 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2084 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2092 ice_reset_fxp_resource(struct ice_hw *hw)
2096 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2098 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2102 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2104 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2112 ice_rss_ctx_init(struct ice_pf *pf)
2114 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
2118 ice_get_supported_rxdid(struct ice_hw *hw)
2120 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2124 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2126 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2127 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2128 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2129 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2130 supported_rxdid |= BIT(i);
2132 return supported_rxdid;
2136 ice_dev_init(struct rte_eth_dev *dev)
2138 struct rte_pci_device *pci_dev;
2139 struct rte_intr_handle *intr_handle;
2140 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2141 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2142 struct ice_adapter *ad =
2143 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2144 struct ice_vsi *vsi;
2146 #ifndef RTE_EXEC_ENV_WINDOWS
2148 uint32_t dsn_low, dsn_high;
2153 dev->dev_ops = &ice_eth_dev_ops;
2154 dev->rx_queue_count = ice_rx_queue_count;
2155 dev->rx_descriptor_status = ice_rx_descriptor_status;
2156 dev->tx_descriptor_status = ice_tx_descriptor_status;
2157 dev->rx_pkt_burst = ice_recv_pkts;
2158 dev->tx_pkt_burst = ice_xmit_pkts;
2159 dev->tx_pkt_prepare = ice_prep_pkts;
2161 /* for secondary processes, we don't initialise any further as primary
2162 * has already done this work.
2164 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2165 ice_set_rx_function(dev);
2166 ice_set_tx_function(dev);
2170 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2172 ice_set_default_ptype_table(dev);
2173 pci_dev = RTE_DEV_TO_PCI(dev->device);
2174 intr_handle = &pci_dev->intr_handle;
2176 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2177 pf->dev_data = dev->data;
2178 hw->back = pf->adapter;
2179 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2180 hw->vendor_id = pci_dev->id.vendor_id;
2181 hw->device_id = pci_dev->id.device_id;
2182 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2183 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2184 hw->bus.device = pci_dev->addr.devid;
2185 hw->bus.func = pci_dev->addr.function;
2187 ret = ice_parse_devargs(dev);
2189 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2193 ice_init_controlq_parameter(hw);
2195 ret = ice_init_hw(hw);
2197 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2201 #ifndef RTE_EXEC_ENV_WINDOWS
2204 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
2206 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0 ||
2207 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) {
2208 PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
2211 dsn = (uint64_t)dsn_high << 32 | dsn_low;
2214 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
2217 ret = ice_load_pkg(pf->adapter, use_dsn, dsn);
2219 ret = ice_init_hw_tbls(hw);
2221 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", ret);
2222 rte_free(hw->pkg_copy);
2227 if (ad->devargs.safe_mode_support == 0) {
2228 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2229 "Use safe-mode-support=1 to enter Safe Mode");
2233 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2234 "Entering Safe Mode");
2235 ad->is_safe_mode = 1;
2239 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2240 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2241 hw->api_maj_ver, hw->api_min_ver);
2243 ice_pf_sw_init(dev);
2244 ret = ice_init_mac_address(dev);
2246 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2250 ret = ice_res_pool_init(&pf->msix_pool, 1,
2251 hw->func_caps.common_cap.num_msix_vectors - 1);
2253 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2254 goto err_msix_pool_init;
2257 ret = ice_pf_setup(pf);
2259 PMD_INIT_LOG(ERR, "Failed to setup PF");
2263 ret = ice_send_driver_ver(hw);
2265 PMD_INIT_LOG(ERR, "Failed to send driver version");
2271 ret = ice_aq_stop_lldp(hw, true, false, NULL);
2272 if (ret != ICE_SUCCESS)
2273 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2274 ret = ice_init_dcb(hw, true);
2275 if (ret != ICE_SUCCESS)
2276 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2277 /* Forward LLDP packets to default VSI */
2278 ret = ice_vsi_config_sw_lldp(vsi, true);
2279 if (ret != ICE_SUCCESS)
2280 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2281 /* register callback func to eal lib */
2282 rte_intr_callback_register(intr_handle,
2283 ice_interrupt_handler, dev);
2285 ice_pf_enable_irq0(hw);
2287 /* enable uio intr after callback register */
2288 rte_intr_enable(intr_handle);
2290 /* get base queue pairs index in the device */
2291 ice_base_queue_get(pf);
2293 /* Initialize RSS context for gtpu_eh */
2294 ice_rss_ctx_init(pf);
2296 if (!ad->is_safe_mode) {
2297 ret = ice_flow_init(ad);
2299 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2304 ret = ice_reset_fxp_resource(hw);
2306 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2310 pf->supported_rxdid = ice_get_supported_rxdid(hw);
2315 ice_flow_uninit(ad);
2316 rte_intr_disable(intr_handle);
2317 ice_pf_disable_irq0(hw);
2318 rte_intr_callback_unregister(intr_handle,
2319 ice_interrupt_handler, dev);
2321 ice_res_pool_destroy(&pf->msix_pool);
2323 rte_free(dev->data->mac_addrs);
2324 dev->data->mac_addrs = NULL;
2326 rte_free(pf->proto_xtr);
2327 #ifndef RTE_EXEC_ENV_WINDOWS
2336 ice_release_vsi(struct ice_vsi *vsi)
2339 struct ice_vsi_ctx vsi_ctx;
2340 enum ice_status ret;
2346 hw = ICE_VSI_TO_HW(vsi);
2348 ice_remove_all_mac_vlan_filters(vsi);
2350 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2352 vsi_ctx.vsi_num = vsi->vsi_id;
2353 vsi_ctx.info = vsi->info;
2354 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2355 if (ret != ICE_SUCCESS) {
2356 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2360 rte_free(vsi->rss_lut);
2361 rte_free(vsi->rss_key);
2367 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2369 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
2370 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2371 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2372 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2373 uint16_t msix_intr, i;
2375 /* disable interrupt and also clear all the exist config */
2376 for (i = 0; i < vsi->nb_qps; i++) {
2377 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2378 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2382 if (rte_intr_allow_others(intr_handle))
2384 for (i = 0; i < vsi->nb_msix; i++) {
2385 msix_intr = vsi->msix_intr + i;
2386 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2387 GLINT_DYN_CTL_WB_ON_ITR_M);
2391 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2395 ice_dev_stop(struct rte_eth_dev *dev)
2397 struct rte_eth_dev_data *data = dev->data;
2398 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2399 struct ice_vsi *main_vsi = pf->main_vsi;
2400 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2401 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2404 /* avoid stopping again */
2405 if (pf->adapter_stopped)
2408 /* stop and clear all Rx queues */
2409 for (i = 0; i < data->nb_rx_queues; i++)
2410 ice_rx_queue_stop(dev, i);
2412 /* stop and clear all Tx queues */
2413 for (i = 0; i < data->nb_tx_queues; i++)
2414 ice_tx_queue_stop(dev, i);
2416 /* disable all queue interrupts */
2417 ice_vsi_disable_queues_intr(main_vsi);
2419 if (pf->init_link_up)
2420 ice_dev_set_link_up(dev);
2422 ice_dev_set_link_down(dev);
2424 /* Clean datapath event and queue/vec mapping */
2425 rte_intr_efd_disable(intr_handle);
2426 if (intr_handle->intr_vec) {
2427 rte_free(intr_handle->intr_vec);
2428 intr_handle->intr_vec = NULL;
2431 pf->adapter_stopped = true;
2432 dev->data->dev_started = 0;
2438 ice_dev_close(struct rte_eth_dev *dev)
2440 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2441 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2442 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2443 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2444 struct ice_adapter *ad =
2445 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2448 uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned;
2449 uint32_t pin_idx = ad->devargs.pin_idx;
2451 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2454 /* Since stop will make link down, then the link event will be
2455 * triggered, disable the irq firstly to avoid the port_infoe etc
2456 * resources deallocation causing the interrupt service thread
2459 ice_pf_disable_irq0(hw);
2461 ret = ice_dev_stop(dev);
2463 if (!ad->is_safe_mode)
2464 ice_flow_uninit(ad);
2466 /* release all queue resource */
2467 ice_free_queues(dev);
2469 ice_res_pool_destroy(&pf->msix_pool);
2470 ice_release_vsi(pf->main_vsi);
2471 ice_sched_cleanup_all(hw);
2472 ice_free_hw_tbls(hw);
2473 rte_free(hw->port_info);
2474 hw->port_info = NULL;
2475 ice_shutdown_all_ctrlq(hw);
2476 rte_free(pf->proto_xtr);
2477 pf->proto_xtr = NULL;
2479 if (ad->devargs.pps_out_ena) {
2480 ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(pin_idx, timer), 0);
2481 ICE_WRITE_REG(hw, GLTSYN_CLKO(pin_idx, timer), 0);
2482 ICE_WRITE_REG(hw, GLTSYN_TGT_L(pin_idx, timer), 0);
2483 ICE_WRITE_REG(hw, GLTSYN_TGT_H(pin_idx, timer), 0);
2485 val = GLGEN_GPIO_CTL_PIN_DIR_M;
2486 ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(pin_idx), val);
2489 /* disable uio intr before callback unregister */
2490 rte_intr_disable(intr_handle);
2492 /* unregister callback func from eal lib */
2493 rte_intr_callback_unregister(intr_handle,
2494 ice_interrupt_handler, dev);
2500 ice_dev_uninit(struct rte_eth_dev *dev)
2508 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2510 return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2514 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2519 cfg->hdr_type = ICE_RSS_OUTER_HEADERS;
2523 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2525 enum ice_status status = ICE_SUCCESS;
2526 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2527 struct ice_vsi *vsi = pf->main_vsi;
2529 if (!is_hash_cfg_valid(cfg))
2532 status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2533 if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2535 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2544 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2546 enum ice_status status = ICE_SUCCESS;
2547 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2548 struct ice_vsi *vsi = pf->main_vsi;
2550 if (!is_hash_cfg_valid(cfg))
2553 status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2556 "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2565 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2569 ret = ice_hash_moveout(pf, cfg);
2570 if (ret && (ret != -ENOENT))
2573 hash_cfg_reset(cfg);
2579 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2585 case ICE_HASH_GTPU_CTX_EH_IP:
2586 ret = ice_hash_remove(pf,
2587 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2588 if (ret && (ret != -ENOENT))
2591 ret = ice_hash_remove(pf,
2592 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2593 if (ret && (ret != -ENOENT))
2596 ret = ice_hash_remove(pf,
2597 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2598 if (ret && (ret != -ENOENT))
2601 ret = ice_hash_remove(pf,
2602 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2603 if (ret && (ret != -ENOENT))
2606 ret = ice_hash_remove(pf,
2607 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2608 if (ret && (ret != -ENOENT))
2611 ret = ice_hash_remove(pf,
2612 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2613 if (ret && (ret != -ENOENT))
2616 ret = ice_hash_remove(pf,
2617 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2618 if (ret && (ret != -ENOENT))
2621 ret = ice_hash_remove(pf,
2622 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2623 if (ret && (ret != -ENOENT))
2627 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2628 ret = ice_hash_remove(pf,
2629 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2630 if (ret && (ret != -ENOENT))
2633 ret = ice_hash_remove(pf,
2634 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2635 if (ret && (ret != -ENOENT))
2638 ret = ice_hash_moveout(pf,
2639 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2640 if (ret && (ret != -ENOENT))
2643 ret = ice_hash_moveout(pf,
2644 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2645 if (ret && (ret != -ENOENT))
2648 ret = ice_hash_moveout(pf,
2649 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2650 if (ret && (ret != -ENOENT))
2653 ret = ice_hash_moveout(pf,
2654 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2655 if (ret && (ret != -ENOENT))
2659 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2660 ret = ice_hash_remove(pf,
2661 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2662 if (ret && (ret != -ENOENT))
2665 ret = ice_hash_remove(pf,
2666 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2667 if (ret && (ret != -ENOENT))
2670 ret = ice_hash_moveout(pf,
2671 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2672 if (ret && (ret != -ENOENT))
2675 ret = ice_hash_moveout(pf,
2676 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2677 if (ret && (ret != -ENOENT))
2680 ret = ice_hash_moveout(pf,
2681 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2682 if (ret && (ret != -ENOENT))
2685 ret = ice_hash_moveout(pf,
2686 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2687 if (ret && (ret != -ENOENT))
2691 case ICE_HASH_GTPU_CTX_UP_IP:
2692 ret = ice_hash_remove(pf,
2693 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2694 if (ret && (ret != -ENOENT))
2697 ret = ice_hash_remove(pf,
2698 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2699 if (ret && (ret != -ENOENT))
2702 ret = ice_hash_moveout(pf,
2703 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2704 if (ret && (ret != -ENOENT))
2707 ret = ice_hash_moveout(pf,
2708 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2709 if (ret && (ret != -ENOENT))
2712 ret = ice_hash_moveout(pf,
2713 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2714 if (ret && (ret != -ENOENT))
2718 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2719 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2720 ret = ice_hash_moveout(pf,
2721 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2722 if (ret && (ret != -ENOENT))
2725 ret = ice_hash_moveout(pf,
2726 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2727 if (ret && (ret != -ENOENT))
2730 ret = ice_hash_moveout(pf,
2731 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2732 if (ret && (ret != -ENOENT))
2736 case ICE_HASH_GTPU_CTX_DW_IP:
2737 ret = ice_hash_remove(pf,
2738 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2739 if (ret && (ret != -ENOENT))
2742 ret = ice_hash_remove(pf,
2743 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2744 if (ret && (ret != -ENOENT))
2747 ret = ice_hash_moveout(pf,
2748 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2749 if (ret && (ret != -ENOENT))
2752 ret = ice_hash_moveout(pf,
2753 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2754 if (ret && (ret != -ENOENT))
2757 ret = ice_hash_moveout(pf,
2758 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2759 if (ret && (ret != -ENOENT))
2763 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2764 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2765 ret = ice_hash_moveout(pf,
2766 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2767 if (ret && (ret != -ENOENT))
2770 ret = ice_hash_moveout(pf,
2771 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2772 if (ret && (ret != -ENOENT))
2775 ret = ice_hash_moveout(pf,
2776 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2777 if (ret && (ret != -ENOENT))
2788 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2792 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2794 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2796 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2799 return ICE_HASH_GTPU_CTX_MAX;
2802 if (hdr & ICE_FLOW_SEG_HDR_UDP)
2804 else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2807 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2808 return eh_idx * 3 + ip_idx;
2810 return ICE_HASH_GTPU_CTX_MAX;
2814 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2816 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2818 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2819 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2821 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2822 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2829 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2830 u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2834 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2835 ctx->ctx[ctx_idx] = *cfg;
2838 case ICE_HASH_GTPU_CTX_EH_IP:
2840 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2841 ret = ice_hash_moveback(pf,
2842 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2843 if (ret && (ret != -ENOENT))
2846 ret = ice_hash_moveback(pf,
2847 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2848 if (ret && (ret != -ENOENT))
2851 ret = ice_hash_moveback(pf,
2852 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2853 if (ret && (ret != -ENOENT))
2856 ret = ice_hash_moveback(pf,
2857 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2858 if (ret && (ret != -ENOENT))
2862 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2863 ret = ice_hash_moveback(pf,
2864 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2865 if (ret && (ret != -ENOENT))
2868 ret = ice_hash_moveback(pf,
2869 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2870 if (ret && (ret != -ENOENT))
2873 ret = ice_hash_moveback(pf,
2874 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2875 if (ret && (ret != -ENOENT))
2878 ret = ice_hash_moveback(pf,
2879 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2880 if (ret && (ret != -ENOENT))
2884 case ICE_HASH_GTPU_CTX_UP_IP:
2885 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2886 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2887 case ICE_HASH_GTPU_CTX_DW_IP:
2888 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2889 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2890 ret = ice_hash_moveback(pf,
2891 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2892 if (ret && (ret != -ENOENT))
2895 ret = ice_hash_moveback(pf,
2896 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2897 if (ret && (ret != -ENOENT))
2900 ret = ice_hash_moveback(pf,
2901 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2902 if (ret && (ret != -ENOENT))
2914 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2916 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2918 if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2919 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2921 else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2922 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2929 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2931 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2933 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2936 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2937 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2938 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2939 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2943 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2944 struct ice_rss_hash_cfg *cfg)
2946 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2949 ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2950 if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2951 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2953 ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2959 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2960 struct ice_rss_hash_cfg *cfg)
2962 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2965 ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2967 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2969 ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2971 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2973 ret = ice_add_rss_cfg_post(pf, cfg);
2975 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2981 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2983 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2984 struct ice_vsi *vsi = pf->main_vsi;
2985 struct ice_rss_hash_cfg cfg;
2988 #define ICE_RSS_HF_ALL ( \
2991 ETH_RSS_NONFRAG_IPV4_UDP | \
2992 ETH_RSS_NONFRAG_IPV6_UDP | \
2993 ETH_RSS_NONFRAG_IPV4_TCP | \
2994 ETH_RSS_NONFRAG_IPV6_TCP | \
2995 ETH_RSS_NONFRAG_IPV4_SCTP | \
2996 ETH_RSS_NONFRAG_IPV6_SCTP)
2998 ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
3000 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
3004 cfg.hdr_type = ICE_RSS_OUTER_HEADERS;
3005 /* Configure RSS for IPv4 with src/dst addr as input set */
3006 if (rss_hf & ETH_RSS_IPV4) {
3007 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3008 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
3009 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3011 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
3015 /* Configure RSS for IPv6 with src/dst addr as input set */
3016 if (rss_hf & ETH_RSS_IPV6) {
3017 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3018 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
3019 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3021 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
3025 /* Configure RSS for udp4 with src/dst addr and port as input set */
3026 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
3027 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
3028 ICE_FLOW_SEG_HDR_IPV_OTHER;
3029 cfg.hash_flds = ICE_HASH_UDP_IPV4;
3030 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3032 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
3036 /* Configure RSS for udp6 with src/dst addr and port as input set */
3037 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
3038 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
3039 ICE_FLOW_SEG_HDR_IPV_OTHER;
3040 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3041 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3043 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
3047 /* Configure RSS for tcp4 with src/dst addr and port as input set */
3048 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3049 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
3050 ICE_FLOW_SEG_HDR_IPV_OTHER;
3051 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3052 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3054 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
3058 /* Configure RSS for tcp6 with src/dst addr and port as input set */
3059 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3060 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
3061 ICE_FLOW_SEG_HDR_IPV_OTHER;
3062 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3063 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3065 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
3069 /* Configure RSS for sctp4 with src/dst addr and port as input set */
3070 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
3071 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
3072 ICE_FLOW_SEG_HDR_IPV_OTHER;
3073 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
3074 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3076 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
3080 /* Configure RSS for sctp6 with src/dst addr and port as input set */
3081 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
3082 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
3083 ICE_FLOW_SEG_HDR_IPV_OTHER;
3084 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
3085 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3087 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
3091 if (rss_hf & ETH_RSS_IPV4) {
3092 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
3093 ICE_FLOW_SEG_HDR_IPV_OTHER;
3094 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
3095 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3097 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
3101 if (rss_hf & ETH_RSS_IPV6) {
3102 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
3103 ICE_FLOW_SEG_HDR_IPV_OTHER;
3104 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
3105 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3107 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
3111 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
3112 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3113 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3114 cfg.hash_flds = ICE_HASH_UDP_IPV4;
3115 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3117 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
3121 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
3122 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3123 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3124 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3125 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3127 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3131 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3132 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3133 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3134 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3135 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3137 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3141 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3142 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3143 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3144 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3145 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3147 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3151 pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3155 ice_get_default_rss_key(uint8_t *rss_key, uint32_t rss_key_size)
3157 static struct ice_aqc_get_set_rss_keys default_key;
3158 static bool default_key_done;
3159 uint8_t *key = (uint8_t *)&default_key;
3162 if (rss_key_size > sizeof(default_key)) {
3163 PMD_DRV_LOG(WARNING,
3164 "requested size %u is larger than default %zu, "
3165 "only %zu bytes are gotten for key\n",
3166 rss_key_size, sizeof(default_key),
3167 sizeof(default_key));
3170 if (!default_key_done) {
3171 /* Calculate the default hash key */
3172 for (i = 0; i < sizeof(default_key); i++)
3173 key[i] = (uint8_t)rte_rand();
3174 default_key_done = true;
3176 rte_memcpy(rss_key, key, RTE_MIN(rss_key_size, sizeof(default_key)));
3179 static int ice_init_rss(struct ice_pf *pf)
3181 struct ice_hw *hw = ICE_PF_TO_HW(pf);
3182 struct ice_vsi *vsi = pf->main_vsi;
3183 struct rte_eth_dev_data *dev_data = pf->dev_data;
3184 struct ice_aq_get_set_rss_lut_params lut_params;
3185 struct rte_eth_rss_conf *rss_conf;
3186 struct ice_aqc_get_set_rss_keys key;
3189 bool is_safe_mode = pf->adapter->is_safe_mode;
3192 rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf;
3193 nb_q = dev_data->nb_rx_queues;
3194 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3195 vsi->rss_lut_size = pf->hash_lut_size;
3198 PMD_DRV_LOG(WARNING,
3199 "RSS is not supported as rx queues number is zero\n");
3204 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3208 if (!vsi->rss_key) {
3209 vsi->rss_key = rte_zmalloc(NULL,
3210 vsi->rss_key_size, 0);
3211 if (vsi->rss_key == NULL) {
3212 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3216 if (!vsi->rss_lut) {
3217 vsi->rss_lut = rte_zmalloc(NULL,
3218 vsi->rss_lut_size, 0);
3219 if (vsi->rss_lut == NULL) {
3220 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3221 rte_free(vsi->rss_key);
3222 vsi->rss_key = NULL;
3226 /* configure RSS key */
3227 if (!rss_conf->rss_key)
3228 ice_get_default_rss_key(vsi->rss_key, vsi->rss_key_size);
3230 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3231 RTE_MIN(rss_conf->rss_key_len,
3232 vsi->rss_key_size));
3234 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3235 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3239 /* init RSS LUT table */
3240 for (i = 0; i < vsi->rss_lut_size; i++)
3241 vsi->rss_lut[i] = i % nb_q;
3243 lut_params.vsi_handle = vsi->idx;
3244 lut_params.lut_size = vsi->rss_lut_size;
3245 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3246 lut_params.lut = vsi->rss_lut;
3247 lut_params.global_lut_id = 0;
3248 ret = ice_aq_set_rss_lut(hw, &lut_params);
3252 /* Enable registers for symmetric_toeplitz function. */
3253 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3254 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3255 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3256 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3258 /* RSS hash configuration */
3259 ice_rss_hash_set(pf, rss_conf->rss_hf);
3263 rte_free(vsi->rss_key);
3264 vsi->rss_key = NULL;
3265 rte_free(vsi->rss_lut);
3266 vsi->rss_lut = NULL;
3271 ice_dev_configure(struct rte_eth_dev *dev)
3273 struct ice_adapter *ad =
3274 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3275 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3278 /* Initialize to TRUE. If any of Rx queues doesn't meet the
3279 * bulk allocation or vector Rx preconditions we will reset it.
3281 ad->rx_bulk_alloc_allowed = true;
3282 ad->tx_simple_allowed = true;
3284 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3285 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3287 if (dev->data->nb_rx_queues) {
3288 ret = ice_init_rss(pf);
3290 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3299 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3300 int base_queue, int nb_queue)
3302 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3303 uint32_t val, val_tx;
3304 int rx_low_latency, i;
3306 rx_low_latency = vsi->adapter->devargs.rx_low_latency;
3307 for (i = 0; i < nb_queue; i++) {
3309 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3310 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3311 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3312 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3314 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3315 base_queue + i, msix_vect);
3317 /* set ITR0 value */
3318 if (rx_low_latency) {
3320 * Empirical configuration for optimal real time
3321 * latency reduced interrupt throttling to 2us
3323 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1);
3324 ICE_WRITE_REG(hw, QRX_ITR(base_queue + i),
3327 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3328 ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), 0);
3331 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3332 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3337 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3339 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3340 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3341 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3342 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3343 uint16_t msix_vect = vsi->msix_intr;
3344 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3345 uint16_t queue_idx = 0;
3349 /* clear Rx/Tx queue interrupt */
3350 for (i = 0; i < vsi->nb_used_qps; i++) {
3351 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3352 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3355 /* PF bind interrupt */
3356 if (rte_intr_dp_is_en(intr_handle)) {
3361 for (i = 0; i < vsi->nb_used_qps; i++) {
3363 if (!rte_intr_allow_others(intr_handle))
3364 msix_vect = ICE_MISC_VEC_ID;
3366 /* uio mapping all queue to one msix_vect */
3367 __vsi_queues_bind_intr(vsi, msix_vect,
3368 vsi->base_queue + i,
3369 vsi->nb_used_qps - i);
3371 for (; !!record && i < vsi->nb_used_qps; i++)
3372 intr_handle->intr_vec[queue_idx + i] =
3377 /* vfio 1:1 queue/msix_vect mapping */
3378 __vsi_queues_bind_intr(vsi, msix_vect,
3379 vsi->base_queue + i, 1);
3382 intr_handle->intr_vec[queue_idx + i] = msix_vect;
3390 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3392 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3393 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3394 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3395 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3396 uint16_t msix_intr, i;
3398 if (rte_intr_allow_others(intr_handle))
3399 for (i = 0; i < vsi->nb_used_qps; i++) {
3400 msix_intr = vsi->msix_intr + i;
3401 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3402 GLINT_DYN_CTL_INTENA_M |
3403 GLINT_DYN_CTL_CLEARPBA_M |
3404 GLINT_DYN_CTL_ITR_INDX_M |
3405 GLINT_DYN_CTL_WB_ON_ITR_M);
3408 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3409 GLINT_DYN_CTL_INTENA_M |
3410 GLINT_DYN_CTL_CLEARPBA_M |
3411 GLINT_DYN_CTL_ITR_INDX_M |
3412 GLINT_DYN_CTL_WB_ON_ITR_M);
3416 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3418 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3419 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3420 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3421 struct ice_vsi *vsi = pf->main_vsi;
3422 uint32_t intr_vector = 0;
3424 rte_intr_disable(intr_handle);
3426 /* check and configure queue intr-vector mapping */
3427 if ((rte_intr_cap_multiple(intr_handle) ||
3428 !RTE_ETH_DEV_SRIOV(dev).active) &&
3429 dev->data->dev_conf.intr_conf.rxq != 0) {
3430 intr_vector = dev->data->nb_rx_queues;
3431 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3432 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3433 ICE_MAX_INTR_QUEUE_NUM);
3436 if (rte_intr_efd_enable(intr_handle, intr_vector))
3440 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3441 intr_handle->intr_vec =
3442 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3444 if (!intr_handle->intr_vec) {
3446 "Failed to allocate %d rx_queues intr_vec",
3447 dev->data->nb_rx_queues);
3452 /* Map queues with MSIX interrupt */
3453 vsi->nb_used_qps = dev->data->nb_rx_queues;
3454 ice_vsi_queues_bind_intr(vsi);
3456 /* Enable interrupts for all the queues */
3457 ice_vsi_enable_queues_intr(vsi);
3459 rte_intr_enable(intr_handle);
3465 ice_get_init_link_status(struct rte_eth_dev *dev)
3467 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3468 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3469 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3470 struct ice_link_status link_status;
3473 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3474 &link_status, NULL);
3475 if (ret != ICE_SUCCESS) {
3476 PMD_DRV_LOG(ERR, "Failed to get link info");
3477 pf->init_link_up = false;
3481 if (link_status.link_info & ICE_AQ_LINK_UP)
3482 pf->init_link_up = true;
3486 ice_pps_out_cfg(struct ice_hw *hw, int idx, int timer)
3488 uint64_t current_time, start_time;
3489 uint32_t hi, lo, lo2, func, val;
3491 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3492 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer));
3493 lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3496 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3497 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer));
3500 current_time = ((uint64_t)hi << 32) | lo;
3502 start_time = (current_time + NSEC_PER_SEC) /
3503 NSEC_PER_SEC * NSEC_PER_SEC;
3504 start_time = start_time - PPS_OUT_DELAY_NS;
3506 func = 8 + idx + timer * 4;
3507 val = GLGEN_GPIO_CTL_PIN_DIR_M |
3508 ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) &
3509 GLGEN_GPIO_CTL_PIN_FUNC_M);
3511 /* Write clkout with half of period value */
3512 ICE_WRITE_REG(hw, GLTSYN_CLKO(idx, timer), NSEC_PER_SEC / 2);
3514 /* Write TARGET time register */
3515 ICE_WRITE_REG(hw, GLTSYN_TGT_L(idx, timer), start_time & 0xffffffff);
3516 ICE_WRITE_REG(hw, GLTSYN_TGT_H(idx, timer), start_time >> 32);
3518 /* Write AUX_OUT register */
3519 ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(idx, timer),
3520 GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M);
3522 /* Write GPIO CTL register */
3523 ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(idx), val);
3529 ice_dev_start(struct rte_eth_dev *dev)
3531 struct rte_eth_dev_data *data = dev->data;
3532 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3533 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3534 struct ice_vsi *vsi = pf->main_vsi;
3535 struct ice_adapter *ad =
3536 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3537 uint16_t nb_rxq = 0;
3539 uint16_t max_frame_size;
3541 uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned;
3542 uint32_t pin_idx = ad->devargs.pin_idx;
3544 /* program Tx queues' context in hardware */
3545 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3546 ret = ice_tx_queue_start(dev, nb_txq);
3548 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3553 /* program Rx queues' context in hardware*/
3554 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3555 ret = ice_rx_queue_start(dev, nb_rxq);
3557 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3562 ice_set_rx_function(dev);
3563 ice_set_tx_function(dev);
3565 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3566 ETH_VLAN_EXTEND_MASK;
3567 ret = ice_vlan_offload_set(dev, mask);
3569 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3573 /* enable Rx interrput and mapping Rx queue to interrupt vector */
3574 if (ice_rxq_intr_setup(dev))
3577 /* Enable receiving broadcast packets and transmitting packets */
3578 ret = ice_set_vsi_promisc(hw, vsi->idx,
3579 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3580 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3582 if (ret != ICE_SUCCESS)
3583 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3585 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3586 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3587 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3588 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3589 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3590 ICE_AQ_LINK_EVENT_AN_COMPLETED |
3591 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3593 if (ret != ICE_SUCCESS)
3594 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3596 ice_get_init_link_status(dev);
3598 ice_dev_set_link_up(dev);
3600 /* Call get_link_info aq commond to enable/disable LSE */
3601 ice_link_update(dev, 0);
3603 pf->adapter_stopped = false;
3605 /* Set the max frame size to default value*/
3606 max_frame_size = pf->dev_data->mtu ?
3607 pf->dev_data->mtu + ICE_ETH_OVERHEAD :
3610 /* Set the max frame size to HW*/
3611 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3613 if (ad->devargs.pps_out_ena) {
3614 ret = ice_pps_out_cfg(hw, pin_idx, timer);
3616 PMD_DRV_LOG(ERR, "Fail to configure 1pps out");
3623 /* stop the started queues if failed to start all queues */
3625 for (i = 0; i < nb_rxq; i++)
3626 ice_rx_queue_stop(dev, i);
3628 for (i = 0; i < nb_txq; i++)
3629 ice_tx_queue_stop(dev, i);
3635 ice_dev_reset(struct rte_eth_dev *dev)
3639 if (dev->data->sriov.active)
3642 ret = ice_dev_uninit(dev);
3644 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3648 ret = ice_dev_init(dev);
3650 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3658 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3660 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3661 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3662 struct ice_vsi *vsi = pf->main_vsi;
3663 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3664 bool is_safe_mode = pf->adapter->is_safe_mode;
3668 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3669 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3670 dev_info->max_rx_queues = vsi->nb_qps;
3671 dev_info->max_tx_queues = vsi->nb_qps;
3672 dev_info->max_mac_addrs = vsi->max_macaddrs;
3673 dev_info->max_vfs = pci_dev->max_vfs;
3674 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3675 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3677 dev_info->rx_offload_capa =
3678 DEV_RX_OFFLOAD_VLAN_STRIP |
3679 DEV_RX_OFFLOAD_JUMBO_FRAME |
3680 DEV_RX_OFFLOAD_KEEP_CRC |
3681 DEV_RX_OFFLOAD_SCATTER |
3682 DEV_RX_OFFLOAD_VLAN_FILTER;
3683 dev_info->tx_offload_capa =
3684 DEV_TX_OFFLOAD_VLAN_INSERT |
3685 DEV_TX_OFFLOAD_TCP_TSO |
3686 DEV_TX_OFFLOAD_MULTI_SEGS |
3687 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3688 dev_info->flow_type_rss_offloads = 0;
3690 if (!is_safe_mode) {
3691 dev_info->rx_offload_capa |=
3692 DEV_RX_OFFLOAD_IPV4_CKSUM |
3693 DEV_RX_OFFLOAD_UDP_CKSUM |
3694 DEV_RX_OFFLOAD_TCP_CKSUM |
3695 DEV_RX_OFFLOAD_QINQ_STRIP |
3696 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3697 DEV_RX_OFFLOAD_VLAN_EXTEND |
3698 DEV_RX_OFFLOAD_RSS_HASH |
3699 DEV_RX_OFFLOAD_TIMESTAMP;
3700 dev_info->tx_offload_capa |=
3701 DEV_TX_OFFLOAD_QINQ_INSERT |
3702 DEV_TX_OFFLOAD_IPV4_CKSUM |
3703 DEV_TX_OFFLOAD_UDP_CKSUM |
3704 DEV_TX_OFFLOAD_TCP_CKSUM |
3705 DEV_TX_OFFLOAD_SCTP_CKSUM |
3706 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3707 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3708 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3711 dev_info->rx_queue_offload_capa = 0;
3712 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3714 dev_info->reta_size = pf->hash_lut_size;
3715 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3717 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3719 .pthresh = ICE_DEFAULT_RX_PTHRESH,
3720 .hthresh = ICE_DEFAULT_RX_HTHRESH,
3721 .wthresh = ICE_DEFAULT_RX_WTHRESH,
3723 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3728 dev_info->default_txconf = (struct rte_eth_txconf) {
3730 .pthresh = ICE_DEFAULT_TX_PTHRESH,
3731 .hthresh = ICE_DEFAULT_TX_HTHRESH,
3732 .wthresh = ICE_DEFAULT_TX_WTHRESH,
3734 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3735 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3739 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3740 .nb_max = ICE_MAX_RING_DESC,
3741 .nb_min = ICE_MIN_RING_DESC,
3742 .nb_align = ICE_ALIGN_RING_DESC,
3745 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3746 .nb_max = ICE_MAX_RING_DESC,
3747 .nb_min = ICE_MIN_RING_DESC,
3748 .nb_align = ICE_ALIGN_RING_DESC,
3751 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3752 ETH_LINK_SPEED_100M |
3754 ETH_LINK_SPEED_2_5G |
3756 ETH_LINK_SPEED_10G |
3757 ETH_LINK_SPEED_20G |
3760 phy_type_low = hw->port_info->phy.phy_type_low;
3761 phy_type_high = hw->port_info->phy.phy_type_high;
3763 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3764 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3766 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3767 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3768 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3770 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3771 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3773 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3774 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3775 dev_info->default_rxportconf.nb_queues = 1;
3776 dev_info->default_txportconf.nb_queues = 1;
3777 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3778 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3784 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3785 struct rte_eth_link *link)
3787 struct rte_eth_link *dst = link;
3788 struct rte_eth_link *src = &dev->data->dev_link;
3790 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3791 *(uint64_t *)src) == 0)
3798 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3799 struct rte_eth_link *link)
3801 struct rte_eth_link *dst = &dev->data->dev_link;
3802 struct rte_eth_link *src = link;
3804 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3805 *(uint64_t *)src) == 0)
3812 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3814 #define CHECK_INTERVAL 100 /* 100ms */
3815 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3816 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3817 struct ice_link_status link_status;
3818 struct rte_eth_link link, old;
3820 unsigned int rep_cnt = MAX_REPEAT_TIME;
3821 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3823 memset(&link, 0, sizeof(link));
3824 memset(&old, 0, sizeof(old));
3825 memset(&link_status, 0, sizeof(link_status));
3826 ice_atomic_read_link_status(dev, &old);
3829 /* Get link status information from hardware */
3830 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3831 &link_status, NULL);
3832 if (status != ICE_SUCCESS) {
3833 link.link_speed = ETH_SPEED_NUM_100M;
3834 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3835 PMD_DRV_LOG(ERR, "Failed to get link info");
3839 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3840 if (!wait_to_complete || link.link_status)
3843 rte_delay_ms(CHECK_INTERVAL);
3844 } while (--rep_cnt);
3846 if (!link.link_status)
3849 /* Full-duplex operation at all supported speeds */
3850 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3852 /* Parse the link status */
3853 switch (link_status.link_speed) {
3854 case ICE_AQ_LINK_SPEED_10MB:
3855 link.link_speed = ETH_SPEED_NUM_10M;
3857 case ICE_AQ_LINK_SPEED_100MB:
3858 link.link_speed = ETH_SPEED_NUM_100M;
3860 case ICE_AQ_LINK_SPEED_1000MB:
3861 link.link_speed = ETH_SPEED_NUM_1G;
3863 case ICE_AQ_LINK_SPEED_2500MB:
3864 link.link_speed = ETH_SPEED_NUM_2_5G;
3866 case ICE_AQ_LINK_SPEED_5GB:
3867 link.link_speed = ETH_SPEED_NUM_5G;
3869 case ICE_AQ_LINK_SPEED_10GB:
3870 link.link_speed = ETH_SPEED_NUM_10G;
3872 case ICE_AQ_LINK_SPEED_20GB:
3873 link.link_speed = ETH_SPEED_NUM_20G;
3875 case ICE_AQ_LINK_SPEED_25GB:
3876 link.link_speed = ETH_SPEED_NUM_25G;
3878 case ICE_AQ_LINK_SPEED_40GB:
3879 link.link_speed = ETH_SPEED_NUM_40G;
3881 case ICE_AQ_LINK_SPEED_50GB:
3882 link.link_speed = ETH_SPEED_NUM_50G;
3884 case ICE_AQ_LINK_SPEED_100GB:
3885 link.link_speed = ETH_SPEED_NUM_100G;
3887 case ICE_AQ_LINK_SPEED_UNKNOWN:
3888 PMD_DRV_LOG(ERR, "Unknown link speed");
3889 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3892 PMD_DRV_LOG(ERR, "None link speed");
3893 link.link_speed = ETH_SPEED_NUM_NONE;
3897 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3898 ETH_LINK_SPEED_FIXED);
3901 ice_atomic_write_link_status(dev, &link);
3902 if (link.link_status == old.link_status)
3908 /* Force the physical link state by getting the current PHY capabilities from
3909 * hardware and setting the PHY config based on the determined capabilities. If
3910 * link changes, link event will be triggered because both the Enable Automatic
3911 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3913 static enum ice_status
3914 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3916 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3917 struct ice_aqc_get_phy_caps_data *pcaps;
3918 struct ice_port_info *pi;
3919 enum ice_status status;
3921 if (!hw || !hw->port_info)
3922 return ICE_ERR_PARAM;
3926 pcaps = (struct ice_aqc_get_phy_caps_data *)
3927 ice_malloc(hw, sizeof(*pcaps));
3929 return ICE_ERR_NO_MEMORY;
3931 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3936 /* No change in link */
3937 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3938 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3941 cfg.phy_type_low = pcaps->phy_type_low;
3942 cfg.phy_type_high = pcaps->phy_type_high;
3943 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3944 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3945 cfg.eee_cap = pcaps->eee_cap;
3946 cfg.eeer_value = pcaps->eeer_value;
3947 cfg.link_fec_opt = pcaps->link_fec_options;
3949 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3951 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3953 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3956 ice_free(hw, pcaps);
3961 ice_dev_set_link_up(struct rte_eth_dev *dev)
3963 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3965 return ice_force_phys_link_state(hw, true);
3969 ice_dev_set_link_down(struct rte_eth_dev *dev)
3971 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3973 return ice_force_phys_link_state(hw, false);
3977 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu __rte_unused)
3979 /* mtu setting is forbidden if port is start */
3980 if (dev->data->dev_started != 0) {
3982 "port %d must be stopped before configuration",
3983 dev->data->port_id);
3990 static int ice_macaddr_set(struct rte_eth_dev *dev,
3991 struct rte_ether_addr *mac_addr)
3993 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3994 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3995 struct ice_vsi *vsi = pf->main_vsi;
3996 struct ice_mac_filter *f;
4000 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
4001 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
4005 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4006 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
4011 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
4015 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
4016 if (ret != ICE_SUCCESS) {
4017 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
4020 ret = ice_add_mac_filter(vsi, mac_addr);
4021 if (ret != ICE_SUCCESS) {
4022 PMD_DRV_LOG(ERR, "Failed to add mac filter");
4025 rte_ether_addr_copy(mac_addr, &pf->dev_addr);
4027 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
4028 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
4029 if (ret != ICE_SUCCESS)
4030 PMD_DRV_LOG(ERR, "Failed to set manage mac");
4035 /* Add a MAC address, and update filters */
4037 ice_macaddr_add(struct rte_eth_dev *dev,
4038 struct rte_ether_addr *mac_addr,
4039 __rte_unused uint32_t index,
4040 __rte_unused uint32_t pool)
4042 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4043 struct ice_vsi *vsi = pf->main_vsi;
4046 ret = ice_add_mac_filter(vsi, mac_addr);
4047 if (ret != ICE_SUCCESS) {
4048 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
4055 /* Remove a MAC address, and update filters */
4057 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4059 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4060 struct ice_vsi *vsi = pf->main_vsi;
4061 struct rte_eth_dev_data *data = dev->data;
4062 struct rte_ether_addr *macaddr;
4065 macaddr = &data->mac_addrs[index];
4066 ret = ice_remove_mac_filter(vsi, macaddr);
4068 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
4074 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4076 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4077 struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
4078 struct ice_vsi *vsi = pf->main_vsi;
4081 PMD_INIT_FUNC_TRACE();
4084 * Vlan 0 is the generic filter for untagged packets
4085 * and can't be removed or added by user.
4091 ret = ice_add_vlan_filter(vsi, &vlan);
4093 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
4097 ret = ice_remove_vlan_filter(vsi, &vlan);
4099 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
4107 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
4108 * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
4109 * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
4110 * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
4112 * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
4113 * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
4114 * traffic in SVM, since the VLAN TPID isn't part of filtering.
4116 * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
4117 * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
4118 * part of filtering.
4121 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
4123 struct ice_vlan vlan;
4126 vlan = ICE_VLAN(0, 0);
4127 err = ice_add_vlan_filter(vsi, &vlan);
4129 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
4133 /* in SVM both VLAN 0 filters are identical */
4134 if (!ice_is_dvm_ena(&vsi->adapter->hw))
4137 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4138 err = ice_add_vlan_filter(vsi, &vlan);
4140 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
4148 * Delete the VLAN 0 filters in the same manner that they were added in
4149 * ice_vsi_add_vlan_zero.
4152 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
4154 struct ice_vlan vlan;
4157 vlan = ICE_VLAN(0, 0);
4158 err = ice_remove_vlan_filter(vsi, &vlan);
4160 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
4164 /* in SVM both VLAN 0 filters are identical */
4165 if (!ice_is_dvm_ena(&vsi->adapter->hw))
4168 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4169 err = ice_remove_vlan_filter(vsi, &vlan);
4171 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
4178 /* Configure vlan filter on or off */
4180 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4182 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4183 struct ice_vsi_ctx ctxt;
4187 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4190 vsi->info.sw_flags2 |= sw_flags2;
4192 vsi->info.sw_flags2 &= ~sw_flags2;
4194 vsi->info.sw_id = hw->port_info->sw_id;
4195 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4196 ctxt.info.valid_sections =
4197 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4198 ICE_AQ_VSI_PROP_SECURITY_VALID);
4199 ctxt.vsi_num = vsi->vsi_id;
4201 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4203 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4204 on ? "enable" : "disable");
4207 vsi->info.valid_sections |=
4208 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4209 ICE_AQ_VSI_PROP_SECURITY_VALID);
4212 /* consist with other drivers, allow untagged packet when vlan filter on */
4214 ret = ice_vsi_add_vlan_zero(vsi);
4216 ret = ice_vsi_del_vlan_zero(vsi);
4221 /* Manage VLAN stripping for the VSI for Rx */
4223 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4225 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4226 struct ice_vsi_ctx ctxt;
4227 enum ice_status status;
4230 /* do not allow modifying VLAN stripping when a port VLAN is configured
4233 if (vsi->info.port_based_inner_vlan)
4236 memset(&ctxt, 0, sizeof(ctxt));
4239 /* Strip VLAN tag from Rx packet and put it in the desc */
4240 ctxt.info.inner_vlan_flags =
4241 ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4243 /* Disable stripping. Leave tag in packet */
4244 ctxt.info.inner_vlan_flags =
4245 ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4247 /* Allow all packets untagged/tagged */
4248 ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4250 ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4252 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4254 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4255 ena ? "enable" : "disable");
4258 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4265 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4267 return ice_vsi_manage_vlan_stripping(vsi, true);
4271 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4273 return ice_vsi_manage_vlan_stripping(vsi, false);
4276 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4278 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4279 struct ice_vsi_ctx ctxt;
4280 enum ice_status status;
4283 /* do not allow modifying VLAN stripping when a port VLAN is configured
4286 if (vsi->info.port_based_outer_vlan)
4289 memset(&ctxt, 0, sizeof(ctxt));
4291 ctxt.info.valid_sections =
4292 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4293 /* clear current outer VLAN strip settings */
4294 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4295 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4296 ctxt.info.outer_vlan_flags |=
4297 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4298 ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4299 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4300 ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4302 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4304 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4307 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4314 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4316 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4317 struct ice_vsi_ctx ctxt;
4318 enum ice_status status;
4321 if (vsi->info.port_based_outer_vlan)
4324 memset(&ctxt, 0, sizeof(ctxt));
4326 ctxt.info.valid_sections =
4327 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4328 /* clear current outer VLAN strip settings */
4329 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4330 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4331 ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4332 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4334 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4336 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4339 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4346 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4348 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4351 if (ice_is_dvm_ena(hw)) {
4353 ret = ice_vsi_ena_outer_stripping(vsi);
4355 ret = ice_vsi_dis_outer_stripping(vsi);
4358 ret = ice_vsi_ena_inner_stripping(vsi);
4360 ret = ice_vsi_dis_inner_stripping(vsi);
4367 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4369 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4370 struct ice_vsi *vsi = pf->main_vsi;
4371 struct rte_eth_rxmode *rxmode;
4373 rxmode = &dev->data->dev_conf.rxmode;
4374 if (mask & ETH_VLAN_FILTER_MASK) {
4375 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4376 ice_vsi_config_vlan_filter(vsi, true);
4378 ice_vsi_config_vlan_filter(vsi, false);
4381 if (mask & ETH_VLAN_STRIP_MASK) {
4382 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4383 ice_vsi_config_vlan_stripping(vsi, true);
4385 ice_vsi_config_vlan_stripping(vsi, false);
4392 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4394 struct ice_aq_get_set_rss_lut_params lut_params;
4395 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4396 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4402 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4403 lut_params.vsi_handle = vsi->idx;
4404 lut_params.lut_size = lut_size;
4405 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4406 lut_params.lut = lut;
4407 lut_params.global_lut_id = 0;
4408 ret = ice_aq_get_rss_lut(hw, &lut_params);
4410 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4414 uint64_t *lut_dw = (uint64_t *)lut;
4415 uint16_t i, lut_size_dw = lut_size / 4;
4417 for (i = 0; i < lut_size_dw; i++)
4418 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4425 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4427 struct ice_aq_get_set_rss_lut_params lut_params;
4435 pf = ICE_VSI_TO_PF(vsi);
4436 hw = ICE_VSI_TO_HW(vsi);
4438 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4439 lut_params.vsi_handle = vsi->idx;
4440 lut_params.lut_size = lut_size;
4441 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4442 lut_params.lut = lut;
4443 lut_params.global_lut_id = 0;
4444 ret = ice_aq_set_rss_lut(hw, &lut_params);
4446 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4450 uint64_t *lut_dw = (uint64_t *)lut;
4451 uint16_t i, lut_size_dw = lut_size / 4;
4453 for (i = 0; i < lut_size_dw; i++)
4454 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4463 ice_rss_reta_update(struct rte_eth_dev *dev,
4464 struct rte_eth_rss_reta_entry64 *reta_conf,
4467 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4468 uint16_t i, lut_size = pf->hash_lut_size;
4469 uint16_t idx, shift;
4473 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4474 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4475 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4477 "The size of hash lookup table configured (%d)"
4478 "doesn't match the number hardware can "
4479 "supported (128, 512, 2048)",
4484 /* It MUST use the current LUT size to get the RSS lookup table,
4485 * otherwise if will fail with -100 error code.
4487 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
4489 PMD_DRV_LOG(ERR, "No memory can be allocated");
4492 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4496 for (i = 0; i < reta_size; i++) {
4497 idx = i / RTE_RETA_GROUP_SIZE;
4498 shift = i % RTE_RETA_GROUP_SIZE;
4499 if (reta_conf[idx].mask & (1ULL << shift))
4500 lut[i] = reta_conf[idx].reta[shift];
4502 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4503 if (ret == 0 && lut_size != reta_size) {
4505 "The size of hash lookup table is changed from (%d) to (%d)",
4506 lut_size, reta_size);
4507 pf->hash_lut_size = reta_size;
4517 ice_rss_reta_query(struct rte_eth_dev *dev,
4518 struct rte_eth_rss_reta_entry64 *reta_conf,
4521 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4522 uint16_t i, lut_size = pf->hash_lut_size;
4523 uint16_t idx, shift;
4527 if (reta_size != lut_size) {
4529 "The size of hash lookup table configured (%d)"
4530 "doesn't match the number hardware can "
4532 reta_size, lut_size);
4536 lut = rte_zmalloc(NULL, reta_size, 0);
4538 PMD_DRV_LOG(ERR, "No memory can be allocated");
4542 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4546 for (i = 0; i < reta_size; i++) {
4547 idx = i / RTE_RETA_GROUP_SIZE;
4548 shift = i % RTE_RETA_GROUP_SIZE;
4549 if (reta_conf[idx].mask & (1ULL << shift))
4550 reta_conf[idx].reta[shift] = lut[i];
4560 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4562 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4565 if (!key || key_len == 0) {
4566 PMD_DRV_LOG(DEBUG, "No key to be configured");
4568 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4570 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4574 struct ice_aqc_get_set_rss_keys *key_dw =
4575 (struct ice_aqc_get_set_rss_keys *)key;
4577 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4579 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4587 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4589 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4592 if (!key || !key_len)
4595 ret = ice_aq_get_rss_key
4597 (struct ice_aqc_get_set_rss_keys *)key);
4599 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4602 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4608 ice_rss_hash_update(struct rte_eth_dev *dev,
4609 struct rte_eth_rss_conf *rss_conf)
4611 enum ice_status status = ICE_SUCCESS;
4612 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4613 struct ice_vsi *vsi = pf->main_vsi;
4616 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4620 if (rss_conf->rss_hf == 0) {
4625 /* RSS hash configuration */
4626 ice_rss_hash_set(pf, rss_conf->rss_hf);
4632 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4633 struct rte_eth_rss_conf *rss_conf)
4635 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4636 struct ice_vsi *vsi = pf->main_vsi;
4638 ice_get_rss_key(vsi, rss_conf->rss_key,
4639 &rss_conf->rss_key_len);
4641 rss_conf->rss_hf = pf->rss_hf;
4646 ice_promisc_enable(struct rte_eth_dev *dev)
4648 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4649 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4650 struct ice_vsi *vsi = pf->main_vsi;
4651 enum ice_status status;
4655 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4656 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4658 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4660 case ICE_ERR_ALREADY_EXISTS:
4661 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4665 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4673 ice_promisc_disable(struct rte_eth_dev *dev)
4675 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4676 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677 struct ice_vsi *vsi = pf->main_vsi;
4678 enum ice_status status;
4682 if (dev->data->all_multicast == 1)
4683 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX;
4685 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4686 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4688 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4689 if (status != ICE_SUCCESS) {
4690 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4698 ice_allmulti_enable(struct rte_eth_dev *dev)
4700 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4701 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702 struct ice_vsi *vsi = pf->main_vsi;
4703 enum ice_status status;
4707 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4709 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4712 case ICE_ERR_ALREADY_EXISTS:
4713 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4717 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4725 ice_allmulti_disable(struct rte_eth_dev *dev)
4727 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4728 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4729 struct ice_vsi *vsi = pf->main_vsi;
4730 enum ice_status status;
4734 if (dev->data->promiscuous == 1)
4735 return 0; /* must remain in all_multicast mode */
4737 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4739 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4740 if (status != ICE_SUCCESS) {
4741 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4748 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4751 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4752 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4753 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4757 msix_intr = intr_handle->intr_vec[queue_id];
4759 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4760 GLINT_DYN_CTL_ITR_INDX_M;
4761 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4763 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4764 rte_intr_ack(&pci_dev->intr_handle);
4769 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4772 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4773 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4774 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4777 msix_intr = intr_handle->intr_vec[queue_id];
4779 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4785 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4787 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4792 ver = hw->flash.orom.major;
4793 patch = hw->flash.orom.patch;
4794 build = hw->flash.orom.build;
4796 ret = snprintf(fw_version, fw_size,
4797 "%x.%02x 0x%08x %d.%d.%d",
4798 hw->flash.nvm.major,
4799 hw->flash.nvm.minor,
4800 hw->flash.nvm.eetrack,
4805 /* add the size of '\0' */
4807 if (fw_size < (size_t)ret)
4814 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4817 struct ice_vsi_ctx ctxt;
4818 uint8_t vlan_flags = 0;
4821 if (!vsi || !info) {
4822 PMD_DRV_LOG(ERR, "invalid parameters");
4827 vsi->info.port_based_inner_vlan = info->config.pvid;
4829 * If insert pvid is enabled, only tagged pkts are
4830 * allowed to be sent out.
4832 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4833 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4835 vsi->info.port_based_inner_vlan = 0;
4836 if (info->config.reject.tagged == 0)
4837 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4839 if (info->config.reject.untagged == 0)
4840 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4842 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4843 ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4844 vsi->info.inner_vlan_flags |= vlan_flags;
4845 memset(&ctxt, 0, sizeof(ctxt));
4846 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4847 ctxt.info.valid_sections =
4848 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4849 ctxt.vsi_num = vsi->vsi_id;
4851 hw = ICE_VSI_TO_HW(vsi);
4852 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4853 if (ret != ICE_SUCCESS) {
4855 "update VSI for VLAN insert failed, err %d",
4860 vsi->info.valid_sections |=
4861 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4867 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4869 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4870 struct ice_vsi *vsi = pf->main_vsi;
4871 struct rte_eth_dev_data *data = pf->dev_data;
4872 struct ice_vsi_vlan_pvid_info info;
4875 memset(&info, 0, sizeof(info));
4878 info.config.pvid = pvid;
4880 info.config.reject.tagged =
4881 data->dev_conf.txmode.hw_vlan_reject_tagged;
4882 info.config.reject.untagged =
4883 data->dev_conf.txmode.hw_vlan_reject_untagged;
4886 ret = ice_vsi_vlan_pvid_set(vsi, &info);
4888 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4896 ice_get_eeprom_length(struct rte_eth_dev *dev)
4898 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4900 return hw->flash.flash_size;
4904 ice_get_eeprom(struct rte_eth_dev *dev,
4905 struct rte_dev_eeprom_info *eeprom)
4907 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4908 enum ice_status status = ICE_SUCCESS;
4909 uint8_t *data = eeprom->data;
4911 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4913 status = ice_acquire_nvm(hw, ICE_RES_READ);
4915 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4919 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4922 ice_release_nvm(hw);
4925 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4933 ice_stat_update_32(struct ice_hw *hw,
4941 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4945 if (new_data >= *offset)
4946 *stat = (uint64_t)(new_data - *offset);
4948 *stat = (uint64_t)((new_data +
4949 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4954 ice_stat_update_40(struct ice_hw *hw,
4963 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4964 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4970 if (new_data >= *offset)
4971 *stat = new_data - *offset;
4973 *stat = (uint64_t)((new_data +
4974 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4977 *stat &= ICE_40_BIT_MASK;
4980 /* Get all the statistics of a VSI */
4982 ice_update_vsi_stats(struct ice_vsi *vsi)
4984 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4985 struct ice_eth_stats *nes = &vsi->eth_stats;
4986 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4987 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4989 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4990 vsi->offset_loaded, &oes->rx_bytes,
4992 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4993 vsi->offset_loaded, &oes->rx_unicast,
4995 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4996 vsi->offset_loaded, &oes->rx_multicast,
4997 &nes->rx_multicast);
4998 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4999 vsi->offset_loaded, &oes->rx_broadcast,
5000 &nes->rx_broadcast);
5001 /* enlarge the limitation when rx_bytes overflowed */
5002 if (vsi->offset_loaded) {
5003 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
5004 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5005 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
5007 vsi->old_rx_bytes = nes->rx_bytes;
5008 /* exclude CRC bytes */
5009 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
5010 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
5012 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
5013 &oes->rx_discards, &nes->rx_discards);
5014 /* GLV_REPC not supported */
5015 /* GLV_RMPC not supported */
5016 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
5017 &oes->rx_unknown_protocol,
5018 &nes->rx_unknown_protocol);
5019 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
5020 vsi->offset_loaded, &oes->tx_bytes,
5022 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
5023 vsi->offset_loaded, &oes->tx_unicast,
5025 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
5026 vsi->offset_loaded, &oes->tx_multicast,
5027 &nes->tx_multicast);
5028 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
5029 vsi->offset_loaded, &oes->tx_broadcast,
5030 &nes->tx_broadcast);
5031 /* GLV_TDPC not supported */
5032 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
5033 &oes->tx_errors, &nes->tx_errors);
5034 /* enlarge the limitation when tx_bytes overflowed */
5035 if (vsi->offset_loaded) {
5036 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
5037 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5038 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
5040 vsi->old_tx_bytes = nes->tx_bytes;
5041 vsi->offset_loaded = true;
5043 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
5045 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
5046 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
5047 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
5048 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
5049 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
5050 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5051 nes->rx_unknown_protocol);
5052 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
5053 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
5054 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
5055 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
5056 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
5057 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
5058 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
5063 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
5065 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5066 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
5068 /* Get statistics of struct ice_eth_stats */
5069 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
5070 GLPRT_GORCL(hw->port_info->lport),
5071 pf->offset_loaded, &os->eth.rx_bytes,
5073 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
5074 GLPRT_UPRCL(hw->port_info->lport),
5075 pf->offset_loaded, &os->eth.rx_unicast,
5076 &ns->eth.rx_unicast);
5077 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
5078 GLPRT_MPRCL(hw->port_info->lport),
5079 pf->offset_loaded, &os->eth.rx_multicast,
5080 &ns->eth.rx_multicast);
5081 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
5082 GLPRT_BPRCL(hw->port_info->lport),
5083 pf->offset_loaded, &os->eth.rx_broadcast,
5084 &ns->eth.rx_broadcast);
5085 ice_stat_update_32(hw, PRTRPB_RDPC,
5086 pf->offset_loaded, &os->eth.rx_discards,
5087 &ns->eth.rx_discards);
5088 /* enlarge the limitation when rx_bytes overflowed */
5089 if (pf->offset_loaded) {
5090 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
5091 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5092 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
5094 pf->old_rx_bytes = ns->eth.rx_bytes;
5096 /* Workaround: CRC size should not be included in byte statistics,
5097 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
5100 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
5101 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
5103 /* GLPRT_REPC not supported */
5104 /* GLPRT_RMPC not supported */
5105 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
5107 &os->eth.rx_unknown_protocol,
5108 &ns->eth.rx_unknown_protocol);
5109 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
5110 GLPRT_GOTCL(hw->port_info->lport),
5111 pf->offset_loaded, &os->eth.tx_bytes,
5113 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
5114 GLPRT_UPTCL(hw->port_info->lport),
5115 pf->offset_loaded, &os->eth.tx_unicast,
5116 &ns->eth.tx_unicast);
5117 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
5118 GLPRT_MPTCL(hw->port_info->lport),
5119 pf->offset_loaded, &os->eth.tx_multicast,
5120 &ns->eth.tx_multicast);
5121 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
5122 GLPRT_BPTCL(hw->port_info->lport),
5123 pf->offset_loaded, &os->eth.tx_broadcast,
5124 &ns->eth.tx_broadcast);
5125 /* enlarge the limitation when tx_bytes overflowed */
5126 if (pf->offset_loaded) {
5127 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
5128 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5129 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
5131 pf->old_tx_bytes = ns->eth.tx_bytes;
5132 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
5133 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
5135 /* GLPRT_TEPC not supported */
5137 /* additional port specific stats */
5138 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
5139 pf->offset_loaded, &os->tx_dropped_link_down,
5140 &ns->tx_dropped_link_down);
5141 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
5142 pf->offset_loaded, &os->crc_errors,
5144 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
5145 pf->offset_loaded, &os->illegal_bytes,
5146 &ns->illegal_bytes);
5147 /* GLPRT_ERRBC not supported */
5148 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
5149 pf->offset_loaded, &os->mac_local_faults,
5150 &ns->mac_local_faults);
5151 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
5152 pf->offset_loaded, &os->mac_remote_faults,
5153 &ns->mac_remote_faults);
5155 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
5156 pf->offset_loaded, &os->rx_len_errors,
5157 &ns->rx_len_errors);
5159 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
5160 pf->offset_loaded, &os->link_xon_rx,
5162 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
5163 pf->offset_loaded, &os->link_xoff_rx,
5165 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
5166 pf->offset_loaded, &os->link_xon_tx,
5168 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
5169 pf->offset_loaded, &os->link_xoff_tx,
5171 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
5172 GLPRT_PRC64L(hw->port_info->lport),
5173 pf->offset_loaded, &os->rx_size_64,
5175 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
5176 GLPRT_PRC127L(hw->port_info->lport),
5177 pf->offset_loaded, &os->rx_size_127,
5179 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
5180 GLPRT_PRC255L(hw->port_info->lport),
5181 pf->offset_loaded, &os->rx_size_255,
5183 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
5184 GLPRT_PRC511L(hw->port_info->lport),
5185 pf->offset_loaded, &os->rx_size_511,
5187 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
5188 GLPRT_PRC1023L(hw->port_info->lport),
5189 pf->offset_loaded, &os->rx_size_1023,
5191 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
5192 GLPRT_PRC1522L(hw->port_info->lport),
5193 pf->offset_loaded, &os->rx_size_1522,
5195 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
5196 GLPRT_PRC9522L(hw->port_info->lport),
5197 pf->offset_loaded, &os->rx_size_big,
5199 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
5200 pf->offset_loaded, &os->rx_undersize,
5202 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
5203 pf->offset_loaded, &os->rx_fragments,
5205 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5206 pf->offset_loaded, &os->rx_oversize,
5208 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5209 pf->offset_loaded, &os->rx_jabber,
5211 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5212 GLPRT_PTC64L(hw->port_info->lport),
5213 pf->offset_loaded, &os->tx_size_64,
5215 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5216 GLPRT_PTC127L(hw->port_info->lport),
5217 pf->offset_loaded, &os->tx_size_127,
5219 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5220 GLPRT_PTC255L(hw->port_info->lport),
5221 pf->offset_loaded, &os->tx_size_255,
5223 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5224 GLPRT_PTC511L(hw->port_info->lport),
5225 pf->offset_loaded, &os->tx_size_511,
5227 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5228 GLPRT_PTC1023L(hw->port_info->lport),
5229 pf->offset_loaded, &os->tx_size_1023,
5231 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5232 GLPRT_PTC1522L(hw->port_info->lport),
5233 pf->offset_loaded, &os->tx_size_1522,
5235 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5236 GLPRT_PTC9522L(hw->port_info->lport),
5237 pf->offset_loaded, &os->tx_size_big,
5240 /* GLPRT_MSPDC not supported */
5241 /* GLPRT_XEC not supported */
5243 pf->offset_loaded = true;
5246 ice_update_vsi_stats(pf->main_vsi);
5249 /* Get all statistics of a port */
5251 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5253 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5254 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5255 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5257 /* call read registers - updates values, now write them to struct */
5258 ice_read_stats_registers(pf, hw);
5260 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5261 pf->main_vsi->eth_stats.rx_multicast +
5262 pf->main_vsi->eth_stats.rx_broadcast -
5263 pf->main_vsi->eth_stats.rx_discards;
5264 stats->opackets = ns->eth.tx_unicast +
5265 ns->eth.tx_multicast +
5266 ns->eth.tx_broadcast;
5267 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
5268 stats->obytes = ns->eth.tx_bytes;
5269 stats->oerrors = ns->eth.tx_errors +
5270 pf->main_vsi->eth_stats.tx_errors;
5273 stats->imissed = ns->eth.rx_discards +
5274 pf->main_vsi->eth_stats.rx_discards;
5275 stats->ierrors = ns->crc_errors +
5277 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5279 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5280 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
5281 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5282 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5283 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5284 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5285 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5286 pf->main_vsi->eth_stats.rx_discards);
5287 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5288 ns->eth.rx_unknown_protocol);
5289 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
5290 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5291 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5292 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5293 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5294 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5295 pf->main_vsi->eth_stats.tx_discards);
5296 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
5298 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
5299 ns->tx_dropped_link_down);
5300 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5301 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
5303 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
5304 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
5305 ns->mac_local_faults);
5306 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
5307 ns->mac_remote_faults);
5308 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
5309 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
5310 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
5311 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
5312 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
5313 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
5314 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
5315 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
5316 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
5317 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
5318 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
5319 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
5320 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
5321 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
5322 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
5323 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
5324 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
5325 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
5326 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
5327 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
5328 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
5329 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
5330 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
5331 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5335 /* Reset the statistics */
5337 ice_stats_reset(struct rte_eth_dev *dev)
5339 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5340 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5342 /* Mark PF and VSI stats to update the offset, aka "reset" */
5343 pf->offset_loaded = false;
5345 pf->main_vsi->offset_loaded = false;
5347 /* read the stats, reading current register values into offset */
5348 ice_read_stats_registers(pf, hw);
5354 ice_xstats_calc_num(void)
5358 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5364 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5367 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5368 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5371 struct ice_hw_port_stats *hw_stats = &pf->stats;
5373 count = ice_xstats_calc_num();
5377 ice_read_stats_registers(pf, hw);
5384 /* Get stats from ice_eth_stats struct */
5385 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5386 xstats[count].value =
5387 *(uint64_t *)((char *)&hw_stats->eth +
5388 ice_stats_strings[i].offset);
5389 xstats[count].id = count;
5393 /* Get individiual stats from ice_hw_port struct */
5394 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5395 xstats[count].value =
5396 *(uint64_t *)((char *)hw_stats +
5397 ice_hw_port_strings[i].offset);
5398 xstats[count].id = count;
5405 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5406 struct rte_eth_xstat_name *xstats_names,
5407 __rte_unused unsigned int limit)
5409 unsigned int count = 0;
5413 return ice_xstats_calc_num();
5415 /* Note: limit checked in rte_eth_xstats_names() */
5417 /* Get stats from ice_eth_stats struct */
5418 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5419 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5420 sizeof(xstats_names[count].name));
5424 /* Get individiual stats from ice_hw_port struct */
5425 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5426 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5427 sizeof(xstats_names[count].name));
5435 ice_dev_flow_ops_get(struct rte_eth_dev *dev,
5436 const struct rte_flow_ops **ops)
5441 *ops = &ice_flow_ops;
5445 /* Add UDP tunneling port */
5447 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5448 struct rte_eth_udp_tunnel *udp_tunnel)
5451 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5453 if (udp_tunnel == NULL)
5456 switch (udp_tunnel->prot_type) {
5457 case RTE_TUNNEL_TYPE_VXLAN:
5458 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5461 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5469 /* Delete UDP tunneling port */
5471 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5472 struct rte_eth_udp_tunnel *udp_tunnel)
5475 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5477 if (udp_tunnel == NULL)
5480 switch (udp_tunnel->prot_type) {
5481 case RTE_TUNNEL_TYPE_VXLAN:
5482 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5485 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5494 ice_timesync_enable(struct rte_eth_dev *dev)
5496 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5497 struct ice_adapter *ad =
5498 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5501 if (dev->data->dev_started && !(dev->data->dev_conf.rxmode.offloads &
5502 DEV_RX_OFFLOAD_TIMESTAMP)) {
5503 PMD_DRV_LOG(ERR, "Rx timestamp offload not configured");
5507 if (hw->func_caps.ts_func_info.src_tmr_owned) {
5508 ret = ice_ptp_init_phc(hw);
5510 PMD_DRV_LOG(ERR, "Failed to initialize PHC");
5514 ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810);
5517 "Failed to write PHC increment time value");
5522 /* Initialize cycle counters for system time/RX/TX timestamp */
5523 memset(&ad->systime_tc, 0, sizeof(struct rte_timecounter));
5524 memset(&ad->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5525 memset(&ad->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5527 ad->systime_tc.cc_mask = ICE_CYCLECOUNTER_MASK;
5528 ad->systime_tc.cc_shift = 0;
5529 ad->systime_tc.nsec_mask = 0;
5531 ad->rx_tstamp_tc.cc_mask = ICE_CYCLECOUNTER_MASK;
5532 ad->rx_tstamp_tc.cc_shift = 0;
5533 ad->rx_tstamp_tc.nsec_mask = 0;
5535 ad->tx_tstamp_tc.cc_mask = ICE_CYCLECOUNTER_MASK;
5536 ad->tx_tstamp_tc.cc_shift = 0;
5537 ad->tx_tstamp_tc.nsec_mask = 0;
5545 ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5546 struct timespec *timestamp, uint32_t flags)
5548 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5549 struct ice_adapter *ad =
5550 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5551 struct ice_rx_queue *rxq;
5555 rxq = dev->data->rx_queues[flags];
5557 ts_high = rxq->time_high;
5558 ts_ns = ice_tstamp_convert_32b_64b(hw, ts_high);
5559 ns = rte_timecounter_update(&ad->rx_tstamp_tc, ts_ns);
5560 *timestamp = rte_ns_to_timespec(ns);
5566 ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5567 struct timespec *timestamp)
5569 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5570 struct ice_adapter *ad =
5571 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5573 uint64_t ts_ns, ns, tstamp;
5574 const uint64_t mask = 0xFFFFFFFF;
5577 lport = hw->port_info->lport;
5579 ret = ice_read_phy_tstamp(hw, lport, 0, &tstamp);
5581 PMD_DRV_LOG(ERR, "Failed to read phy timestamp");
5585 ts_ns = ice_tstamp_convert_32b_64b(hw, (tstamp >> 8) & mask);
5586 ns = rte_timecounter_update(&ad->tx_tstamp_tc, ts_ns);
5587 *timestamp = rte_ns_to_timespec(ns);
5593 ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5595 struct ice_adapter *ad =
5596 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5598 ad->systime_tc.nsec += delta;
5599 ad->rx_tstamp_tc.nsec += delta;
5600 ad->tx_tstamp_tc.nsec += delta;
5606 ice_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5608 struct ice_adapter *ad =
5609 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5612 ns = rte_timespec_to_ns(ts);
5614 ad->systime_tc.nsec = ns;
5615 ad->rx_tstamp_tc.nsec = ns;
5616 ad->tx_tstamp_tc.nsec = ns;
5622 ice_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5624 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5625 struct ice_adapter *ad =
5626 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5627 uint32_t hi, lo, lo2;
5630 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(0));
5631 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(0));
5632 lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(0));
5635 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(0));
5636 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(0));
5639 time = ((uint64_t)hi << 32) | lo;
5640 ns = rte_timecounter_update(&ad->systime_tc, time);
5641 *ts = rte_ns_to_timespec(ns);
5647 ice_timesync_disable(struct rte_eth_dev *dev)
5649 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5650 struct ice_adapter *ad =
5651 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5655 lport = hw->port_info->lport;
5657 ice_clear_phy_tstamp(hw, lport, 0);
5659 val = ICE_READ_REG(hw, GLTSYN_ENA(0));
5660 val &= ~GLTSYN_ENA_TSYN_ENA_M;
5661 ICE_WRITE_REG(hw, GLTSYN_ENA(0), val);
5663 ICE_WRITE_REG(hw, GLTSYN_INCVAL_L(0), 0);
5664 ICE_WRITE_REG(hw, GLTSYN_INCVAL_H(0), 0);
5672 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5673 struct rte_pci_device *pci_dev)
5675 return rte_eth_dev_pci_generic_probe(pci_dev,
5676 sizeof(struct ice_adapter),
5681 ice_pci_remove(struct rte_pci_device *pci_dev)
5683 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5686 static struct rte_pci_driver rte_ice_pmd = {
5687 .id_table = pci_id_ice_map,
5688 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5689 .probe = ice_pci_probe,
5690 .remove = ice_pci_remove,
5694 * Driver initialization routine.
5695 * Invoked once at EAL init time.
5696 * Register itself as the [Poll Mode] Driver of PCI devices.
5698 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5699 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5700 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5701 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5702 ICE_HW_DEBUG_MASK_ARG "=0xXXX"
5703 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5704 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5705 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
5706 ICE_RX_LOW_LATENCY_ARG "=<0|1>");
5708 RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE);
5709 RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE);
5710 #ifdef RTE_ETHDEV_DEBUG_RX
5711 RTE_LOG_REGISTER_SUFFIX(ice_logtype_rx, rx, DEBUG);
5713 #ifdef RTE_ETHDEV_DEBUG_TX
5714 RTE_LOG_REGISTER_SUFFIX(ice_logtype_tx, tx, DEBUG);