drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_FLOW_MARK_SUPPORT_ARG       "flow-mark-support"
  27 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  28
  29 static const char * const ice_valid_args[] = {
  30         ICE_SAFE_MODE_SUPPORT_ARG,
  31         ICE_PIPELINE_MODE_SUPPORT_ARG,
  32         ICE_FLOW_MARK_SUPPORT_ARG,
  33         ICE_PROTO_XTR_ARG,
  34         NULL
  35 };
  36
  37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  38         .name = "ice_dynfield_proto_xtr_metadata",
  39         .size = sizeof(uint32_t),
  40         .align = __alignof__(uint32_t),
  41         .flags = 0,
  42 };
  43
  44 struct proto_xtr_ol_flag {
  45         const struct rte_mbuf_dynflag param;
  46         uint64_t *ol_flag;
  47         bool required;
  48 };
  49
  50 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  51
  52 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  53         [PROTO_XTR_VLAN] = {
  54                 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
  55                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  56         [PROTO_XTR_IPV4] = {
  57                 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
  58                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  59         [PROTO_XTR_IPV6] = {
  60                 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
  61                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  62         [PROTO_XTR_IPV6_FLOW] = {
  63                 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
  64                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  65         [PROTO_XTR_TCP] = {
  66                 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
  67                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  68         [PROTO_XTR_IP_OFFSET] = {
  69                 .param = { .name = "ice_dynflag_proto_xtr_ip_offset" },
  70                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  71 };
  72
  73 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  74
  75 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  76 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  77 #define ICE_MAX_RES_DESC_NUM        1024
  78
  79 static int ice_dev_configure(struct rte_eth_dev *dev);
  80 static int ice_dev_start(struct rte_eth_dev *dev);
  81 static void ice_dev_stop(struct rte_eth_dev *dev);
  82 static void ice_dev_close(struct rte_eth_dev *dev);
  83 static int ice_dev_reset(struct rte_eth_dev *dev);
  84 static int ice_dev_info_get(struct rte_eth_dev *dev,
  85                             struct rte_eth_dev_info *dev_info);
  86 static int ice_link_update(struct rte_eth_dev *dev,
  87                            int wait_to_complete);
  88 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  89 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  90
  91 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  92 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  93 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  94                                struct rte_eth_rss_reta_entry64 *reta_conf,
  95                                uint16_t reta_size);
  96 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  97                               struct rte_eth_rss_reta_entry64 *reta_conf,
  98                               uint16_t reta_size);
  99 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 100                                struct rte_eth_rss_conf *rss_conf);
 101 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 102                                  struct rte_eth_rss_conf *rss_conf);
 103 static int ice_promisc_enable(struct rte_eth_dev *dev);
 104 static int ice_promisc_disable(struct rte_eth_dev *dev);
 105 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 106 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 107 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 108                                uint16_t vlan_id,
 109                                int on);
 110 static int ice_macaddr_set(struct rte_eth_dev *dev,
 111                            struct rte_ether_addr *mac_addr);
 112 static int ice_macaddr_add(struct rte_eth_dev *dev,
 113                            struct rte_ether_addr *mac_addr,
 114                            __rte_unused uint32_t index,
 115                            uint32_t pool);
 116 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 117 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 118                                     uint16_t queue_id);
 119 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 120                                      uint16_t queue_id);
 121 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 122                               size_t fw_size);
 123 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 124                              uint16_t pvid, int on);
 125 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 126 static int ice_get_eeprom(struct rte_eth_dev *dev,
 127                           struct rte_dev_eeprom_info *eeprom);
 128 static int ice_stats_get(struct rte_eth_dev *dev,
 129                          struct rte_eth_stats *stats);
 130 static int ice_stats_reset(struct rte_eth_dev *dev);
 131 static int ice_xstats_get(struct rte_eth_dev *dev,
 132                           struct rte_eth_xstat *xstats, unsigned int n);
 133 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 134                                 struct rte_eth_xstat_name *xstats_names,
 135                                 unsigned int limit);
 136 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 137                         enum rte_filter_type filter_type,
 138                         enum rte_filter_op filter_op,
 139                         void *arg);
 140 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 141                         struct rte_eth_udp_tunnel *udp_tunnel);
 142 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 143                         struct rte_eth_udp_tunnel *udp_tunnel);
 144
 145 static const struct rte_pci_id pci_id_ice_map[] = {
 146         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 147         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 148         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 149         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 150         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 151         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 152         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 162         { .vendor_id = 0, /* sentinel */ },
 163 };
 164
 165 static const struct eth_dev_ops ice_eth_dev_ops = {
 166         .dev_configure                = ice_dev_configure,
 167         .dev_start                    = ice_dev_start,
 168         .dev_stop                     = ice_dev_stop,
 169         .dev_close                    = ice_dev_close,
 170         .dev_reset                    = ice_dev_reset,
 171         .dev_set_link_up              = ice_dev_set_link_up,
 172         .dev_set_link_down            = ice_dev_set_link_down,
 173         .rx_queue_start               = ice_rx_queue_start,
 174         .rx_queue_stop                = ice_rx_queue_stop,
 175         .tx_queue_start               = ice_tx_queue_start,
 176         .tx_queue_stop                = ice_tx_queue_stop,
 177         .rx_queue_setup               = ice_rx_queue_setup,
 178         .rx_queue_release             = ice_rx_queue_release,
 179         .tx_queue_setup               = ice_tx_queue_setup,
 180         .tx_queue_release             = ice_tx_queue_release,
 181         .dev_infos_get                = ice_dev_info_get,
 182         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 183         .link_update                  = ice_link_update,
 184         .mtu_set                      = ice_mtu_set,
 185         .mac_addr_set                 = ice_macaddr_set,
 186         .mac_addr_add                 = ice_macaddr_add,
 187         .mac_addr_remove              = ice_macaddr_remove,
 188         .vlan_filter_set              = ice_vlan_filter_set,
 189         .vlan_offload_set             = ice_vlan_offload_set,
 190         .reta_update                  = ice_rss_reta_update,
 191         .reta_query                   = ice_rss_reta_query,
 192         .rss_hash_update              = ice_rss_hash_update,
 193         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 194         .promiscuous_enable           = ice_promisc_enable,
 195         .promiscuous_disable          = ice_promisc_disable,
 196         .allmulticast_enable          = ice_allmulti_enable,
 197         .allmulticast_disable         = ice_allmulti_disable,
 198         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 199         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 200         .fw_version_get               = ice_fw_version_get,
 201         .vlan_pvid_set                = ice_vlan_pvid_set,
 202         .rxq_info_get                 = ice_rxq_info_get,
 203         .txq_info_get                 = ice_txq_info_get,
 204         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 205         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 206         .get_eeprom_length            = ice_get_eeprom_length,
 207         .get_eeprom                   = ice_get_eeprom,
 208         .rx_queue_count               = ice_rx_queue_count,
 209         .rx_descriptor_status         = ice_rx_descriptor_status,
 210         .tx_descriptor_status         = ice_tx_descriptor_status,
 211         .stats_get                    = ice_stats_get,
 212         .stats_reset                  = ice_stats_reset,
 213         .xstats_get                   = ice_xstats_get,
 214         .xstats_get_names             = ice_xstats_get_names,
 215         .xstats_reset                 = ice_stats_reset,
 216         .filter_ctrl                  = ice_dev_filter_ctrl,
 217         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 218         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 219         .tx_done_cleanup              = ice_tx_done_cleanup,
 220 };
 221
 222 /* store statistics names and its offset in stats structure */
 223 struct ice_xstats_name_off {
 224         char name[RTE_ETH_XSTATS_NAME_SIZE];
 225         unsigned int offset;
 226 };
 227
 228 static const struct ice_xstats_name_off ice_stats_strings[] = {
 229         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 230         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 231         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 232         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 233         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 234                 rx_unknown_protocol)},
 235         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 236         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 237         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 238         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 239 };
 240
 241 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 242                 sizeof(ice_stats_strings[0]))
 243
 244 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 245         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 246                 tx_dropped_link_down)},
 247         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 248         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 249                 illegal_bytes)},
 250         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 251         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 252                 mac_local_faults)},
 253         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 254                 mac_remote_faults)},
 255         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 256                 rx_len_errors)},
 257         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 258         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 259         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 260         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 261         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 262         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 263                 rx_size_127)},
 264         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 265                 rx_size_255)},
 266         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 267                 rx_size_511)},
 268         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 269                 rx_size_1023)},
 270         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 271                 rx_size_1522)},
 272         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 273                 rx_size_big)},
 274         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 275                 rx_undersize)},
 276         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 277                 rx_oversize)},
 278         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 279                 mac_short_pkt_dropped)},
 280         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 281                 rx_fragments)},
 282         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 283         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 284         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 285                 tx_size_127)},
 286         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 287                 tx_size_255)},
 288         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 289                 tx_size_511)},
 290         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 291                 tx_size_1023)},
 292         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 293                 tx_size_1522)},
 294         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 295                 tx_size_big)},
 296 };
 297
 298 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 299                 sizeof(ice_hw_port_strings[0]))
 300
 301 static void
 302 ice_init_controlq_parameter(struct ice_hw *hw)
 303 {
 304         /* fields for adminq */
 305         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 306         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 307         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 308         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 309
 310         /* fields for mailboxq, DPDK used as PF host */
 311         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 312         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 313         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 314         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 315 }
 316
 317 static int
 318 lookup_proto_xtr_type(const char *xtr_name)
 319 {
 320         static struct {
 321                 const char *name;
 322                 enum proto_xtr_type type;
 323         } xtr_type_map[] = {
 324                 { "vlan",      PROTO_XTR_VLAN      },
 325                 { "ipv4",      PROTO_XTR_IPV4      },
 326                 { "ipv6",      PROTO_XTR_IPV6      },
 327                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 328                 { "tcp",       PROTO_XTR_TCP       },
 329                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 330         };
 331         uint32_t i;
 332
 333         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 334                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 335                         return xtr_type_map[i].type;
 336         }
 337
 338         return -1;
 339 }
 340
 341 /*
 342  * Parse elem, the elem could be single number/range or '(' ')' group
 343  * 1) A single number elem, it's just a simple digit. e.g. 9
 344  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 345  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 346  *    Within group elem, '-' used for a range separator;
 347  *                       ',' used for a single number.
 348  */
 349 static int
 350 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 351 {
 352         const char *str = input;
 353         char *end = NULL;
 354         uint32_t min, max;
 355         uint32_t idx;
 356
 357         while (isblank(*str))
 358                 str++;
 359
 360         if (!isdigit(*str) && *str != '(')
 361                 return -1;
 362
 363         /* process single number or single range of number */
 364         if (*str != '(') {
 365                 errno = 0;
 366                 idx = strtoul(str, &end, 10);
 367                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 368                         return -1;
 369
 370                 while (isblank(*end))
 371                         end++;
 372
 373                 min = idx;
 374                 max = idx;
 375
 376                 /* process single <number>-<number> */
 377                 if (*end == '-') {
 378                         end++;
 379                         while (isblank(*end))
 380                                 end++;
 381                         if (!isdigit(*end))
 382                                 return -1;
 383
 384                         errno = 0;
 385                         idx = strtoul(end, &end, 10);
 386                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 387                                 return -1;
 388
 389                         max = idx;
 390                         while (isblank(*end))
 391                                 end++;
 392                 }
 393
 394                 if (*end != ':')
 395                         return -1;
 396
 397                 for (idx = RTE_MIN(min, max);
 398                      idx <= RTE_MAX(min, max); idx++)
 399                         devargs->proto_xtr[idx] = xtr_type;
 400
 401                 return 0;
 402         }
 403
 404         /* process set within bracket */
 405         str++;
 406         while (isblank(*str))
 407                 str++;
 408         if (*str == '\0')
 409                 return -1;
 410
 411         min = ICE_MAX_QUEUE_NUM;
 412         do {
 413                 /* go ahead to the first digit */
 414                 while (isblank(*str))
 415                         str++;
 416                 if (!isdigit(*str))
 417                         return -1;
 418
 419                 /* get the digit value */
 420                 errno = 0;
 421                 idx = strtoul(str, &end, 10);
 422                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 423                         return -1;
 424
 425                 /* go ahead to separator '-',',' and ')' */
 426                 while (isblank(*end))
 427                         end++;
 428                 if (*end == '-') {
 429                         if (min == ICE_MAX_QUEUE_NUM)
 430                                 min = idx;
 431                         else /* avoid continuous '-' */
 432                                 return -1;
 433                 } else if (*end == ',' || *end == ')') {
 434                         max = idx;
 435                         if (min == ICE_MAX_QUEUE_NUM)
 436                                 min = idx;
 437
 438                         for (idx = RTE_MIN(min, max);
 439                              idx <= RTE_MAX(min, max); idx++)
 440                                 devargs->proto_xtr[idx] = xtr_type;
 441
 442                         min = ICE_MAX_QUEUE_NUM;
 443                 } else {
 444                         return -1;
 445                 }
 446
 447                 str = end + 1;
 448         } while (*end != ')' && *end != '\0');
 449
 450         return 0;
 451 }
 452
 453 static int
 454 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 455 {
 456         const char *queue_start;
 457         uint32_t idx;
 458         int xtr_type;
 459         char xtr_name[32];
 460
 461         while (isblank(*queues))
 462                 queues++;
 463
 464         if (*queues != '[') {
 465                 xtr_type = lookup_proto_xtr_type(queues);
 466                 if (xtr_type < 0)
 467                         return -1;
 468
 469                 devargs->proto_xtr_dflt = xtr_type;
 470
 471                 return 0;
 472         }
 473
 474         queues++;
 475         do {
 476                 while (isblank(*queues))
 477                         queues++;
 478                 if (*queues == '\0')
 479                         return -1;
 480
 481                 queue_start = queues;
 482
 483                 /* go across a complete bracket */
 484                 if (*queue_start == '(') {
 485                         queues += strcspn(queues, ")");
 486                         if (*queues != ')')
 487                                 return -1;
 488                 }
 489
 490                 /* scan the separator ':' */
 491                 queues += strcspn(queues, ":");
 492                 if (*queues++ != ':')
 493                         return -1;
 494                 while (isblank(*queues))
 495                         queues++;
 496
 497                 for (idx = 0; ; idx++) {
 498                         if (isblank(queues[idx]) ||
 499                             queues[idx] == ',' ||
 500                             queues[idx] == ']' ||
 501                             queues[idx] == '\0')
 502                                 break;
 503
 504                         if (idx > sizeof(xtr_name) - 2)
 505                                 return -1;
 506
 507                         xtr_name[idx] = queues[idx];
 508                 }
 509                 xtr_name[idx] = '\0';
 510                 xtr_type = lookup_proto_xtr_type(xtr_name);
 511                 if (xtr_type < 0)
 512                         return -1;
 513
 514                 queues += idx;
 515
 516                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 517                         queues++;
 518
 519                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 520                         return -1;
 521         } while (*queues != '\0');
 522
 523         return 0;
 524 }
 525
 526 static int
 527 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 528                      void *extra_args)
 529 {
 530         struct ice_devargs *devargs = extra_args;
 531
 532         if (value == NULL || extra_args == NULL)
 533                 return -EINVAL;
 534
 535         if (parse_queue_proto_xtr(value, devargs) < 0) {
 536                 PMD_DRV_LOG(ERR,
 537                             "The protocol extraction parameter is wrong : '%s'",
 538                             value);
 539                 return -1;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static void
 546 ice_check_proto_xtr_support(struct ice_hw *hw)
 547 {
 548 #define FLX_REG(val, fld, idx) \
 549         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 550          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 551         static struct {
 552                 uint32_t rxdid;
 553                 uint8_t opcode;
 554                 uint8_t protid_0;
 555                 uint8_t protid_1;
 556         } xtr_sets[] = {
 557                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 558                                      ICE_RX_OPC_EXTRACT,
 559                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 560                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 561                                      ICE_RX_OPC_EXTRACT,
 562                                      ICE_PROT_IPV4_OF_OR_S,
 563                                      ICE_PROT_IPV4_OF_OR_S },
 564                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 565                                      ICE_RX_OPC_EXTRACT,
 566                                      ICE_PROT_IPV6_OF_OR_S,
 567                                      ICE_PROT_IPV6_OF_OR_S },
 568                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 569                                           ICE_RX_OPC_EXTRACT,
 570                                           ICE_PROT_IPV6_OF_OR_S,
 571                                           ICE_PROT_IPV6_OF_OR_S },
 572                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 573                                     ICE_RX_OPC_EXTRACT,
 574                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 575                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 576                                           ICE_RX_OPC_PROTID,
 577                                           ICE_PROT_IPV4_OF_OR_S,
 578                                           ICE_PROT_IPV6_OF_OR_S },
 579         };
 580         uint32_t i;
 581
 582         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 583                 uint32_t rxdid = xtr_sets[i].rxdid;
 584                 uint32_t v;
 585
 586                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 587                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 588
 589                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 590                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 591                                 ice_proto_xtr_hw_support[i] = true;
 592                 }
 593
 594                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 595                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 596
 597                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 598                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 599                                 ice_proto_xtr_hw_support[i] = true;
 600                 }
 601         }
 602 }
 603
 604 static int
 605 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 606                   uint32_t num)
 607 {
 608         struct pool_entry *entry;
 609
 610         if (!pool || !num)
 611                 return -EINVAL;
 612
 613         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 614         if (!entry) {
 615                 PMD_INIT_LOG(ERR,
 616                              "Failed to allocate memory for resource pool");
 617                 return -ENOMEM;
 618         }
 619
 620         /* queue heap initialize */
 621         pool->num_free = num;
 622         pool->num_alloc = 0;
 623         pool->base = base;
 624         LIST_INIT(&pool->alloc_list);
 625         LIST_INIT(&pool->free_list);
 626
 627         /* Initialize element  */
 628         entry->base = 0;
 629         entry->len = num;
 630
 631         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 632         return 0;
 633 }
 634
 635 static int
 636 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 637                    uint16_t num)
 638 {
 639         struct pool_entry *entry, *valid_entry;
 640
 641         if (!pool || !num) {
 642                 PMD_INIT_LOG(ERR, "Invalid parameter");
 643                 return -EINVAL;
 644         }
 645
 646         if (pool->num_free < num) {
 647                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 648                              num, pool->num_free);
 649                 return -ENOMEM;
 650         }
 651
 652         valid_entry = NULL;
 653         /* Lookup  in free list and find most fit one */
 654         LIST_FOREACH(entry, &pool->free_list, next) {
 655                 if (entry->len >= num) {
 656                         /* Find best one */
 657                         if (entry->len == num) {
 658                                 valid_entry = entry;
 659                                 break;
 660                         }
 661                         if (!valid_entry ||
 662                             valid_entry->len > entry->len)
 663                                 valid_entry = entry;
 664                 }
 665         }
 666
 667         /* Not find one to satisfy the request, return */
 668         if (!valid_entry) {
 669                 PMD_INIT_LOG(ERR, "No valid entry found");
 670                 return -ENOMEM;
 671         }
 672         /**
 673          * The entry have equal queue number as requested,
 674          * remove it from alloc_list.
 675          */
 676         if (valid_entry->len == num) {
 677                 LIST_REMOVE(valid_entry, next);
 678         } else {
 679                 /**
 680                  * The entry have more numbers than requested,
 681                  * create a new entry for alloc_list and minus its
 682                  * queue base and number in free_list.
 683                  */
 684                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 685                 if (!entry) {
 686                         PMD_INIT_LOG(ERR,
 687                                      "Failed to allocate memory for "
 688                                      "resource pool");
 689                         return -ENOMEM;
 690                 }
 691                 entry->base = valid_entry->base;
 692                 entry->len = num;
 693                 valid_entry->base += num;
 694                 valid_entry->len -= num;
 695                 valid_entry = entry;
 696         }
 697
 698         /* Insert it into alloc list, not sorted */
 699         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 700
 701         pool->num_free -= valid_entry->len;
 702         pool->num_alloc += valid_entry->len;
 703
 704         return valid_entry->base + pool->base;
 705 }
 706
 707 static void
 708 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 709 {
 710         struct pool_entry *entry, *next_entry;
 711
 712         if (!pool)
 713                 return;
 714
 715         for (entry = LIST_FIRST(&pool->alloc_list);
 716              entry && (next_entry = LIST_NEXT(entry, next), 1);
 717              entry = next_entry) {
 718                 LIST_REMOVE(entry, next);
 719                 rte_free(entry);
 720         }
 721
 722         for (entry = LIST_FIRST(&pool->free_list);
 723              entry && (next_entry = LIST_NEXT(entry, next), 1);
 724              entry = next_entry) {
 725                 LIST_REMOVE(entry, next);
 726                 rte_free(entry);
 727         }
 728
 729         pool->num_free = 0;
 730         pool->num_alloc = 0;
 731         pool->base = 0;
 732         LIST_INIT(&pool->alloc_list);
 733         LIST_INIT(&pool->free_list);
 734 }
 735
 736 static void
 737 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 738 {
 739         /* Set VSI LUT selection */
 740         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 741                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 742         /* Set Hash scheme */
 743         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 744                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 745         /* enable TC */
 746         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 747 }
 748
 749 static enum ice_status
 750 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 751                                 struct ice_aqc_vsi_props *info,
 752                                 uint8_t enabled_tcmap)
 753 {
 754         uint16_t bsf, qp_idx;
 755
 756         /* default tc 0 now. Multi-TC supporting need to be done later.
 757          * Configure TC and queue mapping parameters, for enabled TC,
 758          * allocate qpnum_per_tc queues to this traffic.
 759          */
 760         if (enabled_tcmap != 0x01) {
 761                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 762                 return -ENOTSUP;
 763         }
 764
 765         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 766         bsf = rte_bsf32(vsi->nb_qps);
 767         /* Adjust the queue number to actual queues that can be applied */
 768         vsi->nb_qps = 0x1 << bsf;
 769
 770         qp_idx = 0;
 771         /* Set tc and queue mapping with VSI */
 772         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 773                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 774                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 775
 776         /* Associate queue number with VSI */
 777         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 778         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 779         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 780         info->valid_sections |=
 781                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 782         /* Set the info.ingress_table and info.egress_table
 783          * for UP translate table. Now just set it to 1:1 map by default
 784          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 785          */
 786 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 787         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 788         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 789         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 790         return 0;
 791 }
 792
 793 static int
 794 ice_init_mac_address(struct rte_eth_dev *dev)
 795 {
 796         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 797
 798         if (!rte_is_unicast_ether_addr
 799                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 800                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 801                 return -EINVAL;
 802         }
 803
 804         rte_ether_addr_copy(
 805                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 806                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 807
 808         dev->data->mac_addrs =
 809                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 810         if (!dev->data->mac_addrs) {
 811                 PMD_INIT_LOG(ERR,
 812                              "Failed to allocate memory to store mac address");
 813                 return -ENOMEM;
 814         }
 815         /* store it to dev data */
 816         rte_ether_addr_copy(
 817                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 818                 &dev->data->mac_addrs[0]);
 819         return 0;
 820 }
 821
 822 /* Find out specific MAC filter */
 823 static struct ice_mac_filter *
 824 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 825 {
 826         struct ice_mac_filter *f;
 827
 828         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 829                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 830                         return f;
 831         }
 832
 833         return NULL;
 834 }
 835
 836 static int
 837 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 838 {
 839         struct ice_fltr_list_entry *m_list_itr = NULL;
 840         struct ice_mac_filter *f;
 841         struct LIST_HEAD_TYPE list_head;
 842         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 843         int ret = 0;
 844
 845         /* If it's added and configured, return */
 846         f = ice_find_mac_filter(vsi, mac_addr);
 847         if (f) {
 848                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 849                 return 0;
 850         }
 851
 852         INIT_LIST_HEAD(&list_head);
 853
 854         m_list_itr = (struct ice_fltr_list_entry *)
 855                 ice_malloc(hw, sizeof(*m_list_itr));
 856         if (!m_list_itr) {
 857                 ret = -ENOMEM;
 858                 goto DONE;
 859         }
 860         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 861                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 862         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 863         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 864         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 865         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 866         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 867
 868         LIST_ADD(&m_list_itr->list_entry, &list_head);
 869
 870         /* Add the mac */
 871         ret = ice_add_mac(hw, &list_head);
 872         if (ret != ICE_SUCCESS) {
 873                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 874                 ret = -EINVAL;
 875                 goto DONE;
 876         }
 877         /* Add the mac addr into mac list */
 878         f = rte_zmalloc(NULL, sizeof(*f), 0);
 879         if (!f) {
 880                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 881                 ret = -ENOMEM;
 882                 goto DONE;
 883         }
 884         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 885         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 886         vsi->mac_num++;
 887
 888         ret = 0;
 889
 890 DONE:
 891         rte_free(m_list_itr);
 892         return ret;
 893 }
 894
 895 static int
 896 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 897 {
 898         struct ice_fltr_list_entry *m_list_itr = NULL;
 899         struct ice_mac_filter *f;
 900         struct LIST_HEAD_TYPE list_head;
 901         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 902         int ret = 0;
 903
 904         /* Can't find it, return an error */
 905         f = ice_find_mac_filter(vsi, mac_addr);
 906         if (!f)
 907                 return -EINVAL;
 908
 909         INIT_LIST_HEAD(&list_head);
 910
 911         m_list_itr = (struct ice_fltr_list_entry *)
 912                 ice_malloc(hw, sizeof(*m_list_itr));
 913         if (!m_list_itr) {
 914                 ret = -ENOMEM;
 915                 goto DONE;
 916         }
 917         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 918                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 919         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 920         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 921         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 922         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 923         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 924
 925         LIST_ADD(&m_list_itr->list_entry, &list_head);
 926
 927         /* remove the mac filter */
 928         ret = ice_remove_mac(hw, &list_head);
 929         if (ret != ICE_SUCCESS) {
 930                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 931                 ret = -EINVAL;
 932                 goto DONE;
 933         }
 934
 935         /* Remove the mac addr from mac list */
 936         TAILQ_REMOVE(&vsi->mac_list, f, next);
 937         rte_free(f);
 938         vsi->mac_num--;
 939
 940         ret = 0;
 941 DONE:
 942         rte_free(m_list_itr);
 943         return ret;
 944 }
 945
 946 /* Find out specific VLAN filter */
 947 static struct ice_vlan_filter *
 948 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 949 {
 950         struct ice_vlan_filter *f;
 951
 952         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 953                 if (vlan_id == f->vlan_info.vlan_id)
 954                         return f;
 955         }
 956
 957         return NULL;
 958 }
 959
 960 static int
 961 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 962 {
 963         struct ice_fltr_list_entry *v_list_itr = NULL;
 964         struct ice_vlan_filter *f;
 965         struct LIST_HEAD_TYPE list_head;
 966         struct ice_hw *hw;
 967         int ret = 0;
 968
 969         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 970                 return -EINVAL;
 971
 972         hw = ICE_VSI_TO_HW(vsi);
 973
 974         /* If it's added and configured, return. */
 975         f = ice_find_vlan_filter(vsi, vlan_id);
 976         if (f) {
 977                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 978                 return 0;
 979         }
 980
 981         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 982                 return 0;
 983
 984         INIT_LIST_HEAD(&list_head);
 985
 986         v_list_itr = (struct ice_fltr_list_entry *)
 987                       ice_malloc(hw, sizeof(*v_list_itr));
 988         if (!v_list_itr) {
 989                 ret = -ENOMEM;
 990                 goto DONE;
 991         }
 992         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 993         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 994         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 995         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 996         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 997         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 998
 999         LIST_ADD(&v_list_itr->list_entry, &list_head);
1000
1001         /* Add the vlan */
1002         ret = ice_add_vlan(hw, &list_head);
1003         if (ret != ICE_SUCCESS) {
1004                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1005                 ret = -EINVAL;
1006                 goto DONE;
1007         }
1008
1009         /* Add vlan into vlan list */
1010         f = rte_zmalloc(NULL, sizeof(*f), 0);
1011         if (!f) {
1012                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1013                 ret = -ENOMEM;
1014                 goto DONE;
1015         }
1016         f->vlan_info.vlan_id = vlan_id;
1017         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1018         vsi->vlan_num++;
1019
1020         ret = 0;
1021
1022 DONE:
1023         rte_free(v_list_itr);
1024         return ret;
1025 }
1026
1027 static int
1028 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1029 {
1030         struct ice_fltr_list_entry *v_list_itr = NULL;
1031         struct ice_vlan_filter *f;
1032         struct LIST_HEAD_TYPE list_head;
1033         struct ice_hw *hw;
1034         int ret = 0;
1035
1036         /**
1037          * Vlan 0 is the generic filter for untagged packets
1038          * and can't be removed.
1039          */
1040         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1041                 return -EINVAL;
1042
1043         hw = ICE_VSI_TO_HW(vsi);
1044
1045         /* Can't find it, return an error */
1046         f = ice_find_vlan_filter(vsi, vlan_id);
1047         if (!f)
1048                 return -EINVAL;
1049
1050         INIT_LIST_HEAD(&list_head);
1051
1052         v_list_itr = (struct ice_fltr_list_entry *)
1053                       ice_malloc(hw, sizeof(*v_list_itr));
1054         if (!v_list_itr) {
1055                 ret = -ENOMEM;
1056                 goto DONE;
1057         }
1058
1059         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1060         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1061         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1062         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1063         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1064         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1065
1066         LIST_ADD(&v_list_itr->list_entry, &list_head);
1067
1068         /* remove the vlan filter */
1069         ret = ice_remove_vlan(hw, &list_head);
1070         if (ret != ICE_SUCCESS) {
1071                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1072                 ret = -EINVAL;
1073                 goto DONE;
1074         }
1075
1076         /* Remove the vlan id from vlan list */
1077         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1078         rte_free(f);
1079         vsi->vlan_num--;
1080
1081         ret = 0;
1082 DONE:
1083         rte_free(v_list_itr);
1084         return ret;
1085 }
1086
1087 static int
1088 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1089 {
1090         struct ice_mac_filter *m_f;
1091         struct ice_vlan_filter *v_f;
1092         int ret = 0;
1093
1094         if (!vsi || !vsi->mac_num)
1095                 return -EINVAL;
1096
1097         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1098                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1099                 if (ret != ICE_SUCCESS) {
1100                         ret = -EINVAL;
1101                         goto DONE;
1102                 }
1103         }
1104
1105         if (vsi->vlan_num == 0)
1106                 return 0;
1107
1108         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1109                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1110                 if (ret != ICE_SUCCESS) {
1111                         ret = -EINVAL;
1112                         goto DONE;
1113                 }
1114         }
1115
1116 DONE:
1117         return ret;
1118 }
1119
1120 static int
1121 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1122 {
1123         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1124         struct ice_vsi_ctx ctxt;
1125         uint8_t qinq_flags;
1126         int ret = 0;
1127
1128         /* Check if it has been already on or off */
1129         if (vsi->info.valid_sections &
1130                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1131                 if (on) {
1132                         if ((vsi->info.outer_tag_flags &
1133                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1134                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1135                                 return 0; /* already on */
1136                 } else {
1137                         if (!(vsi->info.outer_tag_flags &
1138                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1139                                 return 0; /* already off */
1140                 }
1141         }
1142
1143         if (on)
1144                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1145         else
1146                 qinq_flags = 0;
1147         /* clear global insertion and use per packet insertion */
1148         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1149         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1150         vsi->info.outer_tag_flags |= qinq_flags;
1151         /* use default vlan type 0x8100 */
1152         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1153         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1154                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1155         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1156         ctxt.info.valid_sections =
1157                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1158         ctxt.vsi_num = vsi->vsi_id;
1159         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1160         if (ret) {
1161                 PMD_DRV_LOG(INFO,
1162                             "Update VSI failed to %s qinq stripping",
1163                             on ? "enable" : "disable");
1164                 return -EINVAL;
1165         }
1166
1167         vsi->info.valid_sections |=
1168                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1169
1170         return ret;
1171 }
1172
1173 static int
1174 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1175 {
1176         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1177         struct ice_vsi_ctx ctxt;
1178         uint8_t qinq_flags;
1179         int ret = 0;
1180
1181         /* Check if it has been already on or off */
1182         if (vsi->info.valid_sections &
1183                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1184                 if (on) {
1185                         if ((vsi->info.outer_tag_flags &
1186                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1187                             ICE_AQ_VSI_OUTER_TAG_COPY)
1188                                 return 0; /* already on */
1189                 } else {
1190                         if ((vsi->info.outer_tag_flags &
1191                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1192                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1193                                 return 0; /* already off */
1194                 }
1195         }
1196
1197         if (on)
1198                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1199         else
1200                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1201         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1202         vsi->info.outer_tag_flags |= qinq_flags;
1203         /* use default vlan type 0x8100 */
1204         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1205         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1206                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1207         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1208         ctxt.info.valid_sections =
1209                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1210         ctxt.vsi_num = vsi->vsi_id;
1211         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1212         if (ret) {
1213                 PMD_DRV_LOG(INFO,
1214                             "Update VSI failed to %s qinq stripping",
1215                             on ? "enable" : "disable");
1216                 return -EINVAL;
1217         }
1218
1219         vsi->info.valid_sections |=
1220                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1221
1222         return ret;
1223 }
1224
1225 static int
1226 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1227 {
1228         int ret;
1229
1230         ret = ice_vsi_config_qinq_stripping(vsi, on);
1231         if (ret)
1232                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1233
1234         ret = ice_vsi_config_qinq_insertion(vsi, on);
1235         if (ret)
1236                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1237
1238         return ret;
1239 }
1240
1241 /* Enable IRQ0 */
1242 static void
1243 ice_pf_enable_irq0(struct ice_hw *hw)
1244 {
1245         /* reset the registers */
1246         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1247         ICE_READ_REG(hw, PFINT_OICR);
1248
1249 #ifdef ICE_LSE_SPT
1250         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1251                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1252                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1253
1254         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1255                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1256                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1257                        PFINT_OICR_CTL_ITR_INDX_M) |
1258                       PFINT_OICR_CTL_CAUSE_ENA_M);
1259
1260         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1261                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1262                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1263                        PFINT_FW_CTL_ITR_INDX_M) |
1264                       PFINT_FW_CTL_CAUSE_ENA_M);
1265 #else
1266         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1267 #endif
1268
1269         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1270                       GLINT_DYN_CTL_INTENA_M |
1271                       GLINT_DYN_CTL_CLEARPBA_M |
1272                       GLINT_DYN_CTL_ITR_INDX_M);
1273
1274         ice_flush(hw);
1275 }
1276
1277 /* Disable IRQ0 */
1278 static void
1279 ice_pf_disable_irq0(struct ice_hw *hw)
1280 {
1281         /* Disable all interrupt types */
1282         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1283         ice_flush(hw);
1284 }
1285
1286 #ifdef ICE_LSE_SPT
1287 static void
1288 ice_handle_aq_msg(struct rte_eth_dev *dev)
1289 {
1290         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1291         struct ice_ctl_q_info *cq = &hw->adminq;
1292         struct ice_rq_event_info event;
1293         uint16_t pending, opcode;
1294         int ret;
1295
1296         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1297         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1298         if (!event.msg_buf) {
1299                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1300                 return;
1301         }
1302
1303         pending = 1;
1304         while (pending) {
1305                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1306
1307                 if (ret != ICE_SUCCESS) {
1308                         PMD_DRV_LOG(INFO,
1309                                     "Failed to read msg from AdminQ, "
1310                                     "adminq_err: %u",
1311                                     hw->adminq.sq_last_status);
1312                         break;
1313                 }
1314                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1315
1316                 switch (opcode) {
1317                 case ice_aqc_opc_get_link_status:
1318                         ret = ice_link_update(dev, 0);
1319                         if (!ret)
1320                                 _rte_eth_dev_callback_process
1321                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1322                         break;
1323                 default:
1324                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1325                                     opcode);
1326                         break;
1327                 }
1328         }
1329         rte_free(event.msg_buf);
1330 }
1331 #endif
1332
1333 /**
1334  * Interrupt handler triggered by NIC for handling
1335  * specific interrupt.
1336  *
1337  * @param handle
1338  *  Pointer to interrupt handle.
1339  * @param param
1340  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1341  *
1342  * @return
1343  *  void
1344  */
1345 static void
1346 ice_interrupt_handler(void *param)
1347 {
1348         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1349         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1350         uint32_t oicr;
1351         uint32_t reg;
1352         uint8_t pf_num;
1353         uint8_t event;
1354         uint16_t queue;
1355         int ret;
1356 #ifdef ICE_LSE_SPT
1357         uint32_t int_fw_ctl;
1358 #endif
1359
1360         /* Disable interrupt */
1361         ice_pf_disable_irq0(hw);
1362
1363         /* read out interrupt causes */
1364         oicr = ICE_READ_REG(hw, PFINT_OICR);
1365 #ifdef ICE_LSE_SPT
1366         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1367 #endif
1368
1369         /* No interrupt event indicated */
1370         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1371                 PMD_DRV_LOG(INFO, "No interrupt event");
1372                 goto done;
1373         }
1374
1375 #ifdef ICE_LSE_SPT
1376         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1377                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1378                 ice_handle_aq_msg(dev);
1379         }
1380 #else
1381         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1382                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1383                 ret = ice_link_update(dev, 0);
1384                 if (!ret)
1385                         _rte_eth_dev_callback_process
1386                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1387         }
1388 #endif
1389
1390         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1391                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1392                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1393                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1394                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1395                                  GL_MDET_TX_PQM_PF_NUM_S;
1396                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1397                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1398                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1399                                 GL_MDET_TX_PQM_QNUM_S;
1400
1401                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1402                                     "%d by PQM on TX queue %d PF# %d",
1403                                     event, queue, pf_num);
1404                 }
1405
1406                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1407                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1408                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1409                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1410                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1411                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1412                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1413                                 GL_MDET_TX_TCLAN_QNUM_S;
1414
1415                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1416                                     "%d by TCLAN on TX queue %d PF# %d",
1417                                     event, queue, pf_num);
1418                 }
1419         }
1420 done:
1421         /* Enable interrupt */
1422         ice_pf_enable_irq0(hw);
1423         rte_intr_ack(dev->intr_handle);
1424 }
1425
1426 static void
1427 ice_init_proto_xtr(struct rte_eth_dev *dev)
1428 {
1429         struct ice_adapter *ad =
1430                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1431         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1432         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1433         const struct proto_xtr_ol_flag *ol_flag;
1434         bool proto_xtr_enable = false;
1435         int offset;
1436         uint16_t i;
1437
1438         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1439         if (unlikely(pf->proto_xtr == NULL)) {
1440                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1441                 return;
1442         }
1443
1444         for (i = 0; i < pf->lan_nb_qps; i++) {
1445                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1446                                    ad->devargs.proto_xtr[i] :
1447                                    ad->devargs.proto_xtr_dflt;
1448
1449                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1450                         uint8_t type = pf->proto_xtr[i];
1451
1452                         ice_proto_xtr_ol_flag_params[type].required = true;
1453                         proto_xtr_enable = true;
1454                 }
1455         }
1456
1457         if (likely(!proto_xtr_enable))
1458                 return;
1459
1460         ice_check_proto_xtr_support(hw);
1461
1462         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1463         if (unlikely(offset == -1)) {
1464                 PMD_DRV_LOG(ERR,
1465                             "Protocol extraction metadata is disabled in mbuf with error %d",
1466                             -rte_errno);
1467                 return;
1468         }
1469
1470         PMD_DRV_LOG(DEBUG,
1471                     "Protocol extraction metadata offset in mbuf is : %d",
1472                     offset);
1473         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1474
1475         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1476                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1477
1478                 if (!ol_flag->required)
1479                         continue;
1480
1481                 if (!ice_proto_xtr_hw_support[i]) {
1482                         PMD_DRV_LOG(ERR,
1483                                     "Protocol extraction type %u is not supported in hardware",
1484                                     i);
1485                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1486                         break;
1487                 }
1488
1489                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1490                 if (unlikely(offset == -1)) {
1491                         PMD_DRV_LOG(ERR,
1492                                     "Protocol extraction offload '%s' failed to register with error %d",
1493                                     ol_flag->param.name, -rte_errno);
1494
1495                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1496                         break;
1497                 }
1498
1499                 PMD_DRV_LOG(DEBUG,
1500                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1501                             ol_flag->param.name, offset);
1502                 *ol_flag->ol_flag = 1ULL << offset;
1503         }
1504 }
1505
1506 /*  Initialize SW parameters of PF */
1507 static int
1508 ice_pf_sw_init(struct rte_eth_dev *dev)
1509 {
1510         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1511         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1512
1513         pf->lan_nb_qp_max =
1514                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1515                                   hw->func_caps.common_cap.num_rxq);
1516
1517         pf->lan_nb_qps = pf->lan_nb_qp_max;
1518
1519         ice_init_proto_xtr(dev);
1520
1521         if (hw->func_caps.fd_fltr_guar > 0 ||
1522             hw->func_caps.fd_fltr_best_effort > 0) {
1523                 pf->flags |= ICE_FLAG_FDIR;
1524                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1525                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1526         } else {
1527                 pf->fdir_nb_qps = 0;
1528         }
1529         pf->fdir_qp_offset = 0;
1530
1531         return 0;
1532 }
1533
1534 struct ice_vsi *
1535 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1536 {
1537         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1538         struct ice_vsi *vsi = NULL;
1539         struct ice_vsi_ctx vsi_ctx;
1540         int ret;
1541         struct rte_ether_addr broadcast = {
1542                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1543         struct rte_ether_addr mac_addr;
1544         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1545         uint8_t tc_bitmap = 0x1;
1546         uint16_t cfg;
1547
1548         /* hw->num_lports = 1 in NIC mode */
1549         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1550         if (!vsi)
1551                 return NULL;
1552
1553         vsi->idx = pf->next_vsi_idx;
1554         pf->next_vsi_idx++;
1555         vsi->type = type;
1556         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1557         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1558         vsi->vlan_anti_spoof_on = 0;
1559         vsi->vlan_filter_on = 1;
1560         TAILQ_INIT(&vsi->mac_list);
1561         TAILQ_INIT(&vsi->vlan_list);
1562
1563         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1564         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1565                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1566                         hw->func_caps.common_cap.rss_table_size;
1567         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1568
1569         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1570         switch (type) {
1571         case ICE_VSI_PF:
1572                 vsi->nb_qps = pf->lan_nb_qps;
1573                 vsi->base_queue = 1;
1574                 ice_vsi_config_default_rss(&vsi_ctx.info);
1575                 vsi_ctx.alloc_from_pool = true;
1576                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1577                 /* switch_id is queried by get_switch_config aq, which is done
1578                  * by ice_init_hw
1579                  */
1580                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1581                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1582                 /* Allow all untagged or tagged packets */
1583                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1584                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1585                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1586                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1587
1588                 /* FDIR */
1589                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1590                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1591                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1592                 cfg = ICE_AQ_VSI_FD_ENABLE;
1593                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1594                 vsi_ctx.info.max_fd_fltr_dedicated =
1595                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1596                 vsi_ctx.info.max_fd_fltr_shared =
1597                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1598
1599                 /* Enable VLAN/UP trip */
1600                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1601                                                       &vsi_ctx.info,
1602                                                       ICE_DEFAULT_TCMAP);
1603                 if (ret) {
1604                         PMD_INIT_LOG(ERR,
1605                                      "tc queue mapping with vsi failed, "
1606                                      "err = %d",
1607                                      ret);
1608                         goto fail_mem;
1609                 }
1610
1611                 break;
1612         case ICE_VSI_CTRL:
1613                 vsi->nb_qps = pf->fdir_nb_qps;
1614                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1615                 vsi_ctx.alloc_from_pool = true;
1616                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1617
1618                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1619                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1620                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1621                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1622                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1623                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1624                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1625                                                       &vsi_ctx.info,
1626                                                       ICE_DEFAULT_TCMAP);
1627                 if (ret) {
1628                         PMD_INIT_LOG(ERR,
1629                                      "tc queue mapping with vsi failed, "
1630                                      "err = %d",
1631                                      ret);
1632                         goto fail_mem;
1633                 }
1634                 break;
1635         default:
1636                 /* for other types of VSI */
1637                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1638                 goto fail_mem;
1639         }
1640
1641         /* VF has MSIX interrupt in VF range, don't allocate here */
1642         if (type == ICE_VSI_PF) {
1643                 ret = ice_res_pool_alloc(&pf->msix_pool,
1644                                          RTE_MIN(vsi->nb_qps,
1645                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1646                 if (ret < 0) {
1647                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1648                                      vsi->vsi_id, ret);
1649                 }
1650                 vsi->msix_intr = ret;
1651                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1652         } else if (type == ICE_VSI_CTRL) {
1653                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1654                 if (ret < 0) {
1655                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1656                                     vsi->vsi_id, ret);
1657                 }
1658                 vsi->msix_intr = ret;
1659                 vsi->nb_msix = 1;
1660         } else {
1661                 vsi->msix_intr = 0;
1662                 vsi->nb_msix = 0;
1663         }
1664         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1665         if (ret != ICE_SUCCESS) {
1666                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1667                 goto fail_mem;
1668         }
1669         /* store vsi information is SW structure */
1670         vsi->vsi_id = vsi_ctx.vsi_num;
1671         vsi->info = vsi_ctx.info;
1672         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1673         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1674
1675         if (type == ICE_VSI_PF) {
1676                 /* MAC configuration */
1677                 rte_ether_addr_copy((struct rte_ether_addr *)
1678                                         hw->port_info->mac.perm_addr,
1679                                     &pf->dev_addr);
1680
1681                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1682                 ret = ice_add_mac_filter(vsi, &mac_addr);
1683                 if (ret != ICE_SUCCESS)
1684                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1685
1686                 rte_ether_addr_copy(&broadcast, &mac_addr);
1687                 ret = ice_add_mac_filter(vsi, &mac_addr);
1688                 if (ret != ICE_SUCCESS)
1689                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1690         }
1691
1692         /* At the beginning, only TC0. */
1693         /* What we need here is the maximam number of the TX queues.
1694          * Currently vsi->nb_qps means it.
1695          * Correct it if any change.
1696          */
1697         max_txqs[0] = vsi->nb_qps;
1698         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1699                               tc_bitmap, max_txqs);
1700         if (ret != ICE_SUCCESS)
1701                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1702
1703         return vsi;
1704 fail_mem:
1705         rte_free(vsi);
1706         pf->next_vsi_idx--;
1707         return NULL;
1708 }
1709
1710 static int
1711 ice_send_driver_ver(struct ice_hw *hw)
1712 {
1713         struct ice_driver_ver dv;
1714
1715         /* we don't have driver version use 0 for dummy */
1716         dv.major_ver = 0;
1717         dv.minor_ver = 0;
1718         dv.build_ver = 0;
1719         dv.subbuild_ver = 0;
1720         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1721
1722         return ice_aq_send_driver_ver(hw, &dv, NULL);
1723 }
1724
1725 static int
1726 ice_pf_setup(struct ice_pf *pf)
1727 {
1728         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1729         struct ice_vsi *vsi;
1730         uint16_t unused;
1731
1732         /* Clear all stats counters */
1733         pf->offset_loaded = false;
1734         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1735         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1736         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1737         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1738
1739         /* force guaranteed filter pool for PF */
1740         ice_alloc_fd_guar_item(hw, &unused,
1741                                hw->func_caps.fd_fltr_guar);
1742         /* force shared filter pool for PF */
1743         ice_alloc_fd_shrd_item(hw, &unused,
1744                                hw->func_caps.fd_fltr_best_effort);
1745
1746         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1747         if (!vsi) {
1748                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1749                 return -EINVAL;
1750         }
1751
1752         pf->main_vsi = vsi;
1753
1754         return 0;
1755 }
1756
1757 /* PCIe configuration space setting */
1758 #define PCI_CFG_SPACE_SIZE          256
1759 #define PCI_CFG_SPACE_EXP_SIZE      4096
1760 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1761 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1762 #define PCI_EXT_CAP_ID_DSN          0x03
1763
1764 static int
1765 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1766 {
1767         uint32_t header;
1768         int ttl;
1769         int pos = PCI_CFG_SPACE_SIZE;
1770
1771         /* minimum 8 bytes per capability */
1772         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1773
1774         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1775                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1776                 return -1;
1777         }
1778
1779         /*
1780          * If we have no capabilities, this is indicated by cap ID,
1781          * cap version and next pointer all being 0.
1782          */
1783         if (header == 0)
1784                 return 0;
1785
1786         while (ttl-- > 0) {
1787                 if (PCI_EXT_CAP_ID(header) == cap)
1788                         return pos;
1789
1790                 pos = PCI_EXT_CAP_NEXT(header);
1791
1792                 if (pos < PCI_CFG_SPACE_SIZE)
1793                         break;
1794
1795                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1796                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1797                         return -1;
1798                 }
1799         }
1800
1801         return 0;
1802 }
1803
1804 /*
1805  * Extract device serial number from PCIe Configuration Space and
1806  * determine the pkg file path according to the DSN.
1807  */
1808 static int
1809 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1810 {
1811         int pos;
1812         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1813         uint32_t dsn_low, dsn_high;
1814         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1815
1816         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1817
1818         if (pos) {
1819                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1820                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1821                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1822                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1823         } else {
1824                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1825                 goto fail_dsn;
1826         }
1827
1828         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1829                 ICE_MAX_PKG_FILENAME_SIZE);
1830         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1831                 return 0;
1832
1833         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1834                 ICE_MAX_PKG_FILENAME_SIZE);
1835         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1836                 return 0;
1837
1838 fail_dsn:
1839         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1840         if (!access(pkg_file, 0))
1841                 return 0;
1842         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1843         return 0;
1844 }
1845
1846 enum ice_pkg_type
1847 ice_load_pkg_type(struct ice_hw *hw)
1848 {
1849         enum ice_pkg_type package_type;
1850
1851         /* store the activated package type (OS default or Comms) */
1852         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1853                 ICE_PKG_NAME_SIZE))
1854                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1855         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1856                 ICE_PKG_NAME_SIZE))
1857                 package_type = ICE_PKG_TYPE_COMMS;
1858         else
1859                 package_type = ICE_PKG_TYPE_UNKNOWN;
1860
1861         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1862                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1863                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1864                 hw->active_pkg_name);
1865
1866         return package_type;
1867 }
1868
1869 static int ice_load_pkg(struct rte_eth_dev *dev)
1870 {
1871         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1873         int err;
1874         uint8_t *buf;
1875         int buf_len;
1876         FILE *file;
1877         struct stat fstat;
1878         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1879         struct ice_adapter *ad =
1880                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1881
1882         ice_pkg_file_search_path(pci_dev, pkg_file);
1883
1884         file = fopen(pkg_file, "rb");
1885         if (!file)  {
1886                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1887                 return -1;
1888         }
1889
1890         err = stat(pkg_file, &fstat);
1891         if (err) {
1892                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1893                 fclose(file);
1894                 return err;
1895         }
1896
1897         buf_len = fstat.st_size;
1898         buf = rte_malloc(NULL, buf_len, 0);
1899
1900         if (!buf) {
1901                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1902                                 buf_len);
1903                 fclose(file);
1904                 return -1;
1905         }
1906
1907         err = fread(buf, buf_len, 1, file);
1908         if (err != 1) {
1909                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1910                 fclose(file);
1911                 err = -1;
1912                 goto fail_exit;
1913         }
1914
1915         fclose(file);
1916
1917         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1918         if (err) {
1919                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1920                 goto fail_exit;
1921         }
1922
1923         /* store the loaded pkg type info */
1924         ad->active_pkg_type = ice_load_pkg_type(hw);
1925
1926         err = ice_init_hw_tbls(hw);
1927         if (err) {
1928                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1929                 goto fail_init_tbls;
1930         }
1931
1932         return 0;
1933
1934 fail_init_tbls:
1935         rte_free(hw->pkg_copy);
1936 fail_exit:
1937         rte_free(buf);
1938         return err;
1939 }
1940
1941 static void
1942 ice_base_queue_get(struct ice_pf *pf)
1943 {
1944         uint32_t reg;
1945         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1946
1947         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1948         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1949                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1950         } else {
1951                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1952                                         " index");
1953         }
1954 }
1955
1956 static int
1957 parse_bool(const char *key, const char *value, void *args)
1958 {
1959         int *i = (int *)args;
1960         char *end;
1961         int num;
1962
1963         num = strtoul(value, &end, 10);
1964
1965         if (num != 0 && num != 1) {
1966                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1967                         "value must be 0 or 1",
1968                         value, key);
1969                 return -1;
1970         }
1971
1972         *i = num;
1973         return 0;
1974 }
1975
1976 static int ice_parse_devargs(struct rte_eth_dev *dev)
1977 {
1978         struct ice_adapter *ad =
1979                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1980         struct rte_devargs *devargs = dev->device->devargs;
1981         struct rte_kvargs *kvlist;
1982         int ret;
1983
1984         if (devargs == NULL)
1985                 return 0;
1986
1987         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1988         if (kvlist == NULL) {
1989                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1990                 return -EINVAL;
1991         }
1992
1993         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1994         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1995                sizeof(ad->devargs.proto_xtr));
1996
1997         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1998                                  &handle_proto_xtr_arg, &ad->devargs);
1999         if (ret)
2000                 goto bail;
2001
2002         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
2003                                  &parse_bool, &ad->devargs.safe_mode_support);
2004         if (ret)
2005                 goto bail;
2006
2007         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
2008                                  &parse_bool, &ad->devargs.pipe_mode_support);
2009         if (ret)
2010                 goto bail;
2011
2012         ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
2013                                  &parse_bool, &ad->devargs.flow_mark_support);
2014         if (ret)
2015                 goto bail;
2016
2017 bail:
2018         rte_kvargs_free(kvlist);
2019         return ret;
2020 }
2021
2022 /* Forward LLDP packets to default VSI by set switch rules */
2023 static int
2024 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
2025 {
2026         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2027         struct ice_fltr_list_entry *s_list_itr = NULL;
2028         struct LIST_HEAD_TYPE list_head;
2029         int ret = 0;
2030
2031         INIT_LIST_HEAD(&list_head);
2032
2033         s_list_itr = (struct ice_fltr_list_entry *)
2034                         ice_malloc(hw, sizeof(*s_list_itr));
2035         if (!s_list_itr)
2036                 return -ENOMEM;
2037         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2038         s_list_itr->fltr_info.vsi_handle = vsi->idx;
2039         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2040                         RTE_ETHER_TYPE_LLDP;
2041         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2042         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2043         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2044         LIST_ADD(&s_list_itr->list_entry, &list_head);
2045         if (on)
2046                 ret = ice_add_eth_mac(hw, &list_head);
2047         else
2048                 ret = ice_remove_eth_mac(hw, &list_head);
2049
2050         rte_free(s_list_itr);
2051         return ret;
2052 }
2053
2054 static enum ice_status
2055 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2056                 uint16_t num, uint16_t desc_id,
2057                 uint16_t *prof_buf, uint16_t *num_prof)
2058 {
2059         struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2060         int ret;
2061         uint16_t buf_len;
2062         bool res_shared = 1;
2063         struct ice_aq_desc aq_desc;
2064         struct ice_sq_cd *cd = NULL;
2065         struct ice_aqc_get_allocd_res_desc *cmd =
2066                         &aq_desc.params.get_res_desc;
2067
2068         buf_len = sizeof(resp_buf->elem) * num;
2069         resp_buf = ice_malloc(hw, buf_len);
2070         if (!resp_buf)
2071                 return -ENOMEM;
2072
2073         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2074                         ice_aqc_opc_get_allocd_res_desc);
2075
2076         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2077                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2078                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2079         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2080
2081         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2082         if (!ret)
2083                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2084         else
2085                 goto exit;
2086
2087         ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2088                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2089
2090 exit:
2091         rte_free(resp_buf);
2092         return ret;
2093 }
2094 static int
2095 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2096 {
2097         int ret;
2098         uint16_t prof_id;
2099         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2100         uint16_t first_desc = 1;
2101         uint16_t num_prof = 0;
2102
2103         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2104                         first_desc, prof_buf, &num_prof);
2105         if (ret) {
2106                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2107                 return ret;
2108         }
2109
2110         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2111                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2112                 if (ret) {
2113                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2114                         return ret;
2115                 }
2116         }
2117         return 0;
2118 }
2119
2120 static int
2121 ice_reset_fxp_resource(struct ice_hw *hw)
2122 {
2123         int ret;
2124
2125         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2126         if (ret) {
2127                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2128                 return ret;
2129         }
2130
2131         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2132         if (ret) {
2133                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2134                 return ret;
2135         }
2136
2137         return 0;
2138 }
2139
2140 static void
2141 ice_rss_ctx_init(struct ice_pf *pf)
2142 {
2143         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2144         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2145
2146         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2147         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2148
2149         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2150         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2151 }
2152
2153 static int
2154 ice_dev_init(struct rte_eth_dev *dev)
2155 {
2156         struct rte_pci_device *pci_dev;
2157         struct rte_intr_handle *intr_handle;
2158         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2159         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2160         struct ice_adapter *ad =
2161                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2162         struct ice_vsi *vsi;
2163         int ret;
2164
2165         dev->dev_ops = &ice_eth_dev_ops;
2166         dev->rx_pkt_burst = ice_recv_pkts;
2167         dev->tx_pkt_burst = ice_xmit_pkts;
2168         dev->tx_pkt_prepare = ice_prep_pkts;
2169
2170         /* for secondary processes, we don't initialise any further as primary
2171          * has already done this work.
2172          */
2173         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2174                 ice_set_rx_function(dev);
2175                 ice_set_tx_function(dev);
2176                 return 0;
2177         }
2178
2179         ice_set_default_ptype_table(dev);
2180         pci_dev = RTE_DEV_TO_PCI(dev->device);
2181         intr_handle = &pci_dev->intr_handle;
2182
2183         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2184         pf->adapter->eth_dev = dev;
2185         pf->dev_data = dev->data;
2186         hw->back = pf->adapter;
2187         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2188         hw->vendor_id = pci_dev->id.vendor_id;
2189         hw->device_id = pci_dev->id.device_id;
2190         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2191         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2192         hw->bus.device = pci_dev->addr.devid;
2193         hw->bus.func = pci_dev->addr.function;
2194
2195         ret = ice_parse_devargs(dev);
2196         if (ret) {
2197                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2198                 return -EINVAL;
2199         }
2200
2201         ice_init_controlq_parameter(hw);
2202
2203         ret = ice_init_hw(hw);
2204         if (ret) {
2205                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2206                 return -EINVAL;
2207         }
2208
2209         ret = ice_load_pkg(dev);
2210         if (ret) {
2211                 if (ad->devargs.safe_mode_support == 0) {
2212                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2213                                         "Use safe-mode-support=1 to enter Safe Mode");
2214                         return ret;
2215                 }
2216
2217                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2218                                         "Entering Safe Mode");
2219                 ad->is_safe_mode = 1;
2220         }
2221
2222         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2223                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2224                      hw->api_maj_ver, hw->api_min_ver);
2225
2226         ice_pf_sw_init(dev);
2227         ret = ice_init_mac_address(dev);
2228         if (ret) {
2229                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2230                 goto err_init_mac;
2231         }
2232
2233         /* Pass the information to the rte_eth_dev_close() that it should also
2234          * release the private port resources.
2235          */
2236         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2237
2238         ret = ice_res_pool_init(&pf->msix_pool, 1,
2239                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2240         if (ret) {
2241                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2242                 goto err_msix_pool_init;
2243         }
2244
2245         ret = ice_pf_setup(pf);
2246         if (ret) {
2247                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2248                 goto err_pf_setup;
2249         }
2250
2251         ret = ice_send_driver_ver(hw);
2252         if (ret) {
2253                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2254                 goto err_pf_setup;
2255         }
2256
2257         vsi = pf->main_vsi;
2258
2259         /* Disable double vlan by default */
2260         ice_vsi_config_double_vlan(vsi, false);
2261
2262         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2263         if (ret != ICE_SUCCESS)
2264                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2265         ret = ice_init_dcb(hw, true);
2266         if (ret != ICE_SUCCESS)
2267                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2268         /* Forward LLDP packets to default VSI */
2269         ret = ice_vsi_config_sw_lldp(vsi, true);
2270         if (ret != ICE_SUCCESS)
2271                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2272         /* register callback func to eal lib */
2273         rte_intr_callback_register(intr_handle,
2274                                    ice_interrupt_handler, dev);
2275
2276         ice_pf_enable_irq0(hw);
2277
2278         /* enable uio intr after callback register */
2279         rte_intr_enable(intr_handle);
2280
2281         /* get base queue pairs index  in the device */
2282         ice_base_queue_get(pf);
2283
2284         /* Initialize RSS context for gtpu_eh */
2285         ice_rss_ctx_init(pf);
2286
2287         if (!ad->is_safe_mode) {
2288                 ret = ice_flow_init(ad);
2289                 if (ret) {
2290                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2291                         return ret;
2292                 }
2293         }
2294
2295         ret = ice_reset_fxp_resource(hw);
2296         if (ret) {
2297                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2298                 return ret;
2299         }
2300
2301         return 0;
2302
2303 err_pf_setup:
2304         ice_res_pool_destroy(&pf->msix_pool);
2305 err_msix_pool_init:
2306         rte_free(dev->data->mac_addrs);
2307         dev->data->mac_addrs = NULL;
2308 err_init_mac:
2309         ice_sched_cleanup_all(hw);
2310         rte_free(hw->port_info);
2311         ice_shutdown_all_ctrlq(hw);
2312         rte_free(pf->proto_xtr);
2313
2314         return ret;
2315 }
2316
2317 int
2318 ice_release_vsi(struct ice_vsi *vsi)
2319 {
2320         struct ice_hw *hw;
2321         struct ice_vsi_ctx vsi_ctx;
2322         enum ice_status ret;
2323         int error = 0;
2324
2325         if (!vsi)
2326                 return error;
2327
2328         hw = ICE_VSI_TO_HW(vsi);
2329
2330         ice_remove_all_mac_vlan_filters(vsi);
2331
2332         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2333
2334         vsi_ctx.vsi_num = vsi->vsi_id;
2335         vsi_ctx.info = vsi->info;
2336         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2337         if (ret != ICE_SUCCESS) {
2338                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2339                 error = -1;
2340         }
2341
2342         rte_free(vsi->rss_lut);
2343         rte_free(vsi->rss_key);
2344         rte_free(vsi);
2345         return error;
2346 }
2347
2348 void
2349 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2350 {
2351         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2352         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2353         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2354         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2355         uint16_t msix_intr, i;
2356
2357         /* disable interrupt and also clear all the exist config */
2358         for (i = 0; i < vsi->nb_qps; i++) {
2359                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2360                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2361                 rte_wmb();
2362         }
2363
2364         if (rte_intr_allow_others(intr_handle))
2365                 /* vfio-pci */
2366                 for (i = 0; i < vsi->nb_msix; i++) {
2367                         msix_intr = vsi->msix_intr + i;
2368                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2369                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2370                 }
2371         else
2372                 /* igb_uio */
2373                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2374 }
2375
2376 static void
2377 ice_dev_stop(struct rte_eth_dev *dev)
2378 {
2379         struct rte_eth_dev_data *data = dev->data;
2380         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2381         struct ice_vsi *main_vsi = pf->main_vsi;
2382         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2383         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2384         uint16_t i;
2385
2386         /* avoid stopping again */
2387         if (pf->adapter_stopped)
2388                 return;
2389
2390         /* stop and clear all Rx queues */
2391         for (i = 0; i < data->nb_rx_queues; i++)
2392                 ice_rx_queue_stop(dev, i);
2393
2394         /* stop and clear all Tx queues */
2395         for (i = 0; i < data->nb_tx_queues; i++)
2396                 ice_tx_queue_stop(dev, i);
2397
2398         /* disable all queue interrupts */
2399         ice_vsi_disable_queues_intr(main_vsi);
2400
2401         if (pf->init_link_up)
2402                 ice_dev_set_link_up(dev);
2403         else
2404                 ice_dev_set_link_down(dev);
2405
2406         /* Clean datapath event and queue/vec mapping */
2407         rte_intr_efd_disable(intr_handle);
2408         if (intr_handle->intr_vec) {
2409                 rte_free(intr_handle->intr_vec);
2410                 intr_handle->intr_vec = NULL;
2411         }
2412
2413         pf->adapter_stopped = true;
2414 }
2415
2416 static void
2417 ice_dev_close(struct rte_eth_dev *dev)
2418 {
2419         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2420         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2421         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2422         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2423         struct ice_adapter *ad =
2424                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2425
2426         /* Since stop will make link down, then the link event will be
2427          * triggered, disable the irq firstly to avoid the port_infoe etc
2428          * resources deallocation causing the interrupt service thread
2429          * crash.
2430          */
2431         ice_pf_disable_irq0(hw);
2432
2433         ice_dev_stop(dev);
2434
2435         if (!ad->is_safe_mode)
2436                 ice_flow_uninit(ad);
2437
2438         /* release all queue resource */
2439         ice_free_queues(dev);
2440
2441         ice_res_pool_destroy(&pf->msix_pool);
2442         ice_release_vsi(pf->main_vsi);
2443         ice_sched_cleanup_all(hw);
2444         ice_free_hw_tbls(hw);
2445         rte_free(hw->port_info);
2446         hw->port_info = NULL;
2447         ice_shutdown_all_ctrlq(hw);
2448         rte_free(pf->proto_xtr);
2449         pf->proto_xtr = NULL;
2450
2451         dev->dev_ops = NULL;
2452         dev->rx_pkt_burst = NULL;
2453         dev->tx_pkt_burst = NULL;
2454
2455         rte_free(dev->data->mac_addrs);
2456         dev->data->mac_addrs = NULL;
2457
2458         /* disable uio intr before callback unregister */
2459         rte_intr_disable(intr_handle);
2460
2461         /* unregister callback func from eal lib */
2462         rte_intr_callback_unregister(intr_handle,
2463                                      ice_interrupt_handler, dev);
2464 }
2465
2466 static int
2467 ice_dev_uninit(struct rte_eth_dev *dev)
2468 {
2469         ice_dev_close(dev);
2470
2471         return 0;
2472 }
2473
2474 static int
2475 ice_add_rss_cfg_post(struct ice_pf *pf, uint32_t hdr, uint64_t fld, bool symm)
2476 {
2477         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2478         struct ice_vsi *vsi = pf->main_vsi;
2479
2480         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) {
2481                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2482                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2483                         pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr = hdr;
2484                         pf->gtpu_hash_ctx.ipv4_udp.hash_fld = fld;
2485                         pf->gtpu_hash_ctx.ipv4_udp.symm = symm;
2486                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2487                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2488                         pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr = hdr;
2489                         pf->gtpu_hash_ctx.ipv6_udp.hash_fld = fld;
2490                         pf->gtpu_hash_ctx.ipv6_udp.symm = symm;
2491                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2492                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2493                         pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr = hdr;
2494                         pf->gtpu_hash_ctx.ipv4_tcp.hash_fld = fld;
2495                         pf->gtpu_hash_ctx.ipv4_tcp.symm = symm;
2496                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2497                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2498                         pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr = hdr;
2499                         pf->gtpu_hash_ctx.ipv6_tcp.hash_fld = fld;
2500                         pf->gtpu_hash_ctx.ipv6_tcp.symm = symm;
2501                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2502                         pf->gtpu_hash_ctx.ipv4.pkt_hdr = hdr;
2503                         pf->gtpu_hash_ctx.ipv4.hash_fld = fld;
2504                         pf->gtpu_hash_ctx.ipv4.symm = symm;
2505                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2506                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2507                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2508                         pf->gtpu_hash_ctx.ipv6.pkt_hdr = hdr;
2509                         pf->gtpu_hash_ctx.ipv6.hash_fld = fld;
2510                         pf->gtpu_hash_ctx.ipv6.symm = symm;
2511                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2512                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2513                 }
2514         }
2515
2516         if (hdr & (ICE_FLOW_SEG_HDR_GTPU_DWN |
2517             ICE_FLOW_SEG_HDR_GTPU_UP)) {
2518                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2519                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2520                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv4)) {
2521                                 ice_add_rss_cfg(hw, vsi->idx,
2522                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2523                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr,
2524                                         pf->gtpu_hash_ctx.ipv4.symm);
2525                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv4);
2526                         }
2527                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2528                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2529                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv6)) {
2530                                 ice_add_rss_cfg(hw, vsi->idx,
2531                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2532                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr,
2533                                         pf->gtpu_hash_ctx.ipv6.symm);
2534                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv6);
2535                         }
2536                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2537                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2538                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv4)) {
2539                                 ice_add_rss_cfg(hw, vsi->idx,
2540                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2541                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr,
2542                                         pf->gtpu_hash_ctx.ipv4.symm);
2543                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv4);
2544                         }
2545                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2546                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2547                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv6)) {
2548                                 ice_add_rss_cfg(hw, vsi->idx,
2549                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2550                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr,
2551                                         pf->gtpu_hash_ctx.ipv6.symm);
2552                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv6);
2553                         }
2554                 }
2555         }
2556
2557         return 0;
2558 }
2559
2560 static int
2561 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2562 {
2563         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2564         struct ice_vsi *vsi = pf->main_vsi;
2565
2566         if (hdr & (ICE_FLOW_SEG_HDR_GTPU_DWN |
2567             ICE_FLOW_SEG_HDR_GTPU_UP)) {
2568                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2569                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2570                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_udp)) {
2571                                 ice_rem_rss_cfg(hw, vsi->idx,
2572                                         pf->gtpu_hash_ctx.ipv4_udp.hash_fld,
2573                                         pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr);
2574                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2575                         }
2576
2577                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2578                                 ice_rem_rss_cfg(hw, vsi->idx,
2579                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2580                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2581                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv4);
2582                         }
2583                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2584                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2585                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_udp)) {
2586                                 ice_rem_rss_cfg(hw, vsi->idx,
2587                                         pf->gtpu_hash_ctx.ipv6_udp.hash_fld,
2588                                         pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr);
2589                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2590                         }
2591
2592                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2593                                 ice_rem_rss_cfg(hw, vsi->idx,
2594                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2595                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2596                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv6);
2597                         }
2598                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2599                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2600                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_tcp)) {
2601                                 ice_rem_rss_cfg(hw, vsi->idx,
2602                                         pf->gtpu_hash_ctx.ipv4_tcp.hash_fld,
2603                                         pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr);
2604                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2605                         }
2606
2607                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2608                                 ice_rem_rss_cfg(hw, vsi->idx,
2609                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2610                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2611                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv4);
2612                         }
2613                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2614                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2615                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_tcp)) {
2616                                 ice_rem_rss_cfg(hw, vsi->idx,
2617                                         pf->gtpu_hash_ctx.ipv6_tcp.hash_fld,
2618                                         pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr);
2619                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2620                         }
2621
2622                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2623                                 ice_rem_rss_cfg(hw, vsi->idx,
2624                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2625                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2626                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv6);
2627                         }
2628                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2629                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2630                                 ice_rem_rss_cfg(hw, vsi->idx,
2631                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2632                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2633                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2634                         }
2635
2636                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_udp)) {
2637                                 ice_rem_rss_cfg(hw, vsi->idx,
2638                                         pf->gtpu_hash_ctx.ipv4_udp.hash_fld,
2639                                         pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr);
2640                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2641                         }
2642
2643                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_tcp)) {
2644                                 ice_rem_rss_cfg(hw, vsi->idx,
2645                                         pf->gtpu_hash_ctx.ipv4_tcp.hash_fld,
2646                                         pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr);
2647                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2648                         }
2649                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2650                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2651                                 ice_rem_rss_cfg(hw, vsi->idx,
2652                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2653                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2654                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2655                         }
2656
2657                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_udp)) {
2658                                 ice_rem_rss_cfg(hw, vsi->idx,
2659                                         pf->gtpu_hash_ctx.ipv6_udp.hash_fld,
2660                                         pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr);
2661                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2662                         }
2663
2664                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_tcp)) {
2665                                 ice_rem_rss_cfg(hw, vsi->idx,
2666                                         pf->gtpu_hash_ctx.ipv6_tcp.hash_fld,
2667                                         pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr);
2668                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2669                         }
2670                 }
2671         }
2672
2673         return 0;
2674 }
2675
2676 static int
2677 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2678 {
2679         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) {
2680                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2681                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2682                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2683                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2684                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2685                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2686                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2687                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2688                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2689                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2690                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2691                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2692                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2693                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2694                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2695                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2696                 }
2697         }
2698
2699         return 0;
2700 }
2701
2702 int
2703 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2704                 uint64_t fld, uint32_t hdr)
2705 {
2706         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2707         int ret;
2708
2709         ret = ice_rem_rss_cfg(hw, vsi_id, fld, hdr);
2710         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2711                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2712
2713         ret = ice_rem_rss_cfg_post(pf, hdr);
2714         if (ret)
2715                 PMD_DRV_LOG(ERR, "remove rss cfg post failed\n");
2716
2717         return 0;
2718 }
2719
2720 int
2721 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2722                 uint64_t fld, uint32_t hdr, bool symm)
2723 {
2724         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2725         int ret;
2726
2727         ret = ice_add_rss_cfg_pre(pf, hdr);
2728         if (ret)
2729                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2730
2731         ret = ice_add_rss_cfg(hw, vsi_id, fld, hdr, symm);
2732         if (ret)
2733                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2734
2735         ret = ice_add_rss_cfg_post(pf, hdr, fld, symm);
2736         if (ret)
2737                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2738
2739         return 0;
2740 }
2741
2742 static void
2743 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2744 {
2745         struct ice_vsi *vsi = pf->main_vsi;
2746         int ret;
2747
2748         /* Configure RSS for IPv4 with src/dst addr as input set */
2749         if (rss_hf & ETH_RSS_IPV4) {
2750                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2751                                       ICE_FLOW_SEG_HDR_IPV4 |
2752                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2753                 if (ret)
2754                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2755                                     __func__, ret);
2756         }
2757
2758         /* Configure RSS for IPv6 with src/dst addr as input set */
2759         if (rss_hf & ETH_RSS_IPV6) {
2760                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2761                                       ICE_FLOW_SEG_HDR_IPV6 |
2762                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2763                 if (ret)
2764                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2765                                     __func__, ret);
2766         }
2767
2768         /* Configure RSS for udp4 with src/dst addr and port as input set */
2769         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2770                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2771                                       ICE_FLOW_SEG_HDR_UDP |
2772                                       ICE_FLOW_SEG_HDR_IPV4 |
2773                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2774                 if (ret)
2775                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2776                                     __func__, ret);
2777         }
2778
2779         /* Configure RSS for udp6 with src/dst addr and port as input set */
2780         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2781                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2782                                       ICE_FLOW_SEG_HDR_UDP |
2783                                       ICE_FLOW_SEG_HDR_IPV6 |
2784                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2785                 if (ret)
2786                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2787                                     __func__, ret);
2788         }
2789
2790         /* Configure RSS for tcp4 with src/dst addr and port as input set */
2791         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2792                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2793                                       ICE_FLOW_SEG_HDR_TCP |
2794                                       ICE_FLOW_SEG_HDR_IPV4 |
2795                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2796                 if (ret)
2797                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2798                                     __func__, ret);
2799         }
2800
2801         /* Configure RSS for tcp6 with src/dst addr and port as input set */
2802         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2803                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2804                                       ICE_FLOW_SEG_HDR_TCP |
2805                                       ICE_FLOW_SEG_HDR_IPV6 |
2806                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2807                 if (ret)
2808                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2809                                     __func__, ret);
2810         }
2811
2812         /* Configure RSS for sctp4 with src/dst addr and port as input set */
2813         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2814                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2815                                       ICE_FLOW_SEG_HDR_SCTP |
2816                                       ICE_FLOW_SEG_HDR_IPV4 |
2817                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2818                 if (ret)
2819                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2820                                     __func__, ret);
2821         }
2822
2823         /* Configure RSS for sctp6 with src/dst addr and port as input set */
2824         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2825                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2826                                       ICE_FLOW_SEG_HDR_SCTP |
2827                                       ICE_FLOW_SEG_HDR_IPV6 |
2828                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2829                 if (ret)
2830                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2831                                     __func__, ret);
2832         }
2833
2834         if (rss_hf & ETH_RSS_IPV4) {
2835                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2836                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2837                                 ICE_FLOW_SEG_HDR_IPV4 |
2838                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2839                 if (ret)
2840                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
2841                                     __func__, ret);
2842
2843                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2844                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2845                                 ICE_FLOW_SEG_HDR_IPV4 |
2846                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2847                 if (ret)
2848                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
2849                                     __func__, ret);
2850
2851                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2852                                 ICE_FLOW_SEG_HDR_PPPOE |
2853                                 ICE_FLOW_SEG_HDR_IPV4 |
2854                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2855                 if (ret)
2856                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2857                                     __func__, ret);
2858         }
2859
2860         if (rss_hf & ETH_RSS_IPV6) {
2861                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2862                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2863                                 ICE_FLOW_SEG_HDR_IPV6 |
2864                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2865                 if (ret)
2866                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
2867                                     __func__, ret);
2868
2869                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2870                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2871                                 ICE_FLOW_SEG_HDR_IPV6 |
2872                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2873                 if (ret)
2874                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
2875                                     __func__, ret);
2876
2877                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2878                                 ICE_FLOW_SEG_HDR_PPPOE |
2879                                 ICE_FLOW_SEG_HDR_IPV6 |
2880                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2881                 if (ret)
2882                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2883                                     __func__, ret);
2884         }
2885
2886         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2887                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2888                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2889                                 ICE_FLOW_SEG_HDR_UDP |
2890                                 ICE_FLOW_SEG_HDR_IPV4 |
2891                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2892                 if (ret)
2893                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
2894                                     __func__, ret);
2895
2896                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2897                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2898                                 ICE_FLOW_SEG_HDR_UDP |
2899                                 ICE_FLOW_SEG_HDR_IPV4 |
2900                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2901                 if (ret)
2902                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
2903                                     __func__, ret);
2904
2905                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2906                                 ICE_FLOW_SEG_HDR_PPPOE |
2907                                 ICE_FLOW_SEG_HDR_UDP |
2908                                 ICE_FLOW_SEG_HDR_IPV4 |
2909                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2910                 if (ret)
2911                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2912                                     __func__, ret);
2913         }
2914
2915         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2916                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2917                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2918                                 ICE_FLOW_SEG_HDR_UDP |
2919                                 ICE_FLOW_SEG_HDR_IPV6 |
2920                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2921                 if (ret)
2922                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
2923                                     __func__, ret);
2924
2925                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2926                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2927                                 ICE_FLOW_SEG_HDR_UDP |
2928                                 ICE_FLOW_SEG_HDR_IPV6 |
2929                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2930                 if (ret)
2931                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
2932                                     __func__, ret);
2933
2934                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2935                                 ICE_FLOW_SEG_HDR_PPPOE |
2936                                 ICE_FLOW_SEG_HDR_UDP |
2937                                 ICE_FLOW_SEG_HDR_IPV6 |
2938                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2939                 if (ret)
2940                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
2941                                     __func__, ret);
2942         }
2943
2944         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2945                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2946                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2947                                 ICE_FLOW_SEG_HDR_TCP |
2948                                 ICE_FLOW_SEG_HDR_IPV4 |
2949                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2950                 if (ret)
2951                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
2952                                     __func__, ret);
2953
2954                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2955                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2956                                 ICE_FLOW_SEG_HDR_TCP |
2957                                 ICE_FLOW_SEG_HDR_IPV4 |
2958                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2959                 if (ret)
2960                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
2961                                     __func__, ret);
2962
2963                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2964                                 ICE_FLOW_SEG_HDR_PPPOE |
2965                                 ICE_FLOW_SEG_HDR_TCP |
2966                                 ICE_FLOW_SEG_HDR_IPV4 |
2967                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2968                 if (ret)
2969                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
2970                                     __func__, ret);
2971         }
2972
2973         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2974                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2975                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2976                                 ICE_FLOW_SEG_HDR_TCP |
2977                                 ICE_FLOW_SEG_HDR_IPV6 |
2978                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2979                 if (ret)
2980                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
2981                                     __func__, ret);
2982
2983                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2984                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2985                                 ICE_FLOW_SEG_HDR_TCP |
2986                                 ICE_FLOW_SEG_HDR_IPV6 |
2987                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2988                 if (ret)
2989                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
2990                                     __func__, ret);
2991
2992                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2993                                 ICE_FLOW_SEG_HDR_PPPOE |
2994                                 ICE_FLOW_SEG_HDR_TCP |
2995                                 ICE_FLOW_SEG_HDR_IPV6 |
2996                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2997                 if (ret)
2998                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
2999                                     __func__, ret);
3000         }
3001
3002         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
3003                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4,
3004                                 ICE_FLOW_SEG_HDR_GTPU_IP |
3005                                 ICE_FLOW_SEG_HDR_SCTP |
3006                                 ICE_FLOW_SEG_HDR_IPV4 |
3007                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3008                 if (ret)
3009                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_SCTP rss flow fail %d",
3010                                     __func__, ret);
3011
3012                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4,
3013                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3014                                 ICE_FLOW_SEG_HDR_SCTP |
3015                                 ICE_FLOW_SEG_HDR_IPV4 |
3016                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3017                 if (ret)
3018                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_SCTP rss flow fail %d",
3019                                     __func__, ret);
3020         }
3021
3022         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
3023                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6,
3024                                 ICE_FLOW_SEG_HDR_GTPU_IP |
3025                                 ICE_FLOW_SEG_HDR_SCTP |
3026                                 ICE_FLOW_SEG_HDR_IPV6 |
3027                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3028                 if (ret)
3029                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_SCTP rss flow fail %d",
3030                                     __func__, ret);
3031
3032                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6,
3033                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3034                                 ICE_FLOW_SEG_HDR_SCTP |
3035                                 ICE_FLOW_SEG_HDR_IPV6 |
3036                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3037                 if (ret)
3038                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_SCTP rss flow fail %d",
3039                                     __func__, ret);
3040         }
3041 }
3042
3043 static int ice_init_rss(struct ice_pf *pf)
3044 {
3045         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3046         struct ice_vsi *vsi = pf->main_vsi;
3047         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3048         struct rte_eth_rss_conf *rss_conf;
3049         struct ice_aqc_get_set_rss_keys key;
3050         uint16_t i, nb_q;
3051         int ret = 0;
3052         bool is_safe_mode = pf->adapter->is_safe_mode;
3053         uint32_t reg;
3054
3055         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3056         nb_q = dev->data->nb_rx_queues;
3057         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3058         vsi->rss_lut_size = pf->hash_lut_size;
3059
3060         if (is_safe_mode) {
3061                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3062                 return 0;
3063         }
3064
3065         if (!vsi->rss_key) {
3066                 vsi->rss_key = rte_zmalloc(NULL,
3067                                            vsi->rss_key_size, 0);
3068                 if (vsi->rss_key == NULL) {
3069                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3070                         return -ENOMEM;
3071                 }
3072         }
3073         if (!vsi->rss_lut) {
3074                 vsi->rss_lut = rte_zmalloc(NULL,
3075                                            vsi->rss_lut_size, 0);
3076                 if (vsi->rss_lut == NULL) {
3077                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3078                         rte_free(vsi->rss_key);
3079                         vsi->rss_key = NULL;
3080                         return -ENOMEM;
3081                 }
3082         }
3083         /* configure RSS key */
3084         if (!rss_conf->rss_key) {
3085                 /* Calculate the default hash key */
3086                 for (i = 0; i <= vsi->rss_key_size; i++)
3087                         vsi->rss_key[i] = (uint8_t)rte_rand();
3088         } else {
3089                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3090                            RTE_MIN(rss_conf->rss_key_len,
3091                                    vsi->rss_key_size));
3092         }
3093         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3094         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3095         if (ret)
3096                 goto out;
3097
3098         /* init RSS LUT table */
3099         for (i = 0; i < vsi->rss_lut_size; i++)
3100                 vsi->rss_lut[i] = i % nb_q;
3101
3102         ret = ice_aq_set_rss_lut(hw, vsi->idx,
3103                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
3104                                  vsi->rss_lut, vsi->rss_lut_size);
3105         if (ret)
3106                 goto out;
3107
3108         /* Enable registers for symmetric_toeplitz function. */
3109         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3110         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3111                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3112         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3113
3114         /* RSS hash configuration */
3115         ice_rss_hash_set(pf, rss_conf->rss_hf);
3116
3117         return 0;
3118 out:
3119         rte_free(vsi->rss_key);
3120         vsi->rss_key = NULL;
3121         rte_free(vsi->rss_lut);
3122         vsi->rss_lut = NULL;
3123         return -EINVAL;
3124 }
3125
3126 static int
3127 ice_dev_configure(struct rte_eth_dev *dev)
3128 {
3129         struct ice_adapter *ad =
3130                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3131         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3132         int ret;
3133
3134         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3135          * bulk allocation or vector Rx preconditions we will reset it.
3136          */
3137         ad->rx_bulk_alloc_allowed = true;
3138         ad->tx_simple_allowed = true;
3139
3140         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3141                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3142
3143         ret = ice_init_rss(pf);
3144         if (ret) {
3145                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3146                 return ret;
3147         }
3148
3149         return 0;
3150 }
3151
3152 static void
3153 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3154                        int base_queue, int nb_queue)
3155 {
3156         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3157         uint32_t val, val_tx;
3158         int i;
3159
3160         for (i = 0; i < nb_queue; i++) {
3161                 /*do actual bind*/
3162                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3163                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3164                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3165                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3166
3167                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3168                             base_queue + i, msix_vect);
3169                 /* set ITR0 value */
3170                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
3171                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3172                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3173         }
3174 }
3175
3176 void
3177 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3178 {
3179         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3180         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3181         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3182         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3183         uint16_t msix_vect = vsi->msix_intr;
3184         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3185         uint16_t queue_idx = 0;
3186         int record = 0;
3187         int i;
3188
3189         /* clear Rx/Tx queue interrupt */
3190         for (i = 0; i < vsi->nb_used_qps; i++) {
3191                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3192                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3193         }
3194
3195         /* PF bind interrupt */
3196         if (rte_intr_dp_is_en(intr_handle)) {
3197                 queue_idx = 0;
3198                 record = 1;
3199         }
3200
3201         for (i = 0; i < vsi->nb_used_qps; i++) {
3202                 if (nb_msix <= 1) {
3203                         if (!rte_intr_allow_others(intr_handle))
3204                                 msix_vect = ICE_MISC_VEC_ID;
3205
3206                         /* uio mapping all queue to one msix_vect */
3207                         __vsi_queues_bind_intr(vsi, msix_vect,
3208                                                vsi->base_queue + i,
3209                                                vsi->nb_used_qps - i);
3210
3211                         for (; !!record && i < vsi->nb_used_qps; i++)
3212                                 intr_handle->intr_vec[queue_idx + i] =
3213                                         msix_vect;
3214                         break;
3215                 }
3216
3217                 /* vfio 1:1 queue/msix_vect mapping */
3218                 __vsi_queues_bind_intr(vsi, msix_vect,
3219                                        vsi->base_queue + i, 1);
3220
3221                 if (!!record)
3222                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3223
3224                 msix_vect++;
3225                 nb_msix--;
3226         }
3227 }
3228
3229 void
3230 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3231 {
3232         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3233         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3234         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3235         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3236         uint16_t msix_intr, i;
3237
3238         if (rte_intr_allow_others(intr_handle))
3239                 for (i = 0; i < vsi->nb_used_qps; i++) {
3240                         msix_intr = vsi->msix_intr + i;
3241                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3242                                       GLINT_DYN_CTL_INTENA_M |
3243                                       GLINT_DYN_CTL_CLEARPBA_M |
3244                                       GLINT_DYN_CTL_ITR_INDX_M |
3245                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3246                 }
3247         else
3248                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3249                               GLINT_DYN_CTL_INTENA_M |
3250                               GLINT_DYN_CTL_CLEARPBA_M |
3251                               GLINT_DYN_CTL_ITR_INDX_M |
3252                               GLINT_DYN_CTL_WB_ON_ITR_M);
3253 }
3254
3255 static int
3256 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3257 {
3258         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3259         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3260         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3261         struct ice_vsi *vsi = pf->main_vsi;
3262         uint32_t intr_vector = 0;
3263
3264         rte_intr_disable(intr_handle);
3265
3266         /* check and configure queue intr-vector mapping */
3267         if ((rte_intr_cap_multiple(intr_handle) ||
3268              !RTE_ETH_DEV_SRIOV(dev).active) &&
3269             dev->data->dev_conf.intr_conf.rxq != 0) {
3270                 intr_vector = dev->data->nb_rx_queues;
3271                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3272                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3273                                     ICE_MAX_INTR_QUEUE_NUM);
3274                         return -ENOTSUP;
3275                 }
3276                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3277                         return -1;
3278         }
3279
3280         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3281                 intr_handle->intr_vec =
3282                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3283                             0);
3284                 if (!intr_handle->intr_vec) {
3285                         PMD_DRV_LOG(ERR,
3286                                     "Failed to allocate %d rx_queues intr_vec",
3287                                     dev->data->nb_rx_queues);
3288                         return -ENOMEM;
3289                 }
3290         }
3291
3292         /* Map queues with MSIX interrupt */
3293         vsi->nb_used_qps = dev->data->nb_rx_queues;
3294         ice_vsi_queues_bind_intr(vsi);
3295
3296         /* Enable interrupts for all the queues */
3297         ice_vsi_enable_queues_intr(vsi);
3298
3299         rte_intr_enable(intr_handle);
3300
3301         return 0;
3302 }
3303
3304 static void
3305 ice_get_init_link_status(struct rte_eth_dev *dev)
3306 {
3307         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3308         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3309         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3310         struct ice_link_status link_status;
3311         int ret;
3312
3313         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3314                                    &link_status, NULL);
3315         if (ret != ICE_SUCCESS) {
3316                 PMD_DRV_LOG(ERR, "Failed to get link info");
3317                 pf->init_link_up = false;
3318                 return;
3319         }
3320
3321         if (link_status.link_info & ICE_AQ_LINK_UP)
3322                 pf->init_link_up = true;
3323 }
3324
3325 static int
3326 ice_dev_start(struct rte_eth_dev *dev)
3327 {
3328         struct rte_eth_dev_data *data = dev->data;
3329         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3330         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3331         struct ice_vsi *vsi = pf->main_vsi;
3332         uint16_t nb_rxq = 0;
3333         uint16_t nb_txq, i;
3334         uint16_t max_frame_size;
3335         int mask, ret;
3336
3337         /* program Tx queues' context in hardware */
3338         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3339                 ret = ice_tx_queue_start(dev, nb_txq);
3340                 if (ret) {
3341                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3342                         goto tx_err;
3343                 }
3344         }
3345
3346         /* program Rx queues' context in hardware*/
3347         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3348                 ret = ice_rx_queue_start(dev, nb_rxq);
3349                 if (ret) {
3350                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3351                         goto rx_err;
3352                 }
3353         }
3354
3355         ice_set_rx_function(dev);
3356         ice_set_tx_function(dev);
3357
3358         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3359                         ETH_VLAN_EXTEND_MASK;
3360         ret = ice_vlan_offload_set(dev, mask);
3361         if (ret) {
3362                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3363                 goto rx_err;
3364         }
3365
3366         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3367         if (ice_rxq_intr_setup(dev))
3368                 return -EIO;
3369
3370         /* Enable receiving broadcast packets and transmitting packets */
3371         ret = ice_set_vsi_promisc(hw, vsi->idx,
3372                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3373                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3374                                   0);
3375         if (ret != ICE_SUCCESS)
3376                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3377
3378         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3379                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3380                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3381                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3382                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3383                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3384                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3385                                      NULL);
3386         if (ret != ICE_SUCCESS)
3387                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3388
3389         ice_get_init_link_status(dev);
3390
3391         ice_dev_set_link_up(dev);
3392
3393         /* Call get_link_info aq commond to enable/disable LSE */
3394         ice_link_update(dev, 0);
3395
3396         pf->adapter_stopped = false;
3397
3398         /* Set the max frame size to default value*/
3399         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3400                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3401                 ICE_FRAME_SIZE_MAX;
3402
3403         /* Set the max frame size to HW*/
3404         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3405
3406         return 0;
3407
3408         /* stop the started queues if failed to start all queues */
3409 rx_err:
3410         for (i = 0; i < nb_rxq; i++)
3411                 ice_rx_queue_stop(dev, i);
3412 tx_err:
3413         for (i = 0; i < nb_txq; i++)
3414                 ice_tx_queue_stop(dev, i);
3415
3416         return -EIO;
3417 }
3418
3419 static int
3420 ice_dev_reset(struct rte_eth_dev *dev)
3421 {
3422         int ret;
3423
3424         if (dev->data->sriov.active)
3425                 return -ENOTSUP;
3426
3427         ret = ice_dev_uninit(dev);
3428         if (ret) {
3429                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3430                 return -ENXIO;
3431         }
3432
3433         ret = ice_dev_init(dev);
3434         if (ret) {
3435                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3436                 return -ENXIO;
3437         }
3438
3439         return 0;
3440 }
3441
3442 static int
3443 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3444 {
3445         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3446         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3447         struct ice_vsi *vsi = pf->main_vsi;
3448         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3449         bool is_safe_mode = pf->adapter->is_safe_mode;
3450         u64 phy_type_low;
3451         u64 phy_type_high;
3452
3453         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3454         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3455         dev_info->max_rx_queues = vsi->nb_qps;
3456         dev_info->max_tx_queues = vsi->nb_qps;
3457         dev_info->max_mac_addrs = vsi->max_macaddrs;
3458         dev_info->max_vfs = pci_dev->max_vfs;
3459         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3460         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3461
3462         dev_info->rx_offload_capa =
3463                 DEV_RX_OFFLOAD_VLAN_STRIP |
3464                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3465                 DEV_RX_OFFLOAD_KEEP_CRC |
3466                 DEV_RX_OFFLOAD_SCATTER |
3467                 DEV_RX_OFFLOAD_VLAN_FILTER;
3468         dev_info->tx_offload_capa =
3469                 DEV_TX_OFFLOAD_VLAN_INSERT |
3470                 DEV_TX_OFFLOAD_TCP_TSO |
3471                 DEV_TX_OFFLOAD_MULTI_SEGS |
3472                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3473         dev_info->flow_type_rss_offloads = 0;
3474
3475         if (!is_safe_mode) {
3476                 dev_info->rx_offload_capa |=
3477                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3478                         DEV_RX_OFFLOAD_UDP_CKSUM |
3479                         DEV_RX_OFFLOAD_TCP_CKSUM |
3480                         DEV_RX_OFFLOAD_QINQ_STRIP |
3481                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3482                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3483                         DEV_RX_OFFLOAD_RSS_HASH;
3484                 dev_info->tx_offload_capa |=
3485                         DEV_TX_OFFLOAD_QINQ_INSERT |
3486                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3487                         DEV_TX_OFFLOAD_UDP_CKSUM |
3488                         DEV_TX_OFFLOAD_TCP_CKSUM |
3489                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3490                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3491                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3492                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3493         }
3494
3495         dev_info->rx_queue_offload_capa = 0;
3496         dev_info->tx_queue_offload_capa = 0;
3497
3498         dev_info->reta_size = pf->hash_lut_size;
3499         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3500
3501         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3502                 .rx_thresh = {
3503                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3504                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3505                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3506                 },
3507                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3508                 .rx_drop_en = 0,
3509                 .offloads = 0,
3510         };
3511
3512         dev_info->default_txconf = (struct rte_eth_txconf) {
3513                 .tx_thresh = {
3514                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3515                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3516                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3517                 },
3518                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3519                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3520                 .offloads = 0,
3521         };
3522
3523         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3524                 .nb_max = ICE_MAX_RING_DESC,
3525                 .nb_min = ICE_MIN_RING_DESC,
3526                 .nb_align = ICE_ALIGN_RING_DESC,
3527         };
3528
3529         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3530                 .nb_max = ICE_MAX_RING_DESC,
3531                 .nb_min = ICE_MIN_RING_DESC,
3532                 .nb_align = ICE_ALIGN_RING_DESC,
3533         };
3534
3535         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3536                                ETH_LINK_SPEED_100M |
3537                                ETH_LINK_SPEED_1G |
3538                                ETH_LINK_SPEED_2_5G |
3539                                ETH_LINK_SPEED_5G |
3540                                ETH_LINK_SPEED_10G |
3541                                ETH_LINK_SPEED_20G |
3542                                ETH_LINK_SPEED_25G;
3543
3544         phy_type_low = hw->port_info->phy.phy_type_low;
3545         phy_type_high = hw->port_info->phy.phy_type_high;
3546
3547         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3548                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3549
3550         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3551                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3552                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3553
3554         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3555         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3556
3557         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3558         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3559         dev_info->default_rxportconf.nb_queues = 1;
3560         dev_info->default_txportconf.nb_queues = 1;
3561         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3562         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3563
3564         return 0;
3565 }
3566
3567 static inline int
3568 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3569                             struct rte_eth_link *link)
3570 {
3571         struct rte_eth_link *dst = link;
3572         struct rte_eth_link *src = &dev->data->dev_link;
3573
3574         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3575                                 *(uint64_t *)src) == 0)
3576                 return -1;
3577
3578         return 0;
3579 }
3580
3581 static inline int
3582 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3583                              struct rte_eth_link *link)
3584 {
3585         struct rte_eth_link *dst = &dev->data->dev_link;
3586         struct rte_eth_link *src = link;
3587
3588         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3589                                 *(uint64_t *)src) == 0)
3590                 return -1;
3591
3592         return 0;
3593 }
3594
3595 static int
3596 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3597 {
3598 #define CHECK_INTERVAL 100  /* 100ms */
3599 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3600         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601         struct ice_link_status link_status;
3602         struct rte_eth_link link, old;
3603         int status;
3604         unsigned int rep_cnt = MAX_REPEAT_TIME;
3605         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3606
3607         memset(&link, 0, sizeof(link));
3608         memset(&old, 0, sizeof(old));
3609         memset(&link_status, 0, sizeof(link_status));
3610         ice_atomic_read_link_status(dev, &old);
3611
3612         do {
3613                 /* Get link status information from hardware */
3614                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3615                                               &link_status, NULL);
3616                 if (status != ICE_SUCCESS) {
3617                         link.link_speed = ETH_SPEED_NUM_100M;
3618                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3619                         PMD_DRV_LOG(ERR, "Failed to get link info");
3620                         goto out;
3621                 }
3622
3623                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3624                 if (!wait_to_complete || link.link_status)
3625                         break;
3626
3627                 rte_delay_ms(CHECK_INTERVAL);
3628         } while (--rep_cnt);
3629
3630         if (!link.link_status)
3631                 goto out;
3632
3633         /* Full-duplex operation at all supported speeds */
3634         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3635
3636         /* Parse the link status */
3637         switch (link_status.link_speed) {
3638         case ICE_AQ_LINK_SPEED_10MB:
3639                 link.link_speed = ETH_SPEED_NUM_10M;
3640                 break;
3641         case ICE_AQ_LINK_SPEED_100MB:
3642                 link.link_speed = ETH_SPEED_NUM_100M;
3643                 break;
3644         case ICE_AQ_LINK_SPEED_1000MB:
3645                 link.link_speed = ETH_SPEED_NUM_1G;
3646                 break;
3647         case ICE_AQ_LINK_SPEED_2500MB:
3648                 link.link_speed = ETH_SPEED_NUM_2_5G;
3649                 break;
3650         case ICE_AQ_LINK_SPEED_5GB:
3651                 link.link_speed = ETH_SPEED_NUM_5G;
3652                 break;
3653         case ICE_AQ_LINK_SPEED_10GB:
3654                 link.link_speed = ETH_SPEED_NUM_10G;
3655                 break;
3656         case ICE_AQ_LINK_SPEED_20GB:
3657                 link.link_speed = ETH_SPEED_NUM_20G;
3658                 break;
3659         case ICE_AQ_LINK_SPEED_25GB:
3660                 link.link_speed = ETH_SPEED_NUM_25G;
3661                 break;
3662         case ICE_AQ_LINK_SPEED_40GB:
3663                 link.link_speed = ETH_SPEED_NUM_40G;
3664                 break;
3665         case ICE_AQ_LINK_SPEED_50GB:
3666                 link.link_speed = ETH_SPEED_NUM_50G;
3667                 break;
3668         case ICE_AQ_LINK_SPEED_100GB:
3669                 link.link_speed = ETH_SPEED_NUM_100G;
3670                 break;
3671         case ICE_AQ_LINK_SPEED_UNKNOWN:
3672         default:
3673                 PMD_DRV_LOG(ERR, "Unknown link speed");
3674                 link.link_speed = ETH_SPEED_NUM_NONE;
3675                 break;
3676         }
3677
3678         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3679                               ETH_LINK_SPEED_FIXED);
3680
3681 out:
3682         ice_atomic_write_link_status(dev, &link);
3683         if (link.link_status == old.link_status)
3684                 return -1;
3685
3686         return 0;
3687 }
3688
3689 /* Force the physical link state by getting the current PHY capabilities from
3690  * hardware and setting the PHY config based on the determined capabilities. If
3691  * link changes, link event will be triggered because both the Enable Automatic
3692  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3693  */
3694 static enum ice_status
3695 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3696 {
3697         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3698         struct ice_aqc_get_phy_caps_data *pcaps;
3699         struct ice_port_info *pi;
3700         enum ice_status status;
3701
3702         if (!hw || !hw->port_info)
3703                 return ICE_ERR_PARAM;
3704
3705         pi = hw->port_info;
3706
3707         pcaps = (struct ice_aqc_get_phy_caps_data *)
3708                 ice_malloc(hw, sizeof(*pcaps));
3709         if (!pcaps)
3710                 return ICE_ERR_NO_MEMORY;
3711
3712         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3713                                      NULL);
3714         if (status)
3715                 goto out;
3716
3717         /* No change in link */
3718         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3719             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3720                 goto out;
3721
3722         cfg.phy_type_low = pcaps->phy_type_low;
3723         cfg.phy_type_high = pcaps->phy_type_high;
3724         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3725         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3726         cfg.eee_cap = pcaps->eee_cap;
3727         cfg.eeer_value = pcaps->eeer_value;
3728         cfg.link_fec_opt = pcaps->link_fec_options;
3729         if (link_up)
3730                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3731         else
3732                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3733
3734         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3735
3736 out:
3737         ice_free(hw, pcaps);
3738         return status;
3739 }
3740
3741 static int
3742 ice_dev_set_link_up(struct rte_eth_dev *dev)
3743 {
3744         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3745
3746         return ice_force_phys_link_state(hw, true);
3747 }
3748
3749 static int
3750 ice_dev_set_link_down(struct rte_eth_dev *dev)
3751 {
3752         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3753
3754         return ice_force_phys_link_state(hw, false);
3755 }
3756
3757 static int
3758 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3759 {
3760         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3761         struct rte_eth_dev_data *dev_data = pf->dev_data;
3762         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3763
3764         /* check if mtu is within the allowed range */
3765         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3766                 return -EINVAL;
3767
3768         /* mtu setting is forbidden if port is start */
3769         if (dev_data->dev_started) {
3770                 PMD_DRV_LOG(ERR,
3771                             "port %d must be stopped before configuration",
3772                             dev_data->port_id);
3773                 return -EBUSY;
3774         }
3775
3776         if (frame_size > RTE_ETHER_MAX_LEN)
3777                 dev_data->dev_conf.rxmode.offloads |=
3778                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3779         else
3780                 dev_data->dev_conf.rxmode.offloads &=
3781                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3782
3783         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3784
3785         return 0;
3786 }
3787
3788 static int ice_macaddr_set(struct rte_eth_dev *dev,
3789                            struct rte_ether_addr *mac_addr)
3790 {
3791         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3792         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3793         struct ice_vsi *vsi = pf->main_vsi;
3794         struct ice_mac_filter *f;
3795         uint8_t flags = 0;
3796         int ret;
3797
3798         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3799                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3800                 return -EINVAL;
3801         }
3802
3803         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3804                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3805                         break;
3806         }
3807
3808         if (!f) {
3809                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3810                 return -EIO;
3811         }
3812
3813         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3814         if (ret != ICE_SUCCESS) {
3815                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3816                 return -EIO;
3817         }
3818         ret = ice_add_mac_filter(vsi, mac_addr);
3819         if (ret != ICE_SUCCESS) {
3820                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3821                 return -EIO;
3822         }
3823         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3824
3825         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3826         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3827         if (ret != ICE_SUCCESS)
3828                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3829
3830         return 0;
3831 }
3832
3833 /* Add a MAC address, and update filters */
3834 static int
3835 ice_macaddr_add(struct rte_eth_dev *dev,
3836                 struct rte_ether_addr *mac_addr,
3837                 __rte_unused uint32_t index,
3838                 __rte_unused uint32_t pool)
3839 {
3840         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3841         struct ice_vsi *vsi = pf->main_vsi;
3842         int ret;
3843
3844         ret = ice_add_mac_filter(vsi, mac_addr);
3845         if (ret != ICE_SUCCESS) {
3846                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3847                 return -EINVAL;
3848         }
3849
3850         return ICE_SUCCESS;
3851 }
3852
3853 /* Remove a MAC address, and update filters */
3854 static void
3855 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3856 {
3857         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3858         struct ice_vsi *vsi = pf->main_vsi;
3859         struct rte_eth_dev_data *data = dev->data;
3860         struct rte_ether_addr *macaddr;
3861         int ret;
3862
3863         macaddr = &data->mac_addrs[index];
3864         ret = ice_remove_mac_filter(vsi, macaddr);
3865         if (ret) {
3866                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3867                 return;
3868         }
3869 }
3870
3871 static int
3872 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3873 {
3874         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3875         struct ice_vsi *vsi = pf->main_vsi;
3876         int ret;
3877
3878         PMD_INIT_FUNC_TRACE();
3879
3880         if (on) {
3881                 ret = ice_add_vlan_filter(vsi, vlan_id);
3882                 if (ret < 0) {
3883                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3884                         return -EINVAL;
3885                 }
3886         } else {
3887                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3888                 if (ret < 0) {
3889                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3890                         return -EINVAL;
3891                 }
3892         }
3893
3894         return 0;
3895 }
3896
3897 /* Configure vlan filter on or off */
3898 static int
3899 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3900 {
3901         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3902         struct ice_vsi_ctx ctxt;
3903         uint8_t sec_flags, sw_flags2;
3904         int ret = 0;
3905
3906         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3907                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3908         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3909
3910         if (on) {
3911                 vsi->info.sec_flags |= sec_flags;
3912                 vsi->info.sw_flags2 |= sw_flags2;
3913         } else {
3914                 vsi->info.sec_flags &= ~sec_flags;
3915                 vsi->info.sw_flags2 &= ~sw_flags2;
3916         }
3917         vsi->info.sw_id = hw->port_info->sw_id;
3918         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3919         ctxt.info.valid_sections =
3920                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3921                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3922         ctxt.vsi_num = vsi->vsi_id;
3923
3924         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3925         if (ret) {
3926                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3927                             on ? "enable" : "disable");
3928                 return -EINVAL;
3929         } else {
3930                 vsi->info.valid_sections |=
3931                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3932                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3933         }
3934
3935         /* consist with other drivers, allow untagged packet when vlan filter on */
3936         if (on)
3937                 ret = ice_add_vlan_filter(vsi, 0);
3938         else
3939                 ret = ice_remove_vlan_filter(vsi, 0);
3940
3941         return 0;
3942 }
3943
3944 static int
3945 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3946 {
3947         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3948         struct ice_vsi_ctx ctxt;
3949         uint8_t vlan_flags;
3950         int ret = 0;
3951
3952         /* Check if it has been already on or off */
3953         if (vsi->info.valid_sections &
3954                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3955                 if (on) {
3956                         if ((vsi->info.vlan_flags &
3957                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3958                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3959                                 return 0; /* already on */
3960                 } else {
3961                         if ((vsi->info.vlan_flags &
3962                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3963                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3964                                 return 0; /* already off */
3965                 }
3966         }
3967
3968         if (on)
3969                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3970         else
3971                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3972         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3973         vsi->info.vlan_flags |= vlan_flags;
3974         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3975         ctxt.info.valid_sections =
3976                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3977         ctxt.vsi_num = vsi->vsi_id;
3978         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3979         if (ret) {
3980                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3981                             on ? "enable" : "disable");
3982                 return -EINVAL;
3983         }
3984
3985         vsi->info.valid_sections |=
3986                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3987
3988         return ret;
3989 }
3990
3991 static int
3992 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3993 {
3994         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3995         struct ice_vsi *vsi = pf->main_vsi;
3996         struct rte_eth_rxmode *rxmode;
3997
3998         rxmode = &dev->data->dev_conf.rxmode;
3999         if (mask & ETH_VLAN_FILTER_MASK) {
4000                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4001                         ice_vsi_config_vlan_filter(vsi, true);
4002                 else
4003                         ice_vsi_config_vlan_filter(vsi, false);
4004         }
4005
4006         if (mask & ETH_VLAN_STRIP_MASK) {
4007                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4008                         ice_vsi_config_vlan_stripping(vsi, true);
4009                 else
4010                         ice_vsi_config_vlan_stripping(vsi, false);
4011         }
4012
4013         if (mask & ETH_VLAN_EXTEND_MASK) {
4014                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
4015                         ice_vsi_config_double_vlan(vsi, true);
4016                 else
4017                         ice_vsi_config_double_vlan(vsi, false);
4018         }
4019
4020         return 0;
4021 }
4022
4023 static int
4024 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4025 {
4026         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4027         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4028         int ret;
4029
4030         if (!lut)
4031                 return -EINVAL;
4032
4033         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4034                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
4035                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
4036                 if (ret) {
4037                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4038                         return -EINVAL;
4039                 }
4040         } else {
4041                 uint64_t *lut_dw = (uint64_t *)lut;
4042                 uint16_t i, lut_size_dw = lut_size / 4;
4043
4044                 for (i = 0; i < lut_size_dw; i++)
4045                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4046         }
4047
4048         return 0;
4049 }
4050
4051 static int
4052 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4053 {
4054         struct ice_pf *pf;
4055         struct ice_hw *hw;
4056         int ret;
4057
4058         if (!vsi || !lut)
4059                 return -EINVAL;
4060
4061         pf = ICE_VSI_TO_PF(vsi);
4062         hw = ICE_VSI_TO_HW(vsi);
4063
4064         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4065                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
4066                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
4067                 if (ret) {
4068                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4069                         return -EINVAL;
4070                 }
4071         } else {
4072                 uint64_t *lut_dw = (uint64_t *)lut;
4073                 uint16_t i, lut_size_dw = lut_size / 4;
4074
4075                 for (i = 0; i < lut_size_dw; i++)
4076                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4077
4078                 ice_flush(hw);
4079         }
4080
4081         return 0;
4082 }
4083
4084 static int
4085 ice_rss_reta_update(struct rte_eth_dev *dev,
4086                     struct rte_eth_rss_reta_entry64 *reta_conf,
4087                     uint16_t reta_size)
4088 {
4089         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4090         uint16_t i, lut_size = pf->hash_lut_size;
4091         uint16_t idx, shift;
4092         uint8_t *lut;
4093         int ret;
4094
4095         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4096             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4097             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4098                 PMD_DRV_LOG(ERR,
4099                             "The size of hash lookup table configured (%d)"
4100                             "doesn't match the number hardware can "
4101                             "supported (128, 512, 2048)",
4102                             reta_size);
4103                 return -EINVAL;
4104         }
4105
4106         /* It MUST use the current LUT size to get the RSS lookup table,
4107          * otherwise if will fail with -100 error code.
4108          */
4109         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4110         if (!lut) {
4111                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4112                 return -ENOMEM;
4113         }
4114         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4115         if (ret)
4116                 goto out;
4117
4118         for (i = 0; i < reta_size; i++) {
4119                 idx = i / RTE_RETA_GROUP_SIZE;
4120                 shift = i % RTE_RETA_GROUP_SIZE;
4121                 if (reta_conf[idx].mask & (1ULL << shift))
4122                         lut[i] = reta_conf[idx].reta[shift];
4123         }
4124         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4125         if (ret == 0 && lut_size != reta_size) {
4126                 PMD_DRV_LOG(INFO,
4127                             "The size of hash lookup table is changed from (%d) to (%d)",
4128                             lut_size, reta_size);
4129                 pf->hash_lut_size = reta_size;
4130         }
4131
4132 out:
4133         rte_free(lut);
4134
4135         return ret;
4136 }
4137
4138 static int
4139 ice_rss_reta_query(struct rte_eth_dev *dev,
4140                    struct rte_eth_rss_reta_entry64 *reta_conf,
4141                    uint16_t reta_size)
4142 {
4143         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4144         uint16_t i, lut_size = pf->hash_lut_size;
4145         uint16_t idx, shift;
4146         uint8_t *lut;
4147         int ret;
4148
4149         if (reta_size != lut_size) {
4150                 PMD_DRV_LOG(ERR,
4151                             "The size of hash lookup table configured (%d)"
4152                             "doesn't match the number hardware can "
4153                             "supported (%d)",
4154                             reta_size, lut_size);
4155                 return -EINVAL;
4156         }
4157
4158         lut = rte_zmalloc(NULL, reta_size, 0);
4159         if (!lut) {
4160                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4161                 return -ENOMEM;
4162         }
4163
4164         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4165         if (ret)
4166                 goto out;
4167
4168         for (i = 0; i < reta_size; i++) {
4169                 idx = i / RTE_RETA_GROUP_SIZE;
4170                 shift = i % RTE_RETA_GROUP_SIZE;
4171                 if (reta_conf[idx].mask & (1ULL << shift))
4172                         reta_conf[idx].reta[shift] = lut[i];
4173         }
4174
4175 out:
4176         rte_free(lut);
4177
4178         return ret;
4179 }
4180
4181 static int
4182 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4183 {
4184         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4185         int ret = 0;
4186
4187         if (!key || key_len == 0) {
4188                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4189                 return 0;
4190         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4191                    sizeof(uint32_t)) {
4192                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4193                 return -EINVAL;
4194         }
4195
4196         struct ice_aqc_get_set_rss_keys *key_dw =
4197                 (struct ice_aqc_get_set_rss_keys *)key;
4198
4199         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4200         if (ret) {
4201                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4202                 ret = -EINVAL;
4203         }
4204
4205         return ret;
4206 }
4207
4208 static int
4209 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4210 {
4211         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4212         int ret;
4213
4214         if (!key || !key_len)
4215                 return -EINVAL;
4216
4217         ret = ice_aq_get_rss_key
4218                 (hw, vsi->idx,
4219                  (struct ice_aqc_get_set_rss_keys *)key);
4220         if (ret) {
4221                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4222                 return -EINVAL;
4223         }
4224         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4225
4226         return 0;
4227 }
4228
4229 static int
4230 ice_rss_hash_update(struct rte_eth_dev *dev,
4231                     struct rte_eth_rss_conf *rss_conf)
4232 {
4233         enum ice_status status = ICE_SUCCESS;
4234         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4235         struct ice_vsi *vsi = pf->main_vsi;
4236
4237         /* set hash key */
4238         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4239         if (status)
4240                 return status;
4241
4242         if (rss_conf->rss_hf == 0)
4243                 return 0;
4244
4245         /* RSS hash configuration */
4246         ice_rss_hash_set(pf, rss_conf->rss_hf);
4247
4248         return 0;
4249 }
4250
4251 static int
4252 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4253                       struct rte_eth_rss_conf *rss_conf)
4254 {
4255         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4256         struct ice_vsi *vsi = pf->main_vsi;
4257
4258         ice_get_rss_key(vsi, rss_conf->rss_key,
4259                         &rss_conf->rss_key_len);
4260
4261         /* TODO: default set to 0 as hf config is not supported now */
4262         rss_conf->rss_hf = 0;
4263         return 0;
4264 }
4265
4266 static int
4267 ice_promisc_enable(struct rte_eth_dev *dev)
4268 {
4269         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4270         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271         struct ice_vsi *vsi = pf->main_vsi;
4272         enum ice_status status;
4273         uint8_t pmask;
4274         int ret = 0;
4275
4276         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4277                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4278
4279         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4280         switch (status) {
4281         case ICE_ERR_ALREADY_EXISTS:
4282                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4283         case ICE_SUCCESS:
4284                 break;
4285         default:
4286                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4287                 ret = -EAGAIN;
4288         }
4289
4290         return ret;
4291 }
4292
4293 static int
4294 ice_promisc_disable(struct rte_eth_dev *dev)
4295 {
4296         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4297         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4298         struct ice_vsi *vsi = pf->main_vsi;
4299         enum ice_status status;
4300         uint8_t pmask;
4301         int ret = 0;
4302
4303         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4304                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4305
4306         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4307         if (status != ICE_SUCCESS) {
4308                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4309                 ret = -EAGAIN;
4310         }
4311
4312         return ret;
4313 }
4314
4315 static int
4316 ice_allmulti_enable(struct rte_eth_dev *dev)
4317 {
4318         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4319         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4320         struct ice_vsi *vsi = pf->main_vsi;
4321         enum ice_status status;
4322         uint8_t pmask;
4323         int ret = 0;
4324
4325         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4326
4327         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4328
4329         switch (status) {
4330         case ICE_ERR_ALREADY_EXISTS:
4331                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4332         case ICE_SUCCESS:
4333                 break;
4334         default:
4335                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4336                 ret = -EAGAIN;
4337         }
4338
4339         return ret;
4340 }
4341
4342 static int
4343 ice_allmulti_disable(struct rte_eth_dev *dev)
4344 {
4345         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4346         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4347         struct ice_vsi *vsi = pf->main_vsi;
4348         enum ice_status status;
4349         uint8_t pmask;
4350         int ret = 0;
4351
4352         if (dev->data->promiscuous == 1)
4353                 return 0; /* must remain in all_multicast mode */
4354
4355         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4356
4357         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4358         if (status != ICE_SUCCESS) {
4359                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4360                 ret = -EAGAIN;
4361         }
4362
4363         return ret;
4364 }
4365
4366 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4367                                     uint16_t queue_id)
4368 {
4369         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4370         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4371         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4372         uint32_t val;
4373         uint16_t msix_intr;
4374
4375         msix_intr = intr_handle->intr_vec[queue_id];
4376
4377         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4378               GLINT_DYN_CTL_ITR_INDX_M;
4379         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4380
4381         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4382         rte_intr_ack(&pci_dev->intr_handle);
4383
4384         return 0;
4385 }
4386
4387 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4388                                      uint16_t queue_id)
4389 {
4390         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4391         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4392         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4393         uint16_t msix_intr;
4394
4395         msix_intr = intr_handle->intr_vec[queue_id];
4396
4397         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4398
4399         return 0;
4400 }
4401
4402 static int
4403 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4404 {
4405         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4406         u8 ver, patch;
4407         u16 build;
4408         int ret;
4409
4410         ver = hw->nvm.orom.major;
4411         patch = hw->nvm.orom.patch;
4412         build = hw->nvm.orom.build;
4413
4414         ret = snprintf(fw_version, fw_size,
4415                         "%d.%d 0x%08x %d.%d.%d",
4416                         hw->nvm.major_ver,
4417                         hw->nvm.minor_ver,
4418                         hw->nvm.eetrack,
4419                         ver, build, patch);
4420
4421         /* add the size of '\0' */
4422         ret += 1;
4423         if (fw_size < (u32)ret)
4424                 return ret;
4425         else
4426                 return 0;
4427 }
4428
4429 static int
4430 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4431 {
4432         struct ice_hw *hw;
4433         struct ice_vsi_ctx ctxt;
4434         uint8_t vlan_flags = 0;
4435         int ret;
4436
4437         if (!vsi || !info) {
4438                 PMD_DRV_LOG(ERR, "invalid parameters");
4439                 return -EINVAL;
4440         }
4441
4442         if (info->on) {
4443                 vsi->info.pvid = info->config.pvid;
4444                 /**
4445                  * If insert pvid is enabled, only tagged pkts are
4446                  * allowed to be sent out.
4447                  */
4448                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
4449                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
4450         } else {
4451                 vsi->info.pvid = 0;
4452                 if (info->config.reject.tagged == 0)
4453                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
4454
4455                 if (info->config.reject.untagged == 0)
4456                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
4457         }
4458         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
4459                                   ICE_AQ_VSI_VLAN_MODE_M);
4460         vsi->info.vlan_flags |= vlan_flags;
4461         memset(&ctxt, 0, sizeof(ctxt));
4462         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4463         ctxt.info.valid_sections =
4464                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4465         ctxt.vsi_num = vsi->vsi_id;
4466
4467         hw = ICE_VSI_TO_HW(vsi);
4468         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4469         if (ret != ICE_SUCCESS) {
4470                 PMD_DRV_LOG(ERR,
4471                             "update VSI for VLAN insert failed, err %d",
4472                             ret);
4473                 return -EINVAL;
4474         }
4475
4476         vsi->info.valid_sections |=
4477                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4478
4479         return ret;
4480 }
4481
4482 static int
4483 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4484 {
4485         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4486         struct ice_vsi *vsi = pf->main_vsi;
4487         struct rte_eth_dev_data *data = pf->dev_data;
4488         struct ice_vsi_vlan_pvid_info info;
4489         int ret;
4490
4491         memset(&info, 0, sizeof(info));
4492         info.on = on;
4493         if (info.on) {
4494                 info.config.pvid = pvid;
4495         } else {
4496                 info.config.reject.tagged =
4497                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4498                 info.config.reject.untagged =
4499                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4500         }
4501
4502         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4503         if (ret < 0) {
4504                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4505                 return -EINVAL;
4506         }
4507
4508         return 0;
4509 }
4510
4511 static int
4512 ice_get_eeprom_length(struct rte_eth_dev *dev)
4513 {
4514         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4515
4516         return hw->nvm.flash_size;
4517 }
4518
4519 static int
4520 ice_get_eeprom(struct rte_eth_dev *dev,
4521                struct rte_dev_eeprom_info *eeprom)
4522 {
4523         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524         enum ice_status status = ICE_SUCCESS;
4525         uint8_t *data = eeprom->data;
4526
4527         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4528
4529         status = ice_acquire_nvm(hw, ICE_RES_READ);
4530         if (status) {
4531                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4532                 return -EIO;
4533         }
4534
4535         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4536                                    data, false);
4537
4538         ice_release_nvm(hw);
4539
4540         if (status) {
4541                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4542                 return -EIO;
4543         }
4544
4545         return 0;
4546 }
4547
4548 static void
4549 ice_stat_update_32(struct ice_hw *hw,
4550                    uint32_t reg,
4551                    bool offset_loaded,
4552                    uint64_t *offset,
4553                    uint64_t *stat)
4554 {
4555         uint64_t new_data;
4556
4557         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4558         if (!offset_loaded)
4559                 *offset = new_data;
4560
4561         if (new_data >= *offset)
4562                 *stat = (uint64_t)(new_data - *offset);
4563         else
4564                 *stat = (uint64_t)((new_data +
4565                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4566                                    - *offset);
4567 }
4568
4569 static void
4570 ice_stat_update_40(struct ice_hw *hw,
4571                    uint32_t hireg,
4572                    uint32_t loreg,
4573                    bool offset_loaded,
4574                    uint64_t *offset,
4575                    uint64_t *stat)
4576 {
4577         uint64_t new_data;
4578
4579         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4580         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4581                     ICE_32_BIT_WIDTH;
4582
4583         if (!offset_loaded)
4584                 *offset = new_data;
4585
4586         if (new_data >= *offset)
4587                 *stat = new_data - *offset;
4588         else
4589                 *stat = (uint64_t)((new_data +
4590                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4591                                    *offset);
4592
4593         *stat &= ICE_40_BIT_MASK;
4594 }
4595
4596 /* Get all the statistics of a VSI */
4597 static void
4598 ice_update_vsi_stats(struct ice_vsi *vsi)
4599 {
4600         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4601         struct ice_eth_stats *nes = &vsi->eth_stats;
4602         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4603         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4604
4605         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4606                            vsi->offset_loaded, &oes->rx_bytes,
4607                            &nes->rx_bytes);
4608         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4609                            vsi->offset_loaded, &oes->rx_unicast,
4610                            &nes->rx_unicast);
4611         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4612                            vsi->offset_loaded, &oes->rx_multicast,
4613                            &nes->rx_multicast);
4614         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4615                            vsi->offset_loaded, &oes->rx_broadcast,
4616                            &nes->rx_broadcast);
4617         /* enlarge the limitation when rx_bytes overflowed */
4618         if (vsi->offset_loaded) {
4619                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4620                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4621                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4622         }
4623         vsi->old_rx_bytes = nes->rx_bytes;
4624         /* exclude CRC bytes */
4625         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4626                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4627
4628         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4629                            &oes->rx_discards, &nes->rx_discards);
4630         /* GLV_REPC not supported */
4631         /* GLV_RMPC not supported */
4632         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4633                            &oes->rx_unknown_protocol,
4634                            &nes->rx_unknown_protocol);
4635         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4636                            vsi->offset_loaded, &oes->tx_bytes,
4637                            &nes->tx_bytes);
4638         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4639                            vsi->offset_loaded, &oes->tx_unicast,
4640                            &nes->tx_unicast);
4641         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4642                            vsi->offset_loaded, &oes->tx_multicast,
4643                            &nes->tx_multicast);
4644         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4645                            vsi->offset_loaded,  &oes->tx_broadcast,
4646                            &nes->tx_broadcast);
4647         /* GLV_TDPC not supported */
4648         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4649                            &oes->tx_errors, &nes->tx_errors);
4650         /* enlarge the limitation when tx_bytes overflowed */
4651         if (vsi->offset_loaded) {
4652                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4653                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4654                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4655         }
4656         vsi->old_tx_bytes = nes->tx_bytes;
4657         vsi->offset_loaded = true;
4658
4659         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4660                     vsi->vsi_id);
4661         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4662         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4663         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4664         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4665         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4666         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4667                     nes->rx_unknown_protocol);
4668         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4669         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4670         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4671         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4672         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4673         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4674         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4675                     vsi->vsi_id);
4676 }
4677
4678 static void
4679 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4680 {
4681         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4682         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4683
4684         /* Get statistics of struct ice_eth_stats */
4685         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4686                            GLPRT_GORCL(hw->port_info->lport),
4687                            pf->offset_loaded, &os->eth.rx_bytes,
4688                            &ns->eth.rx_bytes);
4689         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4690                            GLPRT_UPRCL(hw->port_info->lport),
4691                            pf->offset_loaded, &os->eth.rx_unicast,
4692                            &ns->eth.rx_unicast);
4693         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4694                            GLPRT_MPRCL(hw->port_info->lport),
4695                            pf->offset_loaded, &os->eth.rx_multicast,
4696                            &ns->eth.rx_multicast);
4697         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4698                            GLPRT_BPRCL(hw->port_info->lport),
4699                            pf->offset_loaded, &os->eth.rx_broadcast,
4700                            &ns->eth.rx_broadcast);
4701         ice_stat_update_32(hw, PRTRPB_RDPC,
4702                            pf->offset_loaded, &os->eth.rx_discards,
4703                            &ns->eth.rx_discards);
4704         /* enlarge the limitation when rx_bytes overflowed */
4705         if (pf->offset_loaded) {
4706                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4707                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4708                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4709         }
4710         pf->old_rx_bytes = ns->eth.rx_bytes;
4711
4712         /* Workaround: CRC size should not be included in byte statistics,
4713          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4714          * packet.
4715          */
4716         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4717                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4718
4719         /* GLPRT_REPC not supported */
4720         /* GLPRT_RMPC not supported */
4721         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4722                            pf->offset_loaded,
4723                            &os->eth.rx_unknown_protocol,
4724                            &ns->eth.rx_unknown_protocol);
4725         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4726                            GLPRT_GOTCL(hw->port_info->lport),
4727                            pf->offset_loaded, &os->eth.tx_bytes,
4728                            &ns->eth.tx_bytes);
4729         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4730                            GLPRT_UPTCL(hw->port_info->lport),
4731                            pf->offset_loaded, &os->eth.tx_unicast,
4732                            &ns->eth.tx_unicast);
4733         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4734                            GLPRT_MPTCL(hw->port_info->lport),
4735                            pf->offset_loaded, &os->eth.tx_multicast,
4736                            &ns->eth.tx_multicast);
4737         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4738                            GLPRT_BPTCL(hw->port_info->lport),
4739                            pf->offset_loaded, &os->eth.tx_broadcast,
4740                            &ns->eth.tx_broadcast);
4741         /* enlarge the limitation when tx_bytes overflowed */
4742         if (pf->offset_loaded) {
4743                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4744                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4745                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4746         }
4747         pf->old_tx_bytes = ns->eth.tx_bytes;
4748         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4749                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4750
4751         /* GLPRT_TEPC not supported */
4752
4753         /* additional port specific stats */
4754         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4755                            pf->offset_loaded, &os->tx_dropped_link_down,
4756                            &ns->tx_dropped_link_down);
4757         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4758                            pf->offset_loaded, &os->crc_errors,
4759                            &ns->crc_errors);
4760         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4761                            pf->offset_loaded, &os->illegal_bytes,
4762                            &ns->illegal_bytes);
4763         /* GLPRT_ERRBC not supported */
4764         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4765                            pf->offset_loaded, &os->mac_local_faults,
4766                            &ns->mac_local_faults);
4767         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4768                            pf->offset_loaded, &os->mac_remote_faults,
4769                            &ns->mac_remote_faults);
4770
4771         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4772                            pf->offset_loaded, &os->rx_len_errors,
4773                            &ns->rx_len_errors);
4774
4775         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4776                            pf->offset_loaded, &os->link_xon_rx,
4777                            &ns->link_xon_rx);
4778         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4779                            pf->offset_loaded, &os->link_xoff_rx,
4780                            &ns->link_xoff_rx);
4781         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4782                            pf->offset_loaded, &os->link_xon_tx,
4783                            &ns->link_xon_tx);
4784         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4785                            pf->offset_loaded, &os->link_xoff_tx,
4786                            &ns->link_xoff_tx);
4787         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4788                            GLPRT_PRC64L(hw->port_info->lport),
4789                            pf->offset_loaded, &os->rx_size_64,
4790                            &ns->rx_size_64);
4791         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4792                            GLPRT_PRC127L(hw->port_info->lport),
4793                            pf->offset_loaded, &os->rx_size_127,
4794                            &ns->rx_size_127);
4795         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4796                            GLPRT_PRC255L(hw->port_info->lport),
4797                            pf->offset_loaded, &os->rx_size_255,
4798                            &ns->rx_size_255);
4799         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4800                            GLPRT_PRC511L(hw->port_info->lport),
4801                            pf->offset_loaded, &os->rx_size_511,
4802                            &ns->rx_size_511);
4803         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4804                            GLPRT_PRC1023L(hw->port_info->lport),
4805                            pf->offset_loaded, &os->rx_size_1023,
4806                            &ns->rx_size_1023);
4807         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4808                            GLPRT_PRC1522L(hw->port_info->lport),
4809                            pf->offset_loaded, &os->rx_size_1522,
4810                            &ns->rx_size_1522);
4811         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4812                            GLPRT_PRC9522L(hw->port_info->lport),
4813                            pf->offset_loaded, &os->rx_size_big,
4814                            &ns->rx_size_big);
4815         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4816                            pf->offset_loaded, &os->rx_undersize,
4817                            &ns->rx_undersize);
4818         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4819                            pf->offset_loaded, &os->rx_fragments,
4820                            &ns->rx_fragments);
4821         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4822                            pf->offset_loaded, &os->rx_oversize,
4823                            &ns->rx_oversize);
4824         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4825                            pf->offset_loaded, &os->rx_jabber,
4826                            &ns->rx_jabber);
4827         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4828                            GLPRT_PTC64L(hw->port_info->lport),
4829                            pf->offset_loaded, &os->tx_size_64,
4830                            &ns->tx_size_64);
4831         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4832                            GLPRT_PTC127L(hw->port_info->lport),
4833                            pf->offset_loaded, &os->tx_size_127,
4834                            &ns->tx_size_127);
4835         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4836                            GLPRT_PTC255L(hw->port_info->lport),
4837                            pf->offset_loaded, &os->tx_size_255,
4838                            &ns->tx_size_255);
4839         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4840                            GLPRT_PTC511L(hw->port_info->lport),
4841                            pf->offset_loaded, &os->tx_size_511,
4842                            &ns->tx_size_511);
4843         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4844                            GLPRT_PTC1023L(hw->port_info->lport),
4845                            pf->offset_loaded, &os->tx_size_1023,
4846                            &ns->tx_size_1023);
4847         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4848                            GLPRT_PTC1522L(hw->port_info->lport),
4849                            pf->offset_loaded, &os->tx_size_1522,
4850                            &ns->tx_size_1522);
4851         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4852                            GLPRT_PTC9522L(hw->port_info->lport),
4853                            pf->offset_loaded, &os->tx_size_big,
4854                            &ns->tx_size_big);
4855
4856         /* GLPRT_MSPDC not supported */
4857         /* GLPRT_XEC not supported */
4858
4859         pf->offset_loaded = true;
4860
4861         if (pf->main_vsi)
4862                 ice_update_vsi_stats(pf->main_vsi);
4863 }
4864
4865 /* Get all statistics of a port */
4866 static int
4867 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4868 {
4869         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4870         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4871         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4872
4873         /* call read registers - updates values, now write them to struct */
4874         ice_read_stats_registers(pf, hw);
4875
4876         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4877                           pf->main_vsi->eth_stats.rx_multicast +
4878                           pf->main_vsi->eth_stats.rx_broadcast -
4879                           pf->main_vsi->eth_stats.rx_discards;
4880         stats->opackets = ns->eth.tx_unicast +
4881                           ns->eth.tx_multicast +
4882                           ns->eth.tx_broadcast;
4883         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4884         stats->obytes   = ns->eth.tx_bytes;
4885         stats->oerrors  = ns->eth.tx_errors +
4886                           pf->main_vsi->eth_stats.tx_errors;
4887
4888         /* Rx Errors */
4889         stats->imissed  = ns->eth.rx_discards +
4890                           pf->main_vsi->eth_stats.rx_discards;
4891         stats->ierrors  = ns->crc_errors +
4892                           ns->rx_undersize +
4893                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4894
4895         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4896         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4897         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4898         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4899         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4900         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4901         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4902                     pf->main_vsi->eth_stats.rx_discards);
4903         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4904                     ns->eth.rx_unknown_protocol);
4905         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4906         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4907         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4908         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4909         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4910         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4911                     pf->main_vsi->eth_stats.tx_discards);
4912         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4913
4914         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4915                     ns->tx_dropped_link_down);
4916         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4917         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4918                     ns->illegal_bytes);
4919         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4920         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4921                     ns->mac_local_faults);
4922         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4923                     ns->mac_remote_faults);
4924         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4925         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4926         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4927         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4928         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4929         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4930         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4931         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4932         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4933         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4934         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4935         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4936         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4937         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4938         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4939         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4940         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4941         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4942         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4943         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4944         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4945         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4946         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4947         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4948         return 0;
4949 }
4950
4951 /* Reset the statistics */
4952 static int
4953 ice_stats_reset(struct rte_eth_dev *dev)
4954 {
4955         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4956         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4957
4958         /* Mark PF and VSI stats to update the offset, aka "reset" */
4959         pf->offset_loaded = false;
4960         if (pf->main_vsi)
4961                 pf->main_vsi->offset_loaded = false;
4962
4963         /* read the stats, reading current register values into offset */
4964         ice_read_stats_registers(pf, hw);
4965
4966         return 0;
4967 }
4968
4969 static uint32_t
4970 ice_xstats_calc_num(void)
4971 {
4972         uint32_t num;
4973
4974         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4975
4976         return num;
4977 }
4978
4979 static int
4980 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4981                unsigned int n)
4982 {
4983         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4984         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4985         unsigned int i;
4986         unsigned int count;
4987         struct ice_hw_port_stats *hw_stats = &pf->stats;
4988
4989         count = ice_xstats_calc_num();
4990         if (n < count)
4991                 return count;
4992
4993         ice_read_stats_registers(pf, hw);
4994
4995         if (!xstats)
4996                 return 0;
4997
4998         count = 0;
4999
5000         /* Get stats from ice_eth_stats struct */
5001         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5002                 xstats[count].value =
5003                         *(uint64_t *)((char *)&hw_stats->eth +
5004                                       ice_stats_strings[i].offset);
5005                 xstats[count].id = count;
5006                 count++;
5007         }
5008
5009         /* Get individiual stats from ice_hw_port struct */
5010         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5011                 xstats[count].value =
5012                         *(uint64_t *)((char *)hw_stats +
5013                                       ice_hw_port_strings[i].offset);
5014                 xstats[count].id = count;
5015                 count++;
5016         }
5017
5018         return count;
5019 }
5020
5021 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5022                                 struct rte_eth_xstat_name *xstats_names,
5023                                 __rte_unused unsigned int limit)
5024 {
5025         unsigned int count = 0;
5026         unsigned int i;
5027
5028         if (!xstats_names)
5029                 return ice_xstats_calc_num();
5030
5031         /* Note: limit checked in rte_eth_xstats_names() */
5032
5033         /* Get stats from ice_eth_stats struct */
5034         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5035                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5036                         sizeof(xstats_names[count].name));
5037                 count++;
5038         }
5039
5040         /* Get individiual stats from ice_hw_port struct */
5041         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5042                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5043                         sizeof(xstats_names[count].name));
5044                 count++;
5045         }
5046
5047         return count;
5048 }
5049
5050 static int
5051 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
5052                      enum rte_filter_type filter_type,
5053                      enum rte_filter_op filter_op,
5054                      void *arg)
5055 {
5056         int ret = 0;
5057
5058         if (!dev)
5059                 return -EINVAL;
5060
5061         switch (filter_type) {
5062         case RTE_ETH_FILTER_GENERIC:
5063                 if (filter_op != RTE_ETH_FILTER_GET)
5064                         return -EINVAL;
5065                 *(const void **)arg = &ice_flow_ops;
5066                 break;
5067         default:
5068                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5069                                         filter_type);
5070                 ret = -EINVAL;
5071                 break;
5072         }
5073
5074         return ret;
5075 }
5076
5077 /* Add UDP tunneling port */
5078 static int
5079 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5080                              struct rte_eth_udp_tunnel *udp_tunnel)
5081 {
5082         int ret = 0;
5083         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084
5085         if (udp_tunnel == NULL)
5086                 return -EINVAL;
5087
5088         switch (udp_tunnel->prot_type) {
5089         case RTE_TUNNEL_TYPE_VXLAN:
5090                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5091                 break;
5092         default:
5093                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5094                 ret = -EINVAL;
5095                 break;
5096         }
5097
5098         return ret;
5099 }
5100
5101 /* Delete UDP tunneling port */
5102 static int
5103 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5104                              struct rte_eth_udp_tunnel *udp_tunnel)
5105 {
5106         int ret = 0;
5107         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5108
5109         if (udp_tunnel == NULL)
5110                 return -EINVAL;
5111
5112         switch (udp_tunnel->prot_type) {
5113         case RTE_TUNNEL_TYPE_VXLAN:
5114                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5115                 break;
5116         default:
5117                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5118                 ret = -EINVAL;
5119                 break;
5120         }
5121
5122         return ret;
5123 }
5124
5125 static int
5126 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5127               struct rte_pci_device *pci_dev)
5128 {
5129         return rte_eth_dev_pci_generic_probe(pci_dev,
5130                                              sizeof(struct ice_adapter),
5131                                              ice_dev_init);
5132 }
5133
5134 static int
5135 ice_pci_remove(struct rte_pci_device *pci_dev)
5136 {
5137         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5138 }
5139
5140 static struct rte_pci_driver rte_ice_pmd = {
5141         .id_table = pci_id_ice_map,
5142         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5143         .probe = ice_pci_probe,
5144         .remove = ice_pci_remove,
5145 };
5146
5147 /**
5148  * Driver initialization routine.
5149  * Invoked once at EAL init time.
5150  * Register itself as the [Poll Mode] Driver of PCI devices.
5151  */
5152 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5153 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5154 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5155 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5156                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5157                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5158                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
5159                               ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
5160
5161 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5162 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5163 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5164 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5165 #endif
5166 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5167 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5168 #endif
5169 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5170 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);
5171 #endif