drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include <rte_tailq.h>
  14
  15 #include "base/ice_sched.h"
  16 #include "base/ice_flow.h"
  17 #include "base/ice_dcb.h"
  18 #include "base/ice_common.h"
  19
  20 #include "rte_pmd_ice.h"
  21 #include "ice_ethdev.h"
  22 #include "ice_rxtx.h"
  23 #include "ice_generic_flow.h"
  24
  25 /* devargs */
  26 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  27 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  28 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  29 #define ICE_HW_DEBUG_MASK_ARG     "hw_debug_mask"
  30
  31 static const char * const ice_valid_args[] = {
  32         ICE_SAFE_MODE_SUPPORT_ARG,
  33         ICE_PIPELINE_MODE_SUPPORT_ARG,
  34         ICE_PROTO_XTR_ARG,
  35         ICE_HW_DEBUG_MASK_ARG,
  36         NULL
  37 };
  38
  39 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  40         .name = "intel_pmd_dynfield_proto_xtr_metadata",
  41         .size = sizeof(uint32_t),
  42         .align = __alignof__(uint32_t),
  43         .flags = 0,
  44 };
  45
  46 struct proto_xtr_ol_flag {
  47         const struct rte_mbuf_dynflag param;
  48         uint64_t *ol_flag;
  49         bool required;
  50 };
  51
  52 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  53
  54 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  55         [PROTO_XTR_VLAN] = {
  56                 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
  57                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  58         [PROTO_XTR_IPV4] = {
  59                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
  60                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  61         [PROTO_XTR_IPV6] = {
  62                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
  63                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  64         [PROTO_XTR_IPV6_FLOW] = {
  65                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
  66                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  67         [PROTO_XTR_TCP] = {
  68                 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
  69                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  70         [PROTO_XTR_IP_OFFSET] = {
  71                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
  72                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  73 };
  74
  75 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  76 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  77 #define ICE_MAX_RES_DESC_NUM        1024
  78
  79 static int ice_dev_configure(struct rte_eth_dev *dev);
  80 static int ice_dev_start(struct rte_eth_dev *dev);
  81 static int ice_dev_stop(struct rte_eth_dev *dev);
  82 static int ice_dev_close(struct rte_eth_dev *dev);
  83 static int ice_dev_reset(struct rte_eth_dev *dev);
  84 static int ice_dev_info_get(struct rte_eth_dev *dev,
  85                             struct rte_eth_dev_info *dev_info);
  86 static int ice_link_update(struct rte_eth_dev *dev,
  87                            int wait_to_complete);
  88 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  89 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  90
  91 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  92 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  93 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  94                                struct rte_eth_rss_reta_entry64 *reta_conf,
  95                                uint16_t reta_size);
  96 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  97                               struct rte_eth_rss_reta_entry64 *reta_conf,
  98                               uint16_t reta_size);
  99 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 100                                struct rte_eth_rss_conf *rss_conf);
 101 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 102                                  struct rte_eth_rss_conf *rss_conf);
 103 static int ice_promisc_enable(struct rte_eth_dev *dev);
 104 static int ice_promisc_disable(struct rte_eth_dev *dev);
 105 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 106 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 107 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 108                                uint16_t vlan_id,
 109                                int on);
 110 static int ice_macaddr_set(struct rte_eth_dev *dev,
 111                            struct rte_ether_addr *mac_addr);
 112 static int ice_macaddr_add(struct rte_eth_dev *dev,
 113                            struct rte_ether_addr *mac_addr,
 114                            __rte_unused uint32_t index,
 115                            uint32_t pool);
 116 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 117 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 118                                     uint16_t queue_id);
 119 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 120                                      uint16_t queue_id);
 121 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 122                               size_t fw_size);
 123 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 124                              uint16_t pvid, int on);
 125 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 126 static int ice_get_eeprom(struct rte_eth_dev *dev,
 127                           struct rte_dev_eeprom_info *eeprom);
 128 static int ice_stats_get(struct rte_eth_dev *dev,
 129                          struct rte_eth_stats *stats);
 130 static int ice_stats_reset(struct rte_eth_dev *dev);
 131 static int ice_xstats_get(struct rte_eth_dev *dev,
 132                           struct rte_eth_xstat *xstats, unsigned int n);
 133 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 134                                 struct rte_eth_xstat_name *xstats_names,
 135                                 unsigned int limit);
 136 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev,
 137                                 const struct rte_flow_ops **ops);
 138 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 139                         struct rte_eth_udp_tunnel *udp_tunnel);
 140 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 141                         struct rte_eth_udp_tunnel *udp_tunnel);
 142
 143 static const struct rte_pci_id pci_id_ice_map[] = {
 144         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 145         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 146         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 147         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 148         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 149         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 150         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 151         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 152         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 165         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
 166         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
 167         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
 168         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
 169         { .vendor_id = 0, /* sentinel */ },
 170 };
 171
 172 static const struct eth_dev_ops ice_eth_dev_ops = {
 173         .dev_configure                = ice_dev_configure,
 174         .dev_start                    = ice_dev_start,
 175         .dev_stop                     = ice_dev_stop,
 176         .dev_close                    = ice_dev_close,
 177         .dev_reset                    = ice_dev_reset,
 178         .dev_set_link_up              = ice_dev_set_link_up,
 179         .dev_set_link_down            = ice_dev_set_link_down,
 180         .rx_queue_start               = ice_rx_queue_start,
 181         .rx_queue_stop                = ice_rx_queue_stop,
 182         .tx_queue_start               = ice_tx_queue_start,
 183         .tx_queue_stop                = ice_tx_queue_stop,
 184         .rx_queue_setup               = ice_rx_queue_setup,
 185         .rx_queue_release             = ice_rx_queue_release,
 186         .tx_queue_setup               = ice_tx_queue_setup,
 187         .tx_queue_release             = ice_tx_queue_release,
 188         .dev_infos_get                = ice_dev_info_get,
 189         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 190         .link_update                  = ice_link_update,
 191         .mtu_set                      = ice_mtu_set,
 192         .mac_addr_set                 = ice_macaddr_set,
 193         .mac_addr_add                 = ice_macaddr_add,
 194         .mac_addr_remove              = ice_macaddr_remove,
 195         .vlan_filter_set              = ice_vlan_filter_set,
 196         .vlan_offload_set             = ice_vlan_offload_set,
 197         .reta_update                  = ice_rss_reta_update,
 198         .reta_query                   = ice_rss_reta_query,
 199         .rss_hash_update              = ice_rss_hash_update,
 200         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 201         .promiscuous_enable           = ice_promisc_enable,
 202         .promiscuous_disable          = ice_promisc_disable,
 203         .allmulticast_enable          = ice_allmulti_enable,
 204         .allmulticast_disable         = ice_allmulti_disable,
 205         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 206         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 207         .fw_version_get               = ice_fw_version_get,
 208         .vlan_pvid_set                = ice_vlan_pvid_set,
 209         .rxq_info_get                 = ice_rxq_info_get,
 210         .txq_info_get                 = ice_txq_info_get,
 211         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 212         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 213         .get_eeprom_length            = ice_get_eeprom_length,
 214         .get_eeprom                   = ice_get_eeprom,
 215         .stats_get                    = ice_stats_get,
 216         .stats_reset                  = ice_stats_reset,
 217         .xstats_get                   = ice_xstats_get,
 218         .xstats_get_names             = ice_xstats_get_names,
 219         .xstats_reset                 = ice_stats_reset,
 220         .flow_ops_get                 = ice_dev_flow_ops_get,
 221         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 222         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 223         .tx_done_cleanup              = ice_tx_done_cleanup,
 224         .get_monitor_addr             = ice_get_monitor_addr,
 225 };
 226
 227 /* store statistics names and its offset in stats structure */
 228 struct ice_xstats_name_off {
 229         char name[RTE_ETH_XSTATS_NAME_SIZE];
 230         unsigned int offset;
 231 };
 232
 233 static const struct ice_xstats_name_off ice_stats_strings[] = {
 234         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 235         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 236         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 237         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 238         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 239                 rx_unknown_protocol)},
 240         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 241         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 242         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 243         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 244 };
 245
 246 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 247                 sizeof(ice_stats_strings[0]))
 248
 249 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 250         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 251                 tx_dropped_link_down)},
 252         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 253         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 254                 illegal_bytes)},
 255         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 256         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 257                 mac_local_faults)},
 258         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 259                 mac_remote_faults)},
 260         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 261                 rx_len_errors)},
 262         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 263         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 264         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 265         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 266         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 267         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 268                 rx_size_127)},
 269         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_255)},
 271         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_511)},
 273         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 274                 rx_size_1023)},
 275         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 276                 rx_size_1522)},
 277         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 278                 rx_size_big)},
 279         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 280                 rx_undersize)},
 281         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 282                 rx_oversize)},
 283         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 284                 mac_short_pkt_dropped)},
 285         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 286                 rx_fragments)},
 287         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 288         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 289         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 290                 tx_size_127)},
 291         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_255)},
 293         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_511)},
 295         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 296                 tx_size_1023)},
 297         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 298                 tx_size_1522)},
 299         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 300                 tx_size_big)},
 301 };
 302
 303 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 304                 sizeof(ice_hw_port_strings[0]))
 305
 306 static void
 307 ice_init_controlq_parameter(struct ice_hw *hw)
 308 {
 309         /* fields for adminq */
 310         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 311         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 312         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 313         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 314
 315         /* fields for mailboxq, DPDK used as PF host */
 316         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 317         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 318         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 319         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 320 }
 321
 322 static int
 323 lookup_proto_xtr_type(const char *xtr_name)
 324 {
 325         static struct {
 326                 const char *name;
 327                 enum proto_xtr_type type;
 328         } xtr_type_map[] = {
 329                 { "vlan",      PROTO_XTR_VLAN      },
 330                 { "ipv4",      PROTO_XTR_IPV4      },
 331                 { "ipv6",      PROTO_XTR_IPV6      },
 332                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 333                 { "tcp",       PROTO_XTR_TCP       },
 334                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 335         };
 336         uint32_t i;
 337
 338         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 339                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 340                         return xtr_type_map[i].type;
 341         }
 342
 343         return -1;
 344 }
 345
 346 /*
 347  * Parse elem, the elem could be single number/range or '(' ')' group
 348  * 1) A single number elem, it's just a simple digit. e.g. 9
 349  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 350  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 351  *    Within group elem, '-' used for a range separator;
 352  *                       ',' used for a single number.
 353  */
 354 static int
 355 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 356 {
 357         const char *str = input;
 358         char *end = NULL;
 359         uint32_t min, max;
 360         uint32_t idx;
 361
 362         while (isblank(*str))
 363                 str++;
 364
 365         if (!isdigit(*str) && *str != '(')
 366                 return -1;
 367
 368         /* process single number or single range of number */
 369         if (*str != '(') {
 370                 errno = 0;
 371                 idx = strtoul(str, &end, 10);
 372                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 373                         return -1;
 374
 375                 while (isblank(*end))
 376                         end++;
 377
 378                 min = idx;
 379                 max = idx;
 380
 381                 /* process single <number>-<number> */
 382                 if (*end == '-') {
 383                         end++;
 384                         while (isblank(*end))
 385                                 end++;
 386                         if (!isdigit(*end))
 387                                 return -1;
 388
 389                         errno = 0;
 390                         idx = strtoul(end, &end, 10);
 391                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 392                                 return -1;
 393
 394                         max = idx;
 395                         while (isblank(*end))
 396                                 end++;
 397                 }
 398
 399                 if (*end != ':')
 400                         return -1;
 401
 402                 for (idx = RTE_MIN(min, max);
 403                      idx <= RTE_MAX(min, max); idx++)
 404                         devargs->proto_xtr[idx] = xtr_type;
 405
 406                 return 0;
 407         }
 408
 409         /* process set within bracket */
 410         str++;
 411         while (isblank(*str))
 412                 str++;
 413         if (*str == '\0')
 414                 return -1;
 415
 416         min = ICE_MAX_QUEUE_NUM;
 417         do {
 418                 /* go ahead to the first digit */
 419                 while (isblank(*str))
 420                         str++;
 421                 if (!isdigit(*str))
 422                         return -1;
 423
 424                 /* get the digit value */
 425                 errno = 0;
 426                 idx = strtoul(str, &end, 10);
 427                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 428                         return -1;
 429
 430                 /* go ahead to separator '-',',' and ')' */
 431                 while (isblank(*end))
 432                         end++;
 433                 if (*end == '-') {
 434                         if (min == ICE_MAX_QUEUE_NUM)
 435                                 min = idx;
 436                         else /* avoid continuous '-' */
 437                                 return -1;
 438                 } else if (*end == ',' || *end == ')') {
 439                         max = idx;
 440                         if (min == ICE_MAX_QUEUE_NUM)
 441                                 min = idx;
 442
 443                         for (idx = RTE_MIN(min, max);
 444                              idx <= RTE_MAX(min, max); idx++)
 445                                 devargs->proto_xtr[idx] = xtr_type;
 446
 447                         min = ICE_MAX_QUEUE_NUM;
 448                 } else {
 449                         return -1;
 450                 }
 451
 452                 str = end + 1;
 453         } while (*end != ')' && *end != '\0');
 454
 455         return 0;
 456 }
 457
 458 static int
 459 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 460 {
 461         const char *queue_start;
 462         uint32_t idx;
 463         int xtr_type;
 464         char xtr_name[32];
 465
 466         while (isblank(*queues))
 467                 queues++;
 468
 469         if (*queues != '[') {
 470                 xtr_type = lookup_proto_xtr_type(queues);
 471                 if (xtr_type < 0)
 472                         return -1;
 473
 474                 devargs->proto_xtr_dflt = xtr_type;
 475
 476                 return 0;
 477         }
 478
 479         queues++;
 480         do {
 481                 while (isblank(*queues))
 482                         queues++;
 483                 if (*queues == '\0')
 484                         return -1;
 485
 486                 queue_start = queues;
 487
 488                 /* go across a complete bracket */
 489                 if (*queue_start == '(') {
 490                         queues += strcspn(queues, ")");
 491                         if (*queues != ')')
 492                                 return -1;
 493                 }
 494
 495                 /* scan the separator ':' */
 496                 queues += strcspn(queues, ":");
 497                 if (*queues++ != ':')
 498                         return -1;
 499                 while (isblank(*queues))
 500                         queues++;
 501
 502                 for (idx = 0; ; idx++) {
 503                         if (isblank(queues[idx]) ||
 504                             queues[idx] == ',' ||
 505                             queues[idx] == ']' ||
 506                             queues[idx] == '\0')
 507                                 break;
 508
 509                         if (idx > sizeof(xtr_name) - 2)
 510                                 return -1;
 511
 512                         xtr_name[idx] = queues[idx];
 513                 }
 514                 xtr_name[idx] = '\0';
 515                 xtr_type = lookup_proto_xtr_type(xtr_name);
 516                 if (xtr_type < 0)
 517                         return -1;
 518
 519                 queues += idx;
 520
 521                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 522                         queues++;
 523
 524                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 525                         return -1;
 526         } while (*queues != '\0');
 527
 528         return 0;
 529 }
 530
 531 static int
 532 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 533                      void *extra_args)
 534 {
 535         struct ice_devargs *devargs = extra_args;
 536
 537         if (value == NULL || extra_args == NULL)
 538                 return -EINVAL;
 539
 540         if (parse_queue_proto_xtr(value, devargs) < 0) {
 541                 PMD_DRV_LOG(ERR,
 542                             "The protocol extraction parameter is wrong : '%s'",
 543                             value);
 544                 return -1;
 545         }
 546
 547         return 0;
 548 }
 549
 550 static void
 551 ice_check_proto_xtr_support(struct ice_hw *hw)
 552 {
 553 #define FLX_REG(val, fld, idx) \
 554         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 555          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 556         static struct {
 557                 uint32_t rxdid;
 558                 uint8_t opcode;
 559                 uint8_t protid_0;
 560                 uint8_t protid_1;
 561         } xtr_sets[] = {
 562                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 563                                      ICE_RX_OPC_EXTRACT,
 564                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 565                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 566                                      ICE_RX_OPC_EXTRACT,
 567                                      ICE_PROT_IPV4_OF_OR_S,
 568                                      ICE_PROT_IPV4_OF_OR_S },
 569                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 570                                      ICE_RX_OPC_EXTRACT,
 571                                      ICE_PROT_IPV6_OF_OR_S,
 572                                      ICE_PROT_IPV6_OF_OR_S },
 573                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 574                                           ICE_RX_OPC_EXTRACT,
 575                                           ICE_PROT_IPV6_OF_OR_S,
 576                                           ICE_PROT_IPV6_OF_OR_S },
 577                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 578                                     ICE_RX_OPC_EXTRACT,
 579                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 580                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 581                                           ICE_RX_OPC_PROTID,
 582                                           ICE_PROT_IPV4_OF_OR_S,
 583                                           ICE_PROT_IPV6_OF_OR_S },
 584         };
 585         uint32_t i;
 586
 587         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 588                 uint32_t rxdid = xtr_sets[i].rxdid;
 589                 uint32_t v;
 590
 591                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 592                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 593
 594                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 595                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 596                                 ice_proto_xtr_hw_support[i] = true;
 597                 }
 598
 599                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 600                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 601
 602                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 603                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 604                                 ice_proto_xtr_hw_support[i] = true;
 605                 }
 606         }
 607 }
 608
 609 static int
 610 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 611                   uint32_t num)
 612 {
 613         struct pool_entry *entry;
 614
 615         if (!pool || !num)
 616                 return -EINVAL;
 617
 618         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 619         if (!entry) {
 620                 PMD_INIT_LOG(ERR,
 621                              "Failed to allocate memory for resource pool");
 622                 return -ENOMEM;
 623         }
 624
 625         /* queue heap initialize */
 626         pool->num_free = num;
 627         pool->num_alloc = 0;
 628         pool->base = base;
 629         LIST_INIT(&pool->alloc_list);
 630         LIST_INIT(&pool->free_list);
 631
 632         /* Initialize element  */
 633         entry->base = 0;
 634         entry->len = num;
 635
 636         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 637         return 0;
 638 }
 639
 640 static int
 641 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 642                    uint16_t num)
 643 {
 644         struct pool_entry *entry, *valid_entry;
 645
 646         if (!pool || !num) {
 647                 PMD_INIT_LOG(ERR, "Invalid parameter");
 648                 return -EINVAL;
 649         }
 650
 651         if (pool->num_free < num) {
 652                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 653                              num, pool->num_free);
 654                 return -ENOMEM;
 655         }
 656
 657         valid_entry = NULL;
 658         /* Lookup  in free list and find most fit one */
 659         LIST_FOREACH(entry, &pool->free_list, next) {
 660                 if (entry->len >= num) {
 661                         /* Find best one */
 662                         if (entry->len == num) {
 663                                 valid_entry = entry;
 664                                 break;
 665                         }
 666                         if (!valid_entry ||
 667                             valid_entry->len > entry->len)
 668                                 valid_entry = entry;
 669                 }
 670         }
 671
 672         /* Not find one to satisfy the request, return */
 673         if (!valid_entry) {
 674                 PMD_INIT_LOG(ERR, "No valid entry found");
 675                 return -ENOMEM;
 676         }
 677         /**
 678          * The entry have equal queue number as requested,
 679          * remove it from alloc_list.
 680          */
 681         if (valid_entry->len == num) {
 682                 LIST_REMOVE(valid_entry, next);
 683         } else {
 684                 /**
 685                  * The entry have more numbers than requested,
 686                  * create a new entry for alloc_list and minus its
 687                  * queue base and number in free_list.
 688                  */
 689                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 690                 if (!entry) {
 691                         PMD_INIT_LOG(ERR,
 692                                      "Failed to allocate memory for "
 693                                      "resource pool");
 694                         return -ENOMEM;
 695                 }
 696                 entry->base = valid_entry->base;
 697                 entry->len = num;
 698                 valid_entry->base += num;
 699                 valid_entry->len -= num;
 700                 valid_entry = entry;
 701         }
 702
 703         /* Insert it into alloc list, not sorted */
 704         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 705
 706         pool->num_free -= valid_entry->len;
 707         pool->num_alloc += valid_entry->len;
 708
 709         return valid_entry->base + pool->base;
 710 }
 711
 712 static void
 713 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 714 {
 715         struct pool_entry *entry, *next_entry;
 716
 717         if (!pool)
 718                 return;
 719
 720         for (entry = LIST_FIRST(&pool->alloc_list);
 721              entry && (next_entry = LIST_NEXT(entry, next), 1);
 722              entry = next_entry) {
 723                 LIST_REMOVE(entry, next);
 724                 rte_free(entry);
 725         }
 726
 727         for (entry = LIST_FIRST(&pool->free_list);
 728              entry && (next_entry = LIST_NEXT(entry, next), 1);
 729              entry = next_entry) {
 730                 LIST_REMOVE(entry, next);
 731                 rte_free(entry);
 732         }
 733
 734         pool->num_free = 0;
 735         pool->num_alloc = 0;
 736         pool->base = 0;
 737         LIST_INIT(&pool->alloc_list);
 738         LIST_INIT(&pool->free_list);
 739 }
 740
 741 static void
 742 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 743 {
 744         /* Set VSI LUT selection */
 745         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 746                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 747         /* Set Hash scheme */
 748         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 749                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 750         /* enable TC */
 751         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 752 }
 753
 754 static enum ice_status
 755 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 756                                 struct ice_aqc_vsi_props *info,
 757                                 uint8_t enabled_tcmap)
 758 {
 759         uint16_t bsf, qp_idx;
 760
 761         /* default tc 0 now. Multi-TC supporting need to be done later.
 762          * Configure TC and queue mapping parameters, for enabled TC,
 763          * allocate qpnum_per_tc queues to this traffic.
 764          */
 765         if (enabled_tcmap != 0x01) {
 766                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 767                 return -ENOTSUP;
 768         }
 769
 770         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 771         bsf = rte_bsf32(vsi->nb_qps);
 772         /* Adjust the queue number to actual queues that can be applied */
 773         vsi->nb_qps = 0x1 << bsf;
 774
 775         qp_idx = 0;
 776         /* Set tc and queue mapping with VSI */
 777         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 778                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 779                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 780
 781         /* Associate queue number with VSI */
 782         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 783         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 784         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 785         info->valid_sections |=
 786                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 787         /* Set the info.ingress_table and info.egress_table
 788          * for UP translate table. Now just set it to 1:1 map by default
 789          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 790          */
 791 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 792         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 793         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 794         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 795         return 0;
 796 }
 797
 798 static int
 799 ice_init_mac_address(struct rte_eth_dev *dev)
 800 {
 801         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 802
 803         if (!rte_is_unicast_ether_addr
 804                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 805                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 806                 return -EINVAL;
 807         }
 808
 809         rte_ether_addr_copy(
 810                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 811                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 812
 813         dev->data->mac_addrs =
 814                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0);
 815         if (!dev->data->mac_addrs) {
 816                 PMD_INIT_LOG(ERR,
 817                              "Failed to allocate memory to store mac address");
 818                 return -ENOMEM;
 819         }
 820         /* store it to dev data */
 821         rte_ether_addr_copy(
 822                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 823                 &dev->data->mac_addrs[0]);
 824         return 0;
 825 }
 826
 827 /* Find out specific MAC filter */
 828 static struct ice_mac_filter *
 829 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 830 {
 831         struct ice_mac_filter *f;
 832
 833         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 834                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 835                         return f;
 836         }
 837
 838         return NULL;
 839 }
 840
 841 static int
 842 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 843 {
 844         struct ice_fltr_list_entry *m_list_itr = NULL;
 845         struct ice_mac_filter *f;
 846         struct LIST_HEAD_TYPE list_head;
 847         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 848         int ret = 0;
 849
 850         /* If it's added and configured, return */
 851         f = ice_find_mac_filter(vsi, mac_addr);
 852         if (f) {
 853                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 854                 return 0;
 855         }
 856
 857         INIT_LIST_HEAD(&list_head);
 858
 859         m_list_itr = (struct ice_fltr_list_entry *)
 860                 ice_malloc(hw, sizeof(*m_list_itr));
 861         if (!m_list_itr) {
 862                 ret = -ENOMEM;
 863                 goto DONE;
 864         }
 865         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 866                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 867         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 868         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 869         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 870         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 871         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 872
 873         LIST_ADD(&m_list_itr->list_entry, &list_head);
 874
 875         /* Add the mac */
 876         ret = ice_add_mac(hw, &list_head);
 877         if (ret != ICE_SUCCESS) {
 878                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 879                 ret = -EINVAL;
 880                 goto DONE;
 881         }
 882         /* Add the mac addr into mac list */
 883         f = rte_zmalloc(NULL, sizeof(*f), 0);
 884         if (!f) {
 885                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 886                 ret = -ENOMEM;
 887                 goto DONE;
 888         }
 889         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 890         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 891         vsi->mac_num++;
 892
 893         ret = 0;
 894
 895 DONE:
 896         rte_free(m_list_itr);
 897         return ret;
 898 }
 899
 900 static int
 901 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 902 {
 903         struct ice_fltr_list_entry *m_list_itr = NULL;
 904         struct ice_mac_filter *f;
 905         struct LIST_HEAD_TYPE list_head;
 906         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 907         int ret = 0;
 908
 909         /* Can't find it, return an error */
 910         f = ice_find_mac_filter(vsi, mac_addr);
 911         if (!f)
 912                 return -EINVAL;
 913
 914         INIT_LIST_HEAD(&list_head);
 915
 916         m_list_itr = (struct ice_fltr_list_entry *)
 917                 ice_malloc(hw, sizeof(*m_list_itr));
 918         if (!m_list_itr) {
 919                 ret = -ENOMEM;
 920                 goto DONE;
 921         }
 922         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 923                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 924         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 925         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 926         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 927         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 928         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 929
 930         LIST_ADD(&m_list_itr->list_entry, &list_head);
 931
 932         /* remove the mac filter */
 933         ret = ice_remove_mac(hw, &list_head);
 934         if (ret != ICE_SUCCESS) {
 935                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 936                 ret = -EINVAL;
 937                 goto DONE;
 938         }
 939
 940         /* Remove the mac addr from mac list */
 941         TAILQ_REMOVE(&vsi->mac_list, f, next);
 942         rte_free(f);
 943         vsi->mac_num--;
 944
 945         ret = 0;
 946 DONE:
 947         rte_free(m_list_itr);
 948         return ret;
 949 }
 950
 951 /* Find out specific VLAN filter */
 952 static struct ice_vlan_filter *
 953 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 954 {
 955         struct ice_vlan_filter *f;
 956
 957         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 958                 if (vlan->tpid == f->vlan_info.vlan.tpid &&
 959                     vlan->vid == f->vlan_info.vlan.vid)
 960                         return f;
 961         }
 962
 963         return NULL;
 964 }
 965
 966 static int
 967 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 968 {
 969         struct ice_fltr_list_entry *v_list_itr = NULL;
 970         struct ice_vlan_filter *f;
 971         struct LIST_HEAD_TYPE list_head;
 972         struct ice_hw *hw;
 973         int ret = 0;
 974
 975         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
 976                 return -EINVAL;
 977
 978         hw = ICE_VSI_TO_HW(vsi);
 979
 980         /* If it's added and configured, return. */
 981         f = ice_find_vlan_filter(vsi, vlan);
 982         if (f) {
 983                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 984                 return 0;
 985         }
 986
 987         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 988                 return 0;
 989
 990         INIT_LIST_HEAD(&list_head);
 991
 992         v_list_itr = (struct ice_fltr_list_entry *)
 993                       ice_malloc(hw, sizeof(*v_list_itr));
 994         if (!v_list_itr) {
 995                 ret = -ENOMEM;
 996                 goto DONE;
 997         }
 998         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
 999         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1000         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1001         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1002         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1003         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1004         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1005         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1006
1007         LIST_ADD(&v_list_itr->list_entry, &list_head);
1008
1009         /* Add the vlan */
1010         ret = ice_add_vlan(hw, &list_head);
1011         if (ret != ICE_SUCCESS) {
1012                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1013                 ret = -EINVAL;
1014                 goto DONE;
1015         }
1016
1017         /* Add vlan into vlan list */
1018         f = rte_zmalloc(NULL, sizeof(*f), 0);
1019         if (!f) {
1020                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1021                 ret = -ENOMEM;
1022                 goto DONE;
1023         }
1024         f->vlan_info.vlan.tpid = vlan->tpid;
1025         f->vlan_info.vlan.vid = vlan->vid;
1026         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1027         vsi->vlan_num++;
1028
1029         ret = 0;
1030
1031 DONE:
1032         rte_free(v_list_itr);
1033         return ret;
1034 }
1035
1036 static int
1037 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1038 {
1039         struct ice_fltr_list_entry *v_list_itr = NULL;
1040         struct ice_vlan_filter *f;
1041         struct LIST_HEAD_TYPE list_head;
1042         struct ice_hw *hw;
1043         int ret = 0;
1044
1045         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1046                 return -EINVAL;
1047
1048         hw = ICE_VSI_TO_HW(vsi);
1049
1050         /* Can't find it, return an error */
1051         f = ice_find_vlan_filter(vsi, vlan);
1052         if (!f)
1053                 return -EINVAL;
1054
1055         INIT_LIST_HEAD(&list_head);
1056
1057         v_list_itr = (struct ice_fltr_list_entry *)
1058                       ice_malloc(hw, sizeof(*v_list_itr));
1059         if (!v_list_itr) {
1060                 ret = -ENOMEM;
1061                 goto DONE;
1062         }
1063
1064         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1065         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1066         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1067         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1068         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1069         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1070         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1071         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1072
1073         LIST_ADD(&v_list_itr->list_entry, &list_head);
1074
1075         /* remove the vlan filter */
1076         ret = ice_remove_vlan(hw, &list_head);
1077         if (ret != ICE_SUCCESS) {
1078                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1079                 ret = -EINVAL;
1080                 goto DONE;
1081         }
1082
1083         /* Remove the vlan id from vlan list */
1084         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1085         rte_free(f);
1086         vsi->vlan_num--;
1087
1088         ret = 0;
1089 DONE:
1090         rte_free(v_list_itr);
1091         return ret;
1092 }
1093
1094 static int
1095 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1096 {
1097         struct ice_mac_filter *m_f;
1098         struct ice_vlan_filter *v_f;
1099         void *temp;
1100         int ret = 0;
1101
1102         if (!vsi || !vsi->mac_num)
1103                 return -EINVAL;
1104
1105         TAILQ_FOREACH_SAFE(m_f, &vsi->mac_list, next, temp) {
1106                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1107                 if (ret != ICE_SUCCESS) {
1108                         ret = -EINVAL;
1109                         goto DONE;
1110                 }
1111         }
1112
1113         if (vsi->vlan_num == 0)
1114                 return 0;
1115
1116         TAILQ_FOREACH_SAFE(v_f, &vsi->vlan_list, next, temp) {
1117                 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1118                 if (ret != ICE_SUCCESS) {
1119                         ret = -EINVAL;
1120                         goto DONE;
1121                 }
1122         }
1123
1124 DONE:
1125         return ret;
1126 }
1127
1128 /* Enable IRQ0 */
1129 static void
1130 ice_pf_enable_irq0(struct ice_hw *hw)
1131 {
1132         /* reset the registers */
1133         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1134         ICE_READ_REG(hw, PFINT_OICR);
1135
1136 #ifdef ICE_LSE_SPT
1137         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1138                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1139                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1140
1141         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1142                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1143                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1144                        PFINT_OICR_CTL_ITR_INDX_M) |
1145                       PFINT_OICR_CTL_CAUSE_ENA_M);
1146
1147         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1148                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1149                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1150                        PFINT_FW_CTL_ITR_INDX_M) |
1151                       PFINT_FW_CTL_CAUSE_ENA_M);
1152 #else
1153         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1154 #endif
1155
1156         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1157                       GLINT_DYN_CTL_INTENA_M |
1158                       GLINT_DYN_CTL_CLEARPBA_M |
1159                       GLINT_DYN_CTL_ITR_INDX_M);
1160
1161         ice_flush(hw);
1162 }
1163
1164 /* Disable IRQ0 */
1165 static void
1166 ice_pf_disable_irq0(struct ice_hw *hw)
1167 {
1168         /* Disable all interrupt types */
1169         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1170         ice_flush(hw);
1171 }
1172
1173 #ifdef ICE_LSE_SPT
1174 static void
1175 ice_handle_aq_msg(struct rte_eth_dev *dev)
1176 {
1177         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1178         struct ice_ctl_q_info *cq = &hw->adminq;
1179         struct ice_rq_event_info event;
1180         uint16_t pending, opcode;
1181         int ret;
1182
1183         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1184         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1185         if (!event.msg_buf) {
1186                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1187                 return;
1188         }
1189
1190         pending = 1;
1191         while (pending) {
1192                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1193
1194                 if (ret != ICE_SUCCESS) {
1195                         PMD_DRV_LOG(INFO,
1196                                     "Failed to read msg from AdminQ, "
1197                                     "adminq_err: %u",
1198                                     hw->adminq.sq_last_status);
1199                         break;
1200                 }
1201                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1202
1203                 switch (opcode) {
1204                 case ice_aqc_opc_get_link_status:
1205                         ret = ice_link_update(dev, 0);
1206                         if (!ret)
1207                                 rte_eth_dev_callback_process
1208                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1209                         break;
1210                 default:
1211                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1212                                     opcode);
1213                         break;
1214                 }
1215         }
1216         rte_free(event.msg_buf);
1217 }
1218 #endif
1219
1220 /**
1221  * Interrupt handler triggered by NIC for handling
1222  * specific interrupt.
1223  *
1224  * @param handle
1225  *  Pointer to interrupt handle.
1226  * @param param
1227  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1228  *
1229  * @return
1230  *  void
1231  */
1232 static void
1233 ice_interrupt_handler(void *param)
1234 {
1235         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1236         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1237         uint32_t oicr;
1238         uint32_t reg;
1239         uint8_t pf_num;
1240         uint8_t event;
1241         uint16_t queue;
1242         int ret;
1243 #ifdef ICE_LSE_SPT
1244         uint32_t int_fw_ctl;
1245 #endif
1246
1247         /* Disable interrupt */
1248         ice_pf_disable_irq0(hw);
1249
1250         /* read out interrupt causes */
1251         oicr = ICE_READ_REG(hw, PFINT_OICR);
1252 #ifdef ICE_LSE_SPT
1253         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1254 #endif
1255
1256         /* No interrupt event indicated */
1257         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1258                 PMD_DRV_LOG(INFO, "No interrupt event");
1259                 goto done;
1260         }
1261
1262 #ifdef ICE_LSE_SPT
1263         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1264                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1265                 ice_handle_aq_msg(dev);
1266         }
1267 #else
1268         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1269                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1270                 ret = ice_link_update(dev, 0);
1271                 if (!ret)
1272                         rte_eth_dev_callback_process
1273                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1274         }
1275 #endif
1276
1277         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1278                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1279                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1280                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1281                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1282                                  GL_MDET_TX_PQM_PF_NUM_S;
1283                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1284                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1285                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1286                                 GL_MDET_TX_PQM_QNUM_S;
1287
1288                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1289                                     "%d by PQM on TX queue %d PF# %d",
1290                                     event, queue, pf_num);
1291                 }
1292
1293                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1294                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1295                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1296                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1297                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1298                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1299                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1300                                 GL_MDET_TX_TCLAN_QNUM_S;
1301
1302                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1303                                     "%d by TCLAN on TX queue %d PF# %d",
1304                                     event, queue, pf_num);
1305                 }
1306         }
1307 done:
1308         /* Enable interrupt */
1309         ice_pf_enable_irq0(hw);
1310         rte_intr_ack(dev->intr_handle);
1311 }
1312
1313 static void
1314 ice_init_proto_xtr(struct rte_eth_dev *dev)
1315 {
1316         struct ice_adapter *ad =
1317                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1318         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1319         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1320         const struct proto_xtr_ol_flag *ol_flag;
1321         bool proto_xtr_enable = false;
1322         int offset;
1323         uint16_t i;
1324
1325         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1326         if (unlikely(pf->proto_xtr == NULL)) {
1327                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1328                 return;
1329         }
1330
1331         for (i = 0; i < pf->lan_nb_qps; i++) {
1332                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1333                                    ad->devargs.proto_xtr[i] :
1334                                    ad->devargs.proto_xtr_dflt;
1335
1336                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1337                         uint8_t type = pf->proto_xtr[i];
1338
1339                         ice_proto_xtr_ol_flag_params[type].required = true;
1340                         proto_xtr_enable = true;
1341                 }
1342         }
1343
1344         if (likely(!proto_xtr_enable))
1345                 return;
1346
1347         ice_check_proto_xtr_support(hw);
1348
1349         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1350         if (unlikely(offset == -1)) {
1351                 PMD_DRV_LOG(ERR,
1352                             "Protocol extraction metadata is disabled in mbuf with error %d",
1353                             -rte_errno);
1354                 return;
1355         }
1356
1357         PMD_DRV_LOG(DEBUG,
1358                     "Protocol extraction metadata offset in mbuf is : %d",
1359                     offset);
1360         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1361
1362         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1363                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1364
1365                 if (!ol_flag->required)
1366                         continue;
1367
1368                 if (!ice_proto_xtr_hw_support[i]) {
1369                         PMD_DRV_LOG(ERR,
1370                                     "Protocol extraction type %u is not supported in hardware",
1371                                     i);
1372                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1373                         break;
1374                 }
1375
1376                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1377                 if (unlikely(offset == -1)) {
1378                         PMD_DRV_LOG(ERR,
1379                                     "Protocol extraction offload '%s' failed to register with error %d",
1380                                     ol_flag->param.name, -rte_errno);
1381
1382                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1383                         break;
1384                 }
1385
1386                 PMD_DRV_LOG(DEBUG,
1387                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1388                             ol_flag->param.name, offset);
1389                 *ol_flag->ol_flag = 1ULL << offset;
1390         }
1391 }
1392
1393 /*  Initialize SW parameters of PF */
1394 static int
1395 ice_pf_sw_init(struct rte_eth_dev *dev)
1396 {
1397         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1398         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1399
1400         pf->lan_nb_qp_max =
1401                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1402                                   hw->func_caps.common_cap.num_rxq);
1403
1404         pf->lan_nb_qps = pf->lan_nb_qp_max;
1405
1406         ice_init_proto_xtr(dev);
1407
1408         if (hw->func_caps.fd_fltr_guar > 0 ||
1409             hw->func_caps.fd_fltr_best_effort > 0) {
1410                 pf->flags |= ICE_FLAG_FDIR;
1411                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1412                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1413         } else {
1414                 pf->fdir_nb_qps = 0;
1415         }
1416         pf->fdir_qp_offset = 0;
1417
1418         return 0;
1419 }
1420
1421 struct ice_vsi *
1422 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1423 {
1424         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1425         struct ice_vsi *vsi = NULL;
1426         struct ice_vsi_ctx vsi_ctx;
1427         int ret;
1428         struct rte_ether_addr broadcast = {
1429                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1430         struct rte_ether_addr mac_addr;
1431         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1432         uint8_t tc_bitmap = 0x1;
1433         uint16_t cfg;
1434
1435         /* hw->num_lports = 1 in NIC mode */
1436         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1437         if (!vsi)
1438                 return NULL;
1439
1440         vsi->idx = pf->next_vsi_idx;
1441         pf->next_vsi_idx++;
1442         vsi->type = type;
1443         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1444         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1445         vsi->vlan_anti_spoof_on = 0;
1446         vsi->vlan_filter_on = 1;
1447         TAILQ_INIT(&vsi->mac_list);
1448         TAILQ_INIT(&vsi->vlan_list);
1449
1450         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1451         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1452                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1453                         hw->func_caps.common_cap.rss_table_size;
1454         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1455
1456         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1457         switch (type) {
1458         case ICE_VSI_PF:
1459                 vsi->nb_qps = pf->lan_nb_qps;
1460                 vsi->base_queue = 1;
1461                 ice_vsi_config_default_rss(&vsi_ctx.info);
1462                 vsi_ctx.alloc_from_pool = true;
1463                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1464                 /* switch_id is queried by get_switch_config aq, which is done
1465                  * by ice_init_hw
1466                  */
1467                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1468                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1469                 /* Allow all untagged or tagged packets */
1470                 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1471                 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1472                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1473                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1474                 if (ice_is_dvm_ena(hw)) {
1475                         vsi_ctx.info.outer_vlan_flags =
1476                                 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1477                                  ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1478                                 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1479                         vsi_ctx.info.outer_vlan_flags |=
1480                                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1481                                  ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1482                                 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1483                 }
1484
1485                 /* FDIR */
1486                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1487                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1488                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1489                 cfg = ICE_AQ_VSI_FD_ENABLE;
1490                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1491                 vsi_ctx.info.max_fd_fltr_dedicated =
1492                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1493                 vsi_ctx.info.max_fd_fltr_shared =
1494                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1495
1496                 /* Enable VLAN/UP trip */
1497                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1498                                                       &vsi_ctx.info,
1499                                                       ICE_DEFAULT_TCMAP);
1500                 if (ret) {
1501                         PMD_INIT_LOG(ERR,
1502                                      "tc queue mapping with vsi failed, "
1503                                      "err = %d",
1504                                      ret);
1505                         goto fail_mem;
1506                 }
1507
1508                 break;
1509         case ICE_VSI_CTRL:
1510                 vsi->nb_qps = pf->fdir_nb_qps;
1511                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1512                 vsi_ctx.alloc_from_pool = true;
1513                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1514
1515                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1516                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1517                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1518                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1519                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1520                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1521                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1522                                                       &vsi_ctx.info,
1523                                                       ICE_DEFAULT_TCMAP);
1524                 if (ret) {
1525                         PMD_INIT_LOG(ERR,
1526                                      "tc queue mapping with vsi failed, "
1527                                      "err = %d",
1528                                      ret);
1529                         goto fail_mem;
1530                 }
1531                 break;
1532         default:
1533                 /* for other types of VSI */
1534                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1535                 goto fail_mem;
1536         }
1537
1538         /* VF has MSIX interrupt in VF range, don't allocate here */
1539         if (type == ICE_VSI_PF) {
1540                 ret = ice_res_pool_alloc(&pf->msix_pool,
1541                                          RTE_MIN(vsi->nb_qps,
1542                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1543                 if (ret < 0) {
1544                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1545                                      vsi->vsi_id, ret);
1546                 }
1547                 vsi->msix_intr = ret;
1548                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1549         } else if (type == ICE_VSI_CTRL) {
1550                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1551                 if (ret < 0) {
1552                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1553                                     vsi->vsi_id, ret);
1554                 }
1555                 vsi->msix_intr = ret;
1556                 vsi->nb_msix = 1;
1557         } else {
1558                 vsi->msix_intr = 0;
1559                 vsi->nb_msix = 0;
1560         }
1561         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1562         if (ret != ICE_SUCCESS) {
1563                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1564                 goto fail_mem;
1565         }
1566         /* store vsi information is SW structure */
1567         vsi->vsi_id = vsi_ctx.vsi_num;
1568         vsi->info = vsi_ctx.info;
1569         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1570         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1571
1572         if (type == ICE_VSI_PF) {
1573                 /* MAC configuration */
1574                 rte_ether_addr_copy((struct rte_ether_addr *)
1575                                         hw->port_info->mac.perm_addr,
1576                                     &pf->dev_addr);
1577
1578                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1579                 ret = ice_add_mac_filter(vsi, &mac_addr);
1580                 if (ret != ICE_SUCCESS)
1581                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1582
1583                 rte_ether_addr_copy(&broadcast, &mac_addr);
1584                 ret = ice_add_mac_filter(vsi, &mac_addr);
1585                 if (ret != ICE_SUCCESS)
1586                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1587         }
1588
1589         /* At the beginning, only TC0. */
1590         /* What we need here is the maximam number of the TX queues.
1591          * Currently vsi->nb_qps means it.
1592          * Correct it if any change.
1593          */
1594         max_txqs[0] = vsi->nb_qps;
1595         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1596                               tc_bitmap, max_txqs);
1597         if (ret != ICE_SUCCESS)
1598                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1599
1600         return vsi;
1601 fail_mem:
1602         rte_free(vsi);
1603         pf->next_vsi_idx--;
1604         return NULL;
1605 }
1606
1607 static int
1608 ice_send_driver_ver(struct ice_hw *hw)
1609 {
1610         struct ice_driver_ver dv;
1611
1612         /* we don't have driver version use 0 for dummy */
1613         dv.major_ver = 0;
1614         dv.minor_ver = 0;
1615         dv.build_ver = 0;
1616         dv.subbuild_ver = 0;
1617         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1618
1619         return ice_aq_send_driver_ver(hw, &dv, NULL);
1620 }
1621
1622 static int
1623 ice_pf_setup(struct ice_pf *pf)
1624 {
1625         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1626         struct ice_vsi *vsi;
1627         uint16_t unused;
1628
1629         /* Clear all stats counters */
1630         pf->offset_loaded = false;
1631         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1632         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1633         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1634         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1635
1636         /* force guaranteed filter pool for PF */
1637         ice_alloc_fd_guar_item(hw, &unused,
1638                                hw->func_caps.fd_fltr_guar);
1639         /* force shared filter pool for PF */
1640         ice_alloc_fd_shrd_item(hw, &unused,
1641                                hw->func_caps.fd_fltr_best_effort);
1642
1643         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1644         if (!vsi) {
1645                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1646                 return -EINVAL;
1647         }
1648
1649         pf->main_vsi = vsi;
1650
1651         return 0;
1652 }
1653
1654 /*
1655  * Extract device serial number from PCIe Configuration Space and
1656  * determine the pkg file path according to the DSN.
1657  */
1658 #ifndef RTE_EXEC_ENV_WINDOWS
1659 static int
1660 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1661 {
1662         off_t pos;
1663         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1664         uint32_t dsn_low, dsn_high;
1665         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1666
1667         pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1668
1669         if (pos) {
1670                 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0) {
1671                         PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
1672                         return -1;
1673                 }
1674                 if (rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) {
1675                         PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
1676                         return -1;
1677                 }
1678                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1679                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1680         } else {
1681                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1682                 goto fail_dsn;
1683         }
1684
1685         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1686                 ICE_MAX_PKG_FILENAME_SIZE);
1687         if (!ice_access(strcat(pkg_file, opt_ddp_filename), 0))
1688                 return 0;
1689
1690         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1691                 ICE_MAX_PKG_FILENAME_SIZE);
1692         if (!ice_access(strcat(pkg_file, opt_ddp_filename), 0))
1693                 return 0;
1694
1695 fail_dsn:
1696         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1697         if (!ice_access(pkg_file, 0))
1698                 return 0;
1699         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1700         return 0;
1701 }
1702 #endif
1703
1704 enum ice_pkg_type
1705 ice_load_pkg_type(struct ice_hw *hw)
1706 {
1707         enum ice_pkg_type package_type;
1708
1709         /* store the activated package type (OS default or Comms) */
1710         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1711                 ICE_PKG_NAME_SIZE))
1712                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1713         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1714                 ICE_PKG_NAME_SIZE))
1715                 package_type = ICE_PKG_TYPE_COMMS;
1716         else
1717                 package_type = ICE_PKG_TYPE_UNKNOWN;
1718
1719         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1720                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1721                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1722                 hw->active_pkg_name,
1723                 ice_is_dvm_ena(hw) ? "double" : "single");
1724
1725         return package_type;
1726 }
1727
1728 #ifndef RTE_EXEC_ENV_WINDOWS
1729 static int ice_load_pkg(struct rte_eth_dev *dev)
1730 {
1731         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1733         int err;
1734         uint8_t *buf;
1735         int buf_len;
1736         FILE *file;
1737         struct stat fstat;
1738         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1739         struct ice_adapter *ad =
1740                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1741
1742         err = ice_pkg_file_search_path(pci_dev, pkg_file);
1743         if (err) {
1744                 PMD_INIT_LOG(ERR, "failed to search file path\n");
1745                 return err;
1746         }
1747
1748         file = fopen(pkg_file, "rb");
1749         if (!file)  {
1750                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1751                 return -1;
1752         }
1753
1754         err = stat(pkg_file, &fstat);
1755         if (err) {
1756                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1757                 fclose(file);
1758                 return err;
1759         }
1760
1761         buf_len = fstat.st_size;
1762         buf = rte_malloc(NULL, buf_len, 0);
1763
1764         if (!buf) {
1765                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1766                                 buf_len);
1767                 fclose(file);
1768                 return -1;
1769         }
1770
1771         err = fread(buf, buf_len, 1, file);
1772         if (err != 1) {
1773                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1774                 fclose(file);
1775                 err = -1;
1776                 goto fail_exit;
1777         }
1778
1779         fclose(file);
1780
1781         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1782         if (err) {
1783                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1784                 goto fail_exit;
1785         }
1786
1787         /* store the loaded pkg type info */
1788         ad->active_pkg_type = ice_load_pkg_type(hw);
1789
1790         err = ice_init_hw_tbls(hw);
1791         if (err) {
1792                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1793                 goto fail_init_tbls;
1794         }
1795
1796         return 0;
1797
1798 fail_init_tbls:
1799         rte_free(hw->pkg_copy);
1800 fail_exit:
1801         rte_free(buf);
1802         return err;
1803 }
1804 #endif
1805
1806 static void
1807 ice_base_queue_get(struct ice_pf *pf)
1808 {
1809         uint32_t reg;
1810         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1811
1812         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1813         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1814                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1815         } else {
1816                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1817                                         " index");
1818         }
1819 }
1820
1821 static int
1822 parse_bool(const char *key, const char *value, void *args)
1823 {
1824         int *i = (int *)args;
1825         char *end;
1826         int num;
1827
1828         num = strtoul(value, &end, 10);
1829
1830         if (num != 0 && num != 1) {
1831                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1832                         "value must be 0 or 1",
1833                         value, key);
1834                 return -1;
1835         }
1836
1837         *i = num;
1838         return 0;
1839 }
1840
1841 static int
1842 parse_u64(const char *key, const char *value, void *args)
1843 {
1844         u64 *num = (u64 *)args;
1845         u64 tmp;
1846
1847         errno = 0;
1848         tmp = strtoull(value, NULL, 16);
1849         if (errno) {
1850                 PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u64",
1851                             key, value);
1852                 return -1;
1853         }
1854
1855         *num = tmp;
1856
1857         return 0;
1858 }
1859
1860 static int ice_parse_devargs(struct rte_eth_dev *dev)
1861 {
1862         struct ice_adapter *ad =
1863                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1864         struct rte_devargs *devargs = dev->device->devargs;
1865         struct rte_kvargs *kvlist;
1866         int ret;
1867
1868         if (devargs == NULL)
1869                 return 0;
1870
1871         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1872         if (kvlist == NULL) {
1873                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1874                 return -EINVAL;
1875         }
1876
1877         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1878         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1879                sizeof(ad->devargs.proto_xtr));
1880
1881         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1882                                  &handle_proto_xtr_arg, &ad->devargs);
1883         if (ret)
1884                 goto bail;
1885
1886         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1887                                  &parse_bool, &ad->devargs.safe_mode_support);
1888         if (ret)
1889                 goto bail;
1890
1891         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1892                                  &parse_bool, &ad->devargs.pipe_mode_support);
1893         if (ret)
1894                 goto bail;
1895
1896         ret = rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG,
1897                                  &parse_u64, &ad->hw.debug_mask);
1898         if (ret)
1899                 goto bail;
1900
1901 bail:
1902         rte_kvargs_free(kvlist);
1903         return ret;
1904 }
1905
1906 /* Forward LLDP packets to default VSI by set switch rules */
1907 static int
1908 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1909 {
1910         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1911         struct ice_fltr_list_entry *s_list_itr = NULL;
1912         struct LIST_HEAD_TYPE list_head;
1913         int ret = 0;
1914
1915         INIT_LIST_HEAD(&list_head);
1916
1917         s_list_itr = (struct ice_fltr_list_entry *)
1918                         ice_malloc(hw, sizeof(*s_list_itr));
1919         if (!s_list_itr)
1920                 return -ENOMEM;
1921         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1922         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1923         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1924                         RTE_ETHER_TYPE_LLDP;
1925         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1926         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1927         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1928         LIST_ADD(&s_list_itr->list_entry, &list_head);
1929         if (on)
1930                 ret = ice_add_eth_mac(hw, &list_head);
1931         else
1932                 ret = ice_remove_eth_mac(hw, &list_head);
1933
1934         rte_free(s_list_itr);
1935         return ret;
1936 }
1937
1938 static enum ice_status
1939 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1940                 uint16_t num, uint16_t desc_id,
1941                 uint16_t *prof_buf, uint16_t *num_prof)
1942 {
1943         struct ice_aqc_res_elem *resp_buf;
1944         int ret;
1945         uint16_t buf_len;
1946         bool res_shared = 1;
1947         struct ice_aq_desc aq_desc;
1948         struct ice_sq_cd *cd = NULL;
1949         struct ice_aqc_get_allocd_res_desc *cmd =
1950                         &aq_desc.params.get_res_desc;
1951
1952         buf_len = sizeof(*resp_buf) * num;
1953         resp_buf = ice_malloc(hw, buf_len);
1954         if (!resp_buf)
1955                 return -ENOMEM;
1956
1957         ice_fill_dflt_direct_cmd_desc(&aq_desc,
1958                         ice_aqc_opc_get_allocd_res_desc);
1959
1960         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1961                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
1962                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1963         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1964
1965         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1966         if (!ret)
1967                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1968         else
1969                 goto exit;
1970
1971         ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
1972                         (*num_prof), ICE_NONDMA_TO_NONDMA);
1973
1974 exit:
1975         rte_free(resp_buf);
1976         return ret;
1977 }
1978 static int
1979 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1980 {
1981         int ret;
1982         uint16_t prof_id;
1983         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1984         uint16_t first_desc = 1;
1985         uint16_t num_prof = 0;
1986
1987         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1988                         first_desc, prof_buf, &num_prof);
1989         if (ret) {
1990                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
1991                 return ret;
1992         }
1993
1994         for (prof_id = 0; prof_id < num_prof; prof_id++) {
1995                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
1996                 if (ret) {
1997                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
1998                         return ret;
1999                 }
2000         }
2001         return 0;
2002 }
2003
2004 static int
2005 ice_reset_fxp_resource(struct ice_hw *hw)
2006 {
2007         int ret;
2008
2009         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2010         if (ret) {
2011                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2012                 return ret;
2013         }
2014
2015         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2016         if (ret) {
2017                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2018                 return ret;
2019         }
2020
2021         return 0;
2022 }
2023
2024 static void
2025 ice_rss_ctx_init(struct ice_pf *pf)
2026 {
2027         memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
2028 }
2029
2030 static uint64_t
2031 ice_get_supported_rxdid(struct ice_hw *hw)
2032 {
2033         uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2034         uint32_t regval;
2035         int i;
2036
2037         supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2038
2039         for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2040                 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2041                 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2042                         & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2043                         supported_rxdid |= BIT(i);
2044         }
2045         return supported_rxdid;
2046 }
2047
2048 static int
2049 ice_dev_init(struct rte_eth_dev *dev)
2050 {
2051         struct rte_pci_device *pci_dev;
2052         struct rte_intr_handle *intr_handle;
2053         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2055         struct ice_adapter *ad =
2056                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2057         struct ice_vsi *vsi;
2058         int ret;
2059
2060         dev->dev_ops = &ice_eth_dev_ops;
2061         dev->rx_queue_count = ice_rx_queue_count;
2062         dev->rx_descriptor_status = ice_rx_descriptor_status;
2063         dev->tx_descriptor_status = ice_tx_descriptor_status;
2064         dev->rx_pkt_burst = ice_recv_pkts;
2065         dev->tx_pkt_burst = ice_xmit_pkts;
2066         dev->tx_pkt_prepare = ice_prep_pkts;
2067
2068         /* for secondary processes, we don't initialise any further as primary
2069          * has already done this work.
2070          */
2071         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2072                 ice_set_rx_function(dev);
2073                 ice_set_tx_function(dev);
2074                 return 0;
2075         }
2076
2077         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2078
2079         ice_set_default_ptype_table(dev);
2080         pci_dev = RTE_DEV_TO_PCI(dev->device);
2081         intr_handle = &pci_dev->intr_handle;
2082
2083         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2084         pf->dev_data = dev->data;
2085         hw->back = pf->adapter;
2086         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2087         hw->vendor_id = pci_dev->id.vendor_id;
2088         hw->device_id = pci_dev->id.device_id;
2089         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2090         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2091         hw->bus.device = pci_dev->addr.devid;
2092         hw->bus.func = pci_dev->addr.function;
2093
2094         ret = ice_parse_devargs(dev);
2095         if (ret) {
2096                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2097                 return -EINVAL;
2098         }
2099
2100         ice_init_controlq_parameter(hw);
2101
2102         ret = ice_init_hw(hw);
2103         if (ret) {
2104                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2105                 return -EINVAL;
2106         }
2107
2108 #ifndef RTE_EXEC_ENV_WINDOWS
2109         ret = ice_load_pkg(dev);
2110         if (ret) {
2111                 if (ad->devargs.safe_mode_support == 0) {
2112                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2113                                         "Use safe-mode-support=1 to enter Safe Mode");
2114                         return ret;
2115                 }
2116
2117                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2118                                         "Entering Safe Mode");
2119                 ad->is_safe_mode = 1;
2120         }
2121 #endif
2122
2123         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2124                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2125                      hw->api_maj_ver, hw->api_min_ver);
2126
2127         ice_pf_sw_init(dev);
2128         ret = ice_init_mac_address(dev);
2129         if (ret) {
2130                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2131                 goto err_init_mac;
2132         }
2133
2134         ret = ice_res_pool_init(&pf->msix_pool, 1,
2135                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2136         if (ret) {
2137                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2138                 goto err_msix_pool_init;
2139         }
2140
2141         ret = ice_pf_setup(pf);
2142         if (ret) {
2143                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2144                 goto err_pf_setup;
2145         }
2146
2147         ret = ice_send_driver_ver(hw);
2148         if (ret) {
2149                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2150                 goto err_pf_setup;
2151         }
2152
2153         vsi = pf->main_vsi;
2154
2155         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2156         if (ret != ICE_SUCCESS)
2157                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2158         ret = ice_init_dcb(hw, true);
2159         if (ret != ICE_SUCCESS)
2160                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2161         /* Forward LLDP packets to default VSI */
2162         ret = ice_vsi_config_sw_lldp(vsi, true);
2163         if (ret != ICE_SUCCESS)
2164                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2165         /* register callback func to eal lib */
2166         rte_intr_callback_register(intr_handle,
2167                                    ice_interrupt_handler, dev);
2168
2169         ice_pf_enable_irq0(hw);
2170
2171         /* enable uio intr after callback register */
2172         rte_intr_enable(intr_handle);
2173
2174         /* get base queue pairs index  in the device */
2175         ice_base_queue_get(pf);
2176
2177         /* Initialize RSS context for gtpu_eh */
2178         ice_rss_ctx_init(pf);
2179
2180         if (!ad->is_safe_mode) {
2181                 ret = ice_flow_init(ad);
2182                 if (ret) {
2183                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2184                         return ret;
2185                 }
2186         }
2187
2188         ret = ice_reset_fxp_resource(hw);
2189         if (ret) {
2190                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2191                 return ret;
2192         }
2193
2194         pf->supported_rxdid = ice_get_supported_rxdid(hw);
2195
2196         return 0;
2197
2198 err_pf_setup:
2199         ice_res_pool_destroy(&pf->msix_pool);
2200 err_msix_pool_init:
2201         rte_free(dev->data->mac_addrs);
2202         dev->data->mac_addrs = NULL;
2203 err_init_mac:
2204         ice_sched_cleanup_all(hw);
2205         rte_free(hw->port_info);
2206         ice_shutdown_all_ctrlq(hw);
2207         rte_free(pf->proto_xtr);
2208
2209         return ret;
2210 }
2211
2212 int
2213 ice_release_vsi(struct ice_vsi *vsi)
2214 {
2215         struct ice_hw *hw;
2216         struct ice_vsi_ctx vsi_ctx;
2217         enum ice_status ret;
2218         int error = 0;
2219
2220         if (!vsi)
2221                 return error;
2222
2223         hw = ICE_VSI_TO_HW(vsi);
2224
2225         ice_remove_all_mac_vlan_filters(vsi);
2226
2227         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2228
2229         vsi_ctx.vsi_num = vsi->vsi_id;
2230         vsi_ctx.info = vsi->info;
2231         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2232         if (ret != ICE_SUCCESS) {
2233                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2234                 error = -1;
2235         }
2236
2237         rte_free(vsi->rss_lut);
2238         rte_free(vsi->rss_key);
2239         rte_free(vsi);
2240         return error;
2241 }
2242
2243 void
2244 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2245 {
2246         struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
2247         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2248         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2249         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2250         uint16_t msix_intr, i;
2251
2252         /* disable interrupt and also clear all the exist config */
2253         for (i = 0; i < vsi->nb_qps; i++) {
2254                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2255                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2256                 rte_wmb();
2257         }
2258
2259         if (rte_intr_allow_others(intr_handle))
2260                 /* vfio-pci */
2261                 for (i = 0; i < vsi->nb_msix; i++) {
2262                         msix_intr = vsi->msix_intr + i;
2263                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2264                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2265                 }
2266         else
2267                 /* igb_uio */
2268                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2269 }
2270
2271 static int
2272 ice_dev_stop(struct rte_eth_dev *dev)
2273 {
2274         struct rte_eth_dev_data *data = dev->data;
2275         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2276         struct ice_vsi *main_vsi = pf->main_vsi;
2277         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2278         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2279         uint16_t i;
2280
2281         /* avoid stopping again */
2282         if (pf->adapter_stopped)
2283                 return 0;
2284
2285         /* stop and clear all Rx queues */
2286         for (i = 0; i < data->nb_rx_queues; i++)
2287                 ice_rx_queue_stop(dev, i);
2288
2289         /* stop and clear all Tx queues */
2290         for (i = 0; i < data->nb_tx_queues; i++)
2291                 ice_tx_queue_stop(dev, i);
2292
2293         /* disable all queue interrupts */
2294         ice_vsi_disable_queues_intr(main_vsi);
2295
2296         if (pf->init_link_up)
2297                 ice_dev_set_link_up(dev);
2298         else
2299                 ice_dev_set_link_down(dev);
2300
2301         /* Clean datapath event and queue/vec mapping */
2302         rte_intr_efd_disable(intr_handle);
2303         if (intr_handle->intr_vec) {
2304                 rte_free(intr_handle->intr_vec);
2305                 intr_handle->intr_vec = NULL;
2306         }
2307
2308         pf->adapter_stopped = true;
2309         dev->data->dev_started = 0;
2310
2311         return 0;
2312 }
2313
2314 static int
2315 ice_dev_close(struct rte_eth_dev *dev)
2316 {
2317         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2318         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2319         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2320         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2321         struct ice_adapter *ad =
2322                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2323         int ret;
2324
2325         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2326                 return 0;
2327
2328         /* Since stop will make link down, then the link event will be
2329          * triggered, disable the irq firstly to avoid the port_infoe etc
2330          * resources deallocation causing the interrupt service thread
2331          * crash.
2332          */
2333         ice_pf_disable_irq0(hw);
2334
2335         ret = ice_dev_stop(dev);
2336
2337         if (!ad->is_safe_mode)
2338                 ice_flow_uninit(ad);
2339
2340         /* release all queue resource */
2341         ice_free_queues(dev);
2342
2343         ice_res_pool_destroy(&pf->msix_pool);
2344         ice_release_vsi(pf->main_vsi);
2345         ice_sched_cleanup_all(hw);
2346         ice_free_hw_tbls(hw);
2347         rte_free(hw->port_info);
2348         hw->port_info = NULL;
2349         ice_shutdown_all_ctrlq(hw);
2350         rte_free(pf->proto_xtr);
2351         pf->proto_xtr = NULL;
2352
2353         /* disable uio intr before callback unregister */
2354         rte_intr_disable(intr_handle);
2355
2356         /* unregister callback func from eal lib */
2357         rte_intr_callback_unregister(intr_handle,
2358                                      ice_interrupt_handler, dev);
2359
2360         return ret;
2361 }
2362
2363 static int
2364 ice_dev_uninit(struct rte_eth_dev *dev)
2365 {
2366         ice_dev_close(dev);
2367
2368         return 0;
2369 }
2370
2371 static bool
2372 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2373 {
2374         return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2375 }
2376
2377 static void
2378 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2379 {
2380         cfg->hash_flds = 0;
2381         cfg->addl_hdrs = 0;
2382         cfg->symm = 0;
2383         cfg->hdr_type = ICE_RSS_OUTER_HEADERS;
2384 }
2385
2386 static int
2387 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2388 {
2389         enum ice_status status = ICE_SUCCESS;
2390         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2391         struct ice_vsi *vsi = pf->main_vsi;
2392
2393         if (!is_hash_cfg_valid(cfg))
2394                 return -ENOENT;
2395
2396         status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2397         if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2398                 PMD_DRV_LOG(ERR,
2399                             "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2400                             vsi->idx, status);
2401                 return -EBUSY;
2402         }
2403
2404         return 0;
2405 }
2406
2407 static int
2408 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2409 {
2410         enum ice_status status = ICE_SUCCESS;
2411         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2412         struct ice_vsi *vsi = pf->main_vsi;
2413
2414         if (!is_hash_cfg_valid(cfg))
2415                 return -ENOENT;
2416
2417         status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2418         if (status) {
2419                 PMD_DRV_LOG(ERR,
2420                             "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2421                             vsi->idx, status);
2422                 return -EBUSY;
2423         }
2424
2425         return 0;
2426 }
2427
2428 static int
2429 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2430 {
2431         int ret;
2432
2433         ret = ice_hash_moveout(pf, cfg);
2434         if (ret && (ret != -ENOENT))
2435                 return ret;
2436
2437         hash_cfg_reset(cfg);
2438
2439         return 0;
2440 }
2441
2442 static int
2443 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2444                          u8 ctx_idx)
2445 {
2446         int ret;
2447
2448         switch (ctx_idx) {
2449         case ICE_HASH_GTPU_CTX_EH_IP:
2450                 ret = ice_hash_remove(pf,
2451                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2452                 if (ret && (ret != -ENOENT))
2453                         return ret;
2454
2455                 ret = ice_hash_remove(pf,
2456                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2457                 if (ret && (ret != -ENOENT))
2458                         return ret;
2459
2460                 ret = ice_hash_remove(pf,
2461                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2462                 if (ret && (ret != -ENOENT))
2463                         return ret;
2464
2465                 ret = ice_hash_remove(pf,
2466                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2467                 if (ret && (ret != -ENOENT))
2468                         return ret;
2469
2470                 ret = ice_hash_remove(pf,
2471                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2472                 if (ret && (ret != -ENOENT))
2473                         return ret;
2474
2475                 ret = ice_hash_remove(pf,
2476                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2477                 if (ret && (ret != -ENOENT))
2478                         return ret;
2479
2480                 ret = ice_hash_remove(pf,
2481                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2482                 if (ret && (ret != -ENOENT))
2483                         return ret;
2484
2485                 ret = ice_hash_remove(pf,
2486                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2487                 if (ret && (ret != -ENOENT))
2488                         return ret;
2489
2490                 break;
2491         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2492                 ret = ice_hash_remove(pf,
2493                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2494                 if (ret && (ret != -ENOENT))
2495                         return ret;
2496
2497                 ret = ice_hash_remove(pf,
2498                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2499                 if (ret && (ret != -ENOENT))
2500                         return ret;
2501
2502                 ret = ice_hash_moveout(pf,
2503                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2504                 if (ret && (ret != -ENOENT))
2505                         return ret;
2506
2507                 ret = ice_hash_moveout(pf,
2508                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2509                 if (ret && (ret != -ENOENT))
2510                         return ret;
2511
2512                 ret = ice_hash_moveout(pf,
2513                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2514                 if (ret && (ret != -ENOENT))
2515                         return ret;
2516
2517                 ret = ice_hash_moveout(pf,
2518                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2519                 if (ret && (ret != -ENOENT))
2520                         return ret;
2521
2522                 break;
2523         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2524                 ret = ice_hash_remove(pf,
2525                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2526                 if (ret && (ret != -ENOENT))
2527                         return ret;
2528
2529                 ret = ice_hash_remove(pf,
2530                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2531                 if (ret && (ret != -ENOENT))
2532                         return ret;
2533
2534                 ret = ice_hash_moveout(pf,
2535                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2536                 if (ret && (ret != -ENOENT))
2537                         return ret;
2538
2539                 ret = ice_hash_moveout(pf,
2540                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2541                 if (ret && (ret != -ENOENT))
2542                         return ret;
2543
2544                 ret = ice_hash_moveout(pf,
2545                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2546                 if (ret && (ret != -ENOENT))
2547                         return ret;
2548
2549                 ret = ice_hash_moveout(pf,
2550                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2551                 if (ret && (ret != -ENOENT))
2552                         return ret;
2553
2554                 break;
2555         case ICE_HASH_GTPU_CTX_UP_IP:
2556                 ret = ice_hash_remove(pf,
2557                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2558                 if (ret && (ret != -ENOENT))
2559                         return ret;
2560
2561                 ret = ice_hash_remove(pf,
2562                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2563                 if (ret && (ret != -ENOENT))
2564                         return ret;
2565
2566                 ret = ice_hash_moveout(pf,
2567                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2568                 if (ret && (ret != -ENOENT))
2569                         return ret;
2570
2571                 ret = ice_hash_moveout(pf,
2572                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2573                 if (ret && (ret != -ENOENT))
2574                         return ret;
2575
2576                 ret = ice_hash_moveout(pf,
2577                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2578                 if (ret && (ret != -ENOENT))
2579                         return ret;
2580
2581                 break;
2582         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2583         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2584                 ret = ice_hash_moveout(pf,
2585                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2586                 if (ret && (ret != -ENOENT))
2587                         return ret;
2588
2589                 ret = ice_hash_moveout(pf,
2590                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2591                 if (ret && (ret != -ENOENT))
2592                         return ret;
2593
2594                 ret = ice_hash_moveout(pf,
2595                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2596                 if (ret && (ret != -ENOENT))
2597                         return ret;
2598
2599                 break;
2600         case ICE_HASH_GTPU_CTX_DW_IP:
2601                 ret = ice_hash_remove(pf,
2602                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2603                 if (ret && (ret != -ENOENT))
2604                         return ret;
2605
2606                 ret = ice_hash_remove(pf,
2607                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2608                 if (ret && (ret != -ENOENT))
2609                         return ret;
2610
2611                 ret = ice_hash_moveout(pf,
2612                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2613                 if (ret && (ret != -ENOENT))
2614                         return ret;
2615
2616                 ret = ice_hash_moveout(pf,
2617                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2618                 if (ret && (ret != -ENOENT))
2619                         return ret;
2620
2621                 ret = ice_hash_moveout(pf,
2622                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2623                 if (ret && (ret != -ENOENT))
2624                         return ret;
2625
2626                 break;
2627         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2628         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2629                 ret = ice_hash_moveout(pf,
2630                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2631                 if (ret && (ret != -ENOENT))
2632                         return ret;
2633
2634                 ret = ice_hash_moveout(pf,
2635                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2636                 if (ret && (ret != -ENOENT))
2637                         return ret;
2638
2639                 ret = ice_hash_moveout(pf,
2640                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2641                 if (ret && (ret != -ENOENT))
2642                         return ret;
2643
2644                 break;
2645         default:
2646                 break;
2647         }
2648
2649         return 0;
2650 }
2651
2652 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2653 {
2654         u8 eh_idx, ip_idx;
2655
2656         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2657                 eh_idx = 0;
2658         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2659                 eh_idx = 1;
2660         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2661                 eh_idx = 2;
2662         else
2663                 return ICE_HASH_GTPU_CTX_MAX;
2664
2665         ip_idx = 0;
2666         if (hdr & ICE_FLOW_SEG_HDR_UDP)
2667                 ip_idx = 1;
2668         else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2669                 ip_idx = 2;
2670
2671         if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2672                 return eh_idx * 3 + ip_idx;
2673         else
2674                 return ICE_HASH_GTPU_CTX_MAX;
2675 }
2676
2677 static int
2678 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2679 {
2680         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2681
2682         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2683                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2684                                                 gtpu_ctx_idx);
2685         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2686                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2687                                                 gtpu_ctx_idx);
2688
2689         return 0;
2690 }
2691
2692 static int
2693 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2694                           u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2695 {
2696         int ret;
2697
2698         if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2699                 ctx->ctx[ctx_idx] = *cfg;
2700
2701         switch (ctx_idx) {
2702         case ICE_HASH_GTPU_CTX_EH_IP:
2703                 break;
2704         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2705                 ret = ice_hash_moveback(pf,
2706                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2707                 if (ret && (ret != -ENOENT))
2708                         return ret;
2709
2710                 ret = ice_hash_moveback(pf,
2711                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2712                 if (ret && (ret != -ENOENT))
2713                         return ret;
2714
2715                 ret = ice_hash_moveback(pf,
2716                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2717                 if (ret && (ret != -ENOENT))
2718                         return ret;
2719
2720                 ret = ice_hash_moveback(pf,
2721                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2722                 if (ret && (ret != -ENOENT))
2723                         return ret;
2724
2725                 break;
2726         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2727                 ret = ice_hash_moveback(pf,
2728                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2729                 if (ret && (ret != -ENOENT))
2730                         return ret;
2731
2732                 ret = ice_hash_moveback(pf,
2733                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2734                 if (ret && (ret != -ENOENT))
2735                         return ret;
2736
2737                 ret = ice_hash_moveback(pf,
2738                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2739                 if (ret && (ret != -ENOENT))
2740                         return ret;
2741
2742                 ret = ice_hash_moveback(pf,
2743                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2744                 if (ret && (ret != -ENOENT))
2745                         return ret;
2746
2747                 break;
2748         case ICE_HASH_GTPU_CTX_UP_IP:
2749         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2750         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2751         case ICE_HASH_GTPU_CTX_DW_IP:
2752         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2753         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2754                 ret = ice_hash_moveback(pf,
2755                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2756                 if (ret && (ret != -ENOENT))
2757                         return ret;
2758
2759                 ret = ice_hash_moveback(pf,
2760                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2761                 if (ret && (ret != -ENOENT))
2762                         return ret;
2763
2764                 ret = ice_hash_moveback(pf,
2765                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2766                 if (ret && (ret != -ENOENT))
2767                         return ret;
2768
2769                 break;
2770         default:
2771                 break;
2772         }
2773
2774         return 0;
2775 }
2776
2777 static int
2778 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2779 {
2780         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2781
2782         if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2783                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2784                                                  gtpu_ctx_idx, cfg);
2785         else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2786                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2787                                                  gtpu_ctx_idx, cfg);
2788
2789         return 0;
2790 }
2791
2792 static void
2793 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2794 {
2795         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2796
2797         if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2798                 return;
2799
2800         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2801                 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2802         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2803                 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2804 }
2805
2806 int
2807 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2808                      struct ice_rss_hash_cfg *cfg)
2809 {
2810         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2811         int ret;
2812
2813         ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2814         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2815                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2816
2817         ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2818
2819         return 0;
2820 }
2821
2822 int
2823 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2824                      struct ice_rss_hash_cfg *cfg)
2825 {
2826         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2827         int ret;
2828
2829         ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2830         if (ret)
2831                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2832
2833         ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2834         if (ret)
2835                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2836
2837         ret = ice_add_rss_cfg_post(pf, cfg);
2838         if (ret)
2839                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2840
2841         return 0;
2842 }
2843
2844 static void
2845 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2846 {
2847         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2848         struct ice_vsi *vsi = pf->main_vsi;
2849         struct ice_rss_hash_cfg cfg;
2850         int ret;
2851
2852 #define ICE_RSS_HF_ALL ( \
2853         ETH_RSS_IPV4 | \
2854         ETH_RSS_IPV6 | \
2855         ETH_RSS_NONFRAG_IPV4_UDP | \
2856         ETH_RSS_NONFRAG_IPV6_UDP | \
2857         ETH_RSS_NONFRAG_IPV4_TCP | \
2858         ETH_RSS_NONFRAG_IPV6_TCP | \
2859         ETH_RSS_NONFRAG_IPV4_SCTP | \
2860         ETH_RSS_NONFRAG_IPV6_SCTP | \
2861         ETH_RSS_FRAG_IPV4 | \
2862         ETH_RSS_FRAG_IPV6)
2863
2864         ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2865         if (ret)
2866                 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2867                             __func__, ret);
2868
2869         cfg.symm = 0;
2870         cfg.hdr_type = ICE_RSS_OUTER_HEADERS;
2871         /* Configure RSS for IPv4 with src/dst addr as input set */
2872         if (rss_hf & ETH_RSS_IPV4) {
2873                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2874                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2875                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2876                 if (ret)
2877                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2878                                     __func__, ret);
2879         }
2880
2881         /* Configure RSS for IPv6 with src/dst addr as input set */
2882         if (rss_hf & ETH_RSS_IPV6) {
2883                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2884                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2885                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2886                 if (ret)
2887                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2888                                     __func__, ret);
2889         }
2890
2891         /* Configure RSS for udp4 with src/dst addr and port as input set */
2892         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2893                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2894                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2895                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2896                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2897                 if (ret)
2898                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2899                                     __func__, ret);
2900         }
2901
2902         /* Configure RSS for udp6 with src/dst addr and port as input set */
2903         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2904                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
2905                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2906                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2907                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2908                 if (ret)
2909                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2910                                     __func__, ret);
2911         }
2912
2913         /* Configure RSS for tcp4 with src/dst addr and port as input set */
2914         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2915                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
2916                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2917                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2918                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2919                 if (ret)
2920                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2921                                     __func__, ret);
2922         }
2923
2924         /* Configure RSS for tcp6 with src/dst addr and port as input set */
2925         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2926                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
2927                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2928                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2929                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2930                 if (ret)
2931                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2932                                     __func__, ret);
2933         }
2934
2935         /* Configure RSS for sctp4 with src/dst addr and port as input set */
2936         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2937                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
2938                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2939                 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
2940                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2941                 if (ret)
2942                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2943                                     __func__, ret);
2944         }
2945
2946         /* Configure RSS for sctp6 with src/dst addr and port as input set */
2947         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2948                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
2949                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2950                 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
2951                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2952                 if (ret)
2953                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2954                                     __func__, ret);
2955         }
2956
2957         if (rss_hf & ETH_RSS_IPV4) {
2958                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
2959                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2960                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2961                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2962                 if (ret)
2963                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2964                                     __func__, ret);
2965         }
2966
2967         if (rss_hf & ETH_RSS_IPV6) {
2968                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
2969                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2970                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2971                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2972                 if (ret)
2973                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2974                                     __func__, ret);
2975         }
2976
2977         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2978                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2979                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2980                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2981                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2982                 if (ret)
2983                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2984                                     __func__, ret);
2985         }
2986
2987         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2988                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2989                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2990                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2991                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2992                 if (ret)
2993                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
2994                                     __func__, ret);
2995         }
2996
2997         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2998                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
2999                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3000                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3001                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3002                 if (ret)
3003                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3004                                     __func__, ret);
3005         }
3006
3007         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3008                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3009                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3010                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3011                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3012                 if (ret)
3013                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3014                                     __func__, ret);
3015         }
3016
3017         if (rss_hf & ETH_RSS_FRAG_IPV4) {
3018                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_FRAG;
3019                 cfg.hash_flds = ICE_FLOW_HASH_IPV4 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_ID);
3020                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3021                 if (ret)
3022                         PMD_DRV_LOG(ERR, "%s IPV4_FRAG rss flow fail %d",
3023                                     __func__, ret);
3024         }
3025
3026         if (rss_hf & ETH_RSS_FRAG_IPV6) {
3027                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_FRAG;
3028                 cfg.hash_flds = ICE_FLOW_HASH_IPV6 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_ID);
3029                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3030                 if (ret)
3031                         PMD_DRV_LOG(ERR, "%s IPV6_FRAG rss flow fail %d",
3032                                     __func__, ret);
3033         }
3034
3035         pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3036 }
3037
3038 static void
3039 ice_get_default_rss_key(uint8_t *rss_key, uint32_t rss_key_size)
3040 {
3041         static struct ice_aqc_get_set_rss_keys default_key;
3042         static bool default_key_done;
3043         uint8_t *key = (uint8_t *)&default_key;
3044         size_t i;
3045
3046         if (rss_key_size > sizeof(default_key)) {
3047                 PMD_DRV_LOG(WARNING,
3048                             "requested size %u is larger than default %zu, "
3049                             "only %zu bytes are gotten for key\n",
3050                             rss_key_size, sizeof(default_key),
3051                             sizeof(default_key));
3052         }
3053
3054         if (!default_key_done) {
3055                 /* Calculate the default hash key */
3056                 for (i = 0; i < sizeof(default_key); i++)
3057                         key[i] = (uint8_t)rte_rand();
3058                 default_key_done = true;
3059         }
3060         rte_memcpy(rss_key, key, RTE_MIN(rss_key_size, sizeof(default_key)));
3061 }
3062
3063 static int ice_init_rss(struct ice_pf *pf)
3064 {
3065         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3066         struct ice_vsi *vsi = pf->main_vsi;
3067         struct rte_eth_dev_data *dev_data = pf->dev_data;
3068         struct ice_aq_get_set_rss_lut_params lut_params;
3069         struct rte_eth_rss_conf *rss_conf;
3070         struct ice_aqc_get_set_rss_keys key;
3071         uint16_t i, nb_q;
3072         int ret = 0;
3073         bool is_safe_mode = pf->adapter->is_safe_mode;
3074         uint32_t reg;
3075
3076         rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf;
3077         nb_q = dev_data->nb_rx_queues;
3078         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3079         vsi->rss_lut_size = pf->hash_lut_size;
3080
3081         if (nb_q == 0) {
3082                 PMD_DRV_LOG(WARNING,
3083                         "RSS is not supported as rx queues number is zero\n");
3084                 return 0;
3085         }
3086
3087         if (is_safe_mode) {
3088                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3089                 return 0;
3090         }
3091
3092         if (!vsi->rss_key) {
3093                 vsi->rss_key = rte_zmalloc(NULL,
3094                                            vsi->rss_key_size, 0);
3095                 if (vsi->rss_key == NULL) {
3096                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3097                         return -ENOMEM;
3098                 }
3099         }
3100         if (!vsi->rss_lut) {
3101                 vsi->rss_lut = rte_zmalloc(NULL,
3102                                            vsi->rss_lut_size, 0);
3103                 if (vsi->rss_lut == NULL) {
3104                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3105                         rte_free(vsi->rss_key);
3106                         vsi->rss_key = NULL;
3107                         return -ENOMEM;
3108                 }
3109         }
3110         /* configure RSS key */
3111         if (!rss_conf->rss_key)
3112                 ice_get_default_rss_key(vsi->rss_key, vsi->rss_key_size);
3113         else
3114                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3115                            RTE_MIN(rss_conf->rss_key_len,
3116                                    vsi->rss_key_size));
3117
3118         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3119         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3120         if (ret)
3121                 goto out;
3122
3123         /* init RSS LUT table */
3124         for (i = 0; i < vsi->rss_lut_size; i++)
3125                 vsi->rss_lut[i] = i % nb_q;
3126
3127         lut_params.vsi_handle = vsi->idx;
3128         lut_params.lut_size = vsi->rss_lut_size;
3129         lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3130         lut_params.lut = vsi->rss_lut;
3131         lut_params.global_lut_id = 0;
3132         ret = ice_aq_set_rss_lut(hw, &lut_params);
3133         if (ret)
3134                 goto out;
3135
3136         /* Enable registers for symmetric_toeplitz function. */
3137         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3138         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3139                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3140         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3141
3142         /* RSS hash configuration */
3143         ice_rss_hash_set(pf, rss_conf->rss_hf);
3144
3145         return 0;
3146 out:
3147         rte_free(vsi->rss_key);
3148         vsi->rss_key = NULL;
3149         rte_free(vsi->rss_lut);
3150         vsi->rss_lut = NULL;
3151         return -EINVAL;
3152 }
3153
3154 static int
3155 ice_dev_configure(struct rte_eth_dev *dev)
3156 {
3157         struct ice_adapter *ad =
3158                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3159         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3160         int ret;
3161
3162         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3163          * bulk allocation or vector Rx preconditions we will reset it.
3164          */
3165         ad->rx_bulk_alloc_allowed = true;
3166         ad->tx_simple_allowed = true;
3167
3168         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3169                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3170
3171         if (dev->data->nb_rx_queues) {
3172                 ret = ice_init_rss(pf);
3173                 if (ret) {
3174                         PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3175                         return ret;
3176                 }
3177         }
3178
3179         return 0;
3180 }
3181
3182 static void
3183 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3184                        int base_queue, int nb_queue)
3185 {
3186         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3187         uint32_t val, val_tx;
3188         int i;
3189
3190         for (i = 0; i < nb_queue; i++) {
3191                 /*do actual bind*/
3192                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3193                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3194                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3195                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3196
3197                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3198                             base_queue + i, msix_vect);
3199                 /* set ITR0 value */
3200                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3201                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3202                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3203         }
3204 }
3205
3206 void
3207 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3208 {
3209         struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3210         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3211         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3212         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3213         uint16_t msix_vect = vsi->msix_intr;
3214         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3215         uint16_t queue_idx = 0;
3216         int record = 0;
3217         int i;
3218
3219         /* clear Rx/Tx queue interrupt */
3220         for (i = 0; i < vsi->nb_used_qps; i++) {
3221                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3222                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3223         }
3224
3225         /* PF bind interrupt */
3226         if (rte_intr_dp_is_en(intr_handle)) {
3227                 queue_idx = 0;
3228                 record = 1;
3229         }
3230
3231         for (i = 0; i < vsi->nb_used_qps; i++) {
3232                 if (nb_msix <= 1) {
3233                         if (!rte_intr_allow_others(intr_handle))
3234                                 msix_vect = ICE_MISC_VEC_ID;
3235
3236                         /* uio mapping all queue to one msix_vect */
3237                         __vsi_queues_bind_intr(vsi, msix_vect,
3238                                                vsi->base_queue + i,
3239                                                vsi->nb_used_qps - i);
3240
3241                         for (; !!record && i < vsi->nb_used_qps; i++)
3242                                 intr_handle->intr_vec[queue_idx + i] =
3243                                         msix_vect;
3244                         break;
3245                 }
3246
3247                 /* vfio 1:1 queue/msix_vect mapping */
3248                 __vsi_queues_bind_intr(vsi, msix_vect,
3249                                        vsi->base_queue + i, 1);
3250
3251                 if (!!record)
3252                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3253
3254                 msix_vect++;
3255                 nb_msix--;
3256         }
3257 }
3258
3259 void
3260 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3261 {
3262         struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3263         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3264         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3265         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3266         uint16_t msix_intr, i;
3267
3268         if (rte_intr_allow_others(intr_handle))
3269                 for (i = 0; i < vsi->nb_used_qps; i++) {
3270                         msix_intr = vsi->msix_intr + i;
3271                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3272                                       GLINT_DYN_CTL_INTENA_M |
3273                                       GLINT_DYN_CTL_CLEARPBA_M |
3274                                       GLINT_DYN_CTL_ITR_INDX_M |
3275                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3276                 }
3277         else
3278                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3279                               GLINT_DYN_CTL_INTENA_M |
3280                               GLINT_DYN_CTL_CLEARPBA_M |
3281                               GLINT_DYN_CTL_ITR_INDX_M |
3282                               GLINT_DYN_CTL_WB_ON_ITR_M);
3283 }
3284
3285 static int
3286 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3287 {
3288         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3289         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3290         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3291         struct ice_vsi *vsi = pf->main_vsi;
3292         uint32_t intr_vector = 0;
3293
3294         rte_intr_disable(intr_handle);
3295
3296         /* check and configure queue intr-vector mapping */
3297         if ((rte_intr_cap_multiple(intr_handle) ||
3298              !RTE_ETH_DEV_SRIOV(dev).active) &&
3299             dev->data->dev_conf.intr_conf.rxq != 0) {
3300                 intr_vector = dev->data->nb_rx_queues;
3301                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3302                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3303                                     ICE_MAX_INTR_QUEUE_NUM);
3304                         return -ENOTSUP;
3305                 }
3306                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3307                         return -1;
3308         }
3309
3310         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3311                 intr_handle->intr_vec =
3312                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3313                             0);
3314                 if (!intr_handle->intr_vec) {
3315                         PMD_DRV_LOG(ERR,
3316                                     "Failed to allocate %d rx_queues intr_vec",
3317                                     dev->data->nb_rx_queues);
3318                         return -ENOMEM;
3319                 }
3320         }
3321
3322         /* Map queues with MSIX interrupt */
3323         vsi->nb_used_qps = dev->data->nb_rx_queues;
3324         ice_vsi_queues_bind_intr(vsi);
3325
3326         /* Enable interrupts for all the queues */
3327         ice_vsi_enable_queues_intr(vsi);
3328
3329         rte_intr_enable(intr_handle);
3330
3331         return 0;
3332 }
3333
3334 static void
3335 ice_get_init_link_status(struct rte_eth_dev *dev)
3336 {
3337         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3338         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3339         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3340         struct ice_link_status link_status;
3341         int ret;
3342
3343         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3344                                    &link_status, NULL);
3345         if (ret != ICE_SUCCESS) {
3346                 PMD_DRV_LOG(ERR, "Failed to get link info");
3347                 pf->init_link_up = false;
3348                 return;
3349         }
3350
3351         if (link_status.link_info & ICE_AQ_LINK_UP)
3352                 pf->init_link_up = true;
3353 }
3354
3355 static int
3356 ice_dev_start(struct rte_eth_dev *dev)
3357 {
3358         struct rte_eth_dev_data *data = dev->data;
3359         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3361         struct ice_vsi *vsi = pf->main_vsi;
3362         uint16_t nb_rxq = 0;
3363         uint16_t nb_txq, i;
3364         uint16_t max_frame_size;
3365         int mask, ret;
3366
3367         /* program Tx queues' context in hardware */
3368         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3369                 ret = ice_tx_queue_start(dev, nb_txq);
3370                 if (ret) {
3371                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3372                         goto tx_err;
3373                 }
3374         }
3375
3376         /* program Rx queues' context in hardware*/
3377         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3378                 ret = ice_rx_queue_start(dev, nb_rxq);
3379                 if (ret) {
3380                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3381                         goto rx_err;
3382                 }
3383         }
3384
3385         ice_set_rx_function(dev);
3386         ice_set_tx_function(dev);
3387
3388         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3389                         ETH_VLAN_EXTEND_MASK;
3390         ret = ice_vlan_offload_set(dev, mask);
3391         if (ret) {
3392                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3393                 goto rx_err;
3394         }
3395
3396         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3397         if (ice_rxq_intr_setup(dev))
3398                 return -EIO;
3399
3400         /* Enable receiving broadcast packets and transmitting packets */
3401         ret = ice_set_vsi_promisc(hw, vsi->idx,
3402                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3403                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3404                                   0);
3405         if (ret != ICE_SUCCESS)
3406                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3407
3408         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3409                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3410                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3411                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3412                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3413                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3414                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3415                                      NULL);
3416         if (ret != ICE_SUCCESS)
3417                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3418
3419         ice_get_init_link_status(dev);
3420
3421         ice_dev_set_link_up(dev);
3422
3423         /* Call get_link_info aq commond to enable/disable LSE */
3424         ice_link_update(dev, 0);
3425
3426         pf->adapter_stopped = false;
3427
3428         /* Set the max frame size to default value*/
3429         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3430                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3431                 ICE_FRAME_SIZE_MAX;
3432
3433         /* Set the max frame size to HW*/
3434         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3435
3436         return 0;
3437
3438         /* stop the started queues if failed to start all queues */
3439 rx_err:
3440         for (i = 0; i < nb_rxq; i++)
3441                 ice_rx_queue_stop(dev, i);
3442 tx_err:
3443         for (i = 0; i < nb_txq; i++)
3444                 ice_tx_queue_stop(dev, i);
3445
3446         return -EIO;
3447 }
3448
3449 static int
3450 ice_dev_reset(struct rte_eth_dev *dev)
3451 {
3452         int ret;
3453
3454         if (dev->data->sriov.active)
3455                 return -ENOTSUP;
3456
3457         ret = ice_dev_uninit(dev);
3458         if (ret) {
3459                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3460                 return -ENXIO;
3461         }
3462
3463         ret = ice_dev_init(dev);
3464         if (ret) {
3465                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3466                 return -ENXIO;
3467         }
3468
3469         return 0;
3470 }
3471
3472 static int
3473 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3474 {
3475         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3476         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3477         struct ice_vsi *vsi = pf->main_vsi;
3478         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3479         bool is_safe_mode = pf->adapter->is_safe_mode;
3480         u64 phy_type_low;
3481         u64 phy_type_high;
3482
3483         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3484         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3485         dev_info->max_rx_queues = vsi->nb_qps;
3486         dev_info->max_tx_queues = vsi->nb_qps;
3487         dev_info->max_mac_addrs = vsi->max_macaddrs;
3488         dev_info->max_vfs = pci_dev->max_vfs;
3489         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3490         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3491
3492         dev_info->rx_offload_capa =
3493                 DEV_RX_OFFLOAD_VLAN_STRIP |
3494                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3495                 DEV_RX_OFFLOAD_KEEP_CRC |
3496                 DEV_RX_OFFLOAD_SCATTER |
3497                 DEV_RX_OFFLOAD_VLAN_FILTER;
3498         dev_info->tx_offload_capa =
3499                 DEV_TX_OFFLOAD_VLAN_INSERT |
3500                 DEV_TX_OFFLOAD_TCP_TSO |
3501                 DEV_TX_OFFLOAD_MULTI_SEGS |
3502                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3503         dev_info->flow_type_rss_offloads = 0;
3504
3505         if (!is_safe_mode) {
3506                 dev_info->rx_offload_capa |=
3507                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3508                         DEV_RX_OFFLOAD_UDP_CKSUM |
3509                         DEV_RX_OFFLOAD_TCP_CKSUM |
3510                         DEV_RX_OFFLOAD_QINQ_STRIP |
3511                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3512                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3513                         DEV_RX_OFFLOAD_RSS_HASH;
3514                 dev_info->tx_offload_capa |=
3515                         DEV_TX_OFFLOAD_QINQ_INSERT |
3516                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3517                         DEV_TX_OFFLOAD_UDP_CKSUM |
3518                         DEV_TX_OFFLOAD_TCP_CKSUM |
3519                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3520                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3521                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3522                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3523         }
3524
3525         dev_info->rx_queue_offload_capa = 0;
3526         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3527
3528         dev_info->reta_size = pf->hash_lut_size;
3529         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3530
3531         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3532                 .rx_thresh = {
3533                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3534                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3535                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3536                 },
3537                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3538                 .rx_drop_en = 0,
3539                 .offloads = 0,
3540         };
3541
3542         dev_info->default_txconf = (struct rte_eth_txconf) {
3543                 .tx_thresh = {
3544                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3545                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3546                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3547                 },
3548                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3549                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3550                 .offloads = 0,
3551         };
3552
3553         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3554                 .nb_max = ICE_MAX_RING_DESC,
3555                 .nb_min = ICE_MIN_RING_DESC,
3556                 .nb_align = ICE_ALIGN_RING_DESC,
3557         };
3558
3559         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3560                 .nb_max = ICE_MAX_RING_DESC,
3561                 .nb_min = ICE_MIN_RING_DESC,
3562                 .nb_align = ICE_ALIGN_RING_DESC,
3563         };
3564
3565         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3566                                ETH_LINK_SPEED_100M |
3567                                ETH_LINK_SPEED_1G |
3568                                ETH_LINK_SPEED_2_5G |
3569                                ETH_LINK_SPEED_5G |
3570                                ETH_LINK_SPEED_10G |
3571                                ETH_LINK_SPEED_20G |
3572                                ETH_LINK_SPEED_25G;
3573
3574         phy_type_low = hw->port_info->phy.phy_type_low;
3575         phy_type_high = hw->port_info->phy.phy_type_high;
3576
3577         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3578                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3579
3580         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3581                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3582                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3583
3584         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3585         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3586
3587         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3588         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3589         dev_info->default_rxportconf.nb_queues = 1;
3590         dev_info->default_txportconf.nb_queues = 1;
3591         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3592         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3593
3594         return 0;
3595 }
3596
3597 static inline int
3598 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3599                             struct rte_eth_link *link)
3600 {
3601         struct rte_eth_link *dst = link;
3602         struct rte_eth_link *src = &dev->data->dev_link;
3603
3604         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3605                                 *(uint64_t *)src) == 0)
3606                 return -1;
3607
3608         return 0;
3609 }
3610
3611 static inline int
3612 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3613                              struct rte_eth_link *link)
3614 {
3615         struct rte_eth_link *dst = &dev->data->dev_link;
3616         struct rte_eth_link *src = link;
3617
3618         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3619                                 *(uint64_t *)src) == 0)
3620                 return -1;
3621
3622         return 0;
3623 }
3624
3625 static int
3626 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3627 {
3628 #define CHECK_INTERVAL 100  /* 100ms */
3629 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3630         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3631         struct ice_link_status link_status;
3632         struct rte_eth_link link, old;
3633         int status;
3634         unsigned int rep_cnt = MAX_REPEAT_TIME;
3635         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3636
3637         memset(&link, 0, sizeof(link));
3638         memset(&old, 0, sizeof(old));
3639         memset(&link_status, 0, sizeof(link_status));
3640         ice_atomic_read_link_status(dev, &old);
3641
3642         do {
3643                 /* Get link status information from hardware */
3644                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3645                                               &link_status, NULL);
3646                 if (status != ICE_SUCCESS) {
3647                         link.link_speed = ETH_SPEED_NUM_100M;
3648                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3649                         PMD_DRV_LOG(ERR, "Failed to get link info");
3650                         goto out;
3651                 }
3652
3653                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3654                 if (!wait_to_complete || link.link_status)
3655                         break;
3656
3657                 rte_delay_ms(CHECK_INTERVAL);
3658         } while (--rep_cnt);
3659
3660         if (!link.link_status)
3661                 goto out;
3662
3663         /* Full-duplex operation at all supported speeds */
3664         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3665
3666         /* Parse the link status */
3667         switch (link_status.link_speed) {
3668         case ICE_AQ_LINK_SPEED_10MB:
3669                 link.link_speed = ETH_SPEED_NUM_10M;
3670                 break;
3671         case ICE_AQ_LINK_SPEED_100MB:
3672                 link.link_speed = ETH_SPEED_NUM_100M;
3673                 break;
3674         case ICE_AQ_LINK_SPEED_1000MB:
3675                 link.link_speed = ETH_SPEED_NUM_1G;
3676                 break;
3677         case ICE_AQ_LINK_SPEED_2500MB:
3678                 link.link_speed = ETH_SPEED_NUM_2_5G;
3679                 break;
3680         case ICE_AQ_LINK_SPEED_5GB:
3681                 link.link_speed = ETH_SPEED_NUM_5G;
3682                 break;
3683         case ICE_AQ_LINK_SPEED_10GB:
3684                 link.link_speed = ETH_SPEED_NUM_10G;
3685                 break;
3686         case ICE_AQ_LINK_SPEED_20GB:
3687                 link.link_speed = ETH_SPEED_NUM_20G;
3688                 break;
3689         case ICE_AQ_LINK_SPEED_25GB:
3690                 link.link_speed = ETH_SPEED_NUM_25G;
3691                 break;
3692         case ICE_AQ_LINK_SPEED_40GB:
3693                 link.link_speed = ETH_SPEED_NUM_40G;
3694                 break;
3695         case ICE_AQ_LINK_SPEED_50GB:
3696                 link.link_speed = ETH_SPEED_NUM_50G;
3697                 break;
3698         case ICE_AQ_LINK_SPEED_100GB:
3699                 link.link_speed = ETH_SPEED_NUM_100G;
3700                 break;
3701         case ICE_AQ_LINK_SPEED_UNKNOWN:
3702                 PMD_DRV_LOG(ERR, "Unknown link speed");
3703                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3704                 break;
3705         default:
3706                 PMD_DRV_LOG(ERR, "None link speed");
3707                 link.link_speed = ETH_SPEED_NUM_NONE;
3708                 break;
3709         }
3710
3711         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3712                               ETH_LINK_SPEED_FIXED);
3713
3714 out:
3715         ice_atomic_write_link_status(dev, &link);
3716         if (link.link_status == old.link_status)
3717                 return -1;
3718
3719         return 0;
3720 }
3721
3722 /* Force the physical link state by getting the current PHY capabilities from
3723  * hardware and setting the PHY config based on the determined capabilities. If
3724  * link changes, link event will be triggered because both the Enable Automatic
3725  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3726  */
3727 static enum ice_status
3728 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3729 {
3730         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3731         struct ice_aqc_get_phy_caps_data *pcaps;
3732         struct ice_port_info *pi;
3733         enum ice_status status;
3734
3735         if (!hw || !hw->port_info)
3736                 return ICE_ERR_PARAM;
3737
3738         pi = hw->port_info;
3739
3740         pcaps = (struct ice_aqc_get_phy_caps_data *)
3741                 ice_malloc(hw, sizeof(*pcaps));
3742         if (!pcaps)
3743                 return ICE_ERR_NO_MEMORY;
3744
3745         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3746                                      pcaps, NULL);
3747         if (status)
3748                 goto out;
3749
3750         /* No change in link */
3751         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3752             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3753                 goto out;
3754
3755         cfg.phy_type_low = pcaps->phy_type_low;
3756         cfg.phy_type_high = pcaps->phy_type_high;
3757         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3758         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3759         cfg.eee_cap = pcaps->eee_cap;
3760         cfg.eeer_value = pcaps->eeer_value;
3761         cfg.link_fec_opt = pcaps->link_fec_options;
3762         if (link_up)
3763                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3764         else
3765                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3766
3767         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3768
3769 out:
3770         ice_free(hw, pcaps);
3771         return status;
3772 }
3773
3774 static int
3775 ice_dev_set_link_up(struct rte_eth_dev *dev)
3776 {
3777         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3778
3779         return ice_force_phys_link_state(hw, true);
3780 }
3781
3782 static int
3783 ice_dev_set_link_down(struct rte_eth_dev *dev)
3784 {
3785         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786
3787         return ice_force_phys_link_state(hw, false);
3788 }
3789
3790 static int
3791 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3792 {
3793         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3794         struct rte_eth_dev_data *dev_data = pf->dev_data;
3795         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3796
3797         /* check if mtu is within the allowed range */
3798         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3799                 return -EINVAL;
3800
3801         /* mtu setting is forbidden if port is start */
3802         if (dev_data->dev_started) {
3803                 PMD_DRV_LOG(ERR,
3804                             "port %d must be stopped before configuration",
3805                             dev_data->port_id);
3806                 return -EBUSY;
3807         }
3808
3809         if (frame_size > ICE_ETH_MAX_LEN)
3810                 dev_data->dev_conf.rxmode.offloads |=
3811                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3812         else
3813                 dev_data->dev_conf.rxmode.offloads &=
3814                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3815
3816         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3817
3818         return 0;
3819 }
3820
3821 static int ice_macaddr_set(struct rte_eth_dev *dev,
3822                            struct rte_ether_addr *mac_addr)
3823 {
3824         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3825         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3826         struct ice_vsi *vsi = pf->main_vsi;
3827         struct ice_mac_filter *f;
3828         uint8_t flags = 0;
3829         int ret;
3830
3831         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3832                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3833                 return -EINVAL;
3834         }
3835
3836         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3837                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3838                         break;
3839         }
3840
3841         if (!f) {
3842                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3843                 return -EIO;
3844         }
3845
3846         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3847         if (ret != ICE_SUCCESS) {
3848                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3849                 return -EIO;
3850         }
3851         ret = ice_add_mac_filter(vsi, mac_addr);
3852         if (ret != ICE_SUCCESS) {
3853                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3854                 return -EIO;
3855         }
3856         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3857
3858         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3859         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3860         if (ret != ICE_SUCCESS)
3861                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3862
3863         return 0;
3864 }
3865
3866 /* Add a MAC address, and update filters */
3867 static int
3868 ice_macaddr_add(struct rte_eth_dev *dev,
3869                 struct rte_ether_addr *mac_addr,
3870                 __rte_unused uint32_t index,
3871                 __rte_unused uint32_t pool)
3872 {
3873         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3874         struct ice_vsi *vsi = pf->main_vsi;
3875         int ret;
3876
3877         ret = ice_add_mac_filter(vsi, mac_addr);
3878         if (ret != ICE_SUCCESS) {
3879                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3880                 return -EINVAL;
3881         }
3882
3883         return ICE_SUCCESS;
3884 }
3885
3886 /* Remove a MAC address, and update filters */
3887 static void
3888 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3889 {
3890         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3891         struct ice_vsi *vsi = pf->main_vsi;
3892         struct rte_eth_dev_data *data = dev->data;
3893         struct rte_ether_addr *macaddr;
3894         int ret;
3895
3896         macaddr = &data->mac_addrs[index];
3897         ret = ice_remove_mac_filter(vsi, macaddr);
3898         if (ret) {
3899                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3900                 return;
3901         }
3902 }
3903
3904 static int
3905 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3906 {
3907         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3908         struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
3909         struct ice_vsi *vsi = pf->main_vsi;
3910         int ret;
3911
3912         PMD_INIT_FUNC_TRACE();
3913
3914         /**
3915          * Vlan 0 is the generic filter for untagged packets
3916          * and can't be removed or added by user.
3917          */
3918         if (vlan_id == 0)
3919                 return 0;
3920
3921         if (on) {
3922                 ret = ice_add_vlan_filter(vsi, &vlan);
3923                 if (ret < 0) {
3924                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3925                         return -EINVAL;
3926                 }
3927         } else {
3928                 ret = ice_remove_vlan_filter(vsi, &vlan);
3929                 if (ret < 0) {
3930                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3931                         return -EINVAL;
3932                 }
3933         }
3934
3935         return 0;
3936 }
3937
3938 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
3939  * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
3940  * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
3941  * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
3942  *
3943  * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
3944  * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
3945  * traffic in SVM, since the VLAN TPID isn't part of filtering.
3946  *
3947  * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
3948  * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
3949  * part of filtering.
3950  */
3951 static int
3952 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
3953 {
3954         struct ice_vlan vlan;
3955         int err;
3956
3957         vlan = ICE_VLAN(0, 0);
3958         err = ice_add_vlan_filter(vsi, &vlan);
3959         if (err) {
3960                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
3961                 return err;
3962         }
3963
3964         /* in SVM both VLAN 0 filters are identical */
3965         if (!ice_is_dvm_ena(&vsi->adapter->hw))
3966                 return 0;
3967
3968         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3969         err = ice_add_vlan_filter(vsi, &vlan);
3970         if (err) {
3971                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
3972                 return err;
3973         }
3974
3975         return 0;
3976 }
3977
3978 /*
3979  * Delete the VLAN 0 filters in the same manner that they were added in
3980  * ice_vsi_add_vlan_zero.
3981  */
3982 static int
3983 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
3984 {
3985         struct ice_vlan vlan;
3986         int err;
3987
3988         vlan = ICE_VLAN(0, 0);
3989         err = ice_remove_vlan_filter(vsi, &vlan);
3990         if (err) {
3991                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
3992                 return err;
3993         }
3994
3995         /* in SVM both VLAN 0 filters are identical */
3996         if (!ice_is_dvm_ena(&vsi->adapter->hw))
3997                 return 0;
3998
3999         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4000         err = ice_remove_vlan_filter(vsi, &vlan);
4001         if (err) {
4002                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
4003                 return err;
4004         }
4005
4006         return 0;
4007 }
4008
4009 /* Configure vlan filter on or off */
4010 static int
4011 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4012 {
4013         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4014         struct ice_vsi_ctx ctxt;
4015         uint8_t sw_flags2;
4016         int ret = 0;
4017
4018         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4019
4020         if (on)
4021                 vsi->info.sw_flags2 |= sw_flags2;
4022         else
4023                 vsi->info.sw_flags2 &= ~sw_flags2;
4024
4025         vsi->info.sw_id = hw->port_info->sw_id;
4026         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4027         ctxt.info.valid_sections =
4028                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4029                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
4030         ctxt.vsi_num = vsi->vsi_id;
4031
4032         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4033         if (ret) {
4034                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4035                             on ? "enable" : "disable");
4036                 return -EINVAL;
4037         } else {
4038                 vsi->info.valid_sections |=
4039                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4040                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
4041         }
4042
4043         /* consist with other drivers, allow untagged packet when vlan filter on */
4044         if (on)
4045                 ret = ice_vsi_add_vlan_zero(vsi);
4046         else
4047                 ret = ice_vsi_del_vlan_zero(vsi);
4048
4049         return 0;
4050 }
4051
4052 /* Manage VLAN stripping for the VSI for Rx */
4053 static int
4054 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4055 {
4056         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4057         struct ice_vsi_ctx ctxt;
4058         enum ice_status status;
4059         int err = 0;
4060
4061         /* do not allow modifying VLAN stripping when a port VLAN is configured
4062          * on this VSI
4063          */
4064         if (vsi->info.port_based_inner_vlan)
4065                 return 0;
4066
4067         memset(&ctxt, 0, sizeof(ctxt));
4068
4069         if (ena)
4070                 /* Strip VLAN tag from Rx packet and put it in the desc */
4071                 ctxt.info.inner_vlan_flags =
4072                                         ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4073         else
4074                 /* Disable stripping. Leave tag in packet */
4075                 ctxt.info.inner_vlan_flags =
4076                                         ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4077
4078         /* Allow all packets untagged/tagged */
4079         ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4080
4081         ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4082
4083         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4084         if (status) {
4085                 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4086                             ena ? "enable" : "disable");
4087                 err = -EIO;
4088         } else {
4089                 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4090         }
4091
4092         return err;
4093 }
4094
4095 static int
4096 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4097 {
4098         return ice_vsi_manage_vlan_stripping(vsi, true);
4099 }
4100
4101 static int
4102 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4103 {
4104         return ice_vsi_manage_vlan_stripping(vsi, false);
4105 }
4106
4107 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4108 {
4109         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4110         struct ice_vsi_ctx ctxt;
4111         enum ice_status status;
4112         int err = 0;
4113
4114         /* do not allow modifying VLAN stripping when a port VLAN is configured
4115          * on this VSI
4116          */
4117         if (vsi->info.port_based_outer_vlan)
4118                 return 0;
4119
4120         memset(&ctxt, 0, sizeof(ctxt));
4121
4122         ctxt.info.valid_sections =
4123                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4124         /* clear current outer VLAN strip settings */
4125         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4126                 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4127         ctxt.info.outer_vlan_flags |=
4128                 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4129                  ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4130                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4131                  ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4132
4133         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4134         if (status) {
4135                 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4136                 err = -EIO;
4137         } else {
4138                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4139         }
4140
4141         return err;
4142 }
4143
4144 static int
4145 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4146 {
4147         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4148         struct ice_vsi_ctx ctxt;
4149         enum ice_status status;
4150         int err = 0;
4151
4152         if (vsi->info.port_based_outer_vlan)
4153                 return 0;
4154
4155         memset(&ctxt, 0, sizeof(ctxt));
4156
4157         ctxt.info.valid_sections =
4158                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4159         /* clear current outer VLAN strip settings */
4160         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4161                 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4162         ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4163                 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4164
4165         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4166         if (status) {
4167                 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4168                 err = -EIO;
4169         } else {
4170                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4171         }
4172
4173         return err;
4174 }
4175
4176 static int
4177 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4178 {
4179         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4180         int ret;
4181
4182         if (ice_is_dvm_ena(hw)) {
4183                 if (ena)
4184                         ret = ice_vsi_ena_outer_stripping(vsi);
4185                 else
4186                         ret = ice_vsi_dis_outer_stripping(vsi);
4187         } else {
4188                 if (ena)
4189                         ret = ice_vsi_ena_inner_stripping(vsi);
4190                 else
4191                         ret = ice_vsi_dis_inner_stripping(vsi);
4192         }
4193
4194         return ret;
4195 }
4196
4197 static int
4198 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4199 {
4200         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4201         struct ice_vsi *vsi = pf->main_vsi;
4202         struct rte_eth_rxmode *rxmode;
4203
4204         rxmode = &dev->data->dev_conf.rxmode;
4205         if (mask & ETH_VLAN_FILTER_MASK) {
4206                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4207                         ice_vsi_config_vlan_filter(vsi, true);
4208                 else
4209                         ice_vsi_config_vlan_filter(vsi, false);
4210         }
4211
4212         if (mask & ETH_VLAN_STRIP_MASK) {
4213                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4214                         ice_vsi_config_vlan_stripping(vsi, true);
4215                 else
4216                         ice_vsi_config_vlan_stripping(vsi, false);
4217         }
4218
4219         return 0;
4220 }
4221
4222 static int
4223 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4224 {
4225         struct ice_aq_get_set_rss_lut_params lut_params;
4226         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4227         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4228         int ret;
4229
4230         if (!lut)
4231                 return -EINVAL;
4232
4233         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4234                 lut_params.vsi_handle = vsi->idx;
4235                 lut_params.lut_size = lut_size;
4236                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4237                 lut_params.lut = lut;
4238                 lut_params.global_lut_id = 0;
4239                 ret = ice_aq_get_rss_lut(hw, &lut_params);
4240                 if (ret) {
4241                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4242                         return -EINVAL;
4243                 }
4244         } else {
4245                 uint64_t *lut_dw = (uint64_t *)lut;
4246                 uint16_t i, lut_size_dw = lut_size / 4;
4247
4248                 for (i = 0; i < lut_size_dw; i++)
4249                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4250         }
4251
4252         return 0;
4253 }
4254
4255 static int
4256 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4257 {
4258         struct ice_aq_get_set_rss_lut_params lut_params;
4259         struct ice_pf *pf;
4260         struct ice_hw *hw;
4261         int ret;
4262
4263         if (!vsi || !lut)
4264                 return -EINVAL;
4265
4266         pf = ICE_VSI_TO_PF(vsi);
4267         hw = ICE_VSI_TO_HW(vsi);
4268
4269         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4270                 lut_params.vsi_handle = vsi->idx;
4271                 lut_params.lut_size = lut_size;
4272                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4273                 lut_params.lut = lut;
4274                 lut_params.global_lut_id = 0;
4275                 ret = ice_aq_set_rss_lut(hw, &lut_params);
4276                 if (ret) {
4277                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4278                         return -EINVAL;
4279                 }
4280         } else {
4281                 uint64_t *lut_dw = (uint64_t *)lut;
4282                 uint16_t i, lut_size_dw = lut_size / 4;
4283
4284                 for (i = 0; i < lut_size_dw; i++)
4285                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4286
4287                 ice_flush(hw);
4288         }
4289
4290         return 0;
4291 }
4292
4293 static int
4294 ice_rss_reta_update(struct rte_eth_dev *dev,
4295                     struct rte_eth_rss_reta_entry64 *reta_conf,
4296                     uint16_t reta_size)
4297 {
4298         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4299         uint16_t i, lut_size = pf->hash_lut_size;
4300         uint16_t idx, shift;
4301         uint8_t *lut;
4302         int ret;
4303
4304         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4305             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4306             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4307                 PMD_DRV_LOG(ERR,
4308                             "The size of hash lookup table configured (%d)"
4309                             "doesn't match the number hardware can "
4310                             "supported (128, 512, 2048)",
4311                             reta_size);
4312                 return -EINVAL;
4313         }
4314
4315         /* It MUST use the current LUT size to get the RSS lookup table,
4316          * otherwise if will fail with -100 error code.
4317          */
4318         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4319         if (!lut) {
4320                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4321                 return -ENOMEM;
4322         }
4323         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4324         if (ret)
4325                 goto out;
4326
4327         for (i = 0; i < reta_size; i++) {
4328                 idx = i / RTE_RETA_GROUP_SIZE;
4329                 shift = i % RTE_RETA_GROUP_SIZE;
4330                 if (reta_conf[idx].mask & (1ULL << shift))
4331                         lut[i] = reta_conf[idx].reta[shift];
4332         }
4333         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4334         if (ret == 0 && lut_size != reta_size) {
4335                 PMD_DRV_LOG(INFO,
4336                             "The size of hash lookup table is changed from (%d) to (%d)",
4337                             lut_size, reta_size);
4338                 pf->hash_lut_size = reta_size;
4339         }
4340
4341 out:
4342         rte_free(lut);
4343
4344         return ret;
4345 }
4346
4347 static int
4348 ice_rss_reta_query(struct rte_eth_dev *dev,
4349                    struct rte_eth_rss_reta_entry64 *reta_conf,
4350                    uint16_t reta_size)
4351 {
4352         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4353         uint16_t i, lut_size = pf->hash_lut_size;
4354         uint16_t idx, shift;
4355         uint8_t *lut;
4356         int ret;
4357
4358         if (reta_size != lut_size) {
4359                 PMD_DRV_LOG(ERR,
4360                             "The size of hash lookup table configured (%d)"
4361                             "doesn't match the number hardware can "
4362                             "supported (%d)",
4363                             reta_size, lut_size);
4364                 return -EINVAL;
4365         }
4366
4367         lut = rte_zmalloc(NULL, reta_size, 0);
4368         if (!lut) {
4369                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4370                 return -ENOMEM;
4371         }
4372
4373         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4374         if (ret)
4375                 goto out;
4376
4377         for (i = 0; i < reta_size; i++) {
4378                 idx = i / RTE_RETA_GROUP_SIZE;
4379                 shift = i % RTE_RETA_GROUP_SIZE;
4380                 if (reta_conf[idx].mask & (1ULL << shift))
4381                         reta_conf[idx].reta[shift] = lut[i];
4382         }
4383
4384 out:
4385         rte_free(lut);
4386
4387         return ret;
4388 }
4389
4390 static int
4391 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4392 {
4393         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4394         int ret = 0;
4395
4396         if (!key || key_len == 0) {
4397                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4398                 return 0;
4399         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4400                    sizeof(uint32_t)) {
4401                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4402                 return -EINVAL;
4403         }
4404
4405         struct ice_aqc_get_set_rss_keys *key_dw =
4406                 (struct ice_aqc_get_set_rss_keys *)key;
4407
4408         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4409         if (ret) {
4410                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4411                 ret = -EINVAL;
4412         }
4413
4414         return ret;
4415 }
4416
4417 static int
4418 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4419 {
4420         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4421         int ret;
4422
4423         if (!key || !key_len)
4424                 return -EINVAL;
4425
4426         ret = ice_aq_get_rss_key
4427                 (hw, vsi->idx,
4428                  (struct ice_aqc_get_set_rss_keys *)key);
4429         if (ret) {
4430                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4431                 return -EINVAL;
4432         }
4433         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4434
4435         return 0;
4436 }
4437
4438 static int
4439 ice_rss_hash_update(struct rte_eth_dev *dev,
4440                     struct rte_eth_rss_conf *rss_conf)
4441 {
4442         enum ice_status status = ICE_SUCCESS;
4443         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4444         struct ice_vsi *vsi = pf->main_vsi;
4445
4446         /* set hash key */
4447         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4448         if (status)
4449                 return status;
4450
4451         if (rss_conf->rss_hf == 0) {
4452                 pf->rss_hf = 0;
4453                 return 0;
4454         }
4455
4456         /* RSS hash configuration */
4457         ice_rss_hash_set(pf, rss_conf->rss_hf);
4458
4459         return 0;
4460 }
4461
4462 static int
4463 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4464                       struct rte_eth_rss_conf *rss_conf)
4465 {
4466         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4467         struct ice_vsi *vsi = pf->main_vsi;
4468
4469         ice_get_rss_key(vsi, rss_conf->rss_key,
4470                         &rss_conf->rss_key_len);
4471
4472         rss_conf->rss_hf = pf->rss_hf;
4473         return 0;
4474 }
4475
4476 static int
4477 ice_promisc_enable(struct rte_eth_dev *dev)
4478 {
4479         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4480         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481         struct ice_vsi *vsi = pf->main_vsi;
4482         enum ice_status status;
4483         uint8_t pmask;
4484         int ret = 0;
4485
4486         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4487                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4488
4489         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4490         switch (status) {
4491         case ICE_ERR_ALREADY_EXISTS:
4492                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4493         case ICE_SUCCESS:
4494                 break;
4495         default:
4496                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4497                 ret = -EAGAIN;
4498         }
4499
4500         return ret;
4501 }
4502
4503 static int
4504 ice_promisc_disable(struct rte_eth_dev *dev)
4505 {
4506         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4507         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4508         struct ice_vsi *vsi = pf->main_vsi;
4509         enum ice_status status;
4510         uint8_t pmask;
4511         int ret = 0;
4512
4513         if (dev->data->all_multicast == 1)
4514                 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX;
4515         else
4516                 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4517                         ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4518
4519         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4520         if (status != ICE_SUCCESS) {
4521                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4522                 ret = -EAGAIN;
4523         }
4524
4525         return ret;
4526 }
4527
4528 static int
4529 ice_allmulti_enable(struct rte_eth_dev *dev)
4530 {
4531         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4532         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4533         struct ice_vsi *vsi = pf->main_vsi;
4534         enum ice_status status;
4535         uint8_t pmask;
4536         int ret = 0;
4537
4538         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4539
4540         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4541
4542         switch (status) {
4543         case ICE_ERR_ALREADY_EXISTS:
4544                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4545         case ICE_SUCCESS:
4546                 break;
4547         default:
4548                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4549                 ret = -EAGAIN;
4550         }
4551
4552         return ret;
4553 }
4554
4555 static int
4556 ice_allmulti_disable(struct rte_eth_dev *dev)
4557 {
4558         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4559         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4560         struct ice_vsi *vsi = pf->main_vsi;
4561         enum ice_status status;
4562         uint8_t pmask;
4563         int ret = 0;
4564
4565         if (dev->data->promiscuous == 1)
4566                 return 0; /* must remain in all_multicast mode */
4567
4568         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4569
4570         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4571         if (status != ICE_SUCCESS) {
4572                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4573                 ret = -EAGAIN;
4574         }
4575
4576         return ret;
4577 }
4578
4579 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4580                                     uint16_t queue_id)
4581 {
4582         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4583         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4584         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4585         uint32_t val;
4586         uint16_t msix_intr;
4587
4588         msix_intr = intr_handle->intr_vec[queue_id];
4589
4590         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4591               GLINT_DYN_CTL_ITR_INDX_M;
4592         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4593
4594         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4595         rte_intr_ack(&pci_dev->intr_handle);
4596
4597         return 0;
4598 }
4599
4600 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4601                                      uint16_t queue_id)
4602 {
4603         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4604         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4605         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4606         uint16_t msix_intr;
4607
4608         msix_intr = intr_handle->intr_vec[queue_id];
4609
4610         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4611
4612         return 0;
4613 }
4614
4615 static int
4616 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4617 {
4618         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4619         u8 ver, patch;
4620         u16 build;
4621         int ret;
4622
4623         ver = hw->flash.orom.major;
4624         patch = hw->flash.orom.patch;
4625         build = hw->flash.orom.build;
4626
4627         ret = snprintf(fw_version, fw_size,
4628                         "%x.%02x 0x%08x %d.%d.%d",
4629                         hw->flash.nvm.major,
4630                         hw->flash.nvm.minor,
4631                         hw->flash.nvm.eetrack,
4632                         ver, build, patch);
4633         if (ret < 0)
4634                 return -EINVAL;
4635
4636         /* add the size of '\0' */
4637         ret += 1;
4638         if (fw_size < (size_t)ret)
4639                 return ret;
4640         else
4641                 return 0;
4642 }
4643
4644 static int
4645 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4646 {
4647         struct ice_hw *hw;
4648         struct ice_vsi_ctx ctxt;
4649         uint8_t vlan_flags = 0;
4650         int ret;
4651
4652         if (!vsi || !info) {
4653                 PMD_DRV_LOG(ERR, "invalid parameters");
4654                 return -EINVAL;
4655         }
4656
4657         if (info->on) {
4658                 vsi->info.port_based_inner_vlan = info->config.pvid;
4659                 /**
4660                  * If insert pvid is enabled, only tagged pkts are
4661                  * allowed to be sent out.
4662                  */
4663                 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4664                              ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4665         } else {
4666                 vsi->info.port_based_inner_vlan = 0;
4667                 if (info->config.reject.tagged == 0)
4668                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4669
4670                 if (info->config.reject.untagged == 0)
4671                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4672         }
4673         vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4674                                   ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4675         vsi->info.inner_vlan_flags |= vlan_flags;
4676         memset(&ctxt, 0, sizeof(ctxt));
4677         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4678         ctxt.info.valid_sections =
4679                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4680         ctxt.vsi_num = vsi->vsi_id;
4681
4682         hw = ICE_VSI_TO_HW(vsi);
4683         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4684         if (ret != ICE_SUCCESS) {
4685                 PMD_DRV_LOG(ERR,
4686                             "update VSI for VLAN insert failed, err %d",
4687                             ret);
4688                 return -EINVAL;
4689         }
4690
4691         vsi->info.valid_sections |=
4692                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4693
4694         return ret;
4695 }
4696
4697 static int
4698 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4699 {
4700         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4701         struct ice_vsi *vsi = pf->main_vsi;
4702         struct rte_eth_dev_data *data = pf->dev_data;
4703         struct ice_vsi_vlan_pvid_info info;
4704         int ret;
4705
4706         memset(&info, 0, sizeof(info));
4707         info.on = on;
4708         if (info.on) {
4709                 info.config.pvid = pvid;
4710         } else {
4711                 info.config.reject.tagged =
4712                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4713                 info.config.reject.untagged =
4714                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4715         }
4716
4717         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4718         if (ret < 0) {
4719                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4720                 return -EINVAL;
4721         }
4722
4723         return 0;
4724 }
4725
4726 static int
4727 ice_get_eeprom_length(struct rte_eth_dev *dev)
4728 {
4729         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4730
4731         return hw->flash.flash_size;
4732 }
4733
4734 static int
4735 ice_get_eeprom(struct rte_eth_dev *dev,
4736                struct rte_dev_eeprom_info *eeprom)
4737 {
4738         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4739         enum ice_status status = ICE_SUCCESS;
4740         uint8_t *data = eeprom->data;
4741
4742         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4743
4744         status = ice_acquire_nvm(hw, ICE_RES_READ);
4745         if (status) {
4746                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4747                 return -EIO;
4748         }
4749
4750         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4751                                    data, false);
4752
4753         ice_release_nvm(hw);
4754
4755         if (status) {
4756                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4757                 return -EIO;
4758         }
4759
4760         return 0;
4761 }
4762
4763 static void
4764 ice_stat_update_32(struct ice_hw *hw,
4765                    uint32_t reg,
4766                    bool offset_loaded,
4767                    uint64_t *offset,
4768                    uint64_t *stat)
4769 {
4770         uint64_t new_data;
4771
4772         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4773         if (!offset_loaded)
4774                 *offset = new_data;
4775
4776         if (new_data >= *offset)
4777                 *stat = (uint64_t)(new_data - *offset);
4778         else
4779                 *stat = (uint64_t)((new_data +
4780                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4781                                    - *offset);
4782 }
4783
4784 static void
4785 ice_stat_update_40(struct ice_hw *hw,
4786                    uint32_t hireg,
4787                    uint32_t loreg,
4788                    bool offset_loaded,
4789                    uint64_t *offset,
4790                    uint64_t *stat)
4791 {
4792         uint64_t new_data;
4793
4794         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4795         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4796                     ICE_32_BIT_WIDTH;
4797
4798         if (!offset_loaded)
4799                 *offset = new_data;
4800
4801         if (new_data >= *offset)
4802                 *stat = new_data - *offset;
4803         else
4804                 *stat = (uint64_t)((new_data +
4805                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4806                                    *offset);
4807
4808         *stat &= ICE_40_BIT_MASK;
4809 }
4810
4811 /* Get all the statistics of a VSI */
4812 static void
4813 ice_update_vsi_stats(struct ice_vsi *vsi)
4814 {
4815         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4816         struct ice_eth_stats *nes = &vsi->eth_stats;
4817         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4818         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4819
4820         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4821                            vsi->offset_loaded, &oes->rx_bytes,
4822                            &nes->rx_bytes);
4823         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4824                            vsi->offset_loaded, &oes->rx_unicast,
4825                            &nes->rx_unicast);
4826         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4827                            vsi->offset_loaded, &oes->rx_multicast,
4828                            &nes->rx_multicast);
4829         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4830                            vsi->offset_loaded, &oes->rx_broadcast,
4831                            &nes->rx_broadcast);
4832         /* enlarge the limitation when rx_bytes overflowed */
4833         if (vsi->offset_loaded) {
4834                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4835                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4836                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4837         }
4838         vsi->old_rx_bytes = nes->rx_bytes;
4839         /* exclude CRC bytes */
4840         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4841                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4842
4843         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4844                            &oes->rx_discards, &nes->rx_discards);
4845         /* GLV_REPC not supported */
4846         /* GLV_RMPC not supported */
4847         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4848                            &oes->rx_unknown_protocol,
4849                            &nes->rx_unknown_protocol);
4850         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4851                            vsi->offset_loaded, &oes->tx_bytes,
4852                            &nes->tx_bytes);
4853         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4854                            vsi->offset_loaded, &oes->tx_unicast,
4855                            &nes->tx_unicast);
4856         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4857                            vsi->offset_loaded, &oes->tx_multicast,
4858                            &nes->tx_multicast);
4859         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4860                            vsi->offset_loaded,  &oes->tx_broadcast,
4861                            &nes->tx_broadcast);
4862         /* GLV_TDPC not supported */
4863         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4864                            &oes->tx_errors, &nes->tx_errors);
4865         /* enlarge the limitation when tx_bytes overflowed */
4866         if (vsi->offset_loaded) {
4867                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4868                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4869                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4870         }
4871         vsi->old_tx_bytes = nes->tx_bytes;
4872         vsi->offset_loaded = true;
4873
4874         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4875                     vsi->vsi_id);
4876         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4877         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4878         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4879         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4880         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4881         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4882                     nes->rx_unknown_protocol);
4883         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4884         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4885         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4886         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4887         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4888         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4889         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4890                     vsi->vsi_id);
4891 }
4892
4893 static void
4894 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4895 {
4896         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4897         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4898
4899         /* Get statistics of struct ice_eth_stats */
4900         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4901                            GLPRT_GORCL(hw->port_info->lport),
4902                            pf->offset_loaded, &os->eth.rx_bytes,
4903                            &ns->eth.rx_bytes);
4904         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4905                            GLPRT_UPRCL(hw->port_info->lport),
4906                            pf->offset_loaded, &os->eth.rx_unicast,
4907                            &ns->eth.rx_unicast);
4908         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4909                            GLPRT_MPRCL(hw->port_info->lport),
4910                            pf->offset_loaded, &os->eth.rx_multicast,
4911                            &ns->eth.rx_multicast);
4912         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4913                            GLPRT_BPRCL(hw->port_info->lport),
4914                            pf->offset_loaded, &os->eth.rx_broadcast,
4915                            &ns->eth.rx_broadcast);
4916         ice_stat_update_32(hw, PRTRPB_RDPC,
4917                            pf->offset_loaded, &os->eth.rx_discards,
4918                            &ns->eth.rx_discards);
4919         /* enlarge the limitation when rx_bytes overflowed */
4920         if (pf->offset_loaded) {
4921                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4922                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4923                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4924         }
4925         pf->old_rx_bytes = ns->eth.rx_bytes;
4926
4927         /* Workaround: CRC size should not be included in byte statistics,
4928          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4929          * packet.
4930          */
4931         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4932                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4933
4934         /* GLPRT_REPC not supported */
4935         /* GLPRT_RMPC not supported */
4936         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4937                            pf->offset_loaded,
4938                            &os->eth.rx_unknown_protocol,
4939                            &ns->eth.rx_unknown_protocol);
4940         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4941                            GLPRT_GOTCL(hw->port_info->lport),
4942                            pf->offset_loaded, &os->eth.tx_bytes,
4943                            &ns->eth.tx_bytes);
4944         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4945                            GLPRT_UPTCL(hw->port_info->lport),
4946                            pf->offset_loaded, &os->eth.tx_unicast,
4947                            &ns->eth.tx_unicast);
4948         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4949                            GLPRT_MPTCL(hw->port_info->lport),
4950                            pf->offset_loaded, &os->eth.tx_multicast,
4951                            &ns->eth.tx_multicast);
4952         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4953                            GLPRT_BPTCL(hw->port_info->lport),
4954                            pf->offset_loaded, &os->eth.tx_broadcast,
4955                            &ns->eth.tx_broadcast);
4956         /* enlarge the limitation when tx_bytes overflowed */
4957         if (pf->offset_loaded) {
4958                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4959                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4960                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4961         }
4962         pf->old_tx_bytes = ns->eth.tx_bytes;
4963         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4964                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4965
4966         /* GLPRT_TEPC not supported */
4967
4968         /* additional port specific stats */
4969         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4970                            pf->offset_loaded, &os->tx_dropped_link_down,
4971                            &ns->tx_dropped_link_down);
4972         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4973                            pf->offset_loaded, &os->crc_errors,
4974                            &ns->crc_errors);
4975         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4976                            pf->offset_loaded, &os->illegal_bytes,
4977                            &ns->illegal_bytes);
4978         /* GLPRT_ERRBC not supported */
4979         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4980                            pf->offset_loaded, &os->mac_local_faults,
4981                            &ns->mac_local_faults);
4982         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4983                            pf->offset_loaded, &os->mac_remote_faults,
4984                            &ns->mac_remote_faults);
4985
4986         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4987                            pf->offset_loaded, &os->rx_len_errors,
4988                            &ns->rx_len_errors);
4989
4990         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4991                            pf->offset_loaded, &os->link_xon_rx,
4992                            &ns->link_xon_rx);
4993         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4994                            pf->offset_loaded, &os->link_xoff_rx,
4995                            &ns->link_xoff_rx);
4996         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4997                            pf->offset_loaded, &os->link_xon_tx,
4998                            &ns->link_xon_tx);
4999         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
5000                            pf->offset_loaded, &os->link_xoff_tx,
5001                            &ns->link_xoff_tx);
5002         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
5003                            GLPRT_PRC64L(hw->port_info->lport),
5004                            pf->offset_loaded, &os->rx_size_64,
5005                            &ns->rx_size_64);
5006         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
5007                            GLPRT_PRC127L(hw->port_info->lport),
5008                            pf->offset_loaded, &os->rx_size_127,
5009                            &ns->rx_size_127);
5010         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
5011                            GLPRT_PRC255L(hw->port_info->lport),
5012                            pf->offset_loaded, &os->rx_size_255,
5013                            &ns->rx_size_255);
5014         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
5015                            GLPRT_PRC511L(hw->port_info->lport),
5016                            pf->offset_loaded, &os->rx_size_511,
5017                            &ns->rx_size_511);
5018         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
5019                            GLPRT_PRC1023L(hw->port_info->lport),
5020                            pf->offset_loaded, &os->rx_size_1023,
5021                            &ns->rx_size_1023);
5022         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
5023                            GLPRT_PRC1522L(hw->port_info->lport),
5024                            pf->offset_loaded, &os->rx_size_1522,
5025                            &ns->rx_size_1522);
5026         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
5027                            GLPRT_PRC9522L(hw->port_info->lport),
5028                            pf->offset_loaded, &os->rx_size_big,
5029                            &ns->rx_size_big);
5030         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
5031                            pf->offset_loaded, &os->rx_undersize,
5032                            &ns->rx_undersize);
5033         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
5034                            pf->offset_loaded, &os->rx_fragments,
5035                            &ns->rx_fragments);
5036         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5037                            pf->offset_loaded, &os->rx_oversize,
5038                            &ns->rx_oversize);
5039         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5040                            pf->offset_loaded, &os->rx_jabber,
5041                            &ns->rx_jabber);
5042         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5043                            GLPRT_PTC64L(hw->port_info->lport),
5044                            pf->offset_loaded, &os->tx_size_64,
5045                            &ns->tx_size_64);
5046         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5047                            GLPRT_PTC127L(hw->port_info->lport),
5048                            pf->offset_loaded, &os->tx_size_127,
5049                            &ns->tx_size_127);
5050         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5051                            GLPRT_PTC255L(hw->port_info->lport),
5052                            pf->offset_loaded, &os->tx_size_255,
5053                            &ns->tx_size_255);
5054         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5055                            GLPRT_PTC511L(hw->port_info->lport),
5056                            pf->offset_loaded, &os->tx_size_511,
5057                            &ns->tx_size_511);
5058         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5059                            GLPRT_PTC1023L(hw->port_info->lport),
5060                            pf->offset_loaded, &os->tx_size_1023,
5061                            &ns->tx_size_1023);
5062         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5063                            GLPRT_PTC1522L(hw->port_info->lport),
5064                            pf->offset_loaded, &os->tx_size_1522,
5065                            &ns->tx_size_1522);
5066         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5067                            GLPRT_PTC9522L(hw->port_info->lport),
5068                            pf->offset_loaded, &os->tx_size_big,
5069                            &ns->tx_size_big);
5070
5071         /* GLPRT_MSPDC not supported */
5072         /* GLPRT_XEC not supported */
5073
5074         pf->offset_loaded = true;
5075
5076         if (pf->main_vsi)
5077                 ice_update_vsi_stats(pf->main_vsi);
5078 }
5079
5080 /* Get all statistics of a port */
5081 static int
5082 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5083 {
5084         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5085         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5086         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5087
5088         /* call read registers - updates values, now write them to struct */
5089         ice_read_stats_registers(pf, hw);
5090
5091         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5092                           pf->main_vsi->eth_stats.rx_multicast +
5093                           pf->main_vsi->eth_stats.rx_broadcast -
5094                           pf->main_vsi->eth_stats.rx_discards;
5095         stats->opackets = ns->eth.tx_unicast +
5096                           ns->eth.tx_multicast +
5097                           ns->eth.tx_broadcast;
5098         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
5099         stats->obytes   = ns->eth.tx_bytes;
5100         stats->oerrors  = ns->eth.tx_errors +
5101                           pf->main_vsi->eth_stats.tx_errors;
5102
5103         /* Rx Errors */
5104         stats->imissed  = ns->eth.rx_discards +
5105                           pf->main_vsi->eth_stats.rx_discards;
5106         stats->ierrors  = ns->crc_errors +
5107                           ns->rx_undersize +
5108                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5109
5110         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5111         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
5112         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5113         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5114         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5115         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5116         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5117                     pf->main_vsi->eth_stats.rx_discards);
5118         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
5119                     ns->eth.rx_unknown_protocol);
5120         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
5121         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5122         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5123         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5124         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5125         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5126                     pf->main_vsi->eth_stats.tx_discards);
5127         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
5128
5129         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
5130                     ns->tx_dropped_link_down);
5131         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5132         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
5133                     ns->illegal_bytes);
5134         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
5135         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
5136                     ns->mac_local_faults);
5137         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
5138                     ns->mac_remote_faults);
5139         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
5140         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
5141         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
5142         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
5143         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
5144         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
5145         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
5146         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
5147         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
5148         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
5149         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
5150         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
5151         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
5152         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
5153         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
5154         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
5155         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
5156         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
5157         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
5158         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
5159         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
5160         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
5161         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
5162         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5163         return 0;
5164 }
5165
5166 /* Reset the statistics */
5167 static int
5168 ice_stats_reset(struct rte_eth_dev *dev)
5169 {
5170         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5171         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5172
5173         /* Mark PF and VSI stats to update the offset, aka "reset" */
5174         pf->offset_loaded = false;
5175         if (pf->main_vsi)
5176                 pf->main_vsi->offset_loaded = false;
5177
5178         /* read the stats, reading current register values into offset */
5179         ice_read_stats_registers(pf, hw);
5180
5181         return 0;
5182 }
5183
5184 static uint32_t
5185 ice_xstats_calc_num(void)
5186 {
5187         uint32_t num;
5188
5189         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5190
5191         return num;
5192 }
5193
5194 static int
5195 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5196                unsigned int n)
5197 {
5198         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5199         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5200         unsigned int i;
5201         unsigned int count;
5202         struct ice_hw_port_stats *hw_stats = &pf->stats;
5203
5204         count = ice_xstats_calc_num();
5205         if (n < count)
5206                 return count;
5207
5208         ice_read_stats_registers(pf, hw);
5209
5210         if (!xstats)
5211                 return 0;
5212
5213         count = 0;
5214
5215         /* Get stats from ice_eth_stats struct */
5216         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5217                 xstats[count].value =
5218                         *(uint64_t *)((char *)&hw_stats->eth +
5219                                       ice_stats_strings[i].offset);
5220                 xstats[count].id = count;
5221                 count++;
5222         }
5223
5224         /* Get individiual stats from ice_hw_port struct */
5225         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5226                 xstats[count].value =
5227                         *(uint64_t *)((char *)hw_stats +
5228                                       ice_hw_port_strings[i].offset);
5229                 xstats[count].id = count;
5230                 count++;
5231         }
5232
5233         return count;
5234 }
5235
5236 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5237                                 struct rte_eth_xstat_name *xstats_names,
5238                                 __rte_unused unsigned int limit)
5239 {
5240         unsigned int count = 0;
5241         unsigned int i;
5242
5243         if (!xstats_names)
5244                 return ice_xstats_calc_num();
5245
5246         /* Note: limit checked in rte_eth_xstats_names() */
5247
5248         /* Get stats from ice_eth_stats struct */
5249         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5250                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5251                         sizeof(xstats_names[count].name));
5252                 count++;
5253         }
5254
5255         /* Get individiual stats from ice_hw_port struct */
5256         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5257                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5258                         sizeof(xstats_names[count].name));
5259                 count++;
5260         }
5261
5262         return count;
5263 }
5264
5265 static int
5266 ice_dev_flow_ops_get(struct rte_eth_dev *dev,
5267                      const struct rte_flow_ops **ops)
5268 {
5269         if (!dev)
5270                 return -EINVAL;
5271
5272         *ops = &ice_flow_ops;
5273         return 0;
5274 }
5275
5276 /* Add UDP tunneling port */
5277 static int
5278 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5279                              struct rte_eth_udp_tunnel *udp_tunnel)
5280 {
5281         int ret = 0;
5282         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5283
5284         if (udp_tunnel == NULL)
5285                 return -EINVAL;
5286
5287         switch (udp_tunnel->prot_type) {
5288         case RTE_TUNNEL_TYPE_VXLAN:
5289                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5290                 break;
5291         default:
5292                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5293                 ret = -EINVAL;
5294                 break;
5295         }
5296
5297         return ret;
5298 }
5299
5300 /* Delete UDP tunneling port */
5301 static int
5302 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5303                              struct rte_eth_udp_tunnel *udp_tunnel)
5304 {
5305         int ret = 0;
5306         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5307
5308         if (udp_tunnel == NULL)
5309                 return -EINVAL;
5310
5311         switch (udp_tunnel->prot_type) {
5312         case RTE_TUNNEL_TYPE_VXLAN:
5313                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5314                 break;
5315         default:
5316                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5317                 ret = -EINVAL;
5318                 break;
5319         }
5320
5321         return ret;
5322 }
5323
5324 static int
5325 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5326               struct rte_pci_device *pci_dev)
5327 {
5328         return rte_eth_dev_pci_generic_probe(pci_dev,
5329                                              sizeof(struct ice_adapter),
5330                                              ice_dev_init);
5331 }
5332
5333 static int
5334 ice_pci_remove(struct rte_pci_device *pci_dev)
5335 {
5336         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5337 }
5338
5339 static struct rte_pci_driver rte_ice_pmd = {
5340         .id_table = pci_id_ice_map,
5341         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5342         .probe = ice_pci_probe,
5343         .remove = ice_pci_remove,
5344 };
5345
5346 /**
5347  * Driver initialization routine.
5348  * Invoked once at EAL init time.
5349  * Register itself as the [Poll Mode] Driver of PCI devices.
5350  */
5351 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5352 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5353 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5354 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5355                               ICE_HW_DEBUG_MASK_ARG "=0xXXX"
5356                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5357                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5358                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5359
5360 RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE);
5361 RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE);
5362 #ifdef RTE_ETHDEV_DEBUG_RX
5363 RTE_LOG_REGISTER_SUFFIX(ice_logtype_rx, rx, DEBUG);
5364 #endif
5365 #ifdef RTE_ETHDEV_DEBUG_TX
5366 RTE_LOG_REGISTER_SUFFIX(ice_logtype_tx, tx, DEBUG);
5367 #endif