drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_FLOW_MARK_SUPPORT_ARG       "flow-mark-support"
  27 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  28
  29 static const char * const ice_valid_args[] = {
  30         ICE_SAFE_MODE_SUPPORT_ARG,
  31         ICE_PIPELINE_MODE_SUPPORT_ARG,
  32         ICE_FLOW_MARK_SUPPORT_ARG,
  33         ICE_PROTO_XTR_ARG,
  34         NULL
  35 };
  36
  37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  38         .name = "ice_dynfield_proto_xtr_metadata",
  39         .size = sizeof(uint32_t),
  40         .align = __alignof__(uint32_t),
  41         .flags = 0,
  42 };
  43
  44 struct proto_xtr_ol_flag {
  45         const struct rte_mbuf_dynflag param;
  46         uint64_t *ol_flag;
  47         bool required;
  48 };
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66 };
  67
  68 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  69
  70 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  71 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  72 #define ICE_MAX_RES_DESC_NUM        1024
  73
  74 int ice_logtype_init;
  75 int ice_logtype_driver;
  76 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  77 int ice_logtype_rx;
  78 #endif
  79 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  80 int ice_logtype_tx;
  81 #endif
  82 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  83 int ice_logtype_tx_free;
  84 #endif
  85
  86 static int ice_dev_configure(struct rte_eth_dev *dev);
  87 static int ice_dev_start(struct rte_eth_dev *dev);
  88 static void ice_dev_stop(struct rte_eth_dev *dev);
  89 static void ice_dev_close(struct rte_eth_dev *dev);
  90 static int ice_dev_reset(struct rte_eth_dev *dev);
  91 static int ice_dev_info_get(struct rte_eth_dev *dev,
  92                             struct rte_eth_dev_info *dev_info);
  93 static int ice_link_update(struct rte_eth_dev *dev,
  94                            int wait_to_complete);
  95 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  96 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  97
  98 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  99 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 100 static int ice_rss_reta_update(struct rte_eth_dev *dev,
 101                                struct rte_eth_rss_reta_entry64 *reta_conf,
 102                                uint16_t reta_size);
 103 static int ice_rss_reta_query(struct rte_eth_dev *dev,
 104                               struct rte_eth_rss_reta_entry64 *reta_conf,
 105                               uint16_t reta_size);
 106 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 107                                struct rte_eth_rss_conf *rss_conf);
 108 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 109                                  struct rte_eth_rss_conf *rss_conf);
 110 static int ice_promisc_enable(struct rte_eth_dev *dev);
 111 static int ice_promisc_disable(struct rte_eth_dev *dev);
 112 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 113 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 114 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 115                                uint16_t vlan_id,
 116                                int on);
 117 static int ice_macaddr_set(struct rte_eth_dev *dev,
 118                            struct rte_ether_addr *mac_addr);
 119 static int ice_macaddr_add(struct rte_eth_dev *dev,
 120                            struct rte_ether_addr *mac_addr,
 121                            __rte_unused uint32_t index,
 122                            uint32_t pool);
 123 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 124 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 125                                     uint16_t queue_id);
 126 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 127                                      uint16_t queue_id);
 128 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 129                               size_t fw_size);
 130 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 131                              uint16_t pvid, int on);
 132 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 133 static int ice_get_eeprom(struct rte_eth_dev *dev,
 134                           struct rte_dev_eeprom_info *eeprom);
 135 static int ice_stats_get(struct rte_eth_dev *dev,
 136                          struct rte_eth_stats *stats);
 137 static int ice_stats_reset(struct rte_eth_dev *dev);
 138 static int ice_xstats_get(struct rte_eth_dev *dev,
 139                           struct rte_eth_xstat *xstats, unsigned int n);
 140 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 141                                 struct rte_eth_xstat_name *xstats_names,
 142                                 unsigned int limit);
 143 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 144                         enum rte_filter_type filter_type,
 145                         enum rte_filter_op filter_op,
 146                         void *arg);
 147 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 148                         struct rte_eth_udp_tunnel *udp_tunnel);
 149 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 150                         struct rte_eth_udp_tunnel *udp_tunnel);
 151
 152 static const struct rte_pci_id pci_id_ice_map[] = {
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 165         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 166         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 167         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 168         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 169         { .vendor_id = 0, /* sentinel */ },
 170 };
 171
 172 static const struct eth_dev_ops ice_eth_dev_ops = {
 173         .dev_configure                = ice_dev_configure,
 174         .dev_start                    = ice_dev_start,
 175         .dev_stop                     = ice_dev_stop,
 176         .dev_close                    = ice_dev_close,
 177         .dev_reset                    = ice_dev_reset,
 178         .dev_set_link_up              = ice_dev_set_link_up,
 179         .dev_set_link_down            = ice_dev_set_link_down,
 180         .rx_queue_start               = ice_rx_queue_start,
 181         .rx_queue_stop                = ice_rx_queue_stop,
 182         .tx_queue_start               = ice_tx_queue_start,
 183         .tx_queue_stop                = ice_tx_queue_stop,
 184         .rx_queue_setup               = ice_rx_queue_setup,
 185         .rx_queue_release             = ice_rx_queue_release,
 186         .tx_queue_setup               = ice_tx_queue_setup,
 187         .tx_queue_release             = ice_tx_queue_release,
 188         .dev_infos_get                = ice_dev_info_get,
 189         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 190         .link_update                  = ice_link_update,
 191         .mtu_set                      = ice_mtu_set,
 192         .mac_addr_set                 = ice_macaddr_set,
 193         .mac_addr_add                 = ice_macaddr_add,
 194         .mac_addr_remove              = ice_macaddr_remove,
 195         .vlan_filter_set              = ice_vlan_filter_set,
 196         .vlan_offload_set             = ice_vlan_offload_set,
 197         .reta_update                  = ice_rss_reta_update,
 198         .reta_query                   = ice_rss_reta_query,
 199         .rss_hash_update              = ice_rss_hash_update,
 200         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 201         .promiscuous_enable           = ice_promisc_enable,
 202         .promiscuous_disable          = ice_promisc_disable,
 203         .allmulticast_enable          = ice_allmulti_enable,
 204         .allmulticast_disable         = ice_allmulti_disable,
 205         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 206         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 207         .fw_version_get               = ice_fw_version_get,
 208         .vlan_pvid_set                = ice_vlan_pvid_set,
 209         .rxq_info_get                 = ice_rxq_info_get,
 210         .txq_info_get                 = ice_txq_info_get,
 211         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 212         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 213         .get_eeprom_length            = ice_get_eeprom_length,
 214         .get_eeprom                   = ice_get_eeprom,
 215         .rx_queue_count               = ice_rx_queue_count,
 216         .rx_descriptor_status         = ice_rx_descriptor_status,
 217         .tx_descriptor_status         = ice_tx_descriptor_status,
 218         .stats_get                    = ice_stats_get,
 219         .stats_reset                  = ice_stats_reset,
 220         .xstats_get                   = ice_xstats_get,
 221         .xstats_get_names             = ice_xstats_get_names,
 222         .xstats_reset                 = ice_stats_reset,
 223         .filter_ctrl                  = ice_dev_filter_ctrl,
 224         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 225         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 226         .tx_done_cleanup              = ice_tx_done_cleanup,
 227 };
 228
 229 /* store statistics names and its offset in stats structure */
 230 struct ice_xstats_name_off {
 231         char name[RTE_ETH_XSTATS_NAME_SIZE];
 232         unsigned int offset;
 233 };
 234
 235 static const struct ice_xstats_name_off ice_stats_strings[] = {
 236         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 237         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 238         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 239         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 240         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 241                 rx_unknown_protocol)},
 242         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 243         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 244         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 245         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 246 };
 247
 248 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 249                 sizeof(ice_stats_strings[0]))
 250
 251 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 252         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 253                 tx_dropped_link_down)},
 254         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 255         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 256                 illegal_bytes)},
 257         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 258         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 259                 mac_local_faults)},
 260         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 261                 mac_remote_faults)},
 262         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 263                 rx_len_errors)},
 264         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 265         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 266         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 267         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 268         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 269         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_127)},
 271         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_255)},
 273         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 274                 rx_size_511)},
 275         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 276                 rx_size_1023)},
 277         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 278                 rx_size_1522)},
 279         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 280                 rx_size_big)},
 281         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 282                 rx_undersize)},
 283         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 284                 rx_oversize)},
 285         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 286                 mac_short_pkt_dropped)},
 287         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 288                 rx_fragments)},
 289         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 290         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 291         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_127)},
 293         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_255)},
 295         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 296                 tx_size_511)},
 297         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 298                 tx_size_1023)},
 299         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 300                 tx_size_1522)},
 301         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 302                 tx_size_big)},
 303 };
 304
 305 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 306                 sizeof(ice_hw_port_strings[0]))
 307
 308 static void
 309 ice_init_controlq_parameter(struct ice_hw *hw)
 310 {
 311         /* fields for adminq */
 312         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 313         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 314         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 315         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 316
 317         /* fields for mailboxq, DPDK used as PF host */
 318         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 319         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 320         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 321         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 322 }
 323
 324 static int
 325 lookup_proto_xtr_type(const char *xtr_name)
 326 {
 327         static struct {
 328                 const char *name;
 329                 enum proto_xtr_type type;
 330         } xtr_type_map[] = {
 331                 { "vlan",      PROTO_XTR_VLAN      },
 332                 { "ipv4",      PROTO_XTR_IPV4      },
 333                 { "ipv6",      PROTO_XTR_IPV6      },
 334                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 335                 { "tcp",       PROTO_XTR_TCP       },
 336         };
 337         uint32_t i;
 338
 339         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 340                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 341                         return xtr_type_map[i].type;
 342         }
 343
 344         return -1;
 345 }
 346
 347 /*
 348  * Parse elem, the elem could be single number/range or '(' ')' group
 349  * 1) A single number elem, it's just a simple digit. e.g. 9
 350  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 351  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 352  *    Within group elem, '-' used for a range separator;
 353  *                       ',' used for a single number.
 354  */
 355 static int
 356 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 357 {
 358         const char *str = input;
 359         char *end = NULL;
 360         uint32_t min, max;
 361         uint32_t idx;
 362
 363         while (isblank(*str))
 364                 str++;
 365
 366         if (!isdigit(*str) && *str != '(')
 367                 return -1;
 368
 369         /* process single number or single range of number */
 370         if (*str != '(') {
 371                 errno = 0;
 372                 idx = strtoul(str, &end, 10);
 373                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 374                         return -1;
 375
 376                 while (isblank(*end))
 377                         end++;
 378
 379                 min = idx;
 380                 max = idx;
 381
 382                 /* process single <number>-<number> */
 383                 if (*end == '-') {
 384                         end++;
 385                         while (isblank(*end))
 386                                 end++;
 387                         if (!isdigit(*end))
 388                                 return -1;
 389
 390                         errno = 0;
 391                         idx = strtoul(end, &end, 10);
 392                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 393                                 return -1;
 394
 395                         max = idx;
 396                         while (isblank(*end))
 397                                 end++;
 398                 }
 399
 400                 if (*end != ':')
 401                         return -1;
 402
 403                 for (idx = RTE_MIN(min, max);
 404                      idx <= RTE_MAX(min, max); idx++)
 405                         devargs->proto_xtr[idx] = xtr_type;
 406
 407                 return 0;
 408         }
 409
 410         /* process set within bracket */
 411         str++;
 412         while (isblank(*str))
 413                 str++;
 414         if (*str == '\0')
 415                 return -1;
 416
 417         min = ICE_MAX_QUEUE_NUM;
 418         do {
 419                 /* go ahead to the first digit */
 420                 while (isblank(*str))
 421                         str++;
 422                 if (!isdigit(*str))
 423                         return -1;
 424
 425                 /* get the digit value */
 426                 errno = 0;
 427                 idx = strtoul(str, &end, 10);
 428                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 429                         return -1;
 430
 431                 /* go ahead to separator '-',',' and ')' */
 432                 while (isblank(*end))
 433                         end++;
 434                 if (*end == '-') {
 435                         if (min == ICE_MAX_QUEUE_NUM)
 436                                 min = idx;
 437                         else /* avoid continuous '-' */
 438                                 return -1;
 439                 } else if (*end == ',' || *end == ')') {
 440                         max = idx;
 441                         if (min == ICE_MAX_QUEUE_NUM)
 442                                 min = idx;
 443
 444                         for (idx = RTE_MIN(min, max);
 445                              idx <= RTE_MAX(min, max); idx++)
 446                                 devargs->proto_xtr[idx] = xtr_type;
 447
 448                         min = ICE_MAX_QUEUE_NUM;
 449                 } else {
 450                         return -1;
 451                 }
 452
 453                 str = end + 1;
 454         } while (*end != ')' && *end != '\0');
 455
 456         return 0;
 457 }
 458
 459 static int
 460 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 461 {
 462         const char *queue_start;
 463         uint32_t idx;
 464         int xtr_type;
 465         char xtr_name[32];
 466
 467         while (isblank(*queues))
 468                 queues++;
 469
 470         if (*queues != '[') {
 471                 xtr_type = lookup_proto_xtr_type(queues);
 472                 if (xtr_type < 0)
 473                         return -1;
 474
 475                 devargs->proto_xtr_dflt = xtr_type;
 476
 477                 return 0;
 478         }
 479
 480         queues++;
 481         do {
 482                 while (isblank(*queues))
 483                         queues++;
 484                 if (*queues == '\0')
 485                         return -1;
 486
 487                 queue_start = queues;
 488
 489                 /* go across a complete bracket */
 490                 if (*queue_start == '(') {
 491                         queues += strcspn(queues, ")");
 492                         if (*queues != ')')
 493                                 return -1;
 494                 }
 495
 496                 /* scan the separator ':' */
 497                 queues += strcspn(queues, ":");
 498                 if (*queues++ != ':')
 499                         return -1;
 500                 while (isblank(*queues))
 501                         queues++;
 502
 503                 for (idx = 0; ; idx++) {
 504                         if (isblank(queues[idx]) ||
 505                             queues[idx] == ',' ||
 506                             queues[idx] == ']' ||
 507                             queues[idx] == '\0')
 508                                 break;
 509
 510                         if (idx > sizeof(xtr_name) - 2)
 511                                 return -1;
 512
 513                         xtr_name[idx] = queues[idx];
 514                 }
 515                 xtr_name[idx] = '\0';
 516                 xtr_type = lookup_proto_xtr_type(xtr_name);
 517                 if (xtr_type < 0)
 518                         return -1;
 519
 520                 queues += idx;
 521
 522                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 523                         queues++;
 524
 525                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 526                         return -1;
 527         } while (*queues != '\0');
 528
 529         return 0;
 530 }
 531
 532 static int
 533 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 534                      void *extra_args)
 535 {
 536         struct ice_devargs *devargs = extra_args;
 537
 538         if (value == NULL || extra_args == NULL)
 539                 return -EINVAL;
 540
 541         if (parse_queue_proto_xtr(value, devargs) < 0) {
 542                 PMD_DRV_LOG(ERR,
 543                             "The protocol extraction parameter is wrong : '%s'",
 544                             value);
 545                 return -1;
 546         }
 547
 548         return 0;
 549 }
 550
 551 static bool
 552 ice_proto_xtr_support(struct ice_hw *hw)
 553 {
 554 #define FLX_REG(val, fld, idx) \
 555         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 556          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 557         static struct {
 558                 uint32_t rxdid;
 559                 uint16_t protid_0;
 560                 uint16_t protid_1;
 561         } xtr_sets[] = {
 562                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 563                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 564                   ICE_PROT_IPV4_OF_OR_S },
 565                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 566                   ICE_PROT_IPV6_OF_OR_S },
 567                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 568                   ICE_PROT_IPV6_OF_OR_S },
 569                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 570         };
 571         uint32_t i;
 572
 573         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 574                 uint32_t rxdid = xtr_sets[i].rxdid;
 575                 uint32_t v;
 576
 577                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 578                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 579
 580                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 581                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 582                                 return false;
 583                 }
 584
 585                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 586                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 587
 588                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 589                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 590                                 return false;
 591                 }
 592         }
 593
 594         return true;
 595 }
 596
 597 static int
 598 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 599                   uint32_t num)
 600 {
 601         struct pool_entry *entry;
 602
 603         if (!pool || !num)
 604                 return -EINVAL;
 605
 606         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 607         if (!entry) {
 608                 PMD_INIT_LOG(ERR,
 609                              "Failed to allocate memory for resource pool");
 610                 return -ENOMEM;
 611         }
 612
 613         /* queue heap initialize */
 614         pool->num_free = num;
 615         pool->num_alloc = 0;
 616         pool->base = base;
 617         LIST_INIT(&pool->alloc_list);
 618         LIST_INIT(&pool->free_list);
 619
 620         /* Initialize element  */
 621         entry->base = 0;
 622         entry->len = num;
 623
 624         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 625         return 0;
 626 }
 627
 628 static int
 629 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 630                    uint16_t num)
 631 {
 632         struct pool_entry *entry, *valid_entry;
 633
 634         if (!pool || !num) {
 635                 PMD_INIT_LOG(ERR, "Invalid parameter");
 636                 return -EINVAL;
 637         }
 638
 639         if (pool->num_free < num) {
 640                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 641                              num, pool->num_free);
 642                 return -ENOMEM;
 643         }
 644
 645         valid_entry = NULL;
 646         /* Lookup  in free list and find most fit one */
 647         LIST_FOREACH(entry, &pool->free_list, next) {
 648                 if (entry->len >= num) {
 649                         /* Find best one */
 650                         if (entry->len == num) {
 651                                 valid_entry = entry;
 652                                 break;
 653                         }
 654                         if (!valid_entry ||
 655                             valid_entry->len > entry->len)
 656                                 valid_entry = entry;
 657                 }
 658         }
 659
 660         /* Not find one to satisfy the request, return */
 661         if (!valid_entry) {
 662                 PMD_INIT_LOG(ERR, "No valid entry found");
 663                 return -ENOMEM;
 664         }
 665         /**
 666          * The entry have equal queue number as requested,
 667          * remove it from alloc_list.
 668          */
 669         if (valid_entry->len == num) {
 670                 LIST_REMOVE(valid_entry, next);
 671         } else {
 672                 /**
 673                  * The entry have more numbers than requested,
 674                  * create a new entry for alloc_list and minus its
 675                  * queue base and number in free_list.
 676                  */
 677                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 678                 if (!entry) {
 679                         PMD_INIT_LOG(ERR,
 680                                      "Failed to allocate memory for "
 681                                      "resource pool");
 682                         return -ENOMEM;
 683                 }
 684                 entry->base = valid_entry->base;
 685                 entry->len = num;
 686                 valid_entry->base += num;
 687                 valid_entry->len -= num;
 688                 valid_entry = entry;
 689         }
 690
 691         /* Insert it into alloc list, not sorted */
 692         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 693
 694         pool->num_free -= valid_entry->len;
 695         pool->num_alloc += valid_entry->len;
 696
 697         return valid_entry->base + pool->base;
 698 }
 699
 700 static void
 701 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 702 {
 703         struct pool_entry *entry, *next_entry;
 704
 705         if (!pool)
 706                 return;
 707
 708         for (entry = LIST_FIRST(&pool->alloc_list);
 709              entry && (next_entry = LIST_NEXT(entry, next), 1);
 710              entry = next_entry) {
 711                 LIST_REMOVE(entry, next);
 712                 rte_free(entry);
 713         }
 714
 715         for (entry = LIST_FIRST(&pool->free_list);
 716              entry && (next_entry = LIST_NEXT(entry, next), 1);
 717              entry = next_entry) {
 718                 LIST_REMOVE(entry, next);
 719                 rte_free(entry);
 720         }
 721
 722         pool->num_free = 0;
 723         pool->num_alloc = 0;
 724         pool->base = 0;
 725         LIST_INIT(&pool->alloc_list);
 726         LIST_INIT(&pool->free_list);
 727 }
 728
 729 static void
 730 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 731 {
 732         /* Set VSI LUT selection */
 733         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 734                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 735         /* Set Hash scheme */
 736         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 737                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 738         /* enable TC */
 739         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 740 }
 741
 742 static enum ice_status
 743 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 744                                 struct ice_aqc_vsi_props *info,
 745                                 uint8_t enabled_tcmap)
 746 {
 747         uint16_t bsf, qp_idx;
 748
 749         /* default tc 0 now. Multi-TC supporting need to be done later.
 750          * Configure TC and queue mapping parameters, for enabled TC,
 751          * allocate qpnum_per_tc queues to this traffic.
 752          */
 753         if (enabled_tcmap != 0x01) {
 754                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 755                 return -ENOTSUP;
 756         }
 757
 758         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 759         bsf = rte_bsf32(vsi->nb_qps);
 760         /* Adjust the queue number to actual queues that can be applied */
 761         vsi->nb_qps = 0x1 << bsf;
 762
 763         qp_idx = 0;
 764         /* Set tc and queue mapping with VSI */
 765         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 766                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 767                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 768
 769         /* Associate queue number with VSI */
 770         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 771         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 772         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 773         info->valid_sections |=
 774                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 775         /* Set the info.ingress_table and info.egress_table
 776          * for UP translate table. Now just set it to 1:1 map by default
 777          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 778          */
 779 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 780         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 781         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 782         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 783         return 0;
 784 }
 785
 786 static int
 787 ice_init_mac_address(struct rte_eth_dev *dev)
 788 {
 789         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 790
 791         if (!rte_is_unicast_ether_addr
 792                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 793                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 794                 return -EINVAL;
 795         }
 796
 797         rte_ether_addr_copy(
 798                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 799                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 800
 801         dev->data->mac_addrs =
 802                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 803         if (!dev->data->mac_addrs) {
 804                 PMD_INIT_LOG(ERR,
 805                              "Failed to allocate memory to store mac address");
 806                 return -ENOMEM;
 807         }
 808         /* store it to dev data */
 809         rte_ether_addr_copy(
 810                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 811                 &dev->data->mac_addrs[0]);
 812         return 0;
 813 }
 814
 815 /* Find out specific MAC filter */
 816 static struct ice_mac_filter *
 817 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 818 {
 819         struct ice_mac_filter *f;
 820
 821         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 822                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 823                         return f;
 824         }
 825
 826         return NULL;
 827 }
 828
 829 static int
 830 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 831 {
 832         struct ice_fltr_list_entry *m_list_itr = NULL;
 833         struct ice_mac_filter *f;
 834         struct LIST_HEAD_TYPE list_head;
 835         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 836         int ret = 0;
 837
 838         /* If it's added and configured, return */
 839         f = ice_find_mac_filter(vsi, mac_addr);
 840         if (f) {
 841                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 842                 return 0;
 843         }
 844
 845         INIT_LIST_HEAD(&list_head);
 846
 847         m_list_itr = (struct ice_fltr_list_entry *)
 848                 ice_malloc(hw, sizeof(*m_list_itr));
 849         if (!m_list_itr) {
 850                 ret = -ENOMEM;
 851                 goto DONE;
 852         }
 853         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 854                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 855         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 856         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 857         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 858         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 859         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 860
 861         LIST_ADD(&m_list_itr->list_entry, &list_head);
 862
 863         /* Add the mac */
 864         ret = ice_add_mac(hw, &list_head);
 865         if (ret != ICE_SUCCESS) {
 866                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 867                 ret = -EINVAL;
 868                 goto DONE;
 869         }
 870         /* Add the mac addr into mac list */
 871         f = rte_zmalloc(NULL, sizeof(*f), 0);
 872         if (!f) {
 873                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 874                 ret = -ENOMEM;
 875                 goto DONE;
 876         }
 877         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 878         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 879         vsi->mac_num++;
 880
 881         ret = 0;
 882
 883 DONE:
 884         rte_free(m_list_itr);
 885         return ret;
 886 }
 887
 888 static int
 889 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 890 {
 891         struct ice_fltr_list_entry *m_list_itr = NULL;
 892         struct ice_mac_filter *f;
 893         struct LIST_HEAD_TYPE list_head;
 894         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 895         int ret = 0;
 896
 897         /* Can't find it, return an error */
 898         f = ice_find_mac_filter(vsi, mac_addr);
 899         if (!f)
 900                 return -EINVAL;
 901
 902         INIT_LIST_HEAD(&list_head);
 903
 904         m_list_itr = (struct ice_fltr_list_entry *)
 905                 ice_malloc(hw, sizeof(*m_list_itr));
 906         if (!m_list_itr) {
 907                 ret = -ENOMEM;
 908                 goto DONE;
 909         }
 910         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 911                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 912         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 913         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 914         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 915         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 916         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 917
 918         LIST_ADD(&m_list_itr->list_entry, &list_head);
 919
 920         /* remove the mac filter */
 921         ret = ice_remove_mac(hw, &list_head);
 922         if (ret != ICE_SUCCESS) {
 923                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 924                 ret = -EINVAL;
 925                 goto DONE;
 926         }
 927
 928         /* Remove the mac addr from mac list */
 929         TAILQ_REMOVE(&vsi->mac_list, f, next);
 930         rte_free(f);
 931         vsi->mac_num--;
 932
 933         ret = 0;
 934 DONE:
 935         rte_free(m_list_itr);
 936         return ret;
 937 }
 938
 939 /* Find out specific VLAN filter */
 940 static struct ice_vlan_filter *
 941 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 942 {
 943         struct ice_vlan_filter *f;
 944
 945         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 946                 if (vlan_id == f->vlan_info.vlan_id)
 947                         return f;
 948         }
 949
 950         return NULL;
 951 }
 952
 953 static int
 954 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 955 {
 956         struct ice_fltr_list_entry *v_list_itr = NULL;
 957         struct ice_vlan_filter *f;
 958         struct LIST_HEAD_TYPE list_head;
 959         struct ice_hw *hw;
 960         int ret = 0;
 961
 962         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 963                 return -EINVAL;
 964
 965         hw = ICE_VSI_TO_HW(vsi);
 966
 967         /* If it's added and configured, return. */
 968         f = ice_find_vlan_filter(vsi, vlan_id);
 969         if (f) {
 970                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 971                 return 0;
 972         }
 973
 974         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 975                 return 0;
 976
 977         INIT_LIST_HEAD(&list_head);
 978
 979         v_list_itr = (struct ice_fltr_list_entry *)
 980                       ice_malloc(hw, sizeof(*v_list_itr));
 981         if (!v_list_itr) {
 982                 ret = -ENOMEM;
 983                 goto DONE;
 984         }
 985         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 986         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 987         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 988         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 989         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 990         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 991
 992         LIST_ADD(&v_list_itr->list_entry, &list_head);
 993
 994         /* Add the vlan */
 995         ret = ice_add_vlan(hw, &list_head);
 996         if (ret != ICE_SUCCESS) {
 997                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 998                 ret = -EINVAL;
 999                 goto DONE;
1000         }
1001
1002         /* Add vlan into vlan list */
1003         f = rte_zmalloc(NULL, sizeof(*f), 0);
1004         if (!f) {
1005                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1006                 ret = -ENOMEM;
1007                 goto DONE;
1008         }
1009         f->vlan_info.vlan_id = vlan_id;
1010         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1011         vsi->vlan_num++;
1012
1013         ret = 0;
1014
1015 DONE:
1016         rte_free(v_list_itr);
1017         return ret;
1018 }
1019
1020 static int
1021 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1022 {
1023         struct ice_fltr_list_entry *v_list_itr = NULL;
1024         struct ice_vlan_filter *f;
1025         struct LIST_HEAD_TYPE list_head;
1026         struct ice_hw *hw;
1027         int ret = 0;
1028
1029         /**
1030          * Vlan 0 is the generic filter for untagged packets
1031          * and can't be removed.
1032          */
1033         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1034                 return -EINVAL;
1035
1036         hw = ICE_VSI_TO_HW(vsi);
1037
1038         /* Can't find it, return an error */
1039         f = ice_find_vlan_filter(vsi, vlan_id);
1040         if (!f)
1041                 return -EINVAL;
1042
1043         INIT_LIST_HEAD(&list_head);
1044
1045         v_list_itr = (struct ice_fltr_list_entry *)
1046                       ice_malloc(hw, sizeof(*v_list_itr));
1047         if (!v_list_itr) {
1048                 ret = -ENOMEM;
1049                 goto DONE;
1050         }
1051
1052         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1053         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1054         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1055         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1056         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1057         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1058
1059         LIST_ADD(&v_list_itr->list_entry, &list_head);
1060
1061         /* remove the vlan filter */
1062         ret = ice_remove_vlan(hw, &list_head);
1063         if (ret != ICE_SUCCESS) {
1064                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1065                 ret = -EINVAL;
1066                 goto DONE;
1067         }
1068
1069         /* Remove the vlan id from vlan list */
1070         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1071         rte_free(f);
1072         vsi->vlan_num--;
1073
1074         ret = 0;
1075 DONE:
1076         rte_free(v_list_itr);
1077         return ret;
1078 }
1079
1080 static int
1081 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1082 {
1083         struct ice_mac_filter *m_f;
1084         struct ice_vlan_filter *v_f;
1085         int ret = 0;
1086
1087         if (!vsi || !vsi->mac_num)
1088                 return -EINVAL;
1089
1090         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1091                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1092                 if (ret != ICE_SUCCESS) {
1093                         ret = -EINVAL;
1094                         goto DONE;
1095                 }
1096         }
1097
1098         if (vsi->vlan_num == 0)
1099                 return 0;
1100
1101         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1102                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1103                 if (ret != ICE_SUCCESS) {
1104                         ret = -EINVAL;
1105                         goto DONE;
1106                 }
1107         }
1108
1109 DONE:
1110         return ret;
1111 }
1112
1113 static int
1114 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1115 {
1116         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1117         struct ice_vsi_ctx ctxt;
1118         uint8_t qinq_flags;
1119         int ret = 0;
1120
1121         /* Check if it has been already on or off */
1122         if (vsi->info.valid_sections &
1123                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1124                 if (on) {
1125                         if ((vsi->info.outer_tag_flags &
1126                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1127                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1128                                 return 0; /* already on */
1129                 } else {
1130                         if (!(vsi->info.outer_tag_flags &
1131                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1132                                 return 0; /* already off */
1133                 }
1134         }
1135
1136         if (on)
1137                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1138         else
1139                 qinq_flags = 0;
1140         /* clear global insertion and use per packet insertion */
1141         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1142         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1143         vsi->info.outer_tag_flags |= qinq_flags;
1144         /* use default vlan type 0x8100 */
1145         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1146         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1147                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1148         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1149         ctxt.info.valid_sections =
1150                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1151         ctxt.vsi_num = vsi->vsi_id;
1152         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1153         if (ret) {
1154                 PMD_DRV_LOG(INFO,
1155                             "Update VSI failed to %s qinq stripping",
1156                             on ? "enable" : "disable");
1157                 return -EINVAL;
1158         }
1159
1160         vsi->info.valid_sections |=
1161                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1162
1163         return ret;
1164 }
1165
1166 static int
1167 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1168 {
1169         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1170         struct ice_vsi_ctx ctxt;
1171         uint8_t qinq_flags;
1172         int ret = 0;
1173
1174         /* Check if it has been already on or off */
1175         if (vsi->info.valid_sections &
1176                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1177                 if (on) {
1178                         if ((vsi->info.outer_tag_flags &
1179                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1180                             ICE_AQ_VSI_OUTER_TAG_COPY)
1181                                 return 0; /* already on */
1182                 } else {
1183                         if ((vsi->info.outer_tag_flags &
1184                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1185                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1186                                 return 0; /* already off */
1187                 }
1188         }
1189
1190         if (on)
1191                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1192         else
1193                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1194         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1195         vsi->info.outer_tag_flags |= qinq_flags;
1196         /* use default vlan type 0x8100 */
1197         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1198         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1199                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1200         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1201         ctxt.info.valid_sections =
1202                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1203         ctxt.vsi_num = vsi->vsi_id;
1204         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1205         if (ret) {
1206                 PMD_DRV_LOG(INFO,
1207                             "Update VSI failed to %s qinq stripping",
1208                             on ? "enable" : "disable");
1209                 return -EINVAL;
1210         }
1211
1212         vsi->info.valid_sections |=
1213                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1214
1215         return ret;
1216 }
1217
1218 static int
1219 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1220 {
1221         int ret;
1222
1223         ret = ice_vsi_config_qinq_stripping(vsi, on);
1224         if (ret)
1225                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1226
1227         ret = ice_vsi_config_qinq_insertion(vsi, on);
1228         if (ret)
1229                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1230
1231         return ret;
1232 }
1233
1234 /* Enable IRQ0 */
1235 static void
1236 ice_pf_enable_irq0(struct ice_hw *hw)
1237 {
1238         /* reset the registers */
1239         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1240         ICE_READ_REG(hw, PFINT_OICR);
1241
1242 #ifdef ICE_LSE_SPT
1243         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1244                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1245                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1246
1247         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1248                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1249                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1250                        PFINT_OICR_CTL_ITR_INDX_M) |
1251                       PFINT_OICR_CTL_CAUSE_ENA_M);
1252
1253         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1254                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1255                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1256                        PFINT_FW_CTL_ITR_INDX_M) |
1257                       PFINT_FW_CTL_CAUSE_ENA_M);
1258 #else
1259         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1260 #endif
1261
1262         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1263                       GLINT_DYN_CTL_INTENA_M |
1264                       GLINT_DYN_CTL_CLEARPBA_M |
1265                       GLINT_DYN_CTL_ITR_INDX_M);
1266
1267         ice_flush(hw);
1268 }
1269
1270 /* Disable IRQ0 */
1271 static void
1272 ice_pf_disable_irq0(struct ice_hw *hw)
1273 {
1274         /* Disable all interrupt types */
1275         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1276         ice_flush(hw);
1277 }
1278
1279 #ifdef ICE_LSE_SPT
1280 static void
1281 ice_handle_aq_msg(struct rte_eth_dev *dev)
1282 {
1283         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284         struct ice_ctl_q_info *cq = &hw->adminq;
1285         struct ice_rq_event_info event;
1286         uint16_t pending, opcode;
1287         int ret;
1288
1289         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1290         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1291         if (!event.msg_buf) {
1292                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1293                 return;
1294         }
1295
1296         pending = 1;
1297         while (pending) {
1298                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1299
1300                 if (ret != ICE_SUCCESS) {
1301                         PMD_DRV_LOG(INFO,
1302                                     "Failed to read msg from AdminQ, "
1303                                     "adminq_err: %u",
1304                                     hw->adminq.sq_last_status);
1305                         break;
1306                 }
1307                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1308
1309                 switch (opcode) {
1310                 case ice_aqc_opc_get_link_status:
1311                         ret = ice_link_update(dev, 0);
1312                         if (!ret)
1313                                 _rte_eth_dev_callback_process
1314                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1315                         break;
1316                 default:
1317                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1318                                     opcode);
1319                         break;
1320                 }
1321         }
1322         rte_free(event.msg_buf);
1323 }
1324 #endif
1325
1326 /**
1327  * Interrupt handler triggered by NIC for handling
1328  * specific interrupt.
1329  *
1330  * @param handle
1331  *  Pointer to interrupt handle.
1332  * @param param
1333  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1334  *
1335  * @return
1336  *  void
1337  */
1338 static void
1339 ice_interrupt_handler(void *param)
1340 {
1341         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1342         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343         uint32_t oicr;
1344         uint32_t reg;
1345         uint8_t pf_num;
1346         uint8_t event;
1347         uint16_t queue;
1348         int ret;
1349 #ifdef ICE_LSE_SPT
1350         uint32_t int_fw_ctl;
1351 #endif
1352
1353         /* Disable interrupt */
1354         ice_pf_disable_irq0(hw);
1355
1356         /* read out interrupt causes */
1357         oicr = ICE_READ_REG(hw, PFINT_OICR);
1358 #ifdef ICE_LSE_SPT
1359         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1360 #endif
1361
1362         /* No interrupt event indicated */
1363         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1364                 PMD_DRV_LOG(INFO, "No interrupt event");
1365                 goto done;
1366         }
1367
1368 #ifdef ICE_LSE_SPT
1369         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1370                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1371                 ice_handle_aq_msg(dev);
1372         }
1373 #else
1374         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1375                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1376                 ret = ice_link_update(dev, 0);
1377                 if (!ret)
1378                         _rte_eth_dev_callback_process
1379                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1380         }
1381 #endif
1382
1383         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1384                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1385                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1386                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1387                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1388                                  GL_MDET_TX_PQM_PF_NUM_S;
1389                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1390                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1391                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1392                                 GL_MDET_TX_PQM_QNUM_S;
1393
1394                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1395                                     "%d by PQM on TX queue %d PF# %d",
1396                                     event, queue, pf_num);
1397                 }
1398
1399                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1400                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1401                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1402                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1403                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1404                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1405                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1406                                 GL_MDET_TX_TCLAN_QNUM_S;
1407
1408                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1409                                     "%d by TCLAN on TX queue %d PF# %d",
1410                                     event, queue, pf_num);
1411                 }
1412         }
1413 done:
1414         /* Enable interrupt */
1415         ice_pf_enable_irq0(hw);
1416         rte_intr_ack(dev->intr_handle);
1417 }
1418
1419 static void
1420 ice_init_proto_xtr(struct rte_eth_dev *dev)
1421 {
1422         struct ice_adapter *ad =
1423                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1424         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1425         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1426         const struct proto_xtr_ol_flag *ol_flag;
1427         bool proto_xtr_enable = false;
1428         int offset;
1429         uint16_t i;
1430
1431         if (!ice_proto_xtr_support(hw)) {
1432                 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1433                 return;
1434         }
1435
1436         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1437         if (unlikely(pf->proto_xtr == NULL)) {
1438                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1439                 return;
1440         }
1441
1442         for (i = 0; i < pf->lan_nb_qps; i++) {
1443                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1444                                    ad->devargs.proto_xtr[i] :
1445                                    ad->devargs.proto_xtr_dflt;
1446
1447                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1448                         uint8_t type = pf->proto_xtr[i];
1449
1450                         ice_proto_xtr_ol_flag_params[type].required = true;
1451                         proto_xtr_enable = true;
1452                 }
1453         }
1454
1455         if (likely(!proto_xtr_enable))
1456                 return;
1457
1458         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1459         if (unlikely(offset == -1)) {
1460                 PMD_DRV_LOG(ERR,
1461                             "Protocol extraction metadata is disabled in mbuf with error %d",
1462                             -rte_errno);
1463                 return;
1464         }
1465
1466         PMD_DRV_LOG(DEBUG,
1467                     "Protocol extraction metadata offset in mbuf is : %d",
1468                     offset);
1469         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1470
1471         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1472                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1473
1474                 if (!ol_flag->required)
1475                         continue;
1476
1477                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1478                 if (unlikely(offset == -1)) {
1479                         PMD_DRV_LOG(ERR,
1480                                     "Protocol extraction offload '%s' failed to register with error %d",
1481                                     ol_flag->param.name, -rte_errno);
1482
1483                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1484                         break;
1485                 }
1486
1487                 PMD_DRV_LOG(DEBUG,
1488                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1489                             ol_flag->param.name, offset);
1490                 *ol_flag->ol_flag = 1ULL << offset;
1491         }
1492 }
1493
1494 /*  Initialize SW parameters of PF */
1495 static int
1496 ice_pf_sw_init(struct rte_eth_dev *dev)
1497 {
1498         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1499         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1500
1501         pf->lan_nb_qp_max =
1502                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1503                                   hw->func_caps.common_cap.num_rxq);
1504
1505         pf->lan_nb_qps = pf->lan_nb_qp_max;
1506
1507         ice_init_proto_xtr(dev);
1508
1509         if (hw->func_caps.fd_fltr_guar > 0 ||
1510             hw->func_caps.fd_fltr_best_effort > 0) {
1511                 pf->flags |= ICE_FLAG_FDIR;
1512                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1513                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1514         } else {
1515                 pf->fdir_nb_qps = 0;
1516         }
1517         pf->fdir_qp_offset = 0;
1518
1519         return 0;
1520 }
1521
1522 struct ice_vsi *
1523 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1524 {
1525         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1526         struct ice_vsi *vsi = NULL;
1527         struct ice_vsi_ctx vsi_ctx;
1528         int ret;
1529         struct rte_ether_addr broadcast = {
1530                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1531         struct rte_ether_addr mac_addr;
1532         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1533         uint8_t tc_bitmap = 0x1;
1534         uint16_t cfg;
1535
1536         /* hw->num_lports = 1 in NIC mode */
1537         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1538         if (!vsi)
1539                 return NULL;
1540
1541         vsi->idx = pf->next_vsi_idx;
1542         pf->next_vsi_idx++;
1543         vsi->type = type;
1544         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1545         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1546         vsi->vlan_anti_spoof_on = 0;
1547         vsi->vlan_filter_on = 1;
1548         TAILQ_INIT(&vsi->mac_list);
1549         TAILQ_INIT(&vsi->vlan_list);
1550
1551         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1552         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1553                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1554                         hw->func_caps.common_cap.rss_table_size;
1555         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1556
1557         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1558         switch (type) {
1559         case ICE_VSI_PF:
1560                 vsi->nb_qps = pf->lan_nb_qps;
1561                 vsi->base_queue = 1;
1562                 ice_vsi_config_default_rss(&vsi_ctx.info);
1563                 vsi_ctx.alloc_from_pool = true;
1564                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1565                 /* switch_id is queried by get_switch_config aq, which is done
1566                  * by ice_init_hw
1567                  */
1568                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1569                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1570                 /* Allow all untagged or tagged packets */
1571                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1572                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1573                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1574                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1575
1576                 /* FDIR */
1577                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1578                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1579                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1580                 cfg = ICE_AQ_VSI_FD_ENABLE;
1581                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1582                 vsi_ctx.info.max_fd_fltr_dedicated =
1583                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1584                 vsi_ctx.info.max_fd_fltr_shared =
1585                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1586
1587                 /* Enable VLAN/UP trip */
1588                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1589                                                       &vsi_ctx.info,
1590                                                       ICE_DEFAULT_TCMAP);
1591                 if (ret) {
1592                         PMD_INIT_LOG(ERR,
1593                                      "tc queue mapping with vsi failed, "
1594                                      "err = %d",
1595                                      ret);
1596                         goto fail_mem;
1597                 }
1598
1599                 break;
1600         case ICE_VSI_CTRL:
1601                 vsi->nb_qps = pf->fdir_nb_qps;
1602                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1603                 vsi_ctx.alloc_from_pool = true;
1604                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1605
1606                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1607                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1608                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1609                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1610                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1611                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1612                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1613                                                       &vsi_ctx.info,
1614                                                       ICE_DEFAULT_TCMAP);
1615                 if (ret) {
1616                         PMD_INIT_LOG(ERR,
1617                                      "tc queue mapping with vsi failed, "
1618                                      "err = %d",
1619                                      ret);
1620                         goto fail_mem;
1621                 }
1622                 break;
1623         default:
1624                 /* for other types of VSI */
1625                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1626                 goto fail_mem;
1627         }
1628
1629         /* VF has MSIX interrupt in VF range, don't allocate here */
1630         if (type == ICE_VSI_PF) {
1631                 ret = ice_res_pool_alloc(&pf->msix_pool,
1632                                          RTE_MIN(vsi->nb_qps,
1633                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1634                 if (ret < 0) {
1635                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1636                                      vsi->vsi_id, ret);
1637                 }
1638                 vsi->msix_intr = ret;
1639                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1640         } else if (type == ICE_VSI_CTRL) {
1641                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1642                 if (ret < 0) {
1643                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1644                                     vsi->vsi_id, ret);
1645                 }
1646                 vsi->msix_intr = ret;
1647                 vsi->nb_msix = 1;
1648         } else {
1649                 vsi->msix_intr = 0;
1650                 vsi->nb_msix = 0;
1651         }
1652         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1653         if (ret != ICE_SUCCESS) {
1654                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1655                 goto fail_mem;
1656         }
1657         /* store vsi information is SW structure */
1658         vsi->vsi_id = vsi_ctx.vsi_num;
1659         vsi->info = vsi_ctx.info;
1660         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1661         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1662
1663         if (type == ICE_VSI_PF) {
1664                 /* MAC configuration */
1665                 rte_ether_addr_copy((struct rte_ether_addr *)
1666                                         hw->port_info->mac.perm_addr,
1667                                     &pf->dev_addr);
1668
1669                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1670                 ret = ice_add_mac_filter(vsi, &mac_addr);
1671                 if (ret != ICE_SUCCESS)
1672                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1673
1674                 rte_ether_addr_copy(&broadcast, &mac_addr);
1675                 ret = ice_add_mac_filter(vsi, &mac_addr);
1676                 if (ret != ICE_SUCCESS)
1677                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1678         }
1679
1680         /* At the beginning, only TC0. */
1681         /* What we need here is the maximam number of the TX queues.
1682          * Currently vsi->nb_qps means it.
1683          * Correct it if any change.
1684          */
1685         max_txqs[0] = vsi->nb_qps;
1686         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1687                               tc_bitmap, max_txqs);
1688         if (ret != ICE_SUCCESS)
1689                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1690
1691         return vsi;
1692 fail_mem:
1693         rte_free(vsi);
1694         pf->next_vsi_idx--;
1695         return NULL;
1696 }
1697
1698 static int
1699 ice_send_driver_ver(struct ice_hw *hw)
1700 {
1701         struct ice_driver_ver dv;
1702
1703         /* we don't have driver version use 0 for dummy */
1704         dv.major_ver = 0;
1705         dv.minor_ver = 0;
1706         dv.build_ver = 0;
1707         dv.subbuild_ver = 0;
1708         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1709
1710         return ice_aq_send_driver_ver(hw, &dv, NULL);
1711 }
1712
1713 static int
1714 ice_pf_setup(struct ice_pf *pf)
1715 {
1716         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1717         struct ice_vsi *vsi;
1718         uint16_t unused;
1719
1720         /* Clear all stats counters */
1721         pf->offset_loaded = false;
1722         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1723         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1724         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1725         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1726
1727         /* force guaranteed filter pool for PF */
1728         ice_alloc_fd_guar_item(hw, &unused,
1729                                hw->func_caps.fd_fltr_guar);
1730         /* force shared filter pool for PF */
1731         ice_alloc_fd_shrd_item(hw, &unused,
1732                                hw->func_caps.fd_fltr_best_effort);
1733
1734         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1735         if (!vsi) {
1736                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1737                 return -EINVAL;
1738         }
1739
1740         pf->main_vsi = vsi;
1741
1742         return 0;
1743 }
1744
1745 /* PCIe configuration space setting */
1746 #define PCI_CFG_SPACE_SIZE          256
1747 #define PCI_CFG_SPACE_EXP_SIZE      4096
1748 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1749 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1750 #define PCI_EXT_CAP_ID_DSN          0x03
1751
1752 static int
1753 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1754 {
1755         uint32_t header;
1756         int ttl;
1757         int pos = PCI_CFG_SPACE_SIZE;
1758
1759         /* minimum 8 bytes per capability */
1760         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1761
1762         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1763                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1764                 return -1;
1765         }
1766
1767         /*
1768          * If we have no capabilities, this is indicated by cap ID,
1769          * cap version and next pointer all being 0.
1770          */
1771         if (header == 0)
1772                 return 0;
1773
1774         while (ttl-- > 0) {
1775                 if (PCI_EXT_CAP_ID(header) == cap)
1776                         return pos;
1777
1778                 pos = PCI_EXT_CAP_NEXT(header);
1779
1780                 if (pos < PCI_CFG_SPACE_SIZE)
1781                         break;
1782
1783                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1784                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1785                         return -1;
1786                 }
1787         }
1788
1789         return 0;
1790 }
1791
1792 /*
1793  * Extract device serial number from PCIe Configuration Space and
1794  * determine the pkg file path according to the DSN.
1795  */
1796 static int
1797 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1798 {
1799         int pos;
1800         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1801         uint32_t dsn_low, dsn_high;
1802         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1803
1804         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1805
1806         if (pos) {
1807                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1808                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1809                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1810                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1811         } else {
1812                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1813                 goto fail_dsn;
1814         }
1815
1816         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1817                 ICE_MAX_PKG_FILENAME_SIZE);
1818         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1819                 return 0;
1820
1821         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1822                 ICE_MAX_PKG_FILENAME_SIZE);
1823         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1824                 return 0;
1825
1826 fail_dsn:
1827         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1828         if (!access(pkg_file, 0))
1829                 return 0;
1830         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1831         return 0;
1832 }
1833
1834 enum ice_pkg_type
1835 ice_load_pkg_type(struct ice_hw *hw)
1836 {
1837         enum ice_pkg_type package_type;
1838
1839         /* store the activated package type (OS default or Comms) */
1840         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1841                 ICE_PKG_NAME_SIZE))
1842                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1843         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1844                 ICE_PKG_NAME_SIZE))
1845                 package_type = ICE_PKG_TYPE_COMMS;
1846         else
1847                 package_type = ICE_PKG_TYPE_UNKNOWN;
1848
1849         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1850                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1851                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1852                 hw->active_pkg_name);
1853
1854         return package_type;
1855 }
1856
1857 static int ice_load_pkg(struct rte_eth_dev *dev)
1858 {
1859         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1861         int err;
1862         uint8_t *buf;
1863         int buf_len;
1864         FILE *file;
1865         struct stat fstat;
1866         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1867         struct ice_adapter *ad =
1868                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1869
1870         ice_pkg_file_search_path(pci_dev, pkg_file);
1871
1872         file = fopen(pkg_file, "rb");
1873         if (!file)  {
1874                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1875                 return -1;
1876         }
1877
1878         err = stat(pkg_file, &fstat);
1879         if (err) {
1880                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1881                 fclose(file);
1882                 return err;
1883         }
1884
1885         buf_len = fstat.st_size;
1886         buf = rte_malloc(NULL, buf_len, 0);
1887
1888         if (!buf) {
1889                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1890                                 buf_len);
1891                 fclose(file);
1892                 return -1;
1893         }
1894
1895         err = fread(buf, buf_len, 1, file);
1896         if (err != 1) {
1897                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1898                 fclose(file);
1899                 err = -1;
1900                 goto fail_exit;
1901         }
1902
1903         fclose(file);
1904
1905         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1906         if (err) {
1907                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1908                 goto fail_exit;
1909         }
1910
1911         /* store the loaded pkg type info */
1912         ad->active_pkg_type = ice_load_pkg_type(hw);
1913
1914         err = ice_init_hw_tbls(hw);
1915         if (err) {
1916                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1917                 goto fail_init_tbls;
1918         }
1919
1920         return 0;
1921
1922 fail_init_tbls:
1923         rte_free(hw->pkg_copy);
1924 fail_exit:
1925         rte_free(buf);
1926         return err;
1927 }
1928
1929 static void
1930 ice_base_queue_get(struct ice_pf *pf)
1931 {
1932         uint32_t reg;
1933         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1934
1935         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1936         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1937                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1938         } else {
1939                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1940                                         " index");
1941         }
1942 }
1943
1944 static int
1945 parse_bool(const char *key, const char *value, void *args)
1946 {
1947         int *i = (int *)args;
1948         char *end;
1949         int num;
1950
1951         num = strtoul(value, &end, 10);
1952
1953         if (num != 0 && num != 1) {
1954                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1955                         "value must be 0 or 1",
1956                         value, key);
1957                 return -1;
1958         }
1959
1960         *i = num;
1961         return 0;
1962 }
1963
1964 static int ice_parse_devargs(struct rte_eth_dev *dev)
1965 {
1966         struct ice_adapter *ad =
1967                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1968         struct rte_devargs *devargs = dev->device->devargs;
1969         struct rte_kvargs *kvlist;
1970         int ret;
1971
1972         if (devargs == NULL)
1973                 return 0;
1974
1975         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1976         if (kvlist == NULL) {
1977                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1978                 return -EINVAL;
1979         }
1980
1981         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1982         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1983                sizeof(ad->devargs.proto_xtr));
1984
1985         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1986                                  &handle_proto_xtr_arg, &ad->devargs);
1987         if (ret)
1988                 goto bail;
1989
1990         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1991                                  &parse_bool, &ad->devargs.safe_mode_support);
1992         if (ret)
1993                 goto bail;
1994
1995         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1996                                  &parse_bool, &ad->devargs.pipe_mode_support);
1997         if (ret)
1998                 goto bail;
1999
2000         ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
2001                                  &parse_bool, &ad->devargs.flow_mark_support);
2002         if (ret)
2003                 goto bail;
2004
2005 bail:
2006         rte_kvargs_free(kvlist);
2007         return ret;
2008 }
2009
2010 /* Forward LLDP packets to default VSI by set switch rules */
2011 static int
2012 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
2013 {
2014         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2015         struct ice_fltr_list_entry *s_list_itr = NULL;
2016         struct LIST_HEAD_TYPE list_head;
2017         int ret = 0;
2018
2019         INIT_LIST_HEAD(&list_head);
2020
2021         s_list_itr = (struct ice_fltr_list_entry *)
2022                         ice_malloc(hw, sizeof(*s_list_itr));
2023         if (!s_list_itr)
2024                 return -ENOMEM;
2025         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2026         s_list_itr->fltr_info.vsi_handle = vsi->idx;
2027         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2028                         RTE_ETHER_TYPE_LLDP;
2029         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2030         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2031         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2032         LIST_ADD(&s_list_itr->list_entry, &list_head);
2033         if (on)
2034                 ret = ice_add_eth_mac(hw, &list_head);
2035         else
2036                 ret = ice_remove_eth_mac(hw, &list_head);
2037
2038         rte_free(s_list_itr);
2039         return ret;
2040 }
2041
2042 static enum ice_status
2043 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2044                 uint16_t num, uint16_t desc_id,
2045                 uint16_t *prof_buf, uint16_t *num_prof)
2046 {
2047         struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2048         int ret;
2049         uint16_t buf_len;
2050         bool res_shared = 1;
2051         struct ice_aq_desc aq_desc;
2052         struct ice_sq_cd *cd = NULL;
2053         struct ice_aqc_get_allocd_res_desc *cmd =
2054                         &aq_desc.params.get_res_desc;
2055
2056         buf_len = sizeof(resp_buf->elem) * num;
2057         resp_buf = ice_malloc(hw, buf_len);
2058         if (!resp_buf)
2059                 return -ENOMEM;
2060
2061         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2062                         ice_aqc_opc_get_allocd_res_desc);
2063
2064         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2065                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2066                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2067         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2068
2069         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2070         if (!ret)
2071                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2072         else
2073                 goto exit;
2074
2075         ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2076                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2077
2078 exit:
2079         rte_free(resp_buf);
2080         return ret;
2081 }
2082 static int
2083 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2084 {
2085         int ret;
2086         uint16_t prof_id;
2087         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2088         uint16_t first_desc = 1;
2089         uint16_t num_prof = 0;
2090
2091         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2092                         first_desc, prof_buf, &num_prof);
2093         if (ret) {
2094                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2095                 return ret;
2096         }
2097
2098         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2099                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2100                 if (ret) {
2101                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2102                         return ret;
2103                 }
2104         }
2105         return 0;
2106 }
2107
2108 static int
2109 ice_reset_fxp_resource(struct ice_hw *hw)
2110 {
2111         int ret;
2112
2113         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2114         if (ret) {
2115                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2116                 return ret;
2117         }
2118
2119         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2120         if (ret) {
2121                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2122                 return ret;
2123         }
2124
2125         return 0;
2126 }
2127
2128 static int
2129 ice_dev_init(struct rte_eth_dev *dev)
2130 {
2131         struct rte_pci_device *pci_dev;
2132         struct rte_intr_handle *intr_handle;
2133         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2135         struct ice_adapter *ad =
2136                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2137         struct ice_vsi *vsi;
2138         int ret;
2139
2140         dev->dev_ops = &ice_eth_dev_ops;
2141         dev->rx_pkt_burst = ice_recv_pkts;
2142         dev->tx_pkt_burst = ice_xmit_pkts;
2143         dev->tx_pkt_prepare = ice_prep_pkts;
2144
2145         /* for secondary processes, we don't initialise any further as primary
2146          * has already done this work.
2147          */
2148         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2149                 ice_set_rx_function(dev);
2150                 ice_set_tx_function(dev);
2151                 return 0;
2152         }
2153
2154         ice_set_default_ptype_table(dev);
2155         pci_dev = RTE_DEV_TO_PCI(dev->device);
2156         intr_handle = &pci_dev->intr_handle;
2157
2158         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2159         pf->adapter->eth_dev = dev;
2160         pf->dev_data = dev->data;
2161         hw->back = pf->adapter;
2162         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2163         hw->vendor_id = pci_dev->id.vendor_id;
2164         hw->device_id = pci_dev->id.device_id;
2165         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2166         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2167         hw->bus.device = pci_dev->addr.devid;
2168         hw->bus.func = pci_dev->addr.function;
2169
2170         ret = ice_parse_devargs(dev);
2171         if (ret) {
2172                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2173                 return -EINVAL;
2174         }
2175
2176         ice_init_controlq_parameter(hw);
2177
2178         ret = ice_init_hw(hw);
2179         if (ret) {
2180                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2181                 return -EINVAL;
2182         }
2183
2184         ret = ice_load_pkg(dev);
2185         if (ret) {
2186                 if (ad->devargs.safe_mode_support == 0) {
2187                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2188                                         "Use safe-mode-support=1 to enter Safe Mode");
2189                         return ret;
2190                 }
2191
2192                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2193                                         "Entering Safe Mode");
2194                 ad->is_safe_mode = 1;
2195         }
2196
2197         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2198                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2199                      hw->api_maj_ver, hw->api_min_ver);
2200
2201         ice_pf_sw_init(dev);
2202         ret = ice_init_mac_address(dev);
2203         if (ret) {
2204                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2205                 goto err_init_mac;
2206         }
2207
2208         /* Pass the information to the rte_eth_dev_close() that it should also
2209          * release the private port resources.
2210          */
2211         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2212
2213         ret = ice_res_pool_init(&pf->msix_pool, 1,
2214                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2215         if (ret) {
2216                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2217                 goto err_msix_pool_init;
2218         }
2219
2220         ret = ice_pf_setup(pf);
2221         if (ret) {
2222                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2223                 goto err_pf_setup;
2224         }
2225
2226         ret = ice_send_driver_ver(hw);
2227         if (ret) {
2228                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2229                 goto err_pf_setup;
2230         }
2231
2232         vsi = pf->main_vsi;
2233
2234         /* Disable double vlan by default */
2235         ice_vsi_config_double_vlan(vsi, false);
2236
2237         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2238         if (ret != ICE_SUCCESS)
2239                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2240         ret = ice_init_dcb(hw, true);
2241         if (ret != ICE_SUCCESS)
2242                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2243         /* Forward LLDP packets to default VSI */
2244         ret = ice_vsi_config_sw_lldp(vsi, true);
2245         if (ret != ICE_SUCCESS)
2246                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2247         /* register callback func to eal lib */
2248         rte_intr_callback_register(intr_handle,
2249                                    ice_interrupt_handler, dev);
2250
2251         ice_pf_enable_irq0(hw);
2252
2253         /* enable uio intr after callback register */
2254         rte_intr_enable(intr_handle);
2255
2256         /* get base queue pairs index  in the device */
2257         ice_base_queue_get(pf);
2258
2259         if (!ad->is_safe_mode) {
2260                 ret = ice_flow_init(ad);
2261                 if (ret) {
2262                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2263                         return ret;
2264                 }
2265         }
2266
2267         ret = ice_reset_fxp_resource(hw);
2268         if (ret) {
2269                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2270                 return ret;
2271         }
2272
2273         return 0;
2274
2275 err_pf_setup:
2276         ice_res_pool_destroy(&pf->msix_pool);
2277 err_msix_pool_init:
2278         rte_free(dev->data->mac_addrs);
2279         dev->data->mac_addrs = NULL;
2280 err_init_mac:
2281         ice_sched_cleanup_all(hw);
2282         rte_free(hw->port_info);
2283         ice_shutdown_all_ctrlq(hw);
2284         rte_free(pf->proto_xtr);
2285
2286         return ret;
2287 }
2288
2289 int
2290 ice_release_vsi(struct ice_vsi *vsi)
2291 {
2292         struct ice_hw *hw;
2293         struct ice_vsi_ctx vsi_ctx;
2294         enum ice_status ret;
2295
2296         if (!vsi)
2297                 return 0;
2298
2299         hw = ICE_VSI_TO_HW(vsi);
2300
2301         ice_remove_all_mac_vlan_filters(vsi);
2302
2303         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2304
2305         vsi_ctx.vsi_num = vsi->vsi_id;
2306         vsi_ctx.info = vsi->info;
2307         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2308         if (ret != ICE_SUCCESS) {
2309                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2310                 rte_free(vsi);
2311                 return -1;
2312         }
2313
2314         rte_free(vsi);
2315         return 0;
2316 }
2317
2318 void
2319 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2320 {
2321         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2322         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2323         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2324         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2325         uint16_t msix_intr, i;
2326
2327         /* disable interrupt and also clear all the exist config */
2328         for (i = 0; i < vsi->nb_qps; i++) {
2329                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2330                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2331                 rte_wmb();
2332         }
2333
2334         if (rte_intr_allow_others(intr_handle))
2335                 /* vfio-pci */
2336                 for (i = 0; i < vsi->nb_msix; i++) {
2337                         msix_intr = vsi->msix_intr + i;
2338                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2339                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2340                 }
2341         else
2342                 /* igb_uio */
2343                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2344 }
2345
2346 static void
2347 ice_dev_stop(struct rte_eth_dev *dev)
2348 {
2349         struct rte_eth_dev_data *data = dev->data;
2350         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2351         struct ice_vsi *main_vsi = pf->main_vsi;
2352         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2353         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2354         uint16_t i;
2355
2356         /* avoid stopping again */
2357         if (pf->adapter_stopped)
2358                 return;
2359
2360         /* stop and clear all Rx queues */
2361         for (i = 0; i < data->nb_rx_queues; i++)
2362                 ice_rx_queue_stop(dev, i);
2363
2364         /* stop and clear all Tx queues */
2365         for (i = 0; i < data->nb_tx_queues; i++)
2366                 ice_tx_queue_stop(dev, i);
2367
2368         /* disable all queue interrupts */
2369         ice_vsi_disable_queues_intr(main_vsi);
2370
2371         if (pf->init_link_up)
2372                 ice_dev_set_link_up(dev);
2373         else
2374                 ice_dev_set_link_down(dev);
2375
2376         /* Clean datapath event and queue/vec mapping */
2377         rte_intr_efd_disable(intr_handle);
2378         if (intr_handle->intr_vec) {
2379                 rte_free(intr_handle->intr_vec);
2380                 intr_handle->intr_vec = NULL;
2381         }
2382
2383         pf->adapter_stopped = true;
2384 }
2385
2386 static void
2387 ice_dev_close(struct rte_eth_dev *dev)
2388 {
2389         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2390         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2392         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2393         struct ice_adapter *ad =
2394                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2395
2396         /* Since stop will make link down, then the link event will be
2397          * triggered, disable the irq firstly to avoid the port_infoe etc
2398          * resources deallocation causing the interrupt service thread
2399          * crash.
2400          */
2401         ice_pf_disable_irq0(hw);
2402
2403         ice_dev_stop(dev);
2404
2405         if (!ad->is_safe_mode)
2406                 ice_flow_uninit(ad);
2407
2408         /* release all queue resource */
2409         ice_free_queues(dev);
2410
2411         ice_res_pool_destroy(&pf->msix_pool);
2412         ice_release_vsi(pf->main_vsi);
2413         ice_sched_cleanup_all(hw);
2414         ice_free_hw_tbls(hw);
2415         rte_free(hw->port_info);
2416         hw->port_info = NULL;
2417         ice_shutdown_all_ctrlq(hw);
2418         rte_free(pf->proto_xtr);
2419         pf->proto_xtr = NULL;
2420
2421         dev->dev_ops = NULL;
2422         dev->rx_pkt_burst = NULL;
2423         dev->tx_pkt_burst = NULL;
2424
2425         rte_free(dev->data->mac_addrs);
2426         dev->data->mac_addrs = NULL;
2427
2428         /* disable uio intr before callback unregister */
2429         rte_intr_disable(intr_handle);
2430
2431         /* unregister callback func from eal lib */
2432         rte_intr_callback_unregister(intr_handle,
2433                                      ice_interrupt_handler, dev);
2434 }
2435
2436 static int
2437 ice_dev_uninit(struct rte_eth_dev *dev)
2438 {
2439         ice_dev_close(dev);
2440
2441         return 0;
2442 }
2443
2444 static void
2445 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2446 {
2447         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2448         struct ice_vsi *vsi = pf->main_vsi;
2449         int ret;
2450
2451         /* Configure RSS for IPv4 with src/dst addr as input set */
2452         if (rss_hf & ETH_RSS_IPV4) {
2453                 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2454                                       ICE_FLOW_SEG_HDR_IPV4 |
2455                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2456                 if (ret)
2457                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2458                                     __func__, ret);
2459         }
2460
2461         /* Configure RSS for IPv6 with src/dst addr as input set */
2462         if (rss_hf & ETH_RSS_IPV6) {
2463                 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2464                                       ICE_FLOW_SEG_HDR_IPV6 |
2465                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2466                 if (ret)
2467                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2468                                     __func__, ret);
2469         }
2470
2471         /* Configure RSS for udp4 with src/dst addr and port as input set */
2472         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2473                 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2474                                       ICE_FLOW_SEG_HDR_UDP |
2475                                       ICE_FLOW_SEG_HDR_IPV4 |
2476                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2477                 if (ret)
2478                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2479                                     __func__, ret);
2480         }
2481
2482         /* Configure RSS for udp6 with src/dst addr and port as input set */
2483         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2484                 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2485                                       ICE_FLOW_SEG_HDR_UDP |
2486                                       ICE_FLOW_SEG_HDR_IPV6 |
2487                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2488                 if (ret)
2489                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2490                                     __func__, ret);
2491         }
2492
2493         /* Configure RSS for tcp4 with src/dst addr and port as input set */
2494         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2495                 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2496                                       ICE_FLOW_SEG_HDR_TCP |
2497                                       ICE_FLOW_SEG_HDR_IPV4 |
2498                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2499                 if (ret)
2500                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2501                                     __func__, ret);
2502         }
2503
2504         /* Configure RSS for tcp6 with src/dst addr and port as input set */
2505         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2506                 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2507                                       ICE_FLOW_SEG_HDR_TCP |
2508                                       ICE_FLOW_SEG_HDR_IPV6 |
2509                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2510                 if (ret)
2511                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2512                                     __func__, ret);
2513         }
2514
2515         /* Configure RSS for sctp4 with src/dst addr and port as input set */
2516         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2517                 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2518                                       ICE_FLOW_SEG_HDR_SCTP |
2519                                       ICE_FLOW_SEG_HDR_IPV4 |
2520                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2521                 if (ret)
2522                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2523                                     __func__, ret);
2524         }
2525
2526         /* Configure RSS for sctp6 with src/dst addr and port as input set */
2527         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2528                 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2529                                       ICE_FLOW_SEG_HDR_SCTP |
2530                                       ICE_FLOW_SEG_HDR_IPV6 |
2531                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2532                 if (ret)
2533                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2534                                     __func__, ret);
2535         }
2536 }
2537
2538 static int ice_init_rss(struct ice_pf *pf)
2539 {
2540         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2541         struct ice_vsi *vsi = pf->main_vsi;
2542         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2543         struct rte_eth_rss_conf *rss_conf;
2544         struct ice_aqc_get_set_rss_keys key;
2545         uint16_t i, nb_q;
2546         int ret = 0;
2547         bool is_safe_mode = pf->adapter->is_safe_mode;
2548         uint32_t reg;
2549
2550         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2551         nb_q = dev->data->nb_rx_queues;
2552         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2553         vsi->rss_lut_size = pf->hash_lut_size;
2554
2555         if (is_safe_mode) {
2556                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2557                 return 0;
2558         }
2559
2560         if (!vsi->rss_key)
2561                 vsi->rss_key = rte_zmalloc(NULL,
2562                                            vsi->rss_key_size, 0);
2563         if (!vsi->rss_lut)
2564                 vsi->rss_lut = rte_zmalloc(NULL,
2565                                            vsi->rss_lut_size, 0);
2566
2567         /* configure RSS key */
2568         if (!rss_conf->rss_key) {
2569                 /* Calculate the default hash key */
2570                 for (i = 0; i <= vsi->rss_key_size; i++)
2571                         vsi->rss_key[i] = (uint8_t)rte_rand();
2572         } else {
2573                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2574                            RTE_MIN(rss_conf->rss_key_len,
2575                                    vsi->rss_key_size));
2576         }
2577         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2578         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2579         if (ret)
2580                 return -EINVAL;
2581
2582         /* init RSS LUT table */
2583         for (i = 0; i < vsi->rss_lut_size; i++)
2584                 vsi->rss_lut[i] = i % nb_q;
2585
2586         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2587                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2588                                  vsi->rss_lut, vsi->rss_lut_size);
2589         if (ret)
2590                 return -EINVAL;
2591
2592         /* Enable registers for symmetric_toeplitz function. */
2593         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2594         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2595                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2596         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2597
2598         /* RSS hash configuration */
2599         ice_rss_hash_set(pf, rss_conf->rss_hf);
2600
2601         return 0;
2602 }
2603
2604 static int
2605 ice_dev_configure(struct rte_eth_dev *dev)
2606 {
2607         struct ice_adapter *ad =
2608                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2609         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2610         int ret;
2611
2612         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2613          * bulk allocation or vector Rx preconditions we will reset it.
2614          */
2615         ad->rx_bulk_alloc_allowed = true;
2616         ad->tx_simple_allowed = true;
2617
2618         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2619                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2620
2621         ret = ice_init_rss(pf);
2622         if (ret) {
2623                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2624                 return ret;
2625         }
2626
2627         return 0;
2628 }
2629
2630 static void
2631 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2632                        int base_queue, int nb_queue)
2633 {
2634         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2635         uint32_t val, val_tx;
2636         int i;
2637
2638         for (i = 0; i < nb_queue; i++) {
2639                 /*do actual bind*/
2640                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2641                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2642                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2643                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2644
2645                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2646                             base_queue + i, msix_vect);
2647                 /* set ITR0 value */
2648                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2649                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2650                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2651         }
2652 }
2653
2654 void
2655 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2656 {
2657         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2658         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2659         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2660         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2661         uint16_t msix_vect = vsi->msix_intr;
2662         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2663         uint16_t queue_idx = 0;
2664         int record = 0;
2665         int i;
2666
2667         /* clear Rx/Tx queue interrupt */
2668         for (i = 0; i < vsi->nb_used_qps; i++) {
2669                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2670                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2671         }
2672
2673         /* PF bind interrupt */
2674         if (rte_intr_dp_is_en(intr_handle)) {
2675                 queue_idx = 0;
2676                 record = 1;
2677         }
2678
2679         for (i = 0; i < vsi->nb_used_qps; i++) {
2680                 if (nb_msix <= 1) {
2681                         if (!rte_intr_allow_others(intr_handle))
2682                                 msix_vect = ICE_MISC_VEC_ID;
2683
2684                         /* uio mapping all queue to one msix_vect */
2685                         __vsi_queues_bind_intr(vsi, msix_vect,
2686                                                vsi->base_queue + i,
2687                                                vsi->nb_used_qps - i);
2688
2689                         for (; !!record && i < vsi->nb_used_qps; i++)
2690                                 intr_handle->intr_vec[queue_idx + i] =
2691                                         msix_vect;
2692                         break;
2693                 }
2694
2695                 /* vfio 1:1 queue/msix_vect mapping */
2696                 __vsi_queues_bind_intr(vsi, msix_vect,
2697                                        vsi->base_queue + i, 1);
2698
2699                 if (!!record)
2700                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2701
2702                 msix_vect++;
2703                 nb_msix--;
2704         }
2705 }
2706
2707 void
2708 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2709 {
2710         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2711         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2712         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2713         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2714         uint16_t msix_intr, i;
2715
2716         if (rte_intr_allow_others(intr_handle))
2717                 for (i = 0; i < vsi->nb_used_qps; i++) {
2718                         msix_intr = vsi->msix_intr + i;
2719                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2720                                       GLINT_DYN_CTL_INTENA_M |
2721                                       GLINT_DYN_CTL_CLEARPBA_M |
2722                                       GLINT_DYN_CTL_ITR_INDX_M |
2723                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2724                 }
2725         else
2726                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2727                               GLINT_DYN_CTL_INTENA_M |
2728                               GLINT_DYN_CTL_CLEARPBA_M |
2729                               GLINT_DYN_CTL_ITR_INDX_M |
2730                               GLINT_DYN_CTL_WB_ON_ITR_M);
2731 }
2732
2733 static int
2734 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2735 {
2736         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2737         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2738         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2739         struct ice_vsi *vsi = pf->main_vsi;
2740         uint32_t intr_vector = 0;
2741
2742         rte_intr_disable(intr_handle);
2743
2744         /* check and configure queue intr-vector mapping */
2745         if ((rte_intr_cap_multiple(intr_handle) ||
2746              !RTE_ETH_DEV_SRIOV(dev).active) &&
2747             dev->data->dev_conf.intr_conf.rxq != 0) {
2748                 intr_vector = dev->data->nb_rx_queues;
2749                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2750                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2751                                     ICE_MAX_INTR_QUEUE_NUM);
2752                         return -ENOTSUP;
2753                 }
2754                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2755                         return -1;
2756         }
2757
2758         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2759                 intr_handle->intr_vec =
2760                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2761                             0);
2762                 if (!intr_handle->intr_vec) {
2763                         PMD_DRV_LOG(ERR,
2764                                     "Failed to allocate %d rx_queues intr_vec",
2765                                     dev->data->nb_rx_queues);
2766                         return -ENOMEM;
2767                 }
2768         }
2769
2770         /* Map queues with MSIX interrupt */
2771         vsi->nb_used_qps = dev->data->nb_rx_queues;
2772         ice_vsi_queues_bind_intr(vsi);
2773
2774         /* Enable interrupts for all the queues */
2775         ice_vsi_enable_queues_intr(vsi);
2776
2777         rte_intr_enable(intr_handle);
2778
2779         return 0;
2780 }
2781
2782 static void
2783 ice_get_init_link_status(struct rte_eth_dev *dev)
2784 {
2785         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2787         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2788         struct ice_link_status link_status;
2789         int ret;
2790
2791         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
2792                                    &link_status, NULL);
2793         if (ret != ICE_SUCCESS) {
2794                 PMD_DRV_LOG(ERR, "Failed to get link info");
2795                 pf->init_link_up = false;
2796                 return;
2797         }
2798
2799         if (link_status.link_info & ICE_AQ_LINK_UP)
2800                 pf->init_link_up = true;
2801 }
2802
2803 static int
2804 ice_dev_start(struct rte_eth_dev *dev)
2805 {
2806         struct rte_eth_dev_data *data = dev->data;
2807         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2809         struct ice_vsi *vsi = pf->main_vsi;
2810         uint16_t nb_rxq = 0;
2811         uint16_t nb_txq, i;
2812         uint16_t max_frame_size;
2813         int mask, ret;
2814
2815         /* program Tx queues' context in hardware */
2816         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2817                 ret = ice_tx_queue_start(dev, nb_txq);
2818                 if (ret) {
2819                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2820                         goto tx_err;
2821                 }
2822         }
2823
2824         /* program Rx queues' context in hardware*/
2825         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2826                 ret = ice_rx_queue_start(dev, nb_rxq);
2827                 if (ret) {
2828                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2829                         goto rx_err;
2830                 }
2831         }
2832
2833         ice_set_rx_function(dev);
2834         ice_set_tx_function(dev);
2835
2836         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2837                         ETH_VLAN_EXTEND_MASK;
2838         ret = ice_vlan_offload_set(dev, mask);
2839         if (ret) {
2840                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2841                 goto rx_err;
2842         }
2843
2844         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2845         if (ice_rxq_intr_setup(dev))
2846                 return -EIO;
2847
2848         /* Enable receiving broadcast packets and transmitting packets */
2849         ret = ice_set_vsi_promisc(hw, vsi->idx,
2850                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2851                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2852                                   0);
2853         if (ret != ICE_SUCCESS)
2854                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2855
2856         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2857                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2858                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2859                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2860                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2861                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2862                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2863                                      NULL);
2864         if (ret != ICE_SUCCESS)
2865                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2866
2867         ice_get_init_link_status(dev);
2868
2869         ice_dev_set_link_up(dev);
2870
2871         /* Call get_link_info aq commond to enable/disable LSE */
2872         ice_link_update(dev, 0);
2873
2874         pf->adapter_stopped = false;
2875
2876         /* Set the max frame size to default value*/
2877         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2878                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2879                 ICE_FRAME_SIZE_MAX;
2880
2881         /* Set the max frame size to HW*/
2882         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2883
2884         return 0;
2885
2886         /* stop the started queues if failed to start all queues */
2887 rx_err:
2888         for (i = 0; i < nb_rxq; i++)
2889                 ice_rx_queue_stop(dev, i);
2890 tx_err:
2891         for (i = 0; i < nb_txq; i++)
2892                 ice_tx_queue_stop(dev, i);
2893
2894         return -EIO;
2895 }
2896
2897 static int
2898 ice_dev_reset(struct rte_eth_dev *dev)
2899 {
2900         int ret;
2901
2902         if (dev->data->sriov.active)
2903                 return -ENOTSUP;
2904
2905         ret = ice_dev_uninit(dev);
2906         if (ret) {
2907                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2908                 return -ENXIO;
2909         }
2910
2911         ret = ice_dev_init(dev);
2912         if (ret) {
2913                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2914                 return -ENXIO;
2915         }
2916
2917         return 0;
2918 }
2919
2920 static int
2921 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2922 {
2923         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2924         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2925         struct ice_vsi *vsi = pf->main_vsi;
2926         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2927         bool is_safe_mode = pf->adapter->is_safe_mode;
2928         u64 phy_type_low;
2929         u64 phy_type_high;
2930
2931         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2932         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2933         dev_info->max_rx_queues = vsi->nb_qps;
2934         dev_info->max_tx_queues = vsi->nb_qps;
2935         dev_info->max_mac_addrs = vsi->max_macaddrs;
2936         dev_info->max_vfs = pci_dev->max_vfs;
2937         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2938         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2939
2940         dev_info->rx_offload_capa =
2941                 DEV_RX_OFFLOAD_VLAN_STRIP |
2942                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2943                 DEV_RX_OFFLOAD_KEEP_CRC |
2944                 DEV_RX_OFFLOAD_SCATTER |
2945                 DEV_RX_OFFLOAD_VLAN_FILTER;
2946         dev_info->tx_offload_capa =
2947                 DEV_TX_OFFLOAD_VLAN_INSERT |
2948                 DEV_TX_OFFLOAD_TCP_TSO |
2949                 DEV_TX_OFFLOAD_MULTI_SEGS |
2950                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2951         dev_info->flow_type_rss_offloads = 0;
2952
2953         if (!is_safe_mode) {
2954                 dev_info->rx_offload_capa |=
2955                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2956                         DEV_RX_OFFLOAD_UDP_CKSUM |
2957                         DEV_RX_OFFLOAD_TCP_CKSUM |
2958                         DEV_RX_OFFLOAD_QINQ_STRIP |
2959                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2960                         DEV_RX_OFFLOAD_VLAN_EXTEND |
2961                         DEV_RX_OFFLOAD_RSS_HASH;
2962                 dev_info->tx_offload_capa |=
2963                         DEV_TX_OFFLOAD_QINQ_INSERT |
2964                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2965                         DEV_TX_OFFLOAD_UDP_CKSUM |
2966                         DEV_TX_OFFLOAD_TCP_CKSUM |
2967                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2968                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2969                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2970                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2971         }
2972
2973         dev_info->rx_queue_offload_capa = 0;
2974         dev_info->tx_queue_offload_capa = 0;
2975
2976         dev_info->reta_size = pf->hash_lut_size;
2977         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2978
2979         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2980                 .rx_thresh = {
2981                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2982                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2983                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2984                 },
2985                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2986                 .rx_drop_en = 0,
2987                 .offloads = 0,
2988         };
2989
2990         dev_info->default_txconf = (struct rte_eth_txconf) {
2991                 .tx_thresh = {
2992                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2993                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2994                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2995                 },
2996                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2997                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2998                 .offloads = 0,
2999         };
3000
3001         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3002                 .nb_max = ICE_MAX_RING_DESC,
3003                 .nb_min = ICE_MIN_RING_DESC,
3004                 .nb_align = ICE_ALIGN_RING_DESC,
3005         };
3006
3007         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3008                 .nb_max = ICE_MAX_RING_DESC,
3009                 .nb_min = ICE_MIN_RING_DESC,
3010                 .nb_align = ICE_ALIGN_RING_DESC,
3011         };
3012
3013         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3014                                ETH_LINK_SPEED_100M |
3015                                ETH_LINK_SPEED_1G |
3016                                ETH_LINK_SPEED_2_5G |
3017                                ETH_LINK_SPEED_5G |
3018                                ETH_LINK_SPEED_10G |
3019                                ETH_LINK_SPEED_20G |
3020                                ETH_LINK_SPEED_25G;
3021
3022         phy_type_low = hw->port_info->phy.phy_type_low;
3023         phy_type_high = hw->port_info->phy.phy_type_high;
3024
3025         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3026                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3027
3028         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3029                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3030                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3031
3032         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3033         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3034
3035         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3036         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3037         dev_info->default_rxportconf.nb_queues = 1;
3038         dev_info->default_txportconf.nb_queues = 1;
3039         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3040         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3041
3042         return 0;
3043 }
3044
3045 static inline int
3046 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3047                             struct rte_eth_link *link)
3048 {
3049         struct rte_eth_link *dst = link;
3050         struct rte_eth_link *src = &dev->data->dev_link;
3051
3052         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3053                                 *(uint64_t *)src) == 0)
3054                 return -1;
3055
3056         return 0;
3057 }
3058
3059 static inline int
3060 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3061                              struct rte_eth_link *link)
3062 {
3063         struct rte_eth_link *dst = &dev->data->dev_link;
3064         struct rte_eth_link *src = link;
3065
3066         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3067                                 *(uint64_t *)src) == 0)
3068                 return -1;
3069
3070         return 0;
3071 }
3072
3073 static int
3074 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3075 {
3076 #define CHECK_INTERVAL 100  /* 100ms */
3077 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3078         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079         struct ice_link_status link_status;
3080         struct rte_eth_link link, old;
3081         int status;
3082         unsigned int rep_cnt = MAX_REPEAT_TIME;
3083         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3084
3085         memset(&link, 0, sizeof(link));
3086         memset(&old, 0, sizeof(old));
3087         memset(&link_status, 0, sizeof(link_status));
3088         ice_atomic_read_link_status(dev, &old);
3089
3090         do {
3091                 /* Get link status information from hardware */
3092                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3093                                               &link_status, NULL);
3094                 if (status != ICE_SUCCESS) {
3095                         link.link_speed = ETH_SPEED_NUM_100M;
3096                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3097                         PMD_DRV_LOG(ERR, "Failed to get link info");
3098                         goto out;
3099                 }
3100
3101                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3102                 if (!wait_to_complete || link.link_status)
3103                         break;
3104
3105                 rte_delay_ms(CHECK_INTERVAL);
3106         } while (--rep_cnt);
3107
3108         if (!link.link_status)
3109                 goto out;
3110
3111         /* Full-duplex operation at all supported speeds */
3112         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3113
3114         /* Parse the link status */
3115         switch (link_status.link_speed) {
3116         case ICE_AQ_LINK_SPEED_10MB:
3117                 link.link_speed = ETH_SPEED_NUM_10M;
3118                 break;
3119         case ICE_AQ_LINK_SPEED_100MB:
3120                 link.link_speed = ETH_SPEED_NUM_100M;
3121                 break;
3122         case ICE_AQ_LINK_SPEED_1000MB:
3123                 link.link_speed = ETH_SPEED_NUM_1G;
3124                 break;
3125         case ICE_AQ_LINK_SPEED_2500MB:
3126                 link.link_speed = ETH_SPEED_NUM_2_5G;
3127                 break;
3128         case ICE_AQ_LINK_SPEED_5GB:
3129                 link.link_speed = ETH_SPEED_NUM_5G;
3130                 break;
3131         case ICE_AQ_LINK_SPEED_10GB:
3132                 link.link_speed = ETH_SPEED_NUM_10G;
3133                 break;
3134         case ICE_AQ_LINK_SPEED_20GB:
3135                 link.link_speed = ETH_SPEED_NUM_20G;
3136                 break;
3137         case ICE_AQ_LINK_SPEED_25GB:
3138                 link.link_speed = ETH_SPEED_NUM_25G;
3139                 break;
3140         case ICE_AQ_LINK_SPEED_40GB:
3141                 link.link_speed = ETH_SPEED_NUM_40G;
3142                 break;
3143         case ICE_AQ_LINK_SPEED_50GB:
3144                 link.link_speed = ETH_SPEED_NUM_50G;
3145                 break;
3146         case ICE_AQ_LINK_SPEED_100GB:
3147                 link.link_speed = ETH_SPEED_NUM_100G;
3148                 break;
3149         case ICE_AQ_LINK_SPEED_UNKNOWN:
3150         default:
3151                 PMD_DRV_LOG(ERR, "Unknown link speed");
3152                 link.link_speed = ETH_SPEED_NUM_NONE;
3153                 break;
3154         }
3155
3156         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3157                               ETH_LINK_SPEED_FIXED);
3158
3159 out:
3160         ice_atomic_write_link_status(dev, &link);
3161         if (link.link_status == old.link_status)
3162                 return -1;
3163
3164         return 0;
3165 }
3166
3167 /* Force the physical link state by getting the current PHY capabilities from
3168  * hardware and setting the PHY config based on the determined capabilities. If
3169  * link changes, link event will be triggered because both the Enable Automatic
3170  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3171  */
3172 static enum ice_status
3173 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3174 {
3175         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3176         struct ice_aqc_get_phy_caps_data *pcaps;
3177         struct ice_port_info *pi;
3178         enum ice_status status;
3179
3180         if (!hw || !hw->port_info)
3181                 return ICE_ERR_PARAM;
3182
3183         pi = hw->port_info;
3184
3185         pcaps = (struct ice_aqc_get_phy_caps_data *)
3186                 ice_malloc(hw, sizeof(*pcaps));
3187         if (!pcaps)
3188                 return ICE_ERR_NO_MEMORY;
3189
3190         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3191                                      NULL);
3192         if (status)
3193                 goto out;
3194
3195         /* No change in link */
3196         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3197             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3198                 goto out;
3199
3200         cfg.phy_type_low = pcaps->phy_type_low;
3201         cfg.phy_type_high = pcaps->phy_type_high;
3202         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3203         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3204         cfg.eee_cap = pcaps->eee_cap;
3205         cfg.eeer_value = pcaps->eeer_value;
3206         cfg.link_fec_opt = pcaps->link_fec_options;
3207         if (link_up)
3208                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3209         else
3210                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3211
3212         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3213
3214 out:
3215         ice_free(hw, pcaps);
3216         return status;
3217 }
3218
3219 static int
3220 ice_dev_set_link_up(struct rte_eth_dev *dev)
3221 {
3222         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3223
3224         return ice_force_phys_link_state(hw, true);
3225 }
3226
3227 static int
3228 ice_dev_set_link_down(struct rte_eth_dev *dev)
3229 {
3230         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3231
3232         return ice_force_phys_link_state(hw, false);
3233 }
3234
3235 static int
3236 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3237 {
3238         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3239         struct rte_eth_dev_data *dev_data = pf->dev_data;
3240         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3241
3242         /* check if mtu is within the allowed range */
3243         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3244                 return -EINVAL;
3245
3246         /* mtu setting is forbidden if port is start */
3247         if (dev_data->dev_started) {
3248                 PMD_DRV_LOG(ERR,
3249                             "port %d must be stopped before configuration",
3250                             dev_data->port_id);
3251                 return -EBUSY;
3252         }
3253
3254         if (frame_size > RTE_ETHER_MAX_LEN)
3255                 dev_data->dev_conf.rxmode.offloads |=
3256                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3257         else
3258                 dev_data->dev_conf.rxmode.offloads &=
3259                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3260
3261         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3262
3263         return 0;
3264 }
3265
3266 static int ice_macaddr_set(struct rte_eth_dev *dev,
3267                            struct rte_ether_addr *mac_addr)
3268 {
3269         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3270         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3271         struct ice_vsi *vsi = pf->main_vsi;
3272         struct ice_mac_filter *f;
3273         uint8_t flags = 0;
3274         int ret;
3275
3276         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3277                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3278                 return -EINVAL;
3279         }
3280
3281         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3282                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3283                         break;
3284         }
3285
3286         if (!f) {
3287                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3288                 return -EIO;
3289         }
3290
3291         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3292         if (ret != ICE_SUCCESS) {
3293                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3294                 return -EIO;
3295         }
3296         ret = ice_add_mac_filter(vsi, mac_addr);
3297         if (ret != ICE_SUCCESS) {
3298                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3299                 return -EIO;
3300         }
3301         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3302
3303         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3304         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3305         if (ret != ICE_SUCCESS)
3306                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3307
3308         return 0;
3309 }
3310
3311 /* Add a MAC address, and update filters */
3312 static int
3313 ice_macaddr_add(struct rte_eth_dev *dev,
3314                 struct rte_ether_addr *mac_addr,
3315                 __rte_unused uint32_t index,
3316                 __rte_unused uint32_t pool)
3317 {
3318         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3319         struct ice_vsi *vsi = pf->main_vsi;
3320         int ret;
3321
3322         ret = ice_add_mac_filter(vsi, mac_addr);
3323         if (ret != ICE_SUCCESS) {
3324                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3325                 return -EINVAL;
3326         }
3327
3328         return ICE_SUCCESS;
3329 }
3330
3331 /* Remove a MAC address, and update filters */
3332 static void
3333 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3334 {
3335         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3336         struct ice_vsi *vsi = pf->main_vsi;
3337         struct rte_eth_dev_data *data = dev->data;
3338         struct rte_ether_addr *macaddr;
3339         int ret;
3340
3341         macaddr = &data->mac_addrs[index];
3342         ret = ice_remove_mac_filter(vsi, macaddr);
3343         if (ret) {
3344                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3345                 return;
3346         }
3347 }
3348
3349 static int
3350 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3351 {
3352         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3353         struct ice_vsi *vsi = pf->main_vsi;
3354         int ret;
3355
3356         PMD_INIT_FUNC_TRACE();
3357
3358         if (on) {
3359                 ret = ice_add_vlan_filter(vsi, vlan_id);
3360                 if (ret < 0) {
3361                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3362                         return -EINVAL;
3363                 }
3364         } else {
3365                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3366                 if (ret < 0) {
3367                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3368                         return -EINVAL;
3369                 }
3370         }
3371
3372         return 0;
3373 }
3374
3375 /* Configure vlan filter on or off */
3376 static int
3377 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3378 {
3379         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3380         struct ice_vsi_ctx ctxt;
3381         uint8_t sec_flags, sw_flags2;
3382         int ret = 0;
3383
3384         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3385                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3386         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3387
3388         if (on) {
3389                 vsi->info.sec_flags |= sec_flags;
3390                 vsi->info.sw_flags2 |= sw_flags2;
3391         } else {
3392                 vsi->info.sec_flags &= ~sec_flags;
3393                 vsi->info.sw_flags2 &= ~sw_flags2;
3394         }
3395         vsi->info.sw_id = hw->port_info->sw_id;
3396         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3397         ctxt.info.valid_sections =
3398                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3399                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3400         ctxt.vsi_num = vsi->vsi_id;
3401
3402         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3403         if (ret) {
3404                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3405                             on ? "enable" : "disable");
3406                 return -EINVAL;
3407         } else {
3408                 vsi->info.valid_sections |=
3409                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3410                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3411         }
3412
3413         /* consist with other drivers, allow untagged packet when vlan filter on */
3414         if (on)
3415                 ret = ice_add_vlan_filter(vsi, 0);
3416         else
3417                 ret = ice_remove_vlan_filter(vsi, 0);
3418
3419         return 0;
3420 }
3421
3422 static int
3423 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3424 {
3425         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3426         struct ice_vsi_ctx ctxt;
3427         uint8_t vlan_flags;
3428         int ret = 0;
3429
3430         /* Check if it has been already on or off */
3431         if (vsi->info.valid_sections &
3432                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3433                 if (on) {
3434                         if ((vsi->info.vlan_flags &
3435                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3436                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3437                                 return 0; /* already on */
3438                 } else {
3439                         if ((vsi->info.vlan_flags &
3440                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3441                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3442                                 return 0; /* already off */
3443                 }
3444         }
3445
3446         if (on)
3447                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3448         else
3449                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3450         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3451         vsi->info.vlan_flags |= vlan_flags;
3452         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3453         ctxt.info.valid_sections =
3454                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3455         ctxt.vsi_num = vsi->vsi_id;
3456         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3457         if (ret) {
3458                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3459                             on ? "enable" : "disable");
3460                 return -EINVAL;
3461         }
3462
3463         vsi->info.valid_sections |=
3464                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3465
3466         return ret;
3467 }
3468
3469 static int
3470 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3471 {
3472         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3473         struct ice_vsi *vsi = pf->main_vsi;
3474         struct rte_eth_rxmode *rxmode;
3475
3476         rxmode = &dev->data->dev_conf.rxmode;
3477         if (mask & ETH_VLAN_FILTER_MASK) {
3478                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3479                         ice_vsi_config_vlan_filter(vsi, true);
3480                 else
3481                         ice_vsi_config_vlan_filter(vsi, false);
3482         }
3483
3484         if (mask & ETH_VLAN_STRIP_MASK) {
3485                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3486                         ice_vsi_config_vlan_stripping(vsi, true);
3487                 else
3488                         ice_vsi_config_vlan_stripping(vsi, false);
3489         }
3490
3491         if (mask & ETH_VLAN_EXTEND_MASK) {
3492                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3493                         ice_vsi_config_double_vlan(vsi, true);
3494                 else
3495                         ice_vsi_config_double_vlan(vsi, false);
3496         }
3497
3498         return 0;
3499 }
3500
3501 static int
3502 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3503 {
3504         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3505         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3506         int ret;
3507
3508         if (!lut)
3509                 return -EINVAL;
3510
3511         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3512                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3513                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3514                 if (ret) {
3515                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3516                         return -EINVAL;
3517                 }
3518         } else {
3519                 uint64_t *lut_dw = (uint64_t *)lut;
3520                 uint16_t i, lut_size_dw = lut_size / 4;
3521
3522                 for (i = 0; i < lut_size_dw; i++)
3523                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3524         }
3525
3526         return 0;
3527 }
3528
3529 static int
3530 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3531 {
3532         struct ice_pf *pf;
3533         struct ice_hw *hw;
3534         int ret;
3535
3536         if (!vsi || !lut)
3537                 return -EINVAL;
3538
3539         pf = ICE_VSI_TO_PF(vsi);
3540         hw = ICE_VSI_TO_HW(vsi);
3541
3542         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3543                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3544                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3545                 if (ret) {
3546                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3547                         return -EINVAL;
3548                 }
3549         } else {
3550                 uint64_t *lut_dw = (uint64_t *)lut;
3551                 uint16_t i, lut_size_dw = lut_size / 4;
3552
3553                 for (i = 0; i < lut_size_dw; i++)
3554                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3555
3556                 ice_flush(hw);
3557         }
3558
3559         return 0;
3560 }
3561
3562 static int
3563 ice_rss_reta_update(struct rte_eth_dev *dev,
3564                     struct rte_eth_rss_reta_entry64 *reta_conf,
3565                     uint16_t reta_size)
3566 {
3567         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3568         uint16_t i, lut_size = pf->hash_lut_size;
3569         uint16_t idx, shift;
3570         uint8_t *lut;
3571         int ret;
3572
3573         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3574             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3575             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3576                 PMD_DRV_LOG(ERR,
3577                             "The size of hash lookup table configured (%d)"
3578                             "doesn't match the number hardware can "
3579                             "supported (128, 512, 2048)",
3580                             reta_size);
3581                 return -EINVAL;
3582         }
3583
3584         /* It MUST use the current LUT size to get the RSS lookup table,
3585          * otherwise if will fail with -100 error code.
3586          */
3587         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3588         if (!lut) {
3589                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3590                 return -ENOMEM;
3591         }
3592         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3593         if (ret)
3594                 goto out;
3595
3596         for (i = 0; i < reta_size; i++) {
3597                 idx = i / RTE_RETA_GROUP_SIZE;
3598                 shift = i % RTE_RETA_GROUP_SIZE;
3599                 if (reta_conf[idx].mask & (1ULL << shift))
3600                         lut[i] = reta_conf[idx].reta[shift];
3601         }
3602         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3603         if (ret == 0 && lut_size != reta_size) {
3604                 PMD_DRV_LOG(INFO,
3605                             "The size of hash lookup table is changed from (%d) to (%d)",
3606                             lut_size, reta_size);
3607                 pf->hash_lut_size = reta_size;
3608         }
3609
3610 out:
3611         rte_free(lut);
3612
3613         return ret;
3614 }
3615
3616 static int
3617 ice_rss_reta_query(struct rte_eth_dev *dev,
3618                    struct rte_eth_rss_reta_entry64 *reta_conf,
3619                    uint16_t reta_size)
3620 {
3621         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3622         uint16_t i, lut_size = pf->hash_lut_size;
3623         uint16_t idx, shift;
3624         uint8_t *lut;
3625         int ret;
3626
3627         if (reta_size != lut_size) {
3628                 PMD_DRV_LOG(ERR,
3629                             "The size of hash lookup table configured (%d)"
3630                             "doesn't match the number hardware can "
3631                             "supported (%d)",
3632                             reta_size, lut_size);
3633                 return -EINVAL;
3634         }
3635
3636         lut = rte_zmalloc(NULL, reta_size, 0);
3637         if (!lut) {
3638                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3639                 return -ENOMEM;
3640         }
3641
3642         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3643         if (ret)
3644                 goto out;
3645
3646         for (i = 0; i < reta_size; i++) {
3647                 idx = i / RTE_RETA_GROUP_SIZE;
3648                 shift = i % RTE_RETA_GROUP_SIZE;
3649                 if (reta_conf[idx].mask & (1ULL << shift))
3650                         reta_conf[idx].reta[shift] = lut[i];
3651         }
3652
3653 out:
3654         rte_free(lut);
3655
3656         return ret;
3657 }
3658
3659 static int
3660 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3661 {
3662         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3663         int ret = 0;
3664
3665         if (!key || key_len == 0) {
3666                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3667                 return 0;
3668         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3669                    sizeof(uint32_t)) {
3670                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3671                 return -EINVAL;
3672         }
3673
3674         struct ice_aqc_get_set_rss_keys *key_dw =
3675                 (struct ice_aqc_get_set_rss_keys *)key;
3676
3677         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3678         if (ret) {
3679                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3680                 ret = -EINVAL;
3681         }
3682
3683         return ret;
3684 }
3685
3686 static int
3687 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3688 {
3689         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3690         int ret;
3691
3692         if (!key || !key_len)
3693                 return -EINVAL;
3694
3695         ret = ice_aq_get_rss_key
3696                 (hw, vsi->idx,
3697                  (struct ice_aqc_get_set_rss_keys *)key);
3698         if (ret) {
3699                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3700                 return -EINVAL;
3701         }
3702         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3703
3704         return 0;
3705 }
3706
3707 static int
3708 ice_rss_hash_update(struct rte_eth_dev *dev,
3709                     struct rte_eth_rss_conf *rss_conf)
3710 {
3711         enum ice_status status = ICE_SUCCESS;
3712         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3713         struct ice_vsi *vsi = pf->main_vsi;
3714
3715         /* set hash key */
3716         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3717         if (status)
3718                 return status;
3719
3720         if (rss_conf->rss_hf == 0)
3721                 return 0;
3722
3723         /* RSS hash configuration */
3724         ice_rss_hash_set(pf, rss_conf->rss_hf);
3725
3726         return 0;
3727 }
3728
3729 static int
3730 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3731                       struct rte_eth_rss_conf *rss_conf)
3732 {
3733         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3734         struct ice_vsi *vsi = pf->main_vsi;
3735
3736         ice_get_rss_key(vsi, rss_conf->rss_key,
3737                         &rss_conf->rss_key_len);
3738
3739         /* TODO: default set to 0 as hf config is not supported now */
3740         rss_conf->rss_hf = 0;
3741         return 0;
3742 }
3743
3744 static int
3745 ice_promisc_enable(struct rte_eth_dev *dev)
3746 {
3747         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3748         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3749         struct ice_vsi *vsi = pf->main_vsi;
3750         enum ice_status status;
3751         uint8_t pmask;
3752         int ret = 0;
3753
3754         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3755                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3756
3757         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3758         switch (status) {
3759         case ICE_ERR_ALREADY_EXISTS:
3760                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3761         case ICE_SUCCESS:
3762                 break;
3763         default:
3764                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3765                 ret = -EAGAIN;
3766         }
3767
3768         return ret;
3769 }
3770
3771 static int
3772 ice_promisc_disable(struct rte_eth_dev *dev)
3773 {
3774         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3775         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3776         struct ice_vsi *vsi = pf->main_vsi;
3777         enum ice_status status;
3778         uint8_t pmask;
3779         int ret = 0;
3780
3781         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3782                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3783
3784         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3785         if (status != ICE_SUCCESS) {
3786                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3787                 ret = -EAGAIN;
3788         }
3789
3790         return ret;
3791 }
3792
3793 static int
3794 ice_allmulti_enable(struct rte_eth_dev *dev)
3795 {
3796         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3797         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3798         struct ice_vsi *vsi = pf->main_vsi;
3799         enum ice_status status;
3800         uint8_t pmask;
3801         int ret = 0;
3802
3803         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3804
3805         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3806
3807         switch (status) {
3808         case ICE_ERR_ALREADY_EXISTS:
3809                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3810         case ICE_SUCCESS:
3811                 break;
3812         default:
3813                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3814                 ret = -EAGAIN;
3815         }
3816
3817         return ret;
3818 }
3819
3820 static int
3821 ice_allmulti_disable(struct rte_eth_dev *dev)
3822 {
3823         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3824         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3825         struct ice_vsi *vsi = pf->main_vsi;
3826         enum ice_status status;
3827         uint8_t pmask;
3828         int ret = 0;
3829
3830         if (dev->data->promiscuous == 1)
3831                 return 0; /* must remain in all_multicast mode */
3832
3833         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3834
3835         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3836         if (status != ICE_SUCCESS) {
3837                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3838                 ret = -EAGAIN;
3839         }
3840
3841         return ret;
3842 }
3843
3844 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3845                                     uint16_t queue_id)
3846 {
3847         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3848         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3849         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3850         uint32_t val;
3851         uint16_t msix_intr;
3852
3853         msix_intr = intr_handle->intr_vec[queue_id];
3854
3855         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3856               GLINT_DYN_CTL_ITR_INDX_M;
3857         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3858
3859         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3860         rte_intr_ack(&pci_dev->intr_handle);
3861
3862         return 0;
3863 }
3864
3865 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3866                                      uint16_t queue_id)
3867 {
3868         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3869         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3870         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3871         uint16_t msix_intr;
3872
3873         msix_intr = intr_handle->intr_vec[queue_id];
3874
3875         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3876
3877         return 0;
3878 }
3879
3880 static int
3881 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3882 {
3883         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3884         u8 ver, patch;
3885         u16 build;
3886         int ret;
3887
3888         ver = hw->nvm.orom.major;
3889         patch = hw->nvm.orom.patch;
3890         build = hw->nvm.orom.build;
3891
3892         ret = snprintf(fw_version, fw_size,
3893                         "%d.%d 0x%08x %d.%d.%d",
3894                         hw->nvm.major_ver,
3895                         hw->nvm.minor_ver,
3896                         hw->nvm.eetrack,
3897                         ver, build, patch);
3898
3899         /* add the size of '\0' */
3900         ret += 1;
3901         if (fw_size < (u32)ret)
3902                 return ret;
3903         else
3904                 return 0;
3905 }
3906
3907 static int
3908 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3909 {
3910         struct ice_hw *hw;
3911         struct ice_vsi_ctx ctxt;
3912         uint8_t vlan_flags = 0;
3913         int ret;
3914
3915         if (!vsi || !info) {
3916                 PMD_DRV_LOG(ERR, "invalid parameters");
3917                 return -EINVAL;
3918         }
3919
3920         if (info->on) {
3921                 vsi->info.pvid = info->config.pvid;
3922                 /**
3923                  * If insert pvid is enabled, only tagged pkts are
3924                  * allowed to be sent out.
3925                  */
3926                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3927                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3928         } else {
3929                 vsi->info.pvid = 0;
3930                 if (info->config.reject.tagged == 0)
3931                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3932
3933                 if (info->config.reject.untagged == 0)
3934                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3935         }
3936         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3937                                   ICE_AQ_VSI_VLAN_MODE_M);
3938         vsi->info.vlan_flags |= vlan_flags;
3939         memset(&ctxt, 0, sizeof(ctxt));
3940         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3941         ctxt.info.valid_sections =
3942                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3943         ctxt.vsi_num = vsi->vsi_id;
3944
3945         hw = ICE_VSI_TO_HW(vsi);
3946         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3947         if (ret != ICE_SUCCESS) {
3948                 PMD_DRV_LOG(ERR,
3949                             "update VSI for VLAN insert failed, err %d",
3950                             ret);
3951                 return -EINVAL;
3952         }
3953
3954         vsi->info.valid_sections |=
3955                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3956
3957         return ret;
3958 }
3959
3960 static int
3961 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3962 {
3963         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3964         struct ice_vsi *vsi = pf->main_vsi;
3965         struct rte_eth_dev_data *data = pf->dev_data;
3966         struct ice_vsi_vlan_pvid_info info;
3967         int ret;
3968
3969         memset(&info, 0, sizeof(info));
3970         info.on = on;
3971         if (info.on) {
3972                 info.config.pvid = pvid;
3973         } else {
3974                 info.config.reject.tagged =
3975                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3976                 info.config.reject.untagged =
3977                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3978         }
3979
3980         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3981         if (ret < 0) {
3982                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3983                 return -EINVAL;
3984         }
3985
3986         return 0;
3987 }
3988
3989 static int
3990 ice_get_eeprom_length(struct rte_eth_dev *dev)
3991 {
3992         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3993
3994         /* Convert word count to byte count */
3995         return hw->nvm.sr_words << 1;
3996 }
3997
3998 static int
3999 ice_get_eeprom(struct rte_eth_dev *dev,
4000                struct rte_dev_eeprom_info *eeprom)
4001 {
4002         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4003         uint16_t *data = eeprom->data;
4004         uint16_t first_word, last_word, nwords;
4005         enum ice_status status = ICE_SUCCESS;
4006
4007         first_word = eeprom->offset >> 1;
4008         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
4009         nwords = last_word - first_word + 1;
4010
4011         if (first_word >= hw->nvm.sr_words ||
4012             last_word >= hw->nvm.sr_words) {
4013                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
4014                 return -EINVAL;
4015         }
4016
4017         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4018
4019         status = ice_read_sr_buf(hw, first_word, &nwords, data);
4020         if (status) {
4021                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4022                 eeprom->length = sizeof(uint16_t) * nwords;
4023                 return -EIO;
4024         }
4025
4026         return 0;
4027 }
4028
4029 static void
4030 ice_stat_update_32(struct ice_hw *hw,
4031                    uint32_t reg,
4032                    bool offset_loaded,
4033                    uint64_t *offset,
4034                    uint64_t *stat)
4035 {
4036         uint64_t new_data;
4037
4038         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4039         if (!offset_loaded)
4040                 *offset = new_data;
4041
4042         if (new_data >= *offset)
4043                 *stat = (uint64_t)(new_data - *offset);
4044         else
4045                 *stat = (uint64_t)((new_data +
4046                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4047                                    - *offset);
4048 }
4049
4050 static void
4051 ice_stat_update_40(struct ice_hw *hw,
4052                    uint32_t hireg,
4053                    uint32_t loreg,
4054                    bool offset_loaded,
4055                    uint64_t *offset,
4056                    uint64_t *stat)
4057 {
4058         uint64_t new_data;
4059
4060         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4061         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4062                     ICE_32_BIT_WIDTH;
4063
4064         if (!offset_loaded)
4065                 *offset = new_data;
4066
4067         if (new_data >= *offset)
4068                 *stat = new_data - *offset;
4069         else
4070                 *stat = (uint64_t)((new_data +
4071                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4072                                    *offset);
4073
4074         *stat &= ICE_40_BIT_MASK;
4075 }
4076
4077 /* Get all the statistics of a VSI */
4078 static void
4079 ice_update_vsi_stats(struct ice_vsi *vsi)
4080 {
4081         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4082         struct ice_eth_stats *nes = &vsi->eth_stats;
4083         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4084         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4085
4086         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4087                            vsi->offset_loaded, &oes->rx_bytes,
4088                            &nes->rx_bytes);
4089         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4090                            vsi->offset_loaded, &oes->rx_unicast,
4091                            &nes->rx_unicast);
4092         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4093                            vsi->offset_loaded, &oes->rx_multicast,
4094                            &nes->rx_multicast);
4095         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4096                            vsi->offset_loaded, &oes->rx_broadcast,
4097                            &nes->rx_broadcast);
4098         /* exclude CRC bytes */
4099         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4100                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4101
4102         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4103                            &oes->rx_discards, &nes->rx_discards);
4104         /* GLV_REPC not supported */
4105         /* GLV_RMPC not supported */
4106         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4107                            &oes->rx_unknown_protocol,
4108                            &nes->rx_unknown_protocol);
4109         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4110                            vsi->offset_loaded, &oes->tx_bytes,
4111                            &nes->tx_bytes);
4112         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4113                            vsi->offset_loaded, &oes->tx_unicast,
4114                            &nes->tx_unicast);
4115         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4116                            vsi->offset_loaded, &oes->tx_multicast,
4117                            &nes->tx_multicast);
4118         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4119                            vsi->offset_loaded,  &oes->tx_broadcast,
4120                            &nes->tx_broadcast);
4121         /* GLV_TDPC not supported */
4122         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4123                            &oes->tx_errors, &nes->tx_errors);
4124         vsi->offset_loaded = true;
4125
4126         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4127                     vsi->vsi_id);
4128         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4129         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4130         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4131         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4132         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4133         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4134                     nes->rx_unknown_protocol);
4135         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4136         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4137         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4138         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4139         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4140         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4141         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4142                     vsi->vsi_id);
4143 }
4144
4145 static void
4146 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4147 {
4148         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4149         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4150
4151         /* Get statistics of struct ice_eth_stats */
4152         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4153                            GLPRT_GORCL(hw->port_info->lport),
4154                            pf->offset_loaded, &os->eth.rx_bytes,
4155                            &ns->eth.rx_bytes);
4156         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4157                            GLPRT_UPRCL(hw->port_info->lport),
4158                            pf->offset_loaded, &os->eth.rx_unicast,
4159                            &ns->eth.rx_unicast);
4160         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4161                            GLPRT_MPRCL(hw->port_info->lport),
4162                            pf->offset_loaded, &os->eth.rx_multicast,
4163                            &ns->eth.rx_multicast);
4164         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4165                            GLPRT_BPRCL(hw->port_info->lport),
4166                            pf->offset_loaded, &os->eth.rx_broadcast,
4167                            &ns->eth.rx_broadcast);
4168         ice_stat_update_32(hw, PRTRPB_RDPC,
4169                            pf->offset_loaded, &os->eth.rx_discards,
4170                            &ns->eth.rx_discards);
4171
4172         /* Workaround: CRC size should not be included in byte statistics,
4173          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4174          * packet.
4175          */
4176         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4177                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4178
4179         /* GLPRT_REPC not supported */
4180         /* GLPRT_RMPC not supported */
4181         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4182                            pf->offset_loaded,
4183                            &os->eth.rx_unknown_protocol,
4184                            &ns->eth.rx_unknown_protocol);
4185         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4186                            GLPRT_GOTCL(hw->port_info->lport),
4187                            pf->offset_loaded, &os->eth.tx_bytes,
4188                            &ns->eth.tx_bytes);
4189         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4190                            GLPRT_UPTCL(hw->port_info->lport),
4191                            pf->offset_loaded, &os->eth.tx_unicast,
4192                            &ns->eth.tx_unicast);
4193         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4194                            GLPRT_MPTCL(hw->port_info->lport),
4195                            pf->offset_loaded, &os->eth.tx_multicast,
4196                            &ns->eth.tx_multicast);
4197         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4198                            GLPRT_BPTCL(hw->port_info->lport),
4199                            pf->offset_loaded, &os->eth.tx_broadcast,
4200                            &ns->eth.tx_broadcast);
4201         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4202                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4203
4204         /* GLPRT_TEPC not supported */
4205
4206         /* additional port specific stats */
4207         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4208                            pf->offset_loaded, &os->tx_dropped_link_down,
4209                            &ns->tx_dropped_link_down);
4210         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4211                            pf->offset_loaded, &os->crc_errors,
4212                            &ns->crc_errors);
4213         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4214                            pf->offset_loaded, &os->illegal_bytes,
4215                            &ns->illegal_bytes);
4216         /* GLPRT_ERRBC not supported */
4217         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4218                            pf->offset_loaded, &os->mac_local_faults,
4219                            &ns->mac_local_faults);
4220         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4221                            pf->offset_loaded, &os->mac_remote_faults,
4222                            &ns->mac_remote_faults);
4223
4224         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4225                            pf->offset_loaded, &os->rx_len_errors,
4226                            &ns->rx_len_errors);
4227
4228         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4229                            pf->offset_loaded, &os->link_xon_rx,
4230                            &ns->link_xon_rx);
4231         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4232                            pf->offset_loaded, &os->link_xoff_rx,
4233                            &ns->link_xoff_rx);
4234         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4235                            pf->offset_loaded, &os->link_xon_tx,
4236                            &ns->link_xon_tx);
4237         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4238                            pf->offset_loaded, &os->link_xoff_tx,
4239                            &ns->link_xoff_tx);
4240         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4241                            GLPRT_PRC64L(hw->port_info->lport),
4242                            pf->offset_loaded, &os->rx_size_64,
4243                            &ns->rx_size_64);
4244         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4245                            GLPRT_PRC127L(hw->port_info->lport),
4246                            pf->offset_loaded, &os->rx_size_127,
4247                            &ns->rx_size_127);
4248         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4249                            GLPRT_PRC255L(hw->port_info->lport),
4250                            pf->offset_loaded, &os->rx_size_255,
4251                            &ns->rx_size_255);
4252         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4253                            GLPRT_PRC511L(hw->port_info->lport),
4254                            pf->offset_loaded, &os->rx_size_511,
4255                            &ns->rx_size_511);
4256         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4257                            GLPRT_PRC1023L(hw->port_info->lport),
4258                            pf->offset_loaded, &os->rx_size_1023,
4259                            &ns->rx_size_1023);
4260         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4261                            GLPRT_PRC1522L(hw->port_info->lport),
4262                            pf->offset_loaded, &os->rx_size_1522,
4263                            &ns->rx_size_1522);
4264         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4265                            GLPRT_PRC9522L(hw->port_info->lport),
4266                            pf->offset_loaded, &os->rx_size_big,
4267                            &ns->rx_size_big);
4268         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4269                            pf->offset_loaded, &os->rx_undersize,
4270                            &ns->rx_undersize);
4271         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4272                            pf->offset_loaded, &os->rx_fragments,
4273                            &ns->rx_fragments);
4274         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4275                            pf->offset_loaded, &os->rx_oversize,
4276                            &ns->rx_oversize);
4277         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4278                            pf->offset_loaded, &os->rx_jabber,
4279                            &ns->rx_jabber);
4280         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4281                            GLPRT_PTC64L(hw->port_info->lport),
4282                            pf->offset_loaded, &os->tx_size_64,
4283                            &ns->tx_size_64);
4284         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4285                            GLPRT_PTC127L(hw->port_info->lport),
4286                            pf->offset_loaded, &os->tx_size_127,
4287                            &ns->tx_size_127);
4288         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4289                            GLPRT_PTC255L(hw->port_info->lport),
4290                            pf->offset_loaded, &os->tx_size_255,
4291                            &ns->tx_size_255);
4292         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4293                            GLPRT_PTC511L(hw->port_info->lport),
4294                            pf->offset_loaded, &os->tx_size_511,
4295                            &ns->tx_size_511);
4296         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4297                            GLPRT_PTC1023L(hw->port_info->lport),
4298                            pf->offset_loaded, &os->tx_size_1023,
4299                            &ns->tx_size_1023);
4300         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4301                            GLPRT_PTC1522L(hw->port_info->lport),
4302                            pf->offset_loaded, &os->tx_size_1522,
4303                            &ns->tx_size_1522);
4304         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4305                            GLPRT_PTC9522L(hw->port_info->lport),
4306                            pf->offset_loaded, &os->tx_size_big,
4307                            &ns->tx_size_big);
4308
4309         /* GLPRT_MSPDC not supported */
4310         /* GLPRT_XEC not supported */
4311
4312         pf->offset_loaded = true;
4313
4314         if (pf->main_vsi)
4315                 ice_update_vsi_stats(pf->main_vsi);
4316 }
4317
4318 /* Get all statistics of a port */
4319 static int
4320 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4321 {
4322         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4323         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4324         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4325
4326         /* call read registers - updates values, now write them to struct */
4327         ice_read_stats_registers(pf, hw);
4328
4329         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4330                           pf->main_vsi->eth_stats.rx_multicast +
4331                           pf->main_vsi->eth_stats.rx_broadcast -
4332                           pf->main_vsi->eth_stats.rx_discards;
4333         stats->opackets = ns->eth.tx_unicast +
4334                           ns->eth.tx_multicast +
4335                           ns->eth.tx_broadcast;
4336         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4337         stats->obytes   = ns->eth.tx_bytes;
4338         stats->oerrors  = ns->eth.tx_errors +
4339                           pf->main_vsi->eth_stats.tx_errors;
4340
4341         /* Rx Errors */
4342         stats->imissed  = ns->eth.rx_discards +
4343                           pf->main_vsi->eth_stats.rx_discards;
4344         stats->ierrors  = ns->crc_errors +
4345                           ns->rx_undersize +
4346                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4347
4348         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4349         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4350         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4351         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4352         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4353         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4354         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4355                     pf->main_vsi->eth_stats.rx_discards);
4356         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4357                     ns->eth.rx_unknown_protocol);
4358         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4359         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4360         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4361         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4362         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4363         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4364                     pf->main_vsi->eth_stats.tx_discards);
4365         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4366
4367         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4368                     ns->tx_dropped_link_down);
4369         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4370         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4371                     ns->illegal_bytes);
4372         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4373         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4374                     ns->mac_local_faults);
4375         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4376                     ns->mac_remote_faults);
4377         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4378         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4379         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4380         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4381         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4382         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4383         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4384         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4385         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4386         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4387         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4388         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4389         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4390         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4391         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4392         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4393         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4394         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4395         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4396         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4397         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4398         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4399         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4400         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4401         return 0;
4402 }
4403
4404 /* Reset the statistics */
4405 static int
4406 ice_stats_reset(struct rte_eth_dev *dev)
4407 {
4408         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4409         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4410
4411         /* Mark PF and VSI stats to update the offset, aka "reset" */
4412         pf->offset_loaded = false;
4413         if (pf->main_vsi)
4414                 pf->main_vsi->offset_loaded = false;
4415
4416         /* read the stats, reading current register values into offset */
4417         ice_read_stats_registers(pf, hw);
4418
4419         return 0;
4420 }
4421
4422 static uint32_t
4423 ice_xstats_calc_num(void)
4424 {
4425         uint32_t num;
4426
4427         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4428
4429         return num;
4430 }
4431
4432 static int
4433 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4434                unsigned int n)
4435 {
4436         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4437         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4438         unsigned int i;
4439         unsigned int count;
4440         struct ice_hw_port_stats *hw_stats = &pf->stats;
4441
4442         count = ice_xstats_calc_num();
4443         if (n < count)
4444                 return count;
4445
4446         ice_read_stats_registers(pf, hw);
4447
4448         if (!xstats)
4449                 return 0;
4450
4451         count = 0;
4452
4453         /* Get stats from ice_eth_stats struct */
4454         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4455                 xstats[count].value =
4456                         *(uint64_t *)((char *)&hw_stats->eth +
4457                                       ice_stats_strings[i].offset);
4458                 xstats[count].id = count;
4459                 count++;
4460         }
4461
4462         /* Get individiual stats from ice_hw_port struct */
4463         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4464                 xstats[count].value =
4465                         *(uint64_t *)((char *)hw_stats +
4466                                       ice_hw_port_strings[i].offset);
4467                 xstats[count].id = count;
4468                 count++;
4469         }
4470
4471         return count;
4472 }
4473
4474 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4475                                 struct rte_eth_xstat_name *xstats_names,
4476                                 __rte_unused unsigned int limit)
4477 {
4478         unsigned int count = 0;
4479         unsigned int i;
4480
4481         if (!xstats_names)
4482                 return ice_xstats_calc_num();
4483
4484         /* Note: limit checked in rte_eth_xstats_names() */
4485
4486         /* Get stats from ice_eth_stats struct */
4487         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4488                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4489                         sizeof(xstats_names[count].name));
4490                 count++;
4491         }
4492
4493         /* Get individiual stats from ice_hw_port struct */
4494         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4495                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4496                         sizeof(xstats_names[count].name));
4497                 count++;
4498         }
4499
4500         return count;
4501 }
4502
4503 static int
4504 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4505                      enum rte_filter_type filter_type,
4506                      enum rte_filter_op filter_op,
4507                      void *arg)
4508 {
4509         int ret = 0;
4510
4511         if (!dev)
4512                 return -EINVAL;
4513
4514         switch (filter_type) {
4515         case RTE_ETH_FILTER_GENERIC:
4516                 if (filter_op != RTE_ETH_FILTER_GET)
4517                         return -EINVAL;
4518                 *(const void **)arg = &ice_flow_ops;
4519                 break;
4520         default:
4521                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4522                                         filter_type);
4523                 ret = -EINVAL;
4524                 break;
4525         }
4526
4527         return ret;
4528 }
4529
4530 /* Add UDP tunneling port */
4531 static int
4532 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4533                              struct rte_eth_udp_tunnel *udp_tunnel)
4534 {
4535         int ret = 0;
4536         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4537
4538         if (udp_tunnel == NULL)
4539                 return -EINVAL;
4540
4541         switch (udp_tunnel->prot_type) {
4542         case RTE_TUNNEL_TYPE_VXLAN:
4543                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4544                 break;
4545         default:
4546                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4547                 ret = -EINVAL;
4548                 break;
4549         }
4550
4551         return ret;
4552 }
4553
4554 /* Delete UDP tunneling port */
4555 static int
4556 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4557                              struct rte_eth_udp_tunnel *udp_tunnel)
4558 {
4559         int ret = 0;
4560         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4561
4562         if (udp_tunnel == NULL)
4563                 return -EINVAL;
4564
4565         switch (udp_tunnel->prot_type) {
4566         case RTE_TUNNEL_TYPE_VXLAN:
4567                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4568                 break;
4569         default:
4570                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4571                 ret = -EINVAL;
4572                 break;
4573         }
4574
4575         return ret;
4576 }
4577
4578 static int
4579 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4580               struct rte_pci_device *pci_dev)
4581 {
4582         return rte_eth_dev_pci_generic_probe(pci_dev,
4583                                              sizeof(struct ice_adapter),
4584                                              ice_dev_init);
4585 }
4586
4587 static int
4588 ice_pci_remove(struct rte_pci_device *pci_dev)
4589 {
4590         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4591 }
4592
4593 static struct rte_pci_driver rte_ice_pmd = {
4594         .id_table = pci_id_ice_map,
4595         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4596         .probe = ice_pci_probe,
4597         .remove = ice_pci_remove,
4598 };
4599
4600 /**
4601  * Driver initialization routine.
4602  * Invoked once at EAL init time.
4603  * Register itself as the [Poll Mode] Driver of PCI devices.
4604  */
4605 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4606 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4607 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4608 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4609                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4610                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4611                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
4612                               ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
4613
4614 RTE_INIT(ice_init_log)
4615 {
4616         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4617         if (ice_logtype_init >= 0)
4618                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4619         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4620         if (ice_logtype_driver >= 0)
4621                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4622
4623 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4624         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4625         if (ice_logtype_rx >= 0)
4626                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4627 #endif
4628
4629 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4630         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4631         if (ice_logtype_tx >= 0)
4632                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4633 #endif
4634
4635 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4636         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4637         if (ice_logtype_tx_free >= 0)
4638                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4639 #endif
4640 }