1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
18 #include "rte_pmd_ice.h"
19 #include "ice_ethdev.h"
21 #include "ice_generic_flow.h"
24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
26 #define ICE_PROTO_XTR_ARG "proto_xtr"
28 static const char * const ice_valid_args[] = {
29 ICE_SAFE_MODE_SUPPORT_ARG,
30 ICE_PIPELINE_MODE_SUPPORT_ARG,
35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
36 .name = "ice_dynfield_proto_xtr_metadata",
37 .size = sizeof(uint32_t),
38 .align = __alignof__(uint32_t),
42 struct proto_xtr_ol_flag {
43 const struct rte_mbuf_dynflag param;
48 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
50 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
51 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
53 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
54 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
56 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
57 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
58 [PROTO_XTR_IPV6_FLOW] = {
59 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
60 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
62 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
63 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
66 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
68 /* DDP package search path */
69 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
70 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
71 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
72 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
74 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
75 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
76 #define ICE_MAX_PKG_FILENAME_SIZE 256
77 #define ICE_MAX_RES_DESC_NUM 1024
80 int ice_logtype_driver;
81 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
84 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
87 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
88 int ice_logtype_tx_free;
91 static int ice_dev_configure(struct rte_eth_dev *dev);
92 static int ice_dev_start(struct rte_eth_dev *dev);
93 static void ice_dev_stop(struct rte_eth_dev *dev);
94 static void ice_dev_close(struct rte_eth_dev *dev);
95 static int ice_dev_reset(struct rte_eth_dev *dev);
96 static int ice_dev_info_get(struct rte_eth_dev *dev,
97 struct rte_eth_dev_info *dev_info);
98 static int ice_link_update(struct rte_eth_dev *dev,
99 int wait_to_complete);
100 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
101 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
103 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
104 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
105 static int ice_rss_reta_update(struct rte_eth_dev *dev,
106 struct rte_eth_rss_reta_entry64 *reta_conf,
108 static int ice_rss_reta_query(struct rte_eth_dev *dev,
109 struct rte_eth_rss_reta_entry64 *reta_conf,
111 static int ice_rss_hash_update(struct rte_eth_dev *dev,
112 struct rte_eth_rss_conf *rss_conf);
113 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
114 struct rte_eth_rss_conf *rss_conf);
115 static int ice_promisc_enable(struct rte_eth_dev *dev);
116 static int ice_promisc_disable(struct rte_eth_dev *dev);
117 static int ice_allmulti_enable(struct rte_eth_dev *dev);
118 static int ice_allmulti_disable(struct rte_eth_dev *dev);
119 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
122 static int ice_macaddr_set(struct rte_eth_dev *dev,
123 struct rte_ether_addr *mac_addr);
124 static int ice_macaddr_add(struct rte_eth_dev *dev,
125 struct rte_ether_addr *mac_addr,
126 __rte_unused uint32_t index,
128 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
129 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
131 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
133 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
135 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
136 uint16_t pvid, int on);
137 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
138 static int ice_get_eeprom(struct rte_eth_dev *dev,
139 struct rte_dev_eeprom_info *eeprom);
140 static int ice_stats_get(struct rte_eth_dev *dev,
141 struct rte_eth_stats *stats);
142 static int ice_stats_reset(struct rte_eth_dev *dev);
143 static int ice_xstats_get(struct rte_eth_dev *dev,
144 struct rte_eth_xstat *xstats, unsigned int n);
145 static int ice_xstats_get_names(struct rte_eth_dev *dev,
146 struct rte_eth_xstat_name *xstats_names,
148 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
149 enum rte_filter_type filter_type,
150 enum rte_filter_op filter_op,
152 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
153 struct rte_eth_udp_tunnel *udp_tunnel);
154 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
155 struct rte_eth_udp_tunnel *udp_tunnel);
157 static const struct rte_pci_id pci_id_ice_map[] = {
158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
159 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
164 { .vendor_id = 0, /* sentinel */ },
167 static const struct eth_dev_ops ice_eth_dev_ops = {
168 .dev_configure = ice_dev_configure,
169 .dev_start = ice_dev_start,
170 .dev_stop = ice_dev_stop,
171 .dev_close = ice_dev_close,
172 .dev_reset = ice_dev_reset,
173 .dev_set_link_up = ice_dev_set_link_up,
174 .dev_set_link_down = ice_dev_set_link_down,
175 .rx_queue_start = ice_rx_queue_start,
176 .rx_queue_stop = ice_rx_queue_stop,
177 .tx_queue_start = ice_tx_queue_start,
178 .tx_queue_stop = ice_tx_queue_stop,
179 .rx_queue_setup = ice_rx_queue_setup,
180 .rx_queue_release = ice_rx_queue_release,
181 .tx_queue_setup = ice_tx_queue_setup,
182 .tx_queue_release = ice_tx_queue_release,
183 .dev_infos_get = ice_dev_info_get,
184 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
185 .link_update = ice_link_update,
186 .mtu_set = ice_mtu_set,
187 .mac_addr_set = ice_macaddr_set,
188 .mac_addr_add = ice_macaddr_add,
189 .mac_addr_remove = ice_macaddr_remove,
190 .vlan_filter_set = ice_vlan_filter_set,
191 .vlan_offload_set = ice_vlan_offload_set,
192 .reta_update = ice_rss_reta_update,
193 .reta_query = ice_rss_reta_query,
194 .rss_hash_update = ice_rss_hash_update,
195 .rss_hash_conf_get = ice_rss_hash_conf_get,
196 .promiscuous_enable = ice_promisc_enable,
197 .promiscuous_disable = ice_promisc_disable,
198 .allmulticast_enable = ice_allmulti_enable,
199 .allmulticast_disable = ice_allmulti_disable,
200 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
201 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
202 .fw_version_get = ice_fw_version_get,
203 .vlan_pvid_set = ice_vlan_pvid_set,
204 .rxq_info_get = ice_rxq_info_get,
205 .txq_info_get = ice_txq_info_get,
206 .rx_burst_mode_get = ice_rx_burst_mode_get,
207 .tx_burst_mode_get = ice_tx_burst_mode_get,
208 .get_eeprom_length = ice_get_eeprom_length,
209 .get_eeprom = ice_get_eeprom,
210 .rx_queue_count = ice_rx_queue_count,
211 .rx_descriptor_status = ice_rx_descriptor_status,
212 .tx_descriptor_status = ice_tx_descriptor_status,
213 .stats_get = ice_stats_get,
214 .stats_reset = ice_stats_reset,
215 .xstats_get = ice_xstats_get,
216 .xstats_get_names = ice_xstats_get_names,
217 .xstats_reset = ice_stats_reset,
218 .filter_ctrl = ice_dev_filter_ctrl,
219 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
220 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
223 /* store statistics names and its offset in stats structure */
224 struct ice_xstats_name_off {
225 char name[RTE_ETH_XSTATS_NAME_SIZE];
229 static const struct ice_xstats_name_off ice_stats_strings[] = {
230 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
231 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
232 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
233 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
234 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
235 rx_unknown_protocol)},
236 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
237 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
238 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
239 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
242 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
243 sizeof(ice_stats_strings[0]))
245 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
246 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
247 tx_dropped_link_down)},
248 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
249 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
251 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
252 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
254 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
256 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
258 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
259 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
260 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
261 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
262 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
263 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
265 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
267 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
269 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
271 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
273 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
275 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
277 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
279 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
280 mac_short_pkt_dropped)},
281 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
283 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
284 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
285 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
287 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
289 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
291 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
293 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
295 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
299 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
300 sizeof(ice_hw_port_strings[0]))
303 ice_init_controlq_parameter(struct ice_hw *hw)
305 /* fields for adminq */
306 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
307 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
308 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
309 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
311 /* fields for mailboxq, DPDK used as PF host */
312 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
313 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
314 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
315 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
319 lookup_proto_xtr_type(const char *xtr_name)
323 enum proto_xtr_type type;
325 { "vlan", PROTO_XTR_VLAN },
326 { "ipv4", PROTO_XTR_IPV4 },
327 { "ipv6", PROTO_XTR_IPV6 },
328 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
329 { "tcp", PROTO_XTR_TCP },
333 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
334 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
335 return xtr_type_map[i].type;
342 * Parse elem, the elem could be single number/range or '(' ')' group
343 * 1) A single number elem, it's just a simple digit. e.g. 9
344 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
345 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
346 * Within group elem, '-' used for a range separator;
347 * ',' used for a single number.
350 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
352 const char *str = input;
357 while (isblank(*str))
360 if (!isdigit(*str) && *str != '(')
363 /* process single number or single range of number */
366 idx = strtoul(str, &end, 10);
367 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
370 while (isblank(*end))
376 /* process single <number>-<number> */
379 while (isblank(*end))
385 idx = strtoul(end, &end, 10);
386 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
390 while (isblank(*end))
397 for (idx = RTE_MIN(min, max);
398 idx <= RTE_MAX(min, max); idx++)
399 devargs->proto_xtr[idx] = xtr_type;
404 /* process set within bracket */
406 while (isblank(*str))
411 min = ICE_MAX_QUEUE_NUM;
413 /* go ahead to the first digit */
414 while (isblank(*str))
419 /* get the digit value */
421 idx = strtoul(str, &end, 10);
422 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
425 /* go ahead to separator '-',',' and ')' */
426 while (isblank(*end))
429 if (min == ICE_MAX_QUEUE_NUM)
431 else /* avoid continuous '-' */
433 } else if (*end == ',' || *end == ')') {
435 if (min == ICE_MAX_QUEUE_NUM)
438 for (idx = RTE_MIN(min, max);
439 idx <= RTE_MAX(min, max); idx++)
440 devargs->proto_xtr[idx] = xtr_type;
442 min = ICE_MAX_QUEUE_NUM;
448 } while (*end != ')' && *end != '\0');
454 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
456 const char *queue_start;
461 while (isblank(*queues))
464 if (*queues != '[') {
465 xtr_type = lookup_proto_xtr_type(queues);
469 devargs->proto_xtr_dflt = xtr_type;
476 while (isblank(*queues))
481 queue_start = queues;
483 /* go across a complete bracket */
484 if (*queue_start == '(') {
485 queues += strcspn(queues, ")");
490 /* scan the separator ':' */
491 queues += strcspn(queues, ":");
492 if (*queues++ != ':')
494 while (isblank(*queues))
497 for (idx = 0; ; idx++) {
498 if (isblank(queues[idx]) ||
499 queues[idx] == ',' ||
500 queues[idx] == ']' ||
504 if (idx > sizeof(xtr_name) - 2)
507 xtr_name[idx] = queues[idx];
509 xtr_name[idx] = '\0';
510 xtr_type = lookup_proto_xtr_type(xtr_name);
516 while (isblank(*queues) || *queues == ',' || *queues == ']')
519 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
521 } while (*queues != '\0');
527 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
530 struct ice_devargs *devargs = extra_args;
532 if (value == NULL || extra_args == NULL)
535 if (parse_queue_proto_xtr(value, devargs) < 0) {
537 "The protocol extraction parameter is wrong : '%s'",
546 ice_proto_xtr_support(struct ice_hw *hw)
548 #define FLX_REG(val, fld, idx) \
549 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
550 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
556 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
557 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
558 ICE_PROT_IPV4_OF_OR_S },
559 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
560 ICE_PROT_IPV6_OF_OR_S },
561 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
562 ICE_PROT_IPV6_OF_OR_S },
563 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
567 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
568 uint32_t rxdid = xtr_sets[i].rxdid;
571 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
572 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
574 if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
575 FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
579 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
580 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
582 if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
583 FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
592 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
595 struct pool_entry *entry;
600 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
603 "Failed to allocate memory for resource pool");
607 /* queue heap initialize */
608 pool->num_free = num;
611 LIST_INIT(&pool->alloc_list);
612 LIST_INIT(&pool->free_list);
614 /* Initialize element */
618 LIST_INSERT_HEAD(&pool->free_list, entry, next);
623 ice_res_pool_alloc(struct ice_res_pool_info *pool,
626 struct pool_entry *entry, *valid_entry;
629 PMD_INIT_LOG(ERR, "Invalid parameter");
633 if (pool->num_free < num) {
634 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
635 num, pool->num_free);
640 /* Lookup in free list and find most fit one */
641 LIST_FOREACH(entry, &pool->free_list, next) {
642 if (entry->len >= num) {
644 if (entry->len == num) {
649 valid_entry->len > entry->len)
654 /* Not find one to satisfy the request, return */
656 PMD_INIT_LOG(ERR, "No valid entry found");
660 * The entry have equal queue number as requested,
661 * remove it from alloc_list.
663 if (valid_entry->len == num) {
664 LIST_REMOVE(valid_entry, next);
667 * The entry have more numbers than requested,
668 * create a new entry for alloc_list and minus its
669 * queue base and number in free_list.
671 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
674 "Failed to allocate memory for "
678 entry->base = valid_entry->base;
680 valid_entry->base += num;
681 valid_entry->len -= num;
685 /* Insert it into alloc list, not sorted */
686 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
688 pool->num_free -= valid_entry->len;
689 pool->num_alloc += valid_entry->len;
691 return valid_entry->base + pool->base;
695 ice_res_pool_destroy(struct ice_res_pool_info *pool)
697 struct pool_entry *entry, *next_entry;
702 for (entry = LIST_FIRST(&pool->alloc_list);
703 entry && (next_entry = LIST_NEXT(entry, next), 1);
704 entry = next_entry) {
705 LIST_REMOVE(entry, next);
709 for (entry = LIST_FIRST(&pool->free_list);
710 entry && (next_entry = LIST_NEXT(entry, next), 1);
711 entry = next_entry) {
712 LIST_REMOVE(entry, next);
719 LIST_INIT(&pool->alloc_list);
720 LIST_INIT(&pool->free_list);
724 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
726 /* Set VSI LUT selection */
727 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
728 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
729 /* Set Hash scheme */
730 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
731 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
733 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
736 static enum ice_status
737 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
738 struct ice_aqc_vsi_props *info,
739 uint8_t enabled_tcmap)
741 uint16_t bsf, qp_idx;
743 /* default tc 0 now. Multi-TC supporting need to be done later.
744 * Configure TC and queue mapping parameters, for enabled TC,
745 * allocate qpnum_per_tc queues to this traffic.
747 if (enabled_tcmap != 0x01) {
748 PMD_INIT_LOG(ERR, "only TC0 is supported");
752 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
753 bsf = rte_bsf32(vsi->nb_qps);
754 /* Adjust the queue number to actual queues that can be applied */
755 vsi->nb_qps = 0x1 << bsf;
758 /* Set tc and queue mapping with VSI */
759 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
760 ICE_AQ_VSI_TC_Q_OFFSET_S) |
761 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
763 /* Associate queue number with VSI */
764 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
765 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
766 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
767 info->valid_sections |=
768 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
769 /* Set the info.ingress_table and info.egress_table
770 * for UP translate table. Now just set it to 1:1 map by default
771 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
773 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
774 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
775 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
776 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
781 ice_init_mac_address(struct rte_eth_dev *dev)
783 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
785 if (!rte_is_unicast_ether_addr
786 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
787 PMD_INIT_LOG(ERR, "Invalid MAC address");
792 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
793 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
795 dev->data->mac_addrs =
796 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
797 if (!dev->data->mac_addrs) {
799 "Failed to allocate memory to store mac address");
802 /* store it to dev data */
804 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
805 &dev->data->mac_addrs[0]);
809 /* Find out specific MAC filter */
810 static struct ice_mac_filter *
811 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
813 struct ice_mac_filter *f;
815 TAILQ_FOREACH(f, &vsi->mac_list, next) {
816 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
824 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
826 struct ice_fltr_list_entry *m_list_itr = NULL;
827 struct ice_mac_filter *f;
828 struct LIST_HEAD_TYPE list_head;
829 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
832 /* If it's added and configured, return */
833 f = ice_find_mac_filter(vsi, mac_addr);
835 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
839 INIT_LIST_HEAD(&list_head);
841 m_list_itr = (struct ice_fltr_list_entry *)
842 ice_malloc(hw, sizeof(*m_list_itr));
847 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
848 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
849 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
850 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
851 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
852 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
853 m_list_itr->fltr_info.vsi_handle = vsi->idx;
855 LIST_ADD(&m_list_itr->list_entry, &list_head);
858 ret = ice_add_mac(hw, &list_head);
859 if (ret != ICE_SUCCESS) {
860 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
864 /* Add the mac addr into mac list */
865 f = rte_zmalloc(NULL, sizeof(*f), 0);
867 PMD_DRV_LOG(ERR, "failed to allocate memory");
871 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
872 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
878 rte_free(m_list_itr);
883 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
885 struct ice_fltr_list_entry *m_list_itr = NULL;
886 struct ice_mac_filter *f;
887 struct LIST_HEAD_TYPE list_head;
888 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
891 /* Can't find it, return an error */
892 f = ice_find_mac_filter(vsi, mac_addr);
896 INIT_LIST_HEAD(&list_head);
898 m_list_itr = (struct ice_fltr_list_entry *)
899 ice_malloc(hw, sizeof(*m_list_itr));
904 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
905 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
906 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
907 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
908 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
909 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
910 m_list_itr->fltr_info.vsi_handle = vsi->idx;
912 LIST_ADD(&m_list_itr->list_entry, &list_head);
914 /* remove the mac filter */
915 ret = ice_remove_mac(hw, &list_head);
916 if (ret != ICE_SUCCESS) {
917 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
922 /* Remove the mac addr from mac list */
923 TAILQ_REMOVE(&vsi->mac_list, f, next);
929 rte_free(m_list_itr);
933 /* Find out specific VLAN filter */
934 static struct ice_vlan_filter *
935 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
937 struct ice_vlan_filter *f;
939 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
940 if (vlan_id == f->vlan_info.vlan_id)
948 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
950 struct ice_fltr_list_entry *v_list_itr = NULL;
951 struct ice_vlan_filter *f;
952 struct LIST_HEAD_TYPE list_head;
956 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
959 hw = ICE_VSI_TO_HW(vsi);
961 /* If it's added and configured, return. */
962 f = ice_find_vlan_filter(vsi, vlan_id);
964 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
968 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
971 INIT_LIST_HEAD(&list_head);
973 v_list_itr = (struct ice_fltr_list_entry *)
974 ice_malloc(hw, sizeof(*v_list_itr));
979 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
980 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
981 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
982 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
983 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
984 v_list_itr->fltr_info.vsi_handle = vsi->idx;
986 LIST_ADD(&v_list_itr->list_entry, &list_head);
989 ret = ice_add_vlan(hw, &list_head);
990 if (ret != ICE_SUCCESS) {
991 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
996 /* Add vlan into vlan list */
997 f = rte_zmalloc(NULL, sizeof(*f), 0);
999 PMD_DRV_LOG(ERR, "failed to allocate memory");
1003 f->vlan_info.vlan_id = vlan_id;
1004 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1010 rte_free(v_list_itr);
1015 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1017 struct ice_fltr_list_entry *v_list_itr = NULL;
1018 struct ice_vlan_filter *f;
1019 struct LIST_HEAD_TYPE list_head;
1024 * Vlan 0 is the generic filter for untagged packets
1025 * and can't be removed.
1027 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1030 hw = ICE_VSI_TO_HW(vsi);
1032 /* Can't find it, return an error */
1033 f = ice_find_vlan_filter(vsi, vlan_id);
1037 INIT_LIST_HEAD(&list_head);
1039 v_list_itr = (struct ice_fltr_list_entry *)
1040 ice_malloc(hw, sizeof(*v_list_itr));
1046 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1047 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1048 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1049 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1050 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1051 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1053 LIST_ADD(&v_list_itr->list_entry, &list_head);
1055 /* remove the vlan filter */
1056 ret = ice_remove_vlan(hw, &list_head);
1057 if (ret != ICE_SUCCESS) {
1058 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1063 /* Remove the vlan id from vlan list */
1064 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1070 rte_free(v_list_itr);
1075 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1077 struct ice_mac_filter *m_f;
1078 struct ice_vlan_filter *v_f;
1081 if (!vsi || !vsi->mac_num)
1084 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1085 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1086 if (ret != ICE_SUCCESS) {
1092 if (vsi->vlan_num == 0)
1095 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1096 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1097 if (ret != ICE_SUCCESS) {
1108 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1110 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1111 struct ice_vsi_ctx ctxt;
1115 /* Check if it has been already on or off */
1116 if (vsi->info.valid_sections &
1117 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1119 if ((vsi->info.outer_tag_flags &
1120 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1121 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1122 return 0; /* already on */
1124 if (!(vsi->info.outer_tag_flags &
1125 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1126 return 0; /* already off */
1131 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1134 /* clear global insertion and use per packet insertion */
1135 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1136 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1137 vsi->info.outer_tag_flags |= qinq_flags;
1138 /* use default vlan type 0x8100 */
1139 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1140 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1141 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1142 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1143 ctxt.info.valid_sections =
1144 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1145 ctxt.vsi_num = vsi->vsi_id;
1146 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1149 "Update VSI failed to %s qinq stripping",
1150 on ? "enable" : "disable");
1154 vsi->info.valid_sections |=
1155 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1161 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1163 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1164 struct ice_vsi_ctx ctxt;
1168 /* Check if it has been already on or off */
1169 if (vsi->info.valid_sections &
1170 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1172 if ((vsi->info.outer_tag_flags &
1173 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1174 ICE_AQ_VSI_OUTER_TAG_COPY)
1175 return 0; /* already on */
1177 if ((vsi->info.outer_tag_flags &
1178 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1179 ICE_AQ_VSI_OUTER_TAG_NOTHING)
1180 return 0; /* already off */
1185 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1187 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1188 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1189 vsi->info.outer_tag_flags |= qinq_flags;
1190 /* use default vlan type 0x8100 */
1191 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1192 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1193 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1194 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1195 ctxt.info.valid_sections =
1196 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1197 ctxt.vsi_num = vsi->vsi_id;
1198 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1201 "Update VSI failed to %s qinq stripping",
1202 on ? "enable" : "disable");
1206 vsi->info.valid_sections |=
1207 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1213 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1217 ret = ice_vsi_config_qinq_stripping(vsi, on);
1219 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1221 ret = ice_vsi_config_qinq_insertion(vsi, on);
1223 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1230 ice_pf_enable_irq0(struct ice_hw *hw)
1232 /* reset the registers */
1233 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1234 ICE_READ_REG(hw, PFINT_OICR);
1237 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1238 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1239 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1241 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1242 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1243 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1244 PFINT_OICR_CTL_ITR_INDX_M) |
1245 PFINT_OICR_CTL_CAUSE_ENA_M);
1247 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1248 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1249 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1250 PFINT_FW_CTL_ITR_INDX_M) |
1251 PFINT_FW_CTL_CAUSE_ENA_M);
1253 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1256 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1257 GLINT_DYN_CTL_INTENA_M |
1258 GLINT_DYN_CTL_CLEARPBA_M |
1259 GLINT_DYN_CTL_ITR_INDX_M);
1266 ice_pf_disable_irq0(struct ice_hw *hw)
1268 /* Disable all interrupt types */
1269 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1275 ice_handle_aq_msg(struct rte_eth_dev *dev)
1277 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1278 struct ice_ctl_q_info *cq = &hw->adminq;
1279 struct ice_rq_event_info event;
1280 uint16_t pending, opcode;
1283 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1284 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1285 if (!event.msg_buf) {
1286 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1292 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1294 if (ret != ICE_SUCCESS) {
1296 "Failed to read msg from AdminQ, "
1298 hw->adminq.sq_last_status);
1301 opcode = rte_le_to_cpu_16(event.desc.opcode);
1304 case ice_aqc_opc_get_link_status:
1305 ret = ice_link_update(dev, 0);
1307 _rte_eth_dev_callback_process
1308 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1311 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1316 rte_free(event.msg_buf);
1321 * Interrupt handler triggered by NIC for handling
1322 * specific interrupt.
1325 * Pointer to interrupt handle.
1327 * The address of parameter (struct rte_eth_dev *) regsitered before.
1333 ice_interrupt_handler(void *param)
1335 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1336 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1344 uint32_t int_fw_ctl;
1347 /* Disable interrupt */
1348 ice_pf_disable_irq0(hw);
1350 /* read out interrupt causes */
1351 oicr = ICE_READ_REG(hw, PFINT_OICR);
1353 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1356 /* No interrupt event indicated */
1357 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1358 PMD_DRV_LOG(INFO, "No interrupt event");
1363 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1364 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1365 ice_handle_aq_msg(dev);
1368 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1369 PMD_DRV_LOG(INFO, "OICR: link state change event");
1370 ret = ice_link_update(dev, 0);
1372 _rte_eth_dev_callback_process
1373 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1377 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1378 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1379 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1380 if (reg & GL_MDET_TX_PQM_VALID_M) {
1381 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1382 GL_MDET_TX_PQM_PF_NUM_S;
1383 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1384 GL_MDET_TX_PQM_MAL_TYPE_S;
1385 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1386 GL_MDET_TX_PQM_QNUM_S;
1388 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1389 "%d by PQM on TX queue %d PF# %d",
1390 event, queue, pf_num);
1393 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1394 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1395 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1396 GL_MDET_TX_TCLAN_PF_NUM_S;
1397 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1398 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1399 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1400 GL_MDET_TX_TCLAN_QNUM_S;
1402 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1403 "%d by TCLAN on TX queue %d PF# %d",
1404 event, queue, pf_num);
1408 /* Enable interrupt */
1409 ice_pf_enable_irq0(hw);
1410 rte_intr_ack(dev->intr_handle);
1414 ice_init_proto_xtr(struct rte_eth_dev *dev)
1416 struct ice_adapter *ad =
1417 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1418 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1419 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1420 const struct proto_xtr_ol_flag *ol_flag;
1421 bool proto_xtr_enable = false;
1425 if (!ice_proto_xtr_support(hw)) {
1426 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1430 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1431 if (unlikely(pf->proto_xtr == NULL)) {
1432 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1436 for (i = 0; i < pf->lan_nb_qps; i++) {
1437 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1438 ad->devargs.proto_xtr[i] :
1439 ad->devargs.proto_xtr_dflt;
1441 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1442 uint8_t type = pf->proto_xtr[i];
1444 ice_proto_xtr_ol_flag_params[type].required = true;
1445 proto_xtr_enable = true;
1449 if (likely(!proto_xtr_enable))
1452 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1453 if (unlikely(offset == -1)) {
1455 "Protocol extraction metadata is disabled in mbuf with error %d",
1461 "Protocol extraction metadata offset in mbuf is : %d",
1463 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1465 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1466 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1468 if (!ol_flag->required)
1471 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1472 if (unlikely(offset == -1)) {
1474 "Protocol extraction offload '%s' failed to register with error %d",
1475 ol_flag->param.name, -rte_errno);
1477 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1482 "Protocol extraction offload '%s' offset in mbuf is : %d",
1483 ol_flag->param.name, offset);
1484 *ol_flag->ol_flag = 1ULL << offset;
1488 /* Initialize SW parameters of PF */
1490 ice_pf_sw_init(struct rte_eth_dev *dev)
1492 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1493 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1496 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1497 hw->func_caps.common_cap.num_rxq);
1499 pf->lan_nb_qps = pf->lan_nb_qp_max;
1501 ice_init_proto_xtr(dev);
1503 if (hw->func_caps.fd_fltr_guar > 0 ||
1504 hw->func_caps.fd_fltr_best_effort > 0) {
1505 pf->flags |= ICE_FLAG_FDIR;
1506 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1507 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1509 pf->fdir_nb_qps = 0;
1511 pf->fdir_qp_offset = 0;
1517 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1519 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1520 struct ice_vsi *vsi = NULL;
1521 struct ice_vsi_ctx vsi_ctx;
1523 struct rte_ether_addr broadcast = {
1524 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1525 struct rte_ether_addr mac_addr;
1526 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1527 uint8_t tc_bitmap = 0x1;
1530 /* hw->num_lports = 1 in NIC mode */
1531 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1535 vsi->idx = pf->next_vsi_idx;
1538 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1539 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1540 vsi->vlan_anti_spoof_on = 0;
1541 vsi->vlan_filter_on = 1;
1542 TAILQ_INIT(&vsi->mac_list);
1543 TAILQ_INIT(&vsi->vlan_list);
1545 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1546 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1547 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1548 hw->func_caps.common_cap.rss_table_size;
1549 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1551 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1554 vsi->nb_qps = pf->lan_nb_qps;
1555 vsi->base_queue = 1;
1556 ice_vsi_config_default_rss(&vsi_ctx.info);
1557 vsi_ctx.alloc_from_pool = true;
1558 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1559 /* switch_id is queried by get_switch_config aq, which is done
1562 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1563 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1564 /* Allow all untagged or tagged packets */
1565 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1566 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1567 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1568 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1571 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1572 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1573 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1574 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1575 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1576 vsi_ctx.info.max_fd_fltr_dedicated =
1577 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1578 vsi_ctx.info.max_fd_fltr_shared =
1579 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1581 /* Enable VLAN/UP trip */
1582 ret = ice_vsi_config_tc_queue_mapping(vsi,
1587 "tc queue mapping with vsi failed, "
1595 vsi->nb_qps = pf->fdir_nb_qps;
1596 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1597 vsi_ctx.alloc_from_pool = true;
1598 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1600 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1601 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1602 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1603 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1604 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1605 ret = ice_vsi_config_tc_queue_mapping(vsi,
1610 "tc queue mapping with vsi failed, "
1617 /* for other types of VSI */
1618 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1622 /* VF has MSIX interrupt in VF range, don't allocate here */
1623 if (type == ICE_VSI_PF) {
1624 ret = ice_res_pool_alloc(&pf->msix_pool,
1625 RTE_MIN(vsi->nb_qps,
1626 RTE_MAX_RXTX_INTR_VEC_ID));
1628 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1631 vsi->msix_intr = ret;
1632 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1633 } else if (type == ICE_VSI_CTRL) {
1634 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1636 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1639 vsi->msix_intr = ret;
1645 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1646 if (ret != ICE_SUCCESS) {
1647 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1650 /* store vsi information is SW structure */
1651 vsi->vsi_id = vsi_ctx.vsi_num;
1652 vsi->info = vsi_ctx.info;
1653 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1654 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1656 if (type == ICE_VSI_PF) {
1657 /* MAC configuration */
1658 rte_memcpy(pf->dev_addr.addr_bytes,
1659 hw->port_info->mac.perm_addr,
1662 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1663 ret = ice_add_mac_filter(vsi, &mac_addr);
1664 if (ret != ICE_SUCCESS)
1665 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1667 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1668 ret = ice_add_mac_filter(vsi, &mac_addr);
1669 if (ret != ICE_SUCCESS)
1670 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1673 /* At the beginning, only TC0. */
1674 /* What we need here is the maximam number of the TX queues.
1675 * Currently vsi->nb_qps means it.
1676 * Correct it if any change.
1678 max_txqs[0] = vsi->nb_qps;
1679 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1680 tc_bitmap, max_txqs);
1681 if (ret != ICE_SUCCESS)
1682 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1692 ice_send_driver_ver(struct ice_hw *hw)
1694 struct ice_driver_ver dv;
1696 /* we don't have driver version use 0 for dummy */
1700 dv.subbuild_ver = 0;
1701 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1703 return ice_aq_send_driver_ver(hw, &dv, NULL);
1707 ice_pf_setup(struct ice_pf *pf)
1709 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1710 struct ice_vsi *vsi;
1713 /* Clear all stats counters */
1714 pf->offset_loaded = FALSE;
1715 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1716 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1717 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1718 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1720 /* force guaranteed filter pool for PF */
1721 ice_alloc_fd_guar_item(hw, &unused,
1722 hw->func_caps.fd_fltr_guar);
1723 /* force shared filter pool for PF */
1724 ice_alloc_fd_shrd_item(hw, &unused,
1725 hw->func_caps.fd_fltr_best_effort);
1727 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1729 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1738 /* PCIe configuration space setting */
1739 #define PCI_CFG_SPACE_SIZE 256
1740 #define PCI_CFG_SPACE_EXP_SIZE 4096
1741 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
1742 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
1743 #define PCI_EXT_CAP_ID_DSN 0x03
1746 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1750 int pos = PCI_CFG_SPACE_SIZE;
1752 /* minimum 8 bytes per capability */
1753 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1755 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1756 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1761 * If we have no capabilities, this is indicated by cap ID,
1762 * cap version and next pointer all being 0.
1768 if (PCI_EXT_CAP_ID(header) == cap)
1771 pos = PCI_EXT_CAP_NEXT(header);
1773 if (pos < PCI_CFG_SPACE_SIZE)
1776 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1777 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1786 * Extract device serial number from PCIe Configuration Space and
1787 * determine the pkg file path according to the DSN.
1790 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1793 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1794 uint32_t dsn_low, dsn_high;
1795 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1797 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1800 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1801 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1802 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1803 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1805 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1809 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1810 ICE_MAX_PKG_FILENAME_SIZE);
1811 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1814 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1815 ICE_MAX_PKG_FILENAME_SIZE);
1816 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1820 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1821 if (!access(pkg_file, 0))
1823 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1827 static enum ice_pkg_type
1828 ice_load_pkg_type(struct ice_hw *hw)
1830 enum ice_pkg_type package_type;
1832 /* store the activated package type (OS default or Comms) */
1833 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1835 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1836 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1838 package_type = ICE_PKG_TYPE_COMMS;
1840 package_type = ICE_PKG_TYPE_UNKNOWN;
1842 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1843 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1844 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1845 hw->active_pkg_name);
1847 return package_type;
1850 static int ice_load_pkg(struct rte_eth_dev *dev)
1852 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1859 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1860 struct ice_adapter *ad =
1861 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1863 ice_pkg_file_search_path(pci_dev, pkg_file);
1865 file = fopen(pkg_file, "rb");
1867 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1871 err = stat(pkg_file, &fstat);
1873 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1878 buf_len = fstat.st_size;
1879 buf = rte_malloc(NULL, buf_len, 0);
1882 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1888 err = fread(buf, buf_len, 1, file);
1890 PMD_INIT_LOG(ERR, "failed to read package data\n");
1898 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1900 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1904 /* store the loaded pkg type info */
1905 ad->active_pkg_type = ice_load_pkg_type(hw);
1907 err = ice_init_hw_tbls(hw);
1909 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1910 goto fail_init_tbls;
1916 rte_free(hw->pkg_copy);
1923 ice_base_queue_get(struct ice_pf *pf)
1926 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1928 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1929 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1930 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1932 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1938 parse_bool(const char *key, const char *value, void *args)
1940 int *i = (int *)args;
1944 num = strtoul(value, &end, 10);
1946 if (num != 0 && num != 1) {
1947 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1948 "value must be 0 or 1",
1957 static int ice_parse_devargs(struct rte_eth_dev *dev)
1959 struct ice_adapter *ad =
1960 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1961 struct rte_devargs *devargs = dev->device->devargs;
1962 struct rte_kvargs *kvlist;
1965 if (devargs == NULL)
1968 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1969 if (kvlist == NULL) {
1970 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1974 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1975 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1976 sizeof(ad->devargs.proto_xtr));
1978 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1979 &handle_proto_xtr_arg, &ad->devargs);
1983 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1984 &parse_bool, &ad->devargs.safe_mode_support);
1988 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1989 &parse_bool, &ad->devargs.pipe_mode_support);
1992 rte_kvargs_free(kvlist);
1996 /* Forward LLDP packets to default VSI by set switch rules */
1998 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
2000 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2001 struct ice_fltr_list_entry *s_list_itr = NULL;
2002 struct LIST_HEAD_TYPE list_head;
2005 INIT_LIST_HEAD(&list_head);
2007 s_list_itr = (struct ice_fltr_list_entry *)
2008 ice_malloc(hw, sizeof(*s_list_itr));
2011 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2012 s_list_itr->fltr_info.vsi_handle = vsi->idx;
2013 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2014 RTE_ETHER_TYPE_LLDP;
2015 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2016 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2017 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2018 LIST_ADD(&s_list_itr->list_entry, &list_head);
2020 ret = ice_add_eth_mac(hw, &list_head);
2022 ret = ice_remove_eth_mac(hw, &list_head);
2024 rte_free(s_list_itr);
2028 static enum ice_status
2029 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2030 uint16_t num, uint16_t desc_id,
2031 uint16_t *prof_buf, uint16_t *num_prof)
2033 struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2036 bool res_shared = 1;
2037 struct ice_aq_desc aq_desc;
2038 struct ice_sq_cd *cd = NULL;
2039 struct ice_aqc_get_allocd_res_desc *cmd =
2040 &aq_desc.params.get_res_desc;
2042 buf_len = sizeof(resp_buf->elem) * num;
2043 resp_buf = ice_malloc(hw, buf_len);
2047 ice_fill_dflt_direct_cmd_desc(&aq_desc,
2048 ice_aqc_opc_get_allocd_res_desc);
2050 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2051 ICE_AQC_RES_TYPE_M) | (res_shared ?
2052 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2053 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2055 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2057 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2061 ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2062 (*num_prof), ICE_NONDMA_TO_NONDMA);
2069 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2073 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2074 uint16_t first_desc = 1;
2075 uint16_t num_prof = 0;
2077 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2078 first_desc, prof_buf, &num_prof);
2080 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2084 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2085 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2087 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2095 ice_reset_fxp_resource(struct ice_hw *hw)
2099 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2101 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2105 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2107 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2115 ice_dev_init(struct rte_eth_dev *dev)
2117 struct rte_pci_device *pci_dev;
2118 struct rte_intr_handle *intr_handle;
2119 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2121 struct ice_adapter *ad =
2122 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2123 struct ice_vsi *vsi;
2126 dev->dev_ops = &ice_eth_dev_ops;
2127 dev->rx_pkt_burst = ice_recv_pkts;
2128 dev->tx_pkt_burst = ice_xmit_pkts;
2129 dev->tx_pkt_prepare = ice_prep_pkts;
2131 /* for secondary processes, we don't initialise any further as primary
2132 * has already done this work.
2134 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2135 ice_set_rx_function(dev);
2136 ice_set_tx_function(dev);
2140 ice_set_default_ptype_table(dev);
2141 pci_dev = RTE_DEV_TO_PCI(dev->device);
2142 intr_handle = &pci_dev->intr_handle;
2144 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2145 pf->adapter->eth_dev = dev;
2146 pf->dev_data = dev->data;
2147 hw->back = pf->adapter;
2148 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2149 hw->vendor_id = pci_dev->id.vendor_id;
2150 hw->device_id = pci_dev->id.device_id;
2151 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2152 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2153 hw->bus.device = pci_dev->addr.devid;
2154 hw->bus.func = pci_dev->addr.function;
2156 ret = ice_parse_devargs(dev);
2158 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2162 ice_init_controlq_parameter(hw);
2164 ret = ice_init_hw(hw);
2166 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2170 ret = ice_load_pkg(dev);
2172 if (ad->devargs.safe_mode_support == 0) {
2173 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2174 "Use safe-mode-support=1 to enter Safe Mode");
2178 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2179 "Entering Safe Mode");
2180 ad->is_safe_mode = 1;
2183 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2184 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2185 hw->api_maj_ver, hw->api_min_ver);
2187 ice_pf_sw_init(dev);
2188 ret = ice_init_mac_address(dev);
2190 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2194 /* Pass the information to the rte_eth_dev_close() that it should also
2195 * release the private port resources.
2197 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2199 ret = ice_res_pool_init(&pf->msix_pool, 1,
2200 hw->func_caps.common_cap.num_msix_vectors - 1);
2202 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2203 goto err_msix_pool_init;
2206 ret = ice_pf_setup(pf);
2208 PMD_INIT_LOG(ERR, "Failed to setup PF");
2212 ret = ice_send_driver_ver(hw);
2214 PMD_INIT_LOG(ERR, "Failed to send driver version");
2220 /* Disable double vlan by default */
2221 ice_vsi_config_double_vlan(vsi, FALSE);
2223 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
2224 if (ret != ICE_SUCCESS)
2225 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2226 ret = ice_init_dcb(hw, TRUE);
2227 if (ret != ICE_SUCCESS)
2228 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2229 /* Forward LLDP packets to default VSI */
2230 ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2231 if (ret != ICE_SUCCESS)
2232 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2233 /* register callback func to eal lib */
2234 rte_intr_callback_register(intr_handle,
2235 ice_interrupt_handler, dev);
2237 ice_pf_enable_irq0(hw);
2239 /* enable uio intr after callback register */
2240 rte_intr_enable(intr_handle);
2242 /* get base queue pairs index in the device */
2243 ice_base_queue_get(pf);
2245 if (!ad->is_safe_mode) {
2246 ret = ice_flow_init(ad);
2248 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2253 ret = ice_reset_fxp_resource(hw);
2255 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2262 ice_res_pool_destroy(&pf->msix_pool);
2264 rte_free(dev->data->mac_addrs);
2265 dev->data->mac_addrs = NULL;
2267 ice_sched_cleanup_all(hw);
2268 rte_free(hw->port_info);
2269 ice_shutdown_all_ctrlq(hw);
2270 rte_free(pf->proto_xtr);
2276 ice_release_vsi(struct ice_vsi *vsi)
2279 struct ice_vsi_ctx vsi_ctx;
2280 enum ice_status ret;
2285 hw = ICE_VSI_TO_HW(vsi);
2287 ice_remove_all_mac_vlan_filters(vsi);
2289 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2291 vsi_ctx.vsi_num = vsi->vsi_id;
2292 vsi_ctx.info = vsi->info;
2293 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2294 if (ret != ICE_SUCCESS) {
2295 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2305 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2307 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2308 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2309 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2310 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2311 uint16_t msix_intr, i;
2313 /* disable interrupt and also clear all the exist config */
2314 for (i = 0; i < vsi->nb_qps; i++) {
2315 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2316 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2320 if (rte_intr_allow_others(intr_handle))
2322 for (i = 0; i < vsi->nb_msix; i++) {
2323 msix_intr = vsi->msix_intr + i;
2324 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2325 GLINT_DYN_CTL_WB_ON_ITR_M);
2329 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2333 ice_dev_stop(struct rte_eth_dev *dev)
2335 struct rte_eth_dev_data *data = dev->data;
2336 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2337 struct ice_vsi *main_vsi = pf->main_vsi;
2338 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2339 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2342 /* avoid stopping again */
2343 if (pf->adapter_stopped)
2346 /* stop and clear all Rx queues */
2347 for (i = 0; i < data->nb_rx_queues; i++)
2348 ice_rx_queue_stop(dev, i);
2350 /* stop and clear all Tx queues */
2351 for (i = 0; i < data->nb_tx_queues; i++)
2352 ice_tx_queue_stop(dev, i);
2354 /* disable all queue interrupts */
2355 ice_vsi_disable_queues_intr(main_vsi);
2357 if (pf->fdir.fdir_vsi)
2358 ice_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2360 /* Clear all queues and release mbufs */
2361 ice_clear_queues(dev);
2363 if (pf->init_link_up)
2364 ice_dev_set_link_up(dev);
2366 ice_dev_set_link_down(dev);
2368 /* Clean datapath event and queue/vec mapping */
2369 rte_intr_efd_disable(intr_handle);
2370 if (intr_handle->intr_vec) {
2371 rte_free(intr_handle->intr_vec);
2372 intr_handle->intr_vec = NULL;
2375 pf->adapter_stopped = true;
2379 ice_dev_close(struct rte_eth_dev *dev)
2381 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2382 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2383 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2384 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2385 struct ice_adapter *ad =
2386 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2388 /* Since stop will make link down, then the link event will be
2389 * triggered, disable the irq firstly to avoid the port_infoe etc
2390 * resources deallocation causing the interrupt service thread
2393 ice_pf_disable_irq0(hw);
2397 if (!ad->is_safe_mode)
2398 ice_flow_uninit(ad);
2400 /* release all queue resource */
2401 ice_free_queues(dev);
2403 ice_res_pool_destroy(&pf->msix_pool);
2404 ice_release_vsi(pf->main_vsi);
2405 ice_sched_cleanup_all(hw);
2406 ice_free_hw_tbls(hw);
2407 rte_free(hw->port_info);
2408 hw->port_info = NULL;
2409 ice_shutdown_all_ctrlq(hw);
2410 rte_free(pf->proto_xtr);
2411 pf->proto_xtr = NULL;
2413 dev->dev_ops = NULL;
2414 dev->rx_pkt_burst = NULL;
2415 dev->tx_pkt_burst = NULL;
2417 rte_free(dev->data->mac_addrs);
2418 dev->data->mac_addrs = NULL;
2420 /* disable uio intr before callback unregister */
2421 rte_intr_disable(intr_handle);
2423 /* unregister callback func from eal lib */
2424 rte_intr_callback_unregister(intr_handle,
2425 ice_interrupt_handler, dev);
2429 ice_dev_uninit(struct rte_eth_dev *dev)
2437 ice_dev_configure(struct rte_eth_dev *dev)
2439 struct ice_adapter *ad =
2440 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2442 /* Initialize to TRUE. If any of Rx queues doesn't meet the
2443 * bulk allocation or vector Rx preconditions we will reset it.
2445 ad->rx_bulk_alloc_allowed = true;
2446 ad->tx_simple_allowed = true;
2448 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2453 static int ice_init_rss(struct ice_pf *pf)
2455 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2456 struct ice_vsi *vsi = pf->main_vsi;
2457 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2458 struct rte_eth_rss_conf *rss_conf;
2459 struct ice_aqc_get_set_rss_keys key;
2462 bool is_safe_mode = pf->adapter->is_safe_mode;
2465 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2466 nb_q = dev->data->nb_rx_queues;
2467 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2468 vsi->rss_lut_size = pf->hash_lut_size;
2471 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2476 vsi->rss_key = rte_zmalloc(NULL,
2477 vsi->rss_key_size, 0);
2479 vsi->rss_lut = rte_zmalloc(NULL,
2480 vsi->rss_lut_size, 0);
2482 /* configure RSS key */
2483 if (!rss_conf->rss_key) {
2484 /* Calculate the default hash key */
2485 for (i = 0; i <= vsi->rss_key_size; i++)
2486 vsi->rss_key[i] = (uint8_t)rte_rand();
2488 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2489 RTE_MIN(rss_conf->rss_key_len,
2490 vsi->rss_key_size));
2492 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2493 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2497 /* init RSS LUT table */
2498 for (i = 0; i < vsi->rss_lut_size; i++)
2499 vsi->rss_lut[i] = i % nb_q;
2501 ret = ice_aq_set_rss_lut(hw, vsi->idx,
2502 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2503 vsi->rss_lut, vsi->rss_lut_size);
2507 /* Enable registers for symmetric_toeplitz function. */
2508 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2509 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2510 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2511 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2513 /* configure RSS for IPv4 with input set IPv4 src/dst */
2514 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2515 ICE_FLOW_SEG_HDR_IPV4, 0);
2517 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2519 /* configure RSS for IPv6 with input set IPv6 src/dst */
2520 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2521 ICE_FLOW_SEG_HDR_IPV6, 0);
2523 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2525 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2526 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2527 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2529 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2531 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2532 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2533 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2535 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2537 /* configure RSS for sctp6 with input set IPv6 src/dst */
2538 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2539 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2541 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2544 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2545 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2546 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2548 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2550 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2551 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2552 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2554 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2556 /* configure RSS for sctp4 with input set IP src/dst */
2557 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2558 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2560 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2563 /* configure RSS for gtpu with input set TEID */
2564 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2565 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2567 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2571 * configure RSS for pppoe/pppod with input set
2572 * Source MAC and Session ID
2574 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2575 ICE_FLOW_SEG_HDR_PPPOE, 0);
2577 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2584 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2585 int base_queue, int nb_queue)
2587 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2588 uint32_t val, val_tx;
2591 for (i = 0; i < nb_queue; i++) {
2593 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2594 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2595 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2596 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2598 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2599 base_queue + i, msix_vect);
2600 /* set ITR0 value */
2601 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2602 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2603 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2608 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2610 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2611 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2612 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2613 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2614 uint16_t msix_vect = vsi->msix_intr;
2615 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2616 uint16_t queue_idx = 0;
2620 /* clear Rx/Tx queue interrupt */
2621 for (i = 0; i < vsi->nb_used_qps; i++) {
2622 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2623 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2626 /* PF bind interrupt */
2627 if (rte_intr_dp_is_en(intr_handle)) {
2632 for (i = 0; i < vsi->nb_used_qps; i++) {
2634 if (!rte_intr_allow_others(intr_handle))
2635 msix_vect = ICE_MISC_VEC_ID;
2637 /* uio mapping all queue to one msix_vect */
2638 __vsi_queues_bind_intr(vsi, msix_vect,
2639 vsi->base_queue + i,
2640 vsi->nb_used_qps - i);
2642 for (; !!record && i < vsi->nb_used_qps; i++)
2643 intr_handle->intr_vec[queue_idx + i] =
2648 /* vfio 1:1 queue/msix_vect mapping */
2649 __vsi_queues_bind_intr(vsi, msix_vect,
2650 vsi->base_queue + i, 1);
2653 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2661 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2663 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2664 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2665 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2666 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2667 uint16_t msix_intr, i;
2669 if (rte_intr_allow_others(intr_handle))
2670 for (i = 0; i < vsi->nb_used_qps; i++) {
2671 msix_intr = vsi->msix_intr + i;
2672 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2673 GLINT_DYN_CTL_INTENA_M |
2674 GLINT_DYN_CTL_CLEARPBA_M |
2675 GLINT_DYN_CTL_ITR_INDX_M |
2676 GLINT_DYN_CTL_WB_ON_ITR_M);
2679 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2680 GLINT_DYN_CTL_INTENA_M |
2681 GLINT_DYN_CTL_CLEARPBA_M |
2682 GLINT_DYN_CTL_ITR_INDX_M |
2683 GLINT_DYN_CTL_WB_ON_ITR_M);
2687 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2689 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2690 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2691 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2692 struct ice_vsi *vsi = pf->main_vsi;
2693 uint32_t intr_vector = 0;
2695 rte_intr_disable(intr_handle);
2697 /* check and configure queue intr-vector mapping */
2698 if ((rte_intr_cap_multiple(intr_handle) ||
2699 !RTE_ETH_DEV_SRIOV(dev).active) &&
2700 dev->data->dev_conf.intr_conf.rxq != 0) {
2701 intr_vector = dev->data->nb_rx_queues;
2702 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2703 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2704 ICE_MAX_INTR_QUEUE_NUM);
2707 if (rte_intr_efd_enable(intr_handle, intr_vector))
2711 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2712 intr_handle->intr_vec =
2713 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2715 if (!intr_handle->intr_vec) {
2717 "Failed to allocate %d rx_queues intr_vec",
2718 dev->data->nb_rx_queues);
2723 /* Map queues with MSIX interrupt */
2724 vsi->nb_used_qps = dev->data->nb_rx_queues;
2725 ice_vsi_queues_bind_intr(vsi);
2727 /* Enable interrupts for all the queues */
2728 ice_vsi_enable_queues_intr(vsi);
2730 /* Enable FDIR MSIX interrupt */
2731 if (pf->fdir.fdir_vsi) {
2732 ice_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
2733 ice_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2736 rte_intr_enable(intr_handle);
2742 ice_get_init_link_status(struct rte_eth_dev *dev)
2744 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2745 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2746 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2747 struct ice_link_status link_status;
2750 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
2751 &link_status, NULL);
2752 if (ret != ICE_SUCCESS) {
2753 PMD_DRV_LOG(ERR, "Failed to get link info");
2754 pf->init_link_up = false;
2758 if (link_status.link_info & ICE_AQ_LINK_UP)
2759 pf->init_link_up = true;
2763 ice_dev_start(struct rte_eth_dev *dev)
2765 struct rte_eth_dev_data *data = dev->data;
2766 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2767 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2768 struct ice_vsi *vsi = pf->main_vsi;
2769 uint16_t nb_rxq = 0;
2771 uint16_t max_frame_size;
2774 /* program Tx queues' context in hardware */
2775 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2776 ret = ice_tx_queue_start(dev, nb_txq);
2778 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2783 /* program Rx queues' context in hardware*/
2784 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2785 ret = ice_rx_queue_start(dev, nb_rxq);
2787 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2792 ret = ice_init_rss(pf);
2794 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2798 ice_set_rx_function(dev);
2799 ice_set_tx_function(dev);
2801 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2802 ETH_VLAN_EXTEND_MASK;
2803 ret = ice_vlan_offload_set(dev, mask);
2805 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2809 /* enable Rx interrput and mapping Rx queue to interrupt vector */
2810 if (ice_rxq_intr_setup(dev))
2813 /* Enable receiving broadcast packets and transmitting packets */
2814 ret = ice_set_vsi_promisc(hw, vsi->idx,
2815 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2816 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2818 if (ret != ICE_SUCCESS)
2819 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2821 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2822 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2823 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2824 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2825 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2826 ICE_AQ_LINK_EVENT_AN_COMPLETED |
2827 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2829 if (ret != ICE_SUCCESS)
2830 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2832 ice_get_init_link_status(dev);
2834 ice_dev_set_link_up(dev);
2836 /* Call get_link_info aq commond to enable/disable LSE */
2837 ice_link_update(dev, 0);
2839 pf->adapter_stopped = false;
2841 /* Set the max frame size to default value*/
2842 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2843 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2846 /* Set the max frame size to HW*/
2847 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2851 /* stop the started queues if failed to start all queues */
2853 for (i = 0; i < nb_rxq; i++)
2854 ice_rx_queue_stop(dev, i);
2856 for (i = 0; i < nb_txq; i++)
2857 ice_tx_queue_stop(dev, i);
2863 ice_dev_reset(struct rte_eth_dev *dev)
2867 if (dev->data->sriov.active)
2870 ret = ice_dev_uninit(dev);
2872 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2876 ret = ice_dev_init(dev);
2878 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2886 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2888 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2889 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890 struct ice_vsi *vsi = pf->main_vsi;
2891 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2892 bool is_safe_mode = pf->adapter->is_safe_mode;
2896 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2897 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2898 dev_info->max_rx_queues = vsi->nb_qps;
2899 dev_info->max_tx_queues = vsi->nb_qps;
2900 dev_info->max_mac_addrs = vsi->max_macaddrs;
2901 dev_info->max_vfs = pci_dev->max_vfs;
2902 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2903 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2905 dev_info->rx_offload_capa =
2906 DEV_RX_OFFLOAD_VLAN_STRIP |
2907 DEV_RX_OFFLOAD_JUMBO_FRAME |
2908 DEV_RX_OFFLOAD_KEEP_CRC |
2909 DEV_RX_OFFLOAD_SCATTER |
2910 DEV_RX_OFFLOAD_VLAN_FILTER;
2911 dev_info->tx_offload_capa =
2912 DEV_TX_OFFLOAD_VLAN_INSERT |
2913 DEV_TX_OFFLOAD_TCP_TSO |
2914 DEV_TX_OFFLOAD_MULTI_SEGS |
2915 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2916 dev_info->flow_type_rss_offloads = 0;
2918 if (!is_safe_mode) {
2919 dev_info->rx_offload_capa |=
2920 DEV_RX_OFFLOAD_IPV4_CKSUM |
2921 DEV_RX_OFFLOAD_UDP_CKSUM |
2922 DEV_RX_OFFLOAD_TCP_CKSUM |
2923 DEV_RX_OFFLOAD_QINQ_STRIP |
2924 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2925 DEV_RX_OFFLOAD_VLAN_EXTEND |
2926 DEV_RX_OFFLOAD_RSS_HASH;
2927 dev_info->tx_offload_capa |=
2928 DEV_TX_OFFLOAD_QINQ_INSERT |
2929 DEV_TX_OFFLOAD_IPV4_CKSUM |
2930 DEV_TX_OFFLOAD_UDP_CKSUM |
2931 DEV_TX_OFFLOAD_TCP_CKSUM |
2932 DEV_TX_OFFLOAD_SCTP_CKSUM |
2933 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2934 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2935 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2938 dev_info->rx_queue_offload_capa = 0;
2939 dev_info->tx_queue_offload_capa = 0;
2941 dev_info->reta_size = pf->hash_lut_size;
2942 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2944 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2946 .pthresh = ICE_DEFAULT_RX_PTHRESH,
2947 .hthresh = ICE_DEFAULT_RX_HTHRESH,
2948 .wthresh = ICE_DEFAULT_RX_WTHRESH,
2950 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2955 dev_info->default_txconf = (struct rte_eth_txconf) {
2957 .pthresh = ICE_DEFAULT_TX_PTHRESH,
2958 .hthresh = ICE_DEFAULT_TX_HTHRESH,
2959 .wthresh = ICE_DEFAULT_TX_WTHRESH,
2961 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2962 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2966 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2967 .nb_max = ICE_MAX_RING_DESC,
2968 .nb_min = ICE_MIN_RING_DESC,
2969 .nb_align = ICE_ALIGN_RING_DESC,
2972 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2973 .nb_max = ICE_MAX_RING_DESC,
2974 .nb_min = ICE_MIN_RING_DESC,
2975 .nb_align = ICE_ALIGN_RING_DESC,
2978 dev_info->speed_capa = ETH_LINK_SPEED_10M |
2979 ETH_LINK_SPEED_100M |
2981 ETH_LINK_SPEED_2_5G |
2983 ETH_LINK_SPEED_10G |
2984 ETH_LINK_SPEED_20G |
2987 phy_type_low = hw->port_info->phy.phy_type_low;
2988 phy_type_high = hw->port_info->phy.phy_type_high;
2990 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2991 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2993 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2994 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2995 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2997 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2998 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3000 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3001 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3002 dev_info->default_rxportconf.nb_queues = 1;
3003 dev_info->default_txportconf.nb_queues = 1;
3004 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3005 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3011 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3012 struct rte_eth_link *link)
3014 struct rte_eth_link *dst = link;
3015 struct rte_eth_link *src = &dev->data->dev_link;
3017 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3018 *(uint64_t *)src) == 0)
3025 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3026 struct rte_eth_link *link)
3028 struct rte_eth_link *dst = &dev->data->dev_link;
3029 struct rte_eth_link *src = link;
3031 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3032 *(uint64_t *)src) == 0)
3039 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3041 #define CHECK_INTERVAL 100 /* 100ms */
3042 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3043 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3044 struct ice_link_status link_status;
3045 struct rte_eth_link link, old;
3047 unsigned int rep_cnt = MAX_REPEAT_TIME;
3048 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3050 memset(&link, 0, sizeof(link));
3051 memset(&old, 0, sizeof(old));
3052 memset(&link_status, 0, sizeof(link_status));
3053 ice_atomic_read_link_status(dev, &old);
3056 /* Get link status information from hardware */
3057 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3058 &link_status, NULL);
3059 if (status != ICE_SUCCESS) {
3060 link.link_speed = ETH_SPEED_NUM_100M;
3061 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3062 PMD_DRV_LOG(ERR, "Failed to get link info");
3066 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3067 if (!wait_to_complete || link.link_status)
3070 rte_delay_ms(CHECK_INTERVAL);
3071 } while (--rep_cnt);
3073 if (!link.link_status)
3076 /* Full-duplex operation at all supported speeds */
3077 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3079 /* Parse the link status */
3080 switch (link_status.link_speed) {
3081 case ICE_AQ_LINK_SPEED_10MB:
3082 link.link_speed = ETH_SPEED_NUM_10M;
3084 case ICE_AQ_LINK_SPEED_100MB:
3085 link.link_speed = ETH_SPEED_NUM_100M;
3087 case ICE_AQ_LINK_SPEED_1000MB:
3088 link.link_speed = ETH_SPEED_NUM_1G;
3090 case ICE_AQ_LINK_SPEED_2500MB:
3091 link.link_speed = ETH_SPEED_NUM_2_5G;
3093 case ICE_AQ_LINK_SPEED_5GB:
3094 link.link_speed = ETH_SPEED_NUM_5G;
3096 case ICE_AQ_LINK_SPEED_10GB:
3097 link.link_speed = ETH_SPEED_NUM_10G;
3099 case ICE_AQ_LINK_SPEED_20GB:
3100 link.link_speed = ETH_SPEED_NUM_20G;
3102 case ICE_AQ_LINK_SPEED_25GB:
3103 link.link_speed = ETH_SPEED_NUM_25G;
3105 case ICE_AQ_LINK_SPEED_40GB:
3106 link.link_speed = ETH_SPEED_NUM_40G;
3108 case ICE_AQ_LINK_SPEED_50GB:
3109 link.link_speed = ETH_SPEED_NUM_50G;
3111 case ICE_AQ_LINK_SPEED_100GB:
3112 link.link_speed = ETH_SPEED_NUM_100G;
3114 case ICE_AQ_LINK_SPEED_UNKNOWN:
3116 PMD_DRV_LOG(ERR, "Unknown link speed");
3117 link.link_speed = ETH_SPEED_NUM_NONE;
3121 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3122 ETH_LINK_SPEED_FIXED);
3125 ice_atomic_write_link_status(dev, &link);
3126 if (link.link_status == old.link_status)
3132 /* Force the physical link state by getting the current PHY capabilities from
3133 * hardware and setting the PHY config based on the determined capabilities. If
3134 * link changes, link event will be triggered because both the Enable Automatic
3135 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3137 static enum ice_status
3138 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3140 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3141 struct ice_aqc_get_phy_caps_data *pcaps;
3142 struct ice_port_info *pi;
3143 enum ice_status status;
3145 if (!hw || !hw->port_info)
3146 return ICE_ERR_PARAM;
3150 pcaps = (struct ice_aqc_get_phy_caps_data *)
3151 ice_malloc(hw, sizeof(*pcaps));
3153 return ICE_ERR_NO_MEMORY;
3155 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3160 /* No change in link */
3161 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3162 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3165 cfg.phy_type_low = pcaps->phy_type_low;
3166 cfg.phy_type_high = pcaps->phy_type_high;
3167 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3168 cfg.low_power_ctrl = pcaps->low_power_ctrl;
3169 cfg.eee_cap = pcaps->eee_cap;
3170 cfg.eeer_value = pcaps->eeer_value;
3171 cfg.link_fec_opt = pcaps->link_fec_options;
3173 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3175 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3177 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3180 ice_free(hw, pcaps);
3185 ice_dev_set_link_up(struct rte_eth_dev *dev)
3187 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3189 return ice_force_phys_link_state(hw, true);
3193 ice_dev_set_link_down(struct rte_eth_dev *dev)
3195 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3197 return ice_force_phys_link_state(hw, false);
3201 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3203 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3204 struct rte_eth_dev_data *dev_data = pf->dev_data;
3205 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3207 /* check if mtu is within the allowed range */
3208 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3211 /* mtu setting is forbidden if port is start */
3212 if (dev_data->dev_started) {
3214 "port %d must be stopped before configuration",
3219 if (frame_size > RTE_ETHER_MAX_LEN)
3220 dev_data->dev_conf.rxmode.offloads |=
3221 DEV_RX_OFFLOAD_JUMBO_FRAME;
3223 dev_data->dev_conf.rxmode.offloads &=
3224 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3226 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3231 static int ice_macaddr_set(struct rte_eth_dev *dev,
3232 struct rte_ether_addr *mac_addr)
3234 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3235 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3236 struct ice_vsi *vsi = pf->main_vsi;
3237 struct ice_mac_filter *f;
3241 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3242 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3246 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3247 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3252 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3256 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3257 if (ret != ICE_SUCCESS) {
3258 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3261 ret = ice_add_mac_filter(vsi, mac_addr);
3262 if (ret != ICE_SUCCESS) {
3263 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3266 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
3268 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3269 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3270 if (ret != ICE_SUCCESS)
3271 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3276 /* Add a MAC address, and update filters */
3278 ice_macaddr_add(struct rte_eth_dev *dev,
3279 struct rte_ether_addr *mac_addr,
3280 __rte_unused uint32_t index,
3281 __rte_unused uint32_t pool)
3283 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3284 struct ice_vsi *vsi = pf->main_vsi;
3287 ret = ice_add_mac_filter(vsi, mac_addr);
3288 if (ret != ICE_SUCCESS) {
3289 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3296 /* Remove a MAC address, and update filters */
3298 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3300 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3301 struct ice_vsi *vsi = pf->main_vsi;
3302 struct rte_eth_dev_data *data = dev->data;
3303 struct rte_ether_addr *macaddr;
3306 macaddr = &data->mac_addrs[index];
3307 ret = ice_remove_mac_filter(vsi, macaddr);
3309 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3315 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3317 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3318 struct ice_vsi *vsi = pf->main_vsi;
3321 PMD_INIT_FUNC_TRACE();
3324 ret = ice_add_vlan_filter(vsi, vlan_id);
3326 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3330 ret = ice_remove_vlan_filter(vsi, vlan_id);
3332 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3340 /* Configure vlan filter on or off */
3342 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3344 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3345 struct ice_vsi_ctx ctxt;
3346 uint8_t sec_flags, sw_flags2;
3349 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3350 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3351 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3354 vsi->info.sec_flags |= sec_flags;
3355 vsi->info.sw_flags2 |= sw_flags2;
3357 vsi->info.sec_flags &= ~sec_flags;
3358 vsi->info.sw_flags2 &= ~sw_flags2;
3360 vsi->info.sw_id = hw->port_info->sw_id;
3361 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3362 ctxt.info.valid_sections =
3363 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3364 ICE_AQ_VSI_PROP_SECURITY_VALID);
3365 ctxt.vsi_num = vsi->vsi_id;
3367 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3369 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3370 on ? "enable" : "disable");
3373 vsi->info.valid_sections |=
3374 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3375 ICE_AQ_VSI_PROP_SECURITY_VALID);
3378 /* consist with other drivers, allow untagged packet when vlan filter on */
3380 ret = ice_add_vlan_filter(vsi, 0);
3382 ret = ice_remove_vlan_filter(vsi, 0);
3388 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3390 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3391 struct ice_vsi_ctx ctxt;
3395 /* Check if it has been already on or off */
3396 if (vsi->info.valid_sections &
3397 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3399 if ((vsi->info.vlan_flags &
3400 ICE_AQ_VSI_VLAN_EMOD_M) ==
3401 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3402 return 0; /* already on */
3404 if ((vsi->info.vlan_flags &
3405 ICE_AQ_VSI_VLAN_EMOD_M) ==
3406 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3407 return 0; /* already off */
3412 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3414 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3415 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3416 vsi->info.vlan_flags |= vlan_flags;
3417 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3418 ctxt.info.valid_sections =
3419 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3420 ctxt.vsi_num = vsi->vsi_id;
3421 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3423 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3424 on ? "enable" : "disable");
3428 vsi->info.valid_sections |=
3429 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3435 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3437 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3438 struct ice_vsi *vsi = pf->main_vsi;
3439 struct rte_eth_rxmode *rxmode;
3441 rxmode = &dev->data->dev_conf.rxmode;
3442 if (mask & ETH_VLAN_FILTER_MASK) {
3443 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3444 ice_vsi_config_vlan_filter(vsi, TRUE);
3446 ice_vsi_config_vlan_filter(vsi, FALSE);
3449 if (mask & ETH_VLAN_STRIP_MASK) {
3450 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3451 ice_vsi_config_vlan_stripping(vsi, TRUE);
3453 ice_vsi_config_vlan_stripping(vsi, FALSE);
3456 if (mask & ETH_VLAN_EXTEND_MASK) {
3457 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3458 ice_vsi_config_double_vlan(vsi, TRUE);
3460 ice_vsi_config_double_vlan(vsi, FALSE);
3467 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3469 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3470 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3476 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3477 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3478 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3480 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3484 uint64_t *lut_dw = (uint64_t *)lut;
3485 uint16_t i, lut_size_dw = lut_size / 4;
3487 for (i = 0; i < lut_size_dw; i++)
3488 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3495 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3504 pf = ICE_VSI_TO_PF(vsi);
3505 hw = ICE_VSI_TO_HW(vsi);
3507 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3508 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3509 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3511 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3515 uint64_t *lut_dw = (uint64_t *)lut;
3516 uint16_t i, lut_size_dw = lut_size / 4;
3518 for (i = 0; i < lut_size_dw; i++)
3519 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3528 ice_rss_reta_update(struct rte_eth_dev *dev,
3529 struct rte_eth_rss_reta_entry64 *reta_conf,
3532 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3533 uint16_t i, lut_size = pf->hash_lut_size;
3534 uint16_t idx, shift;
3538 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3539 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3540 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3542 "The size of hash lookup table configured (%d)"
3543 "doesn't match the number hardware can "
3544 "supported (128, 512, 2048)",
3549 /* It MUST use the current LUT size to get the RSS lookup table,
3550 * otherwise if will fail with -100 error code.
3552 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
3554 PMD_DRV_LOG(ERR, "No memory can be allocated");
3557 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3561 for (i = 0; i < reta_size; i++) {
3562 idx = i / RTE_RETA_GROUP_SIZE;
3563 shift = i % RTE_RETA_GROUP_SIZE;
3564 if (reta_conf[idx].mask & (1ULL << shift))
3565 lut[i] = reta_conf[idx].reta[shift];
3567 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3568 if (ret == 0 && lut_size != reta_size) {
3570 "The size of hash lookup table is changed from (%d) to (%d)",
3571 lut_size, reta_size);
3572 pf->hash_lut_size = reta_size;
3582 ice_rss_reta_query(struct rte_eth_dev *dev,
3583 struct rte_eth_rss_reta_entry64 *reta_conf,
3586 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3587 uint16_t i, lut_size = pf->hash_lut_size;
3588 uint16_t idx, shift;
3592 if (reta_size != lut_size) {
3594 "The size of hash lookup table configured (%d)"
3595 "doesn't match the number hardware can "
3597 reta_size, lut_size);
3601 lut = rte_zmalloc(NULL, reta_size, 0);
3603 PMD_DRV_LOG(ERR, "No memory can be allocated");
3607 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3611 for (i = 0; i < reta_size; i++) {
3612 idx = i / RTE_RETA_GROUP_SIZE;
3613 shift = i % RTE_RETA_GROUP_SIZE;
3614 if (reta_conf[idx].mask & (1ULL << shift))
3615 reta_conf[idx].reta[shift] = lut[i];
3625 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3627 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3630 if (!key || key_len == 0) {
3631 PMD_DRV_LOG(DEBUG, "No key to be configured");
3633 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3635 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3639 struct ice_aqc_get_set_rss_keys *key_dw =
3640 (struct ice_aqc_get_set_rss_keys *)key;
3642 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3644 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3652 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3654 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3657 if (!key || !key_len)
3660 ret = ice_aq_get_rss_key
3662 (struct ice_aqc_get_set_rss_keys *)key);
3664 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3667 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3673 ice_rss_hash_update(struct rte_eth_dev *dev,
3674 struct rte_eth_rss_conf *rss_conf)
3676 enum ice_status status = ICE_SUCCESS;
3677 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3678 struct ice_vsi *vsi = pf->main_vsi;
3681 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3685 /* TODO: hash enable config, ice_add_rss_cfg */
3690 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3691 struct rte_eth_rss_conf *rss_conf)
3693 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3694 struct ice_vsi *vsi = pf->main_vsi;
3696 ice_get_rss_key(vsi, rss_conf->rss_key,
3697 &rss_conf->rss_key_len);
3699 /* TODO: default set to 0 as hf config is not supported now */
3700 rss_conf->rss_hf = 0;
3705 ice_promisc_enable(struct rte_eth_dev *dev)
3707 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3708 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709 struct ice_vsi *vsi = pf->main_vsi;
3710 enum ice_status status;
3714 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3715 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3717 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3719 case ICE_ERR_ALREADY_EXISTS:
3720 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3724 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3732 ice_promisc_disable(struct rte_eth_dev *dev)
3734 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3735 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3736 struct ice_vsi *vsi = pf->main_vsi;
3737 enum ice_status status;
3741 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3742 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3744 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3745 if (status != ICE_SUCCESS) {
3746 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3754 ice_allmulti_enable(struct rte_eth_dev *dev)
3756 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3757 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3758 struct ice_vsi *vsi = pf->main_vsi;
3759 enum ice_status status;
3763 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3765 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3768 case ICE_ERR_ALREADY_EXISTS:
3769 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3773 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3781 ice_allmulti_disable(struct rte_eth_dev *dev)
3783 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3784 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785 struct ice_vsi *vsi = pf->main_vsi;
3786 enum ice_status status;
3790 if (dev->data->promiscuous == 1)
3791 return 0; /* must remain in all_multicast mode */
3793 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3795 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3796 if (status != ICE_SUCCESS) {
3797 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3804 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3807 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3808 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3809 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3813 msix_intr = intr_handle->intr_vec[queue_id];
3815 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3816 GLINT_DYN_CTL_ITR_INDX_M;
3817 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3819 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3820 rte_intr_ack(&pci_dev->intr_handle);
3825 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3828 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3829 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3830 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3833 msix_intr = intr_handle->intr_vec[queue_id];
3835 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3841 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3843 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849 full_ver = hw->nvm.oem_ver;
3850 ver = (u8)(full_ver >> 24);
3851 build = (u16)((full_ver >> 8) & 0xffff);
3852 patch = (u8)(full_ver & 0xff);
3854 ret = snprintf(fw_version, fw_size,
3855 "%d.%d%d 0x%08x %d.%d.%d",
3856 ((hw->nvm.ver >> 12) & 0xf),
3857 ((hw->nvm.ver >> 4) & 0xff),
3858 (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3861 /* add the size of '\0' */
3863 if (fw_size < (u32)ret)
3870 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3873 struct ice_vsi_ctx ctxt;
3874 uint8_t vlan_flags = 0;
3877 if (!vsi || !info) {
3878 PMD_DRV_LOG(ERR, "invalid parameters");
3883 vsi->info.pvid = info->config.pvid;
3885 * If insert pvid is enabled, only tagged pkts are
3886 * allowed to be sent out.
3888 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3889 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3892 if (info->config.reject.tagged == 0)
3893 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3895 if (info->config.reject.untagged == 0)
3896 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3898 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3899 ICE_AQ_VSI_VLAN_MODE_M);
3900 vsi->info.vlan_flags |= vlan_flags;
3901 memset(&ctxt, 0, sizeof(ctxt));
3902 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3903 ctxt.info.valid_sections =
3904 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3905 ctxt.vsi_num = vsi->vsi_id;
3907 hw = ICE_VSI_TO_HW(vsi);
3908 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3909 if (ret != ICE_SUCCESS) {
3911 "update VSI for VLAN insert failed, err %d",
3916 vsi->info.valid_sections |=
3917 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3923 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3925 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3926 struct ice_vsi *vsi = pf->main_vsi;
3927 struct rte_eth_dev_data *data = pf->dev_data;
3928 struct ice_vsi_vlan_pvid_info info;
3931 memset(&info, 0, sizeof(info));
3934 info.config.pvid = pvid;
3936 info.config.reject.tagged =
3937 data->dev_conf.txmode.hw_vlan_reject_tagged;
3938 info.config.reject.untagged =
3939 data->dev_conf.txmode.hw_vlan_reject_untagged;
3942 ret = ice_vsi_vlan_pvid_set(vsi, &info);
3944 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3952 ice_get_eeprom_length(struct rte_eth_dev *dev)
3954 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3956 /* Convert word count to byte count */
3957 return hw->nvm.sr_words << 1;
3961 ice_get_eeprom(struct rte_eth_dev *dev,
3962 struct rte_dev_eeprom_info *eeprom)
3964 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3965 uint16_t *data = eeprom->data;
3966 uint16_t first_word, last_word, nwords;
3967 enum ice_status status = ICE_SUCCESS;
3969 first_word = eeprom->offset >> 1;
3970 last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3971 nwords = last_word - first_word + 1;
3973 if (first_word >= hw->nvm.sr_words ||
3974 last_word >= hw->nvm.sr_words) {
3975 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3979 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3981 status = ice_read_sr_buf(hw, first_word, &nwords, data);
3983 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3984 eeprom->length = sizeof(uint16_t) * nwords;
3992 ice_stat_update_32(struct ice_hw *hw,
4000 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4004 if (new_data >= *offset)
4005 *stat = (uint64_t)(new_data - *offset);
4007 *stat = (uint64_t)((new_data +
4008 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4013 ice_stat_update_40(struct ice_hw *hw,
4022 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4023 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4029 if (new_data >= *offset)
4030 *stat = new_data - *offset;
4032 *stat = (uint64_t)((new_data +
4033 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4036 *stat &= ICE_40_BIT_MASK;
4039 /* Get all the statistics of a VSI */
4041 ice_update_vsi_stats(struct ice_vsi *vsi)
4043 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4044 struct ice_eth_stats *nes = &vsi->eth_stats;
4045 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4046 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4048 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4049 vsi->offset_loaded, &oes->rx_bytes,
4051 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4052 vsi->offset_loaded, &oes->rx_unicast,
4054 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4055 vsi->offset_loaded, &oes->rx_multicast,
4056 &nes->rx_multicast);
4057 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4058 vsi->offset_loaded, &oes->rx_broadcast,
4059 &nes->rx_broadcast);
4060 /* exclude CRC bytes */
4061 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4062 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4064 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4065 &oes->rx_discards, &nes->rx_discards);
4066 /* GLV_REPC not supported */
4067 /* GLV_RMPC not supported */
4068 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4069 &oes->rx_unknown_protocol,
4070 &nes->rx_unknown_protocol);
4071 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4072 vsi->offset_loaded, &oes->tx_bytes,
4074 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4075 vsi->offset_loaded, &oes->tx_unicast,
4077 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4078 vsi->offset_loaded, &oes->tx_multicast,
4079 &nes->tx_multicast);
4080 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4081 vsi->offset_loaded, &oes->tx_broadcast,
4082 &nes->tx_broadcast);
4083 /* GLV_TDPC not supported */
4084 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4085 &oes->tx_errors, &nes->tx_errors);
4086 vsi->offset_loaded = true;
4088 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4090 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4091 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4092 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4093 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4094 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4095 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4096 nes->rx_unknown_protocol);
4097 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4098 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4099 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4100 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4101 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4102 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4103 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4108 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4110 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4111 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4113 /* Get statistics of struct ice_eth_stats */
4114 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4115 GLPRT_GORCL(hw->port_info->lport),
4116 pf->offset_loaded, &os->eth.rx_bytes,
4118 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4119 GLPRT_UPRCL(hw->port_info->lport),
4120 pf->offset_loaded, &os->eth.rx_unicast,
4121 &ns->eth.rx_unicast);
4122 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4123 GLPRT_MPRCL(hw->port_info->lport),
4124 pf->offset_loaded, &os->eth.rx_multicast,
4125 &ns->eth.rx_multicast);
4126 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4127 GLPRT_BPRCL(hw->port_info->lport),
4128 pf->offset_loaded, &os->eth.rx_broadcast,
4129 &ns->eth.rx_broadcast);
4130 ice_stat_update_32(hw, PRTRPB_RDPC,
4131 pf->offset_loaded, &os->eth.rx_discards,
4132 &ns->eth.rx_discards);
4134 /* Workaround: CRC size should not be included in byte statistics,
4135 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4138 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4139 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4141 /* GLPRT_REPC not supported */
4142 /* GLPRT_RMPC not supported */
4143 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4145 &os->eth.rx_unknown_protocol,
4146 &ns->eth.rx_unknown_protocol);
4147 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4148 GLPRT_GOTCL(hw->port_info->lport),
4149 pf->offset_loaded, &os->eth.tx_bytes,
4151 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4152 GLPRT_UPTCL(hw->port_info->lport),
4153 pf->offset_loaded, &os->eth.tx_unicast,
4154 &ns->eth.tx_unicast);
4155 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4156 GLPRT_MPTCL(hw->port_info->lport),
4157 pf->offset_loaded, &os->eth.tx_multicast,
4158 &ns->eth.tx_multicast);
4159 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4160 GLPRT_BPTCL(hw->port_info->lport),
4161 pf->offset_loaded, &os->eth.tx_broadcast,
4162 &ns->eth.tx_broadcast);
4163 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4164 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4166 /* GLPRT_TEPC not supported */
4168 /* additional port specific stats */
4169 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4170 pf->offset_loaded, &os->tx_dropped_link_down,
4171 &ns->tx_dropped_link_down);
4172 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4173 pf->offset_loaded, &os->crc_errors,
4175 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4176 pf->offset_loaded, &os->illegal_bytes,
4177 &ns->illegal_bytes);
4178 /* GLPRT_ERRBC not supported */
4179 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4180 pf->offset_loaded, &os->mac_local_faults,
4181 &ns->mac_local_faults);
4182 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4183 pf->offset_loaded, &os->mac_remote_faults,
4184 &ns->mac_remote_faults);
4186 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4187 pf->offset_loaded, &os->rx_len_errors,
4188 &ns->rx_len_errors);
4190 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4191 pf->offset_loaded, &os->link_xon_rx,
4193 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4194 pf->offset_loaded, &os->link_xoff_rx,
4196 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4197 pf->offset_loaded, &os->link_xon_tx,
4199 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4200 pf->offset_loaded, &os->link_xoff_tx,
4202 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4203 GLPRT_PRC64L(hw->port_info->lport),
4204 pf->offset_loaded, &os->rx_size_64,
4206 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4207 GLPRT_PRC127L(hw->port_info->lport),
4208 pf->offset_loaded, &os->rx_size_127,
4210 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4211 GLPRT_PRC255L(hw->port_info->lport),
4212 pf->offset_loaded, &os->rx_size_255,
4214 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4215 GLPRT_PRC511L(hw->port_info->lport),
4216 pf->offset_loaded, &os->rx_size_511,
4218 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4219 GLPRT_PRC1023L(hw->port_info->lport),
4220 pf->offset_loaded, &os->rx_size_1023,
4222 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4223 GLPRT_PRC1522L(hw->port_info->lport),
4224 pf->offset_loaded, &os->rx_size_1522,
4226 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4227 GLPRT_PRC9522L(hw->port_info->lport),
4228 pf->offset_loaded, &os->rx_size_big,
4230 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4231 pf->offset_loaded, &os->rx_undersize,
4233 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4234 pf->offset_loaded, &os->rx_fragments,
4236 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4237 pf->offset_loaded, &os->rx_oversize,
4239 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4240 pf->offset_loaded, &os->rx_jabber,
4242 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4243 GLPRT_PTC64L(hw->port_info->lport),
4244 pf->offset_loaded, &os->tx_size_64,
4246 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4247 GLPRT_PTC127L(hw->port_info->lport),
4248 pf->offset_loaded, &os->tx_size_127,
4250 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4251 GLPRT_PTC255L(hw->port_info->lport),
4252 pf->offset_loaded, &os->tx_size_255,
4254 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4255 GLPRT_PTC511L(hw->port_info->lport),
4256 pf->offset_loaded, &os->tx_size_511,
4258 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4259 GLPRT_PTC1023L(hw->port_info->lport),
4260 pf->offset_loaded, &os->tx_size_1023,
4262 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4263 GLPRT_PTC1522L(hw->port_info->lport),
4264 pf->offset_loaded, &os->tx_size_1522,
4266 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4267 GLPRT_PTC9522L(hw->port_info->lport),
4268 pf->offset_loaded, &os->tx_size_big,
4271 /* GLPRT_MSPDC not supported */
4272 /* GLPRT_XEC not supported */
4274 pf->offset_loaded = true;
4277 ice_update_vsi_stats(pf->main_vsi);
4280 /* Get all statistics of a port */
4282 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4284 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4285 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4286 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4288 /* call read registers - updates values, now write them to struct */
4289 ice_read_stats_registers(pf, hw);
4291 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4292 pf->main_vsi->eth_stats.rx_multicast +
4293 pf->main_vsi->eth_stats.rx_broadcast -
4294 pf->main_vsi->eth_stats.rx_discards;
4295 stats->opackets = ns->eth.tx_unicast +
4296 ns->eth.tx_multicast +
4297 ns->eth.tx_broadcast;
4298 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
4299 stats->obytes = ns->eth.tx_bytes;
4300 stats->oerrors = ns->eth.tx_errors +
4301 pf->main_vsi->eth_stats.tx_errors;
4304 stats->imissed = ns->eth.rx_discards +
4305 pf->main_vsi->eth_stats.rx_discards;
4306 stats->ierrors = ns->crc_errors +
4308 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4310 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4311 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
4312 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4313 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4314 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4315 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4316 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4317 pf->main_vsi->eth_stats.rx_discards);
4318 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4319 ns->eth.rx_unknown_protocol);
4320 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
4321 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4322 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4323 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4324 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4325 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4326 pf->main_vsi->eth_stats.tx_discards);
4327 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
4329 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
4330 ns->tx_dropped_link_down);
4331 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4332 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
4334 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
4335 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
4336 ns->mac_local_faults);
4337 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
4338 ns->mac_remote_faults);
4339 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
4340 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
4341 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
4342 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
4343 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
4344 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
4345 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
4346 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
4347 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
4348 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
4349 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
4350 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
4351 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
4352 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
4353 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
4354 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
4355 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
4356 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
4357 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
4358 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
4359 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
4360 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
4361 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
4362 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4366 /* Reset the statistics */
4368 ice_stats_reset(struct rte_eth_dev *dev)
4370 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4371 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4373 /* Mark PF and VSI stats to update the offset, aka "reset" */
4374 pf->offset_loaded = false;
4376 pf->main_vsi->offset_loaded = false;
4378 /* read the stats, reading current register values into offset */
4379 ice_read_stats_registers(pf, hw);
4385 ice_xstats_calc_num(void)
4389 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4395 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4398 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4399 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4402 struct ice_hw_port_stats *hw_stats = &pf->stats;
4404 count = ice_xstats_calc_num();
4408 ice_read_stats_registers(pf, hw);
4415 /* Get stats from ice_eth_stats struct */
4416 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4417 xstats[count].value =
4418 *(uint64_t *)((char *)&hw_stats->eth +
4419 ice_stats_strings[i].offset);
4420 xstats[count].id = count;
4424 /* Get individiual stats from ice_hw_port struct */
4425 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4426 xstats[count].value =
4427 *(uint64_t *)((char *)hw_stats +
4428 ice_hw_port_strings[i].offset);
4429 xstats[count].id = count;
4436 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4437 struct rte_eth_xstat_name *xstats_names,
4438 __rte_unused unsigned int limit)
4440 unsigned int count = 0;
4444 return ice_xstats_calc_num();
4446 /* Note: limit checked in rte_eth_xstats_names() */
4448 /* Get stats from ice_eth_stats struct */
4449 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4450 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4451 sizeof(xstats_names[count].name));
4455 /* Get individiual stats from ice_hw_port struct */
4456 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4457 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4458 sizeof(xstats_names[count].name));
4466 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4467 enum rte_filter_type filter_type,
4468 enum rte_filter_op filter_op,
4476 switch (filter_type) {
4477 case RTE_ETH_FILTER_GENERIC:
4478 if (filter_op != RTE_ETH_FILTER_GET)
4480 *(const void **)arg = &ice_flow_ops;
4483 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4492 /* Add UDP tunneling port */
4494 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4495 struct rte_eth_udp_tunnel *udp_tunnel)
4498 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4500 if (udp_tunnel == NULL)
4503 switch (udp_tunnel->prot_type) {
4504 case RTE_TUNNEL_TYPE_VXLAN:
4505 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4508 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4516 /* Delete UDP tunneling port */
4518 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4519 struct rte_eth_udp_tunnel *udp_tunnel)
4522 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524 if (udp_tunnel == NULL)
4527 switch (udp_tunnel->prot_type) {
4528 case RTE_TUNNEL_TYPE_VXLAN:
4529 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4532 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4541 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4542 struct rte_pci_device *pci_dev)
4544 return rte_eth_dev_pci_generic_probe(pci_dev,
4545 sizeof(struct ice_adapter),
4550 ice_pci_remove(struct rte_pci_device *pci_dev)
4552 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4555 static struct rte_pci_driver rte_ice_pmd = {
4556 .id_table = pci_id_ice_map,
4557 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4558 .probe = ice_pci_probe,
4559 .remove = ice_pci_remove,
4563 * Driver initialization routine.
4564 * Invoked once at EAL init time.
4565 * Register itself as the [Poll Mode] Driver of PCI devices.
4567 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4568 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4569 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4570 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4571 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4572 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4573 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
4575 RTE_INIT(ice_init_log)
4577 ice_logtype_init = rte_log_register("pmd.net.ice.init");
4578 if (ice_logtype_init >= 0)
4579 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4580 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4581 if (ice_logtype_driver >= 0)
4582 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4584 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4585 ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4586 if (ice_logtype_rx >= 0)
4587 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4590 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4591 ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4592 if (ice_logtype_tx >= 0)
4593 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4596 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4597 ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4598 if (ice_logtype_tx_free >= 0)
4599 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);