1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
18 #include "rte_pmd_ice.h"
19 #include "ice_ethdev.h"
21 #include "ice_generic_flow.h"
24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
26 #define ICE_FLOW_MARK_SUPPORT_ARG "flow-mark-support"
27 #define ICE_PROTO_XTR_ARG "proto_xtr"
29 static const char * const ice_valid_args[] = {
30 ICE_SAFE_MODE_SUPPORT_ARG,
31 ICE_PIPELINE_MODE_SUPPORT_ARG,
32 ICE_FLOW_MARK_SUPPORT_ARG,
37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
38 .name = "ice_dynfield_proto_xtr_metadata",
39 .size = sizeof(uint32_t),
40 .align = __alignof__(uint32_t),
44 struct proto_xtr_ol_flag {
45 const struct rte_mbuf_dynflag param;
50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
52 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
55 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
58 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
60 [PROTO_XTR_IPV6_FLOW] = {
61 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
64 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
68 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
70 /* DDP package search path */
71 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
72 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
73 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
74 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
76 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
77 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
78 #define ICE_MAX_PKG_FILENAME_SIZE 256
79 #define ICE_MAX_RES_DESC_NUM 1024
82 int ice_logtype_driver;
83 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
86 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
89 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
90 int ice_logtype_tx_free;
93 static int ice_dev_configure(struct rte_eth_dev *dev);
94 static int ice_dev_start(struct rte_eth_dev *dev);
95 static void ice_dev_stop(struct rte_eth_dev *dev);
96 static void ice_dev_close(struct rte_eth_dev *dev);
97 static int ice_dev_reset(struct rte_eth_dev *dev);
98 static int ice_dev_info_get(struct rte_eth_dev *dev,
99 struct rte_eth_dev_info *dev_info);
100 static int ice_link_update(struct rte_eth_dev *dev,
101 int wait_to_complete);
102 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
103 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
105 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
106 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
107 static int ice_rss_reta_update(struct rte_eth_dev *dev,
108 struct rte_eth_rss_reta_entry64 *reta_conf,
110 static int ice_rss_reta_query(struct rte_eth_dev *dev,
111 struct rte_eth_rss_reta_entry64 *reta_conf,
113 static int ice_rss_hash_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_conf *rss_conf);
115 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
116 struct rte_eth_rss_conf *rss_conf);
117 static int ice_promisc_enable(struct rte_eth_dev *dev);
118 static int ice_promisc_disable(struct rte_eth_dev *dev);
119 static int ice_allmulti_enable(struct rte_eth_dev *dev);
120 static int ice_allmulti_disable(struct rte_eth_dev *dev);
121 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
124 static int ice_macaddr_set(struct rte_eth_dev *dev,
125 struct rte_ether_addr *mac_addr);
126 static int ice_macaddr_add(struct rte_eth_dev *dev,
127 struct rte_ether_addr *mac_addr,
128 __rte_unused uint32_t index,
130 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
131 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
133 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
135 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
137 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
138 uint16_t pvid, int on);
139 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
140 static int ice_get_eeprom(struct rte_eth_dev *dev,
141 struct rte_dev_eeprom_info *eeprom);
142 static int ice_stats_get(struct rte_eth_dev *dev,
143 struct rte_eth_stats *stats);
144 static int ice_stats_reset(struct rte_eth_dev *dev);
145 static int ice_xstats_get(struct rte_eth_dev *dev,
146 struct rte_eth_xstat *xstats, unsigned int n);
147 static int ice_xstats_get_names(struct rte_eth_dev *dev,
148 struct rte_eth_xstat_name *xstats_names,
150 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
151 enum rte_filter_type filter_type,
152 enum rte_filter_op filter_op,
154 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
155 struct rte_eth_udp_tunnel *udp_tunnel);
156 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
157 struct rte_eth_udp_tunnel *udp_tunnel);
159 static const struct rte_pci_id pci_id_ice_map[] = {
160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
164 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
165 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
166 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_BACKPLANE) },
167 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_QSFP) },
168 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_SFP) },
169 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_10G_BASE_T) },
170 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_SGMII) },
171 { .vendor_id = 0, /* sentinel */ },
174 static const struct eth_dev_ops ice_eth_dev_ops = {
175 .dev_configure = ice_dev_configure,
176 .dev_start = ice_dev_start,
177 .dev_stop = ice_dev_stop,
178 .dev_close = ice_dev_close,
179 .dev_reset = ice_dev_reset,
180 .dev_set_link_up = ice_dev_set_link_up,
181 .dev_set_link_down = ice_dev_set_link_down,
182 .rx_queue_start = ice_rx_queue_start,
183 .rx_queue_stop = ice_rx_queue_stop,
184 .tx_queue_start = ice_tx_queue_start,
185 .tx_queue_stop = ice_tx_queue_stop,
186 .rx_queue_setup = ice_rx_queue_setup,
187 .rx_queue_release = ice_rx_queue_release,
188 .tx_queue_setup = ice_tx_queue_setup,
189 .tx_queue_release = ice_tx_queue_release,
190 .dev_infos_get = ice_dev_info_get,
191 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
192 .link_update = ice_link_update,
193 .mtu_set = ice_mtu_set,
194 .mac_addr_set = ice_macaddr_set,
195 .mac_addr_add = ice_macaddr_add,
196 .mac_addr_remove = ice_macaddr_remove,
197 .vlan_filter_set = ice_vlan_filter_set,
198 .vlan_offload_set = ice_vlan_offload_set,
199 .reta_update = ice_rss_reta_update,
200 .reta_query = ice_rss_reta_query,
201 .rss_hash_update = ice_rss_hash_update,
202 .rss_hash_conf_get = ice_rss_hash_conf_get,
203 .promiscuous_enable = ice_promisc_enable,
204 .promiscuous_disable = ice_promisc_disable,
205 .allmulticast_enable = ice_allmulti_enable,
206 .allmulticast_disable = ice_allmulti_disable,
207 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
208 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
209 .fw_version_get = ice_fw_version_get,
210 .vlan_pvid_set = ice_vlan_pvid_set,
211 .rxq_info_get = ice_rxq_info_get,
212 .txq_info_get = ice_txq_info_get,
213 .rx_burst_mode_get = ice_rx_burst_mode_get,
214 .tx_burst_mode_get = ice_tx_burst_mode_get,
215 .get_eeprom_length = ice_get_eeprom_length,
216 .get_eeprom = ice_get_eeprom,
217 .rx_queue_count = ice_rx_queue_count,
218 .rx_descriptor_status = ice_rx_descriptor_status,
219 .tx_descriptor_status = ice_tx_descriptor_status,
220 .stats_get = ice_stats_get,
221 .stats_reset = ice_stats_reset,
222 .xstats_get = ice_xstats_get,
223 .xstats_get_names = ice_xstats_get_names,
224 .xstats_reset = ice_stats_reset,
225 .filter_ctrl = ice_dev_filter_ctrl,
226 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
227 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
230 /* store statistics names and its offset in stats structure */
231 struct ice_xstats_name_off {
232 char name[RTE_ETH_XSTATS_NAME_SIZE];
236 static const struct ice_xstats_name_off ice_stats_strings[] = {
237 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
238 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
239 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
240 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
241 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
242 rx_unknown_protocol)},
243 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
244 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
245 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
246 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
249 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
250 sizeof(ice_stats_strings[0]))
252 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
253 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
254 tx_dropped_link_down)},
255 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
256 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
258 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
259 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
261 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
263 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
265 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
266 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
267 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
268 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
269 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
270 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
272 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
274 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
276 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
278 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
280 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
282 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
284 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
286 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
287 mac_short_pkt_dropped)},
288 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
290 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
291 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
292 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
294 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
296 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
298 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
300 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
302 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
306 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
307 sizeof(ice_hw_port_strings[0]))
310 ice_init_controlq_parameter(struct ice_hw *hw)
312 /* fields for adminq */
313 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
314 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
315 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
316 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
318 /* fields for mailboxq, DPDK used as PF host */
319 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
320 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
321 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
322 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
326 lookup_proto_xtr_type(const char *xtr_name)
330 enum proto_xtr_type type;
332 { "vlan", PROTO_XTR_VLAN },
333 { "ipv4", PROTO_XTR_IPV4 },
334 { "ipv6", PROTO_XTR_IPV6 },
335 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
336 { "tcp", PROTO_XTR_TCP },
340 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
341 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
342 return xtr_type_map[i].type;
349 * Parse elem, the elem could be single number/range or '(' ')' group
350 * 1) A single number elem, it's just a simple digit. e.g. 9
351 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
352 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
353 * Within group elem, '-' used for a range separator;
354 * ',' used for a single number.
357 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
359 const char *str = input;
364 while (isblank(*str))
367 if (!isdigit(*str) && *str != '(')
370 /* process single number or single range of number */
373 idx = strtoul(str, &end, 10);
374 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
377 while (isblank(*end))
383 /* process single <number>-<number> */
386 while (isblank(*end))
392 idx = strtoul(end, &end, 10);
393 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
397 while (isblank(*end))
404 for (idx = RTE_MIN(min, max);
405 idx <= RTE_MAX(min, max); idx++)
406 devargs->proto_xtr[idx] = xtr_type;
411 /* process set within bracket */
413 while (isblank(*str))
418 min = ICE_MAX_QUEUE_NUM;
420 /* go ahead to the first digit */
421 while (isblank(*str))
426 /* get the digit value */
428 idx = strtoul(str, &end, 10);
429 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
432 /* go ahead to separator '-',',' and ')' */
433 while (isblank(*end))
436 if (min == ICE_MAX_QUEUE_NUM)
438 else /* avoid continuous '-' */
440 } else if (*end == ',' || *end == ')') {
442 if (min == ICE_MAX_QUEUE_NUM)
445 for (idx = RTE_MIN(min, max);
446 idx <= RTE_MAX(min, max); idx++)
447 devargs->proto_xtr[idx] = xtr_type;
449 min = ICE_MAX_QUEUE_NUM;
455 } while (*end != ')' && *end != '\0');
461 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
463 const char *queue_start;
468 while (isblank(*queues))
471 if (*queues != '[') {
472 xtr_type = lookup_proto_xtr_type(queues);
476 devargs->proto_xtr_dflt = xtr_type;
483 while (isblank(*queues))
488 queue_start = queues;
490 /* go across a complete bracket */
491 if (*queue_start == '(') {
492 queues += strcspn(queues, ")");
497 /* scan the separator ':' */
498 queues += strcspn(queues, ":");
499 if (*queues++ != ':')
501 while (isblank(*queues))
504 for (idx = 0; ; idx++) {
505 if (isblank(queues[idx]) ||
506 queues[idx] == ',' ||
507 queues[idx] == ']' ||
511 if (idx > sizeof(xtr_name) - 2)
514 xtr_name[idx] = queues[idx];
516 xtr_name[idx] = '\0';
517 xtr_type = lookup_proto_xtr_type(xtr_name);
523 while (isblank(*queues) || *queues == ',' || *queues == ']')
526 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
528 } while (*queues != '\0');
534 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
537 struct ice_devargs *devargs = extra_args;
539 if (value == NULL || extra_args == NULL)
542 if (parse_queue_proto_xtr(value, devargs) < 0) {
544 "The protocol extraction parameter is wrong : '%s'",
553 ice_proto_xtr_support(struct ice_hw *hw)
555 #define FLX_REG(val, fld, idx) \
556 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
557 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
563 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
564 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
565 ICE_PROT_IPV4_OF_OR_S },
566 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
567 ICE_PROT_IPV6_OF_OR_S },
568 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
569 ICE_PROT_IPV6_OF_OR_S },
570 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
574 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
575 uint32_t rxdid = xtr_sets[i].rxdid;
578 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
579 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
581 if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
582 FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
586 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
587 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
589 if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
590 FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
599 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
602 struct pool_entry *entry;
607 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
610 "Failed to allocate memory for resource pool");
614 /* queue heap initialize */
615 pool->num_free = num;
618 LIST_INIT(&pool->alloc_list);
619 LIST_INIT(&pool->free_list);
621 /* Initialize element */
625 LIST_INSERT_HEAD(&pool->free_list, entry, next);
630 ice_res_pool_alloc(struct ice_res_pool_info *pool,
633 struct pool_entry *entry, *valid_entry;
636 PMD_INIT_LOG(ERR, "Invalid parameter");
640 if (pool->num_free < num) {
641 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
642 num, pool->num_free);
647 /* Lookup in free list and find most fit one */
648 LIST_FOREACH(entry, &pool->free_list, next) {
649 if (entry->len >= num) {
651 if (entry->len == num) {
656 valid_entry->len > entry->len)
661 /* Not find one to satisfy the request, return */
663 PMD_INIT_LOG(ERR, "No valid entry found");
667 * The entry have equal queue number as requested,
668 * remove it from alloc_list.
670 if (valid_entry->len == num) {
671 LIST_REMOVE(valid_entry, next);
674 * The entry have more numbers than requested,
675 * create a new entry for alloc_list and minus its
676 * queue base and number in free_list.
678 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
681 "Failed to allocate memory for "
685 entry->base = valid_entry->base;
687 valid_entry->base += num;
688 valid_entry->len -= num;
692 /* Insert it into alloc list, not sorted */
693 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
695 pool->num_free -= valid_entry->len;
696 pool->num_alloc += valid_entry->len;
698 return valid_entry->base + pool->base;
702 ice_res_pool_destroy(struct ice_res_pool_info *pool)
704 struct pool_entry *entry, *next_entry;
709 for (entry = LIST_FIRST(&pool->alloc_list);
710 entry && (next_entry = LIST_NEXT(entry, next), 1);
711 entry = next_entry) {
712 LIST_REMOVE(entry, next);
716 for (entry = LIST_FIRST(&pool->free_list);
717 entry && (next_entry = LIST_NEXT(entry, next), 1);
718 entry = next_entry) {
719 LIST_REMOVE(entry, next);
726 LIST_INIT(&pool->alloc_list);
727 LIST_INIT(&pool->free_list);
731 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
733 /* Set VSI LUT selection */
734 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
735 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
736 /* Set Hash scheme */
737 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
738 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
740 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
743 static enum ice_status
744 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
745 struct ice_aqc_vsi_props *info,
746 uint8_t enabled_tcmap)
748 uint16_t bsf, qp_idx;
750 /* default tc 0 now. Multi-TC supporting need to be done later.
751 * Configure TC and queue mapping parameters, for enabled TC,
752 * allocate qpnum_per_tc queues to this traffic.
754 if (enabled_tcmap != 0x01) {
755 PMD_INIT_LOG(ERR, "only TC0 is supported");
759 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
760 bsf = rte_bsf32(vsi->nb_qps);
761 /* Adjust the queue number to actual queues that can be applied */
762 vsi->nb_qps = 0x1 << bsf;
765 /* Set tc and queue mapping with VSI */
766 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
767 ICE_AQ_VSI_TC_Q_OFFSET_S) |
768 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
770 /* Associate queue number with VSI */
771 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
772 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
773 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
774 info->valid_sections |=
775 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
776 /* Set the info.ingress_table and info.egress_table
777 * for UP translate table. Now just set it to 1:1 map by default
778 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
780 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
781 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
782 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
783 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
788 ice_init_mac_address(struct rte_eth_dev *dev)
790 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
792 if (!rte_is_unicast_ether_addr
793 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
794 PMD_INIT_LOG(ERR, "Invalid MAC address");
799 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
800 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
802 dev->data->mac_addrs =
803 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
804 if (!dev->data->mac_addrs) {
806 "Failed to allocate memory to store mac address");
809 /* store it to dev data */
811 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
812 &dev->data->mac_addrs[0]);
816 /* Find out specific MAC filter */
817 static struct ice_mac_filter *
818 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
820 struct ice_mac_filter *f;
822 TAILQ_FOREACH(f, &vsi->mac_list, next) {
823 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
831 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
833 struct ice_fltr_list_entry *m_list_itr = NULL;
834 struct ice_mac_filter *f;
835 struct LIST_HEAD_TYPE list_head;
836 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
839 /* If it's added and configured, return */
840 f = ice_find_mac_filter(vsi, mac_addr);
842 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
846 INIT_LIST_HEAD(&list_head);
848 m_list_itr = (struct ice_fltr_list_entry *)
849 ice_malloc(hw, sizeof(*m_list_itr));
854 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
855 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
856 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
857 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
858 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
859 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
860 m_list_itr->fltr_info.vsi_handle = vsi->idx;
862 LIST_ADD(&m_list_itr->list_entry, &list_head);
865 ret = ice_add_mac(hw, &list_head);
866 if (ret != ICE_SUCCESS) {
867 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
871 /* Add the mac addr into mac list */
872 f = rte_zmalloc(NULL, sizeof(*f), 0);
874 PMD_DRV_LOG(ERR, "failed to allocate memory");
878 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
879 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
885 rte_free(m_list_itr);
890 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
892 struct ice_fltr_list_entry *m_list_itr = NULL;
893 struct ice_mac_filter *f;
894 struct LIST_HEAD_TYPE list_head;
895 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
898 /* Can't find it, return an error */
899 f = ice_find_mac_filter(vsi, mac_addr);
903 INIT_LIST_HEAD(&list_head);
905 m_list_itr = (struct ice_fltr_list_entry *)
906 ice_malloc(hw, sizeof(*m_list_itr));
911 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
912 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
913 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
914 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
915 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
916 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
917 m_list_itr->fltr_info.vsi_handle = vsi->idx;
919 LIST_ADD(&m_list_itr->list_entry, &list_head);
921 /* remove the mac filter */
922 ret = ice_remove_mac(hw, &list_head);
923 if (ret != ICE_SUCCESS) {
924 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
929 /* Remove the mac addr from mac list */
930 TAILQ_REMOVE(&vsi->mac_list, f, next);
936 rte_free(m_list_itr);
940 /* Find out specific VLAN filter */
941 static struct ice_vlan_filter *
942 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
944 struct ice_vlan_filter *f;
946 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
947 if (vlan_id == f->vlan_info.vlan_id)
955 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
957 struct ice_fltr_list_entry *v_list_itr = NULL;
958 struct ice_vlan_filter *f;
959 struct LIST_HEAD_TYPE list_head;
963 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
966 hw = ICE_VSI_TO_HW(vsi);
968 /* If it's added and configured, return. */
969 f = ice_find_vlan_filter(vsi, vlan_id);
971 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
975 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
978 INIT_LIST_HEAD(&list_head);
980 v_list_itr = (struct ice_fltr_list_entry *)
981 ice_malloc(hw, sizeof(*v_list_itr));
986 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
987 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
988 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
989 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
990 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
991 v_list_itr->fltr_info.vsi_handle = vsi->idx;
993 LIST_ADD(&v_list_itr->list_entry, &list_head);
996 ret = ice_add_vlan(hw, &list_head);
997 if (ret != ICE_SUCCESS) {
998 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1003 /* Add vlan into vlan list */
1004 f = rte_zmalloc(NULL, sizeof(*f), 0);
1006 PMD_DRV_LOG(ERR, "failed to allocate memory");
1010 f->vlan_info.vlan_id = vlan_id;
1011 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1017 rte_free(v_list_itr);
1022 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1024 struct ice_fltr_list_entry *v_list_itr = NULL;
1025 struct ice_vlan_filter *f;
1026 struct LIST_HEAD_TYPE list_head;
1031 * Vlan 0 is the generic filter for untagged packets
1032 * and can't be removed.
1034 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1037 hw = ICE_VSI_TO_HW(vsi);
1039 /* Can't find it, return an error */
1040 f = ice_find_vlan_filter(vsi, vlan_id);
1044 INIT_LIST_HEAD(&list_head);
1046 v_list_itr = (struct ice_fltr_list_entry *)
1047 ice_malloc(hw, sizeof(*v_list_itr));
1053 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1054 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1055 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1056 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1057 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1058 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1060 LIST_ADD(&v_list_itr->list_entry, &list_head);
1062 /* remove the vlan filter */
1063 ret = ice_remove_vlan(hw, &list_head);
1064 if (ret != ICE_SUCCESS) {
1065 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1070 /* Remove the vlan id from vlan list */
1071 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1077 rte_free(v_list_itr);
1082 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1084 struct ice_mac_filter *m_f;
1085 struct ice_vlan_filter *v_f;
1088 if (!vsi || !vsi->mac_num)
1091 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1092 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1093 if (ret != ICE_SUCCESS) {
1099 if (vsi->vlan_num == 0)
1102 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1103 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1104 if (ret != ICE_SUCCESS) {
1115 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1117 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1118 struct ice_vsi_ctx ctxt;
1122 /* Check if it has been already on or off */
1123 if (vsi->info.valid_sections &
1124 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1126 if ((vsi->info.outer_tag_flags &
1127 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1128 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1129 return 0; /* already on */
1131 if (!(vsi->info.outer_tag_flags &
1132 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1133 return 0; /* already off */
1138 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1141 /* clear global insertion and use per packet insertion */
1142 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1143 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1144 vsi->info.outer_tag_flags |= qinq_flags;
1145 /* use default vlan type 0x8100 */
1146 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1147 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1148 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1149 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1150 ctxt.info.valid_sections =
1151 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1152 ctxt.vsi_num = vsi->vsi_id;
1153 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1156 "Update VSI failed to %s qinq stripping",
1157 on ? "enable" : "disable");
1161 vsi->info.valid_sections |=
1162 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1168 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1170 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1171 struct ice_vsi_ctx ctxt;
1175 /* Check if it has been already on or off */
1176 if (vsi->info.valid_sections &
1177 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1179 if ((vsi->info.outer_tag_flags &
1180 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1181 ICE_AQ_VSI_OUTER_TAG_COPY)
1182 return 0; /* already on */
1184 if ((vsi->info.outer_tag_flags &
1185 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1186 ICE_AQ_VSI_OUTER_TAG_NOTHING)
1187 return 0; /* already off */
1192 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1194 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1195 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1196 vsi->info.outer_tag_flags |= qinq_flags;
1197 /* use default vlan type 0x8100 */
1198 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1199 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1200 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1201 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1202 ctxt.info.valid_sections =
1203 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1204 ctxt.vsi_num = vsi->vsi_id;
1205 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1208 "Update VSI failed to %s qinq stripping",
1209 on ? "enable" : "disable");
1213 vsi->info.valid_sections |=
1214 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1220 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1224 ret = ice_vsi_config_qinq_stripping(vsi, on);
1226 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1228 ret = ice_vsi_config_qinq_insertion(vsi, on);
1230 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1237 ice_pf_enable_irq0(struct ice_hw *hw)
1239 /* reset the registers */
1240 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1241 ICE_READ_REG(hw, PFINT_OICR);
1244 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1245 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1246 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1248 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1249 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1250 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1251 PFINT_OICR_CTL_ITR_INDX_M) |
1252 PFINT_OICR_CTL_CAUSE_ENA_M);
1254 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1255 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1256 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1257 PFINT_FW_CTL_ITR_INDX_M) |
1258 PFINT_FW_CTL_CAUSE_ENA_M);
1260 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1263 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1264 GLINT_DYN_CTL_INTENA_M |
1265 GLINT_DYN_CTL_CLEARPBA_M |
1266 GLINT_DYN_CTL_ITR_INDX_M);
1273 ice_pf_disable_irq0(struct ice_hw *hw)
1275 /* Disable all interrupt types */
1276 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1282 ice_handle_aq_msg(struct rte_eth_dev *dev)
1284 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285 struct ice_ctl_q_info *cq = &hw->adminq;
1286 struct ice_rq_event_info event;
1287 uint16_t pending, opcode;
1290 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1291 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1292 if (!event.msg_buf) {
1293 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1299 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1301 if (ret != ICE_SUCCESS) {
1303 "Failed to read msg from AdminQ, "
1305 hw->adminq.sq_last_status);
1308 opcode = rte_le_to_cpu_16(event.desc.opcode);
1311 case ice_aqc_opc_get_link_status:
1312 ret = ice_link_update(dev, 0);
1314 _rte_eth_dev_callback_process
1315 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1318 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1323 rte_free(event.msg_buf);
1328 * Interrupt handler triggered by NIC for handling
1329 * specific interrupt.
1332 * Pointer to interrupt handle.
1334 * The address of parameter (struct rte_eth_dev *) regsitered before.
1340 ice_interrupt_handler(void *param)
1342 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1343 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351 uint32_t int_fw_ctl;
1354 /* Disable interrupt */
1355 ice_pf_disable_irq0(hw);
1357 /* read out interrupt causes */
1358 oicr = ICE_READ_REG(hw, PFINT_OICR);
1360 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1363 /* No interrupt event indicated */
1364 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1365 PMD_DRV_LOG(INFO, "No interrupt event");
1370 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1371 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1372 ice_handle_aq_msg(dev);
1375 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1376 PMD_DRV_LOG(INFO, "OICR: link state change event");
1377 ret = ice_link_update(dev, 0);
1379 _rte_eth_dev_callback_process
1380 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1384 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1385 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1386 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1387 if (reg & GL_MDET_TX_PQM_VALID_M) {
1388 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1389 GL_MDET_TX_PQM_PF_NUM_S;
1390 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1391 GL_MDET_TX_PQM_MAL_TYPE_S;
1392 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1393 GL_MDET_TX_PQM_QNUM_S;
1395 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1396 "%d by PQM on TX queue %d PF# %d",
1397 event, queue, pf_num);
1400 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1401 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1402 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1403 GL_MDET_TX_TCLAN_PF_NUM_S;
1404 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1405 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1406 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1407 GL_MDET_TX_TCLAN_QNUM_S;
1409 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1410 "%d by TCLAN on TX queue %d PF# %d",
1411 event, queue, pf_num);
1415 /* Enable interrupt */
1416 ice_pf_enable_irq0(hw);
1417 rte_intr_ack(dev->intr_handle);
1421 ice_init_proto_xtr(struct rte_eth_dev *dev)
1423 struct ice_adapter *ad =
1424 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1425 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1426 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1427 const struct proto_xtr_ol_flag *ol_flag;
1428 bool proto_xtr_enable = false;
1432 if (!ice_proto_xtr_support(hw)) {
1433 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1437 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1438 if (unlikely(pf->proto_xtr == NULL)) {
1439 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1443 for (i = 0; i < pf->lan_nb_qps; i++) {
1444 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1445 ad->devargs.proto_xtr[i] :
1446 ad->devargs.proto_xtr_dflt;
1448 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1449 uint8_t type = pf->proto_xtr[i];
1451 ice_proto_xtr_ol_flag_params[type].required = true;
1452 proto_xtr_enable = true;
1456 if (likely(!proto_xtr_enable))
1459 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1460 if (unlikely(offset == -1)) {
1462 "Protocol extraction metadata is disabled in mbuf with error %d",
1468 "Protocol extraction metadata offset in mbuf is : %d",
1470 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1472 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1473 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1475 if (!ol_flag->required)
1478 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1479 if (unlikely(offset == -1)) {
1481 "Protocol extraction offload '%s' failed to register with error %d",
1482 ol_flag->param.name, -rte_errno);
1484 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1489 "Protocol extraction offload '%s' offset in mbuf is : %d",
1490 ol_flag->param.name, offset);
1491 *ol_flag->ol_flag = 1ULL << offset;
1495 /* Initialize SW parameters of PF */
1497 ice_pf_sw_init(struct rte_eth_dev *dev)
1499 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1500 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1503 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1504 hw->func_caps.common_cap.num_rxq);
1506 pf->lan_nb_qps = pf->lan_nb_qp_max;
1508 ice_init_proto_xtr(dev);
1510 if (hw->func_caps.fd_fltr_guar > 0 ||
1511 hw->func_caps.fd_fltr_best_effort > 0) {
1512 pf->flags |= ICE_FLAG_FDIR;
1513 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1514 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1516 pf->fdir_nb_qps = 0;
1518 pf->fdir_qp_offset = 0;
1524 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1526 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1527 struct ice_vsi *vsi = NULL;
1528 struct ice_vsi_ctx vsi_ctx;
1530 struct rte_ether_addr broadcast = {
1531 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1532 struct rte_ether_addr mac_addr;
1533 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1534 uint8_t tc_bitmap = 0x1;
1537 /* hw->num_lports = 1 in NIC mode */
1538 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1542 vsi->idx = pf->next_vsi_idx;
1545 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1546 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1547 vsi->vlan_anti_spoof_on = 0;
1548 vsi->vlan_filter_on = 1;
1549 TAILQ_INIT(&vsi->mac_list);
1550 TAILQ_INIT(&vsi->vlan_list);
1552 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1553 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1554 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1555 hw->func_caps.common_cap.rss_table_size;
1556 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1558 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1561 vsi->nb_qps = pf->lan_nb_qps;
1562 vsi->base_queue = 1;
1563 ice_vsi_config_default_rss(&vsi_ctx.info);
1564 vsi_ctx.alloc_from_pool = true;
1565 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1566 /* switch_id is queried by get_switch_config aq, which is done
1569 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1570 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1571 /* Allow all untagged or tagged packets */
1572 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1573 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1574 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1575 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1578 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1579 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1580 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1581 cfg = ICE_AQ_VSI_FD_ENABLE;
1582 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1583 vsi_ctx.info.max_fd_fltr_dedicated =
1584 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1585 vsi_ctx.info.max_fd_fltr_shared =
1586 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1588 /* Enable VLAN/UP trip */
1589 ret = ice_vsi_config_tc_queue_mapping(vsi,
1594 "tc queue mapping with vsi failed, "
1602 vsi->nb_qps = pf->fdir_nb_qps;
1603 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1604 vsi_ctx.alloc_from_pool = true;
1605 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1607 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1608 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1609 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1610 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1611 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1612 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1613 ret = ice_vsi_config_tc_queue_mapping(vsi,
1618 "tc queue mapping with vsi failed, "
1625 /* for other types of VSI */
1626 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1630 /* VF has MSIX interrupt in VF range, don't allocate here */
1631 if (type == ICE_VSI_PF) {
1632 ret = ice_res_pool_alloc(&pf->msix_pool,
1633 RTE_MIN(vsi->nb_qps,
1634 RTE_MAX_RXTX_INTR_VEC_ID));
1636 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1639 vsi->msix_intr = ret;
1640 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1641 } else if (type == ICE_VSI_CTRL) {
1642 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1644 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1647 vsi->msix_intr = ret;
1653 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1654 if (ret != ICE_SUCCESS) {
1655 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1658 /* store vsi information is SW structure */
1659 vsi->vsi_id = vsi_ctx.vsi_num;
1660 vsi->info = vsi_ctx.info;
1661 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1662 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1664 if (type == ICE_VSI_PF) {
1665 /* MAC configuration */
1666 rte_memcpy(pf->dev_addr.addr_bytes,
1667 hw->port_info->mac.perm_addr,
1670 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1671 ret = ice_add_mac_filter(vsi, &mac_addr);
1672 if (ret != ICE_SUCCESS)
1673 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1675 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1676 ret = ice_add_mac_filter(vsi, &mac_addr);
1677 if (ret != ICE_SUCCESS)
1678 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1681 /* At the beginning, only TC0. */
1682 /* What we need here is the maximam number of the TX queues.
1683 * Currently vsi->nb_qps means it.
1684 * Correct it if any change.
1686 max_txqs[0] = vsi->nb_qps;
1687 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1688 tc_bitmap, max_txqs);
1689 if (ret != ICE_SUCCESS)
1690 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1700 ice_send_driver_ver(struct ice_hw *hw)
1702 struct ice_driver_ver dv;
1704 /* we don't have driver version use 0 for dummy */
1708 dv.subbuild_ver = 0;
1709 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1711 return ice_aq_send_driver_ver(hw, &dv, NULL);
1715 ice_pf_setup(struct ice_pf *pf)
1717 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1718 struct ice_vsi *vsi;
1721 /* Clear all stats counters */
1722 pf->offset_loaded = FALSE;
1723 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1724 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1725 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1726 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1728 /* force guaranteed filter pool for PF */
1729 ice_alloc_fd_guar_item(hw, &unused,
1730 hw->func_caps.fd_fltr_guar);
1731 /* force shared filter pool for PF */
1732 ice_alloc_fd_shrd_item(hw, &unused,
1733 hw->func_caps.fd_fltr_best_effort);
1735 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1737 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1746 /* PCIe configuration space setting */
1747 #define PCI_CFG_SPACE_SIZE 256
1748 #define PCI_CFG_SPACE_EXP_SIZE 4096
1749 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
1750 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
1751 #define PCI_EXT_CAP_ID_DSN 0x03
1754 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1758 int pos = PCI_CFG_SPACE_SIZE;
1760 /* minimum 8 bytes per capability */
1761 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1763 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1764 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1769 * If we have no capabilities, this is indicated by cap ID,
1770 * cap version and next pointer all being 0.
1776 if (PCI_EXT_CAP_ID(header) == cap)
1779 pos = PCI_EXT_CAP_NEXT(header);
1781 if (pos < PCI_CFG_SPACE_SIZE)
1784 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1785 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1794 * Extract device serial number from PCIe Configuration Space and
1795 * determine the pkg file path according to the DSN.
1798 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1801 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1802 uint32_t dsn_low, dsn_high;
1803 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1805 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1808 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1809 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1810 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1811 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1813 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1817 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1818 ICE_MAX_PKG_FILENAME_SIZE);
1819 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1822 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1823 ICE_MAX_PKG_FILENAME_SIZE);
1824 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1828 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1829 if (!access(pkg_file, 0))
1831 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1835 static enum ice_pkg_type
1836 ice_load_pkg_type(struct ice_hw *hw)
1838 enum ice_pkg_type package_type;
1840 /* store the activated package type (OS default or Comms) */
1841 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1843 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1844 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1846 package_type = ICE_PKG_TYPE_COMMS;
1848 package_type = ICE_PKG_TYPE_UNKNOWN;
1850 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1851 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1852 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1853 hw->active_pkg_name);
1855 return package_type;
1858 static int ice_load_pkg(struct rte_eth_dev *dev)
1860 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1861 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1867 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1868 struct ice_adapter *ad =
1869 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1871 ice_pkg_file_search_path(pci_dev, pkg_file);
1873 file = fopen(pkg_file, "rb");
1875 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1879 err = stat(pkg_file, &fstat);
1881 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1886 buf_len = fstat.st_size;
1887 buf = rte_malloc(NULL, buf_len, 0);
1890 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1896 err = fread(buf, buf_len, 1, file);
1898 PMD_INIT_LOG(ERR, "failed to read package data\n");
1906 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1908 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1912 /* store the loaded pkg type info */
1913 ad->active_pkg_type = ice_load_pkg_type(hw);
1915 err = ice_init_hw_tbls(hw);
1917 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1918 goto fail_init_tbls;
1924 rte_free(hw->pkg_copy);
1931 ice_base_queue_get(struct ice_pf *pf)
1934 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1936 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1937 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1938 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1940 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1946 parse_bool(const char *key, const char *value, void *args)
1948 int *i = (int *)args;
1952 num = strtoul(value, &end, 10);
1954 if (num != 0 && num != 1) {
1955 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1956 "value must be 0 or 1",
1965 static int ice_parse_devargs(struct rte_eth_dev *dev)
1967 struct ice_adapter *ad =
1968 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1969 struct rte_devargs *devargs = dev->device->devargs;
1970 struct rte_kvargs *kvlist;
1973 if (devargs == NULL)
1976 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1977 if (kvlist == NULL) {
1978 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1982 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1983 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1984 sizeof(ad->devargs.proto_xtr));
1986 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1987 &handle_proto_xtr_arg, &ad->devargs);
1991 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1992 &parse_bool, &ad->devargs.safe_mode_support);
1996 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1997 &parse_bool, &ad->devargs.pipe_mode_support);
2001 ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
2002 &parse_bool, &ad->devargs.flow_mark_support);
2007 rte_kvargs_free(kvlist);
2011 /* Forward LLDP packets to default VSI by set switch rules */
2013 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
2015 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2016 struct ice_fltr_list_entry *s_list_itr = NULL;
2017 struct LIST_HEAD_TYPE list_head;
2020 INIT_LIST_HEAD(&list_head);
2022 s_list_itr = (struct ice_fltr_list_entry *)
2023 ice_malloc(hw, sizeof(*s_list_itr));
2026 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2027 s_list_itr->fltr_info.vsi_handle = vsi->idx;
2028 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2029 RTE_ETHER_TYPE_LLDP;
2030 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2031 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2032 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2033 LIST_ADD(&s_list_itr->list_entry, &list_head);
2035 ret = ice_add_eth_mac(hw, &list_head);
2037 ret = ice_remove_eth_mac(hw, &list_head);
2039 rte_free(s_list_itr);
2043 static enum ice_status
2044 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2045 uint16_t num, uint16_t desc_id,
2046 uint16_t *prof_buf, uint16_t *num_prof)
2048 struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2051 bool res_shared = 1;
2052 struct ice_aq_desc aq_desc;
2053 struct ice_sq_cd *cd = NULL;
2054 struct ice_aqc_get_allocd_res_desc *cmd =
2055 &aq_desc.params.get_res_desc;
2057 buf_len = sizeof(resp_buf->elem) * num;
2058 resp_buf = ice_malloc(hw, buf_len);
2062 ice_fill_dflt_direct_cmd_desc(&aq_desc,
2063 ice_aqc_opc_get_allocd_res_desc);
2065 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2066 ICE_AQC_RES_TYPE_M) | (res_shared ?
2067 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2068 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2070 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2072 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2076 ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2077 (*num_prof), ICE_NONDMA_TO_NONDMA);
2084 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2088 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2089 uint16_t first_desc = 1;
2090 uint16_t num_prof = 0;
2092 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2093 first_desc, prof_buf, &num_prof);
2095 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2099 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2100 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2102 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2110 ice_reset_fxp_resource(struct ice_hw *hw)
2114 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2116 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2120 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2122 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2130 ice_dev_init(struct rte_eth_dev *dev)
2132 struct rte_pci_device *pci_dev;
2133 struct rte_intr_handle *intr_handle;
2134 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2135 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2136 struct ice_adapter *ad =
2137 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2138 struct ice_vsi *vsi;
2141 dev->dev_ops = &ice_eth_dev_ops;
2142 dev->rx_pkt_burst = ice_recv_pkts;
2143 dev->tx_pkt_burst = ice_xmit_pkts;
2144 dev->tx_pkt_prepare = ice_prep_pkts;
2146 /* for secondary processes, we don't initialise any further as primary
2147 * has already done this work.
2149 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2150 ice_set_rx_function(dev);
2151 ice_set_tx_function(dev);
2155 ice_set_default_ptype_table(dev);
2156 pci_dev = RTE_DEV_TO_PCI(dev->device);
2157 intr_handle = &pci_dev->intr_handle;
2159 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2160 pf->adapter->eth_dev = dev;
2161 pf->dev_data = dev->data;
2162 hw->back = pf->adapter;
2163 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2164 hw->vendor_id = pci_dev->id.vendor_id;
2165 hw->device_id = pci_dev->id.device_id;
2166 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2167 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2168 hw->bus.device = pci_dev->addr.devid;
2169 hw->bus.func = pci_dev->addr.function;
2171 ret = ice_parse_devargs(dev);
2173 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2177 ice_init_controlq_parameter(hw);
2179 ret = ice_init_hw(hw);
2181 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2185 ret = ice_load_pkg(dev);
2187 if (ad->devargs.safe_mode_support == 0) {
2188 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2189 "Use safe-mode-support=1 to enter Safe Mode");
2193 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2194 "Entering Safe Mode");
2195 ad->is_safe_mode = 1;
2198 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2199 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2200 hw->api_maj_ver, hw->api_min_ver);
2202 ice_pf_sw_init(dev);
2203 ret = ice_init_mac_address(dev);
2205 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2209 /* Pass the information to the rte_eth_dev_close() that it should also
2210 * release the private port resources.
2212 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2214 ret = ice_res_pool_init(&pf->msix_pool, 1,
2215 hw->func_caps.common_cap.num_msix_vectors - 1);
2217 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2218 goto err_msix_pool_init;
2221 ret = ice_pf_setup(pf);
2223 PMD_INIT_LOG(ERR, "Failed to setup PF");
2227 ret = ice_send_driver_ver(hw);
2229 PMD_INIT_LOG(ERR, "Failed to send driver version");
2235 /* Disable double vlan by default */
2236 ice_vsi_config_double_vlan(vsi, FALSE);
2238 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
2239 if (ret != ICE_SUCCESS)
2240 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2241 ret = ice_init_dcb(hw, TRUE);
2242 if (ret != ICE_SUCCESS)
2243 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2244 /* Forward LLDP packets to default VSI */
2245 ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2246 if (ret != ICE_SUCCESS)
2247 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2248 /* register callback func to eal lib */
2249 rte_intr_callback_register(intr_handle,
2250 ice_interrupt_handler, dev);
2252 ice_pf_enable_irq0(hw);
2254 /* enable uio intr after callback register */
2255 rte_intr_enable(intr_handle);
2257 /* get base queue pairs index in the device */
2258 ice_base_queue_get(pf);
2260 if (!ad->is_safe_mode) {
2261 ret = ice_flow_init(ad);
2263 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2268 ret = ice_reset_fxp_resource(hw);
2270 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2277 ice_res_pool_destroy(&pf->msix_pool);
2279 rte_free(dev->data->mac_addrs);
2280 dev->data->mac_addrs = NULL;
2282 ice_sched_cleanup_all(hw);
2283 rte_free(hw->port_info);
2284 ice_shutdown_all_ctrlq(hw);
2285 rte_free(pf->proto_xtr);
2291 ice_release_vsi(struct ice_vsi *vsi)
2294 struct ice_vsi_ctx vsi_ctx;
2295 enum ice_status ret;
2300 hw = ICE_VSI_TO_HW(vsi);
2302 ice_remove_all_mac_vlan_filters(vsi);
2304 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2306 vsi_ctx.vsi_num = vsi->vsi_id;
2307 vsi_ctx.info = vsi->info;
2308 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2309 if (ret != ICE_SUCCESS) {
2310 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2320 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2322 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2323 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2324 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2325 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2326 uint16_t msix_intr, i;
2328 /* disable interrupt and also clear all the exist config */
2329 for (i = 0; i < vsi->nb_qps; i++) {
2330 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2331 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2335 if (rte_intr_allow_others(intr_handle))
2337 for (i = 0; i < vsi->nb_msix; i++) {
2338 msix_intr = vsi->msix_intr + i;
2339 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2340 GLINT_DYN_CTL_WB_ON_ITR_M);
2344 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2348 ice_dev_stop(struct rte_eth_dev *dev)
2350 struct rte_eth_dev_data *data = dev->data;
2351 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2352 struct ice_vsi *main_vsi = pf->main_vsi;
2353 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2354 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2357 /* avoid stopping again */
2358 if (pf->adapter_stopped)
2361 /* stop and clear all Rx queues */
2362 for (i = 0; i < data->nb_rx_queues; i++)
2363 ice_rx_queue_stop(dev, i);
2365 /* stop and clear all Tx queues */
2366 for (i = 0; i < data->nb_tx_queues; i++)
2367 ice_tx_queue_stop(dev, i);
2369 /* disable all queue interrupts */
2370 ice_vsi_disable_queues_intr(main_vsi);
2372 /* Clear all queues and release mbufs */
2373 ice_clear_queues(dev);
2375 if (pf->init_link_up)
2376 ice_dev_set_link_up(dev);
2378 ice_dev_set_link_down(dev);
2380 /* Clean datapath event and queue/vec mapping */
2381 rte_intr_efd_disable(intr_handle);
2382 if (intr_handle->intr_vec) {
2383 rte_free(intr_handle->intr_vec);
2384 intr_handle->intr_vec = NULL;
2387 pf->adapter_stopped = true;
2391 ice_dev_close(struct rte_eth_dev *dev)
2393 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2394 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2396 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2397 struct ice_adapter *ad =
2398 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2400 /* Since stop will make link down, then the link event will be
2401 * triggered, disable the irq firstly to avoid the port_infoe etc
2402 * resources deallocation causing the interrupt service thread
2405 ice_pf_disable_irq0(hw);
2409 if (!ad->is_safe_mode)
2410 ice_flow_uninit(ad);
2412 /* release all queue resource */
2413 ice_free_queues(dev);
2415 ice_res_pool_destroy(&pf->msix_pool);
2416 ice_release_vsi(pf->main_vsi);
2417 ice_sched_cleanup_all(hw);
2418 ice_free_hw_tbls(hw);
2419 rte_free(hw->port_info);
2420 hw->port_info = NULL;
2421 ice_shutdown_all_ctrlq(hw);
2422 rte_free(pf->proto_xtr);
2423 pf->proto_xtr = NULL;
2425 dev->dev_ops = NULL;
2426 dev->rx_pkt_burst = NULL;
2427 dev->tx_pkt_burst = NULL;
2429 rte_free(dev->data->mac_addrs);
2430 dev->data->mac_addrs = NULL;
2432 /* disable uio intr before callback unregister */
2433 rte_intr_disable(intr_handle);
2435 /* unregister callback func from eal lib */
2436 rte_intr_callback_unregister(intr_handle,
2437 ice_interrupt_handler, dev);
2441 ice_dev_uninit(struct rte_eth_dev *dev)
2449 ice_dev_configure(struct rte_eth_dev *dev)
2451 struct ice_adapter *ad =
2452 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2454 /* Initialize to TRUE. If any of Rx queues doesn't meet the
2455 * bulk allocation or vector Rx preconditions we will reset it.
2457 ad->rx_bulk_alloc_allowed = true;
2458 ad->tx_simple_allowed = true;
2460 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2461 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2466 static int ice_init_rss(struct ice_pf *pf)
2468 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2469 struct ice_vsi *vsi = pf->main_vsi;
2470 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2471 struct rte_eth_rss_conf *rss_conf;
2472 struct ice_aqc_get_set_rss_keys key;
2475 bool is_safe_mode = pf->adapter->is_safe_mode;
2478 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2479 nb_q = dev->data->nb_rx_queues;
2480 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2481 vsi->rss_lut_size = pf->hash_lut_size;
2484 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2489 vsi->rss_key = rte_zmalloc(NULL,
2490 vsi->rss_key_size, 0);
2492 vsi->rss_lut = rte_zmalloc(NULL,
2493 vsi->rss_lut_size, 0);
2495 /* configure RSS key */
2496 if (!rss_conf->rss_key) {
2497 /* Calculate the default hash key */
2498 for (i = 0; i <= vsi->rss_key_size; i++)
2499 vsi->rss_key[i] = (uint8_t)rte_rand();
2501 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2502 RTE_MIN(rss_conf->rss_key_len,
2503 vsi->rss_key_size));
2505 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2506 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2510 /* init RSS LUT table */
2511 for (i = 0; i < vsi->rss_lut_size; i++)
2512 vsi->rss_lut[i] = i % nb_q;
2514 ret = ice_aq_set_rss_lut(hw, vsi->idx,
2515 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2516 vsi->rss_lut, vsi->rss_lut_size);
2520 /* Enable registers for symmetric_toeplitz function. */
2521 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2522 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2523 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2524 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2526 /* configure RSS for IPv4 with input set IPv4 src/dst */
2527 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2528 ICE_FLOW_SEG_HDR_IPV4, 0);
2530 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2532 /* configure RSS for IPv6 with input set IPv6 src/dst */
2533 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2534 ICE_FLOW_SEG_HDR_IPV6, 0);
2536 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2538 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2539 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2540 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2542 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2544 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2545 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2546 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2548 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2550 /* configure RSS for sctp6 with input set IPv6 src/dst */
2551 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2552 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2554 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2557 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2558 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2559 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2561 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2563 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2564 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2565 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2567 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2569 /* configure RSS for sctp4 with input set IP src/dst */
2570 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2571 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2573 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2576 /* configure RSS for gtpu with input set TEID */
2577 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2578 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2580 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2584 * configure RSS for pppoe/pppod with input set
2585 * Source MAC and Session ID
2587 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2588 ICE_FLOW_SEG_HDR_PPPOE, 0);
2590 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2597 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2598 int base_queue, int nb_queue)
2600 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2601 uint32_t val, val_tx;
2604 for (i = 0; i < nb_queue; i++) {
2606 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2607 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2608 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2609 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2611 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2612 base_queue + i, msix_vect);
2613 /* set ITR0 value */
2614 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2615 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2616 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2621 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2623 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2624 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2625 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2626 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2627 uint16_t msix_vect = vsi->msix_intr;
2628 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2629 uint16_t queue_idx = 0;
2633 /* clear Rx/Tx queue interrupt */
2634 for (i = 0; i < vsi->nb_used_qps; i++) {
2635 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2636 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2639 /* PF bind interrupt */
2640 if (rte_intr_dp_is_en(intr_handle)) {
2645 for (i = 0; i < vsi->nb_used_qps; i++) {
2647 if (!rte_intr_allow_others(intr_handle))
2648 msix_vect = ICE_MISC_VEC_ID;
2650 /* uio mapping all queue to one msix_vect */
2651 __vsi_queues_bind_intr(vsi, msix_vect,
2652 vsi->base_queue + i,
2653 vsi->nb_used_qps - i);
2655 for (; !!record && i < vsi->nb_used_qps; i++)
2656 intr_handle->intr_vec[queue_idx + i] =
2661 /* vfio 1:1 queue/msix_vect mapping */
2662 __vsi_queues_bind_intr(vsi, msix_vect,
2663 vsi->base_queue + i, 1);
2666 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2674 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2676 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2677 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2678 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2679 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2680 uint16_t msix_intr, i;
2682 if (rte_intr_allow_others(intr_handle))
2683 for (i = 0; i < vsi->nb_used_qps; i++) {
2684 msix_intr = vsi->msix_intr + i;
2685 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2686 GLINT_DYN_CTL_INTENA_M |
2687 GLINT_DYN_CTL_CLEARPBA_M |
2688 GLINT_DYN_CTL_ITR_INDX_M |
2689 GLINT_DYN_CTL_WB_ON_ITR_M);
2692 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2693 GLINT_DYN_CTL_INTENA_M |
2694 GLINT_DYN_CTL_CLEARPBA_M |
2695 GLINT_DYN_CTL_ITR_INDX_M |
2696 GLINT_DYN_CTL_WB_ON_ITR_M);
2700 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2702 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2703 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2704 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2705 struct ice_vsi *vsi = pf->main_vsi;
2706 uint32_t intr_vector = 0;
2708 rte_intr_disable(intr_handle);
2710 /* check and configure queue intr-vector mapping */
2711 if ((rte_intr_cap_multiple(intr_handle) ||
2712 !RTE_ETH_DEV_SRIOV(dev).active) &&
2713 dev->data->dev_conf.intr_conf.rxq != 0) {
2714 intr_vector = dev->data->nb_rx_queues;
2715 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2716 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2717 ICE_MAX_INTR_QUEUE_NUM);
2720 if (rte_intr_efd_enable(intr_handle, intr_vector))
2724 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2725 intr_handle->intr_vec =
2726 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2728 if (!intr_handle->intr_vec) {
2730 "Failed to allocate %d rx_queues intr_vec",
2731 dev->data->nb_rx_queues);
2736 /* Map queues with MSIX interrupt */
2737 vsi->nb_used_qps = dev->data->nb_rx_queues;
2738 ice_vsi_queues_bind_intr(vsi);
2740 /* Enable interrupts for all the queues */
2741 ice_vsi_enable_queues_intr(vsi);
2743 rte_intr_enable(intr_handle);
2749 ice_get_init_link_status(struct rte_eth_dev *dev)
2751 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2752 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2753 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2754 struct ice_link_status link_status;
2757 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
2758 &link_status, NULL);
2759 if (ret != ICE_SUCCESS) {
2760 PMD_DRV_LOG(ERR, "Failed to get link info");
2761 pf->init_link_up = false;
2765 if (link_status.link_info & ICE_AQ_LINK_UP)
2766 pf->init_link_up = true;
2770 ice_dev_start(struct rte_eth_dev *dev)
2772 struct rte_eth_dev_data *data = dev->data;
2773 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2775 struct ice_vsi *vsi = pf->main_vsi;
2776 uint16_t nb_rxq = 0;
2778 uint16_t max_frame_size;
2781 /* program Tx queues' context in hardware */
2782 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2783 ret = ice_tx_queue_start(dev, nb_txq);
2785 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2790 /* program Rx queues' context in hardware*/
2791 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2792 ret = ice_rx_queue_start(dev, nb_rxq);
2794 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2799 ret = ice_init_rss(pf);
2801 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2805 ice_set_rx_function(dev);
2806 ice_set_tx_function(dev);
2808 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2809 ETH_VLAN_EXTEND_MASK;
2810 ret = ice_vlan_offload_set(dev, mask);
2812 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2816 /* enable Rx interrput and mapping Rx queue to interrupt vector */
2817 if (ice_rxq_intr_setup(dev))
2820 /* Enable receiving broadcast packets and transmitting packets */
2821 ret = ice_set_vsi_promisc(hw, vsi->idx,
2822 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2823 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2825 if (ret != ICE_SUCCESS)
2826 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2828 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2829 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2830 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2831 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2832 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2833 ICE_AQ_LINK_EVENT_AN_COMPLETED |
2834 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2836 if (ret != ICE_SUCCESS)
2837 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2839 ice_get_init_link_status(dev);
2841 ice_dev_set_link_up(dev);
2843 /* Call get_link_info aq commond to enable/disable LSE */
2844 ice_link_update(dev, 0);
2846 pf->adapter_stopped = false;
2848 /* Set the max frame size to default value*/
2849 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2850 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2853 /* Set the max frame size to HW*/
2854 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2858 /* stop the started queues if failed to start all queues */
2860 for (i = 0; i < nb_rxq; i++)
2861 ice_rx_queue_stop(dev, i);
2863 for (i = 0; i < nb_txq; i++)
2864 ice_tx_queue_stop(dev, i);
2870 ice_dev_reset(struct rte_eth_dev *dev)
2874 if (dev->data->sriov.active)
2877 ret = ice_dev_uninit(dev);
2879 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2883 ret = ice_dev_init(dev);
2885 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2893 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2895 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2896 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897 struct ice_vsi *vsi = pf->main_vsi;
2898 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2899 bool is_safe_mode = pf->adapter->is_safe_mode;
2903 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2904 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2905 dev_info->max_rx_queues = vsi->nb_qps;
2906 dev_info->max_tx_queues = vsi->nb_qps;
2907 dev_info->max_mac_addrs = vsi->max_macaddrs;
2908 dev_info->max_vfs = pci_dev->max_vfs;
2909 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2910 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2912 dev_info->rx_offload_capa =
2913 DEV_RX_OFFLOAD_VLAN_STRIP |
2914 DEV_RX_OFFLOAD_JUMBO_FRAME |
2915 DEV_RX_OFFLOAD_KEEP_CRC |
2916 DEV_RX_OFFLOAD_SCATTER |
2917 DEV_RX_OFFLOAD_VLAN_FILTER;
2918 dev_info->tx_offload_capa =
2919 DEV_TX_OFFLOAD_VLAN_INSERT |
2920 DEV_TX_OFFLOAD_TCP_TSO |
2921 DEV_TX_OFFLOAD_MULTI_SEGS |
2922 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2923 dev_info->flow_type_rss_offloads = 0;
2925 if (!is_safe_mode) {
2926 dev_info->rx_offload_capa |=
2927 DEV_RX_OFFLOAD_IPV4_CKSUM |
2928 DEV_RX_OFFLOAD_UDP_CKSUM |
2929 DEV_RX_OFFLOAD_TCP_CKSUM |
2930 DEV_RX_OFFLOAD_QINQ_STRIP |
2931 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2932 DEV_RX_OFFLOAD_VLAN_EXTEND |
2933 DEV_RX_OFFLOAD_RSS_HASH;
2934 dev_info->tx_offload_capa |=
2935 DEV_TX_OFFLOAD_QINQ_INSERT |
2936 DEV_TX_OFFLOAD_IPV4_CKSUM |
2937 DEV_TX_OFFLOAD_UDP_CKSUM |
2938 DEV_TX_OFFLOAD_TCP_CKSUM |
2939 DEV_TX_OFFLOAD_SCTP_CKSUM |
2940 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2941 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2942 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2945 dev_info->rx_queue_offload_capa = 0;
2946 dev_info->tx_queue_offload_capa = 0;
2948 dev_info->reta_size = pf->hash_lut_size;
2949 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2951 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2953 .pthresh = ICE_DEFAULT_RX_PTHRESH,
2954 .hthresh = ICE_DEFAULT_RX_HTHRESH,
2955 .wthresh = ICE_DEFAULT_RX_WTHRESH,
2957 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2962 dev_info->default_txconf = (struct rte_eth_txconf) {
2964 .pthresh = ICE_DEFAULT_TX_PTHRESH,
2965 .hthresh = ICE_DEFAULT_TX_HTHRESH,
2966 .wthresh = ICE_DEFAULT_TX_WTHRESH,
2968 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2969 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2973 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2974 .nb_max = ICE_MAX_RING_DESC,
2975 .nb_min = ICE_MIN_RING_DESC,
2976 .nb_align = ICE_ALIGN_RING_DESC,
2979 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2980 .nb_max = ICE_MAX_RING_DESC,
2981 .nb_min = ICE_MIN_RING_DESC,
2982 .nb_align = ICE_ALIGN_RING_DESC,
2985 dev_info->speed_capa = ETH_LINK_SPEED_10M |
2986 ETH_LINK_SPEED_100M |
2988 ETH_LINK_SPEED_2_5G |
2990 ETH_LINK_SPEED_10G |
2991 ETH_LINK_SPEED_20G |
2994 phy_type_low = hw->port_info->phy.phy_type_low;
2995 phy_type_high = hw->port_info->phy.phy_type_high;
2997 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2998 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3000 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3001 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3002 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3004 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3005 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3007 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3008 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3009 dev_info->default_rxportconf.nb_queues = 1;
3010 dev_info->default_txportconf.nb_queues = 1;
3011 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3012 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3018 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3019 struct rte_eth_link *link)
3021 struct rte_eth_link *dst = link;
3022 struct rte_eth_link *src = &dev->data->dev_link;
3024 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3025 *(uint64_t *)src) == 0)
3032 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3033 struct rte_eth_link *link)
3035 struct rte_eth_link *dst = &dev->data->dev_link;
3036 struct rte_eth_link *src = link;
3038 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3039 *(uint64_t *)src) == 0)
3046 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3048 #define CHECK_INTERVAL 100 /* 100ms */
3049 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3050 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3051 struct ice_link_status link_status;
3052 struct rte_eth_link link, old;
3054 unsigned int rep_cnt = MAX_REPEAT_TIME;
3055 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3057 memset(&link, 0, sizeof(link));
3058 memset(&old, 0, sizeof(old));
3059 memset(&link_status, 0, sizeof(link_status));
3060 ice_atomic_read_link_status(dev, &old);
3063 /* Get link status information from hardware */
3064 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3065 &link_status, NULL);
3066 if (status != ICE_SUCCESS) {
3067 link.link_speed = ETH_SPEED_NUM_100M;
3068 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3069 PMD_DRV_LOG(ERR, "Failed to get link info");
3073 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3074 if (!wait_to_complete || link.link_status)
3077 rte_delay_ms(CHECK_INTERVAL);
3078 } while (--rep_cnt);
3080 if (!link.link_status)
3083 /* Full-duplex operation at all supported speeds */
3084 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3086 /* Parse the link status */
3087 switch (link_status.link_speed) {
3088 case ICE_AQ_LINK_SPEED_10MB:
3089 link.link_speed = ETH_SPEED_NUM_10M;
3091 case ICE_AQ_LINK_SPEED_100MB:
3092 link.link_speed = ETH_SPEED_NUM_100M;
3094 case ICE_AQ_LINK_SPEED_1000MB:
3095 link.link_speed = ETH_SPEED_NUM_1G;
3097 case ICE_AQ_LINK_SPEED_2500MB:
3098 link.link_speed = ETH_SPEED_NUM_2_5G;
3100 case ICE_AQ_LINK_SPEED_5GB:
3101 link.link_speed = ETH_SPEED_NUM_5G;
3103 case ICE_AQ_LINK_SPEED_10GB:
3104 link.link_speed = ETH_SPEED_NUM_10G;
3106 case ICE_AQ_LINK_SPEED_20GB:
3107 link.link_speed = ETH_SPEED_NUM_20G;
3109 case ICE_AQ_LINK_SPEED_25GB:
3110 link.link_speed = ETH_SPEED_NUM_25G;
3112 case ICE_AQ_LINK_SPEED_40GB:
3113 link.link_speed = ETH_SPEED_NUM_40G;
3115 case ICE_AQ_LINK_SPEED_50GB:
3116 link.link_speed = ETH_SPEED_NUM_50G;
3118 case ICE_AQ_LINK_SPEED_100GB:
3119 link.link_speed = ETH_SPEED_NUM_100G;
3121 case ICE_AQ_LINK_SPEED_UNKNOWN:
3123 PMD_DRV_LOG(ERR, "Unknown link speed");
3124 link.link_speed = ETH_SPEED_NUM_NONE;
3128 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3129 ETH_LINK_SPEED_FIXED);
3132 ice_atomic_write_link_status(dev, &link);
3133 if (link.link_status == old.link_status)
3139 /* Force the physical link state by getting the current PHY capabilities from
3140 * hardware and setting the PHY config based on the determined capabilities. If
3141 * link changes, link event will be triggered because both the Enable Automatic
3142 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3144 static enum ice_status
3145 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3147 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3148 struct ice_aqc_get_phy_caps_data *pcaps;
3149 struct ice_port_info *pi;
3150 enum ice_status status;
3152 if (!hw || !hw->port_info)
3153 return ICE_ERR_PARAM;
3157 pcaps = (struct ice_aqc_get_phy_caps_data *)
3158 ice_malloc(hw, sizeof(*pcaps));
3160 return ICE_ERR_NO_MEMORY;
3162 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3167 /* No change in link */
3168 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3169 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3172 cfg.phy_type_low = pcaps->phy_type_low;
3173 cfg.phy_type_high = pcaps->phy_type_high;
3174 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3175 cfg.low_power_ctrl = pcaps->low_power_ctrl;
3176 cfg.eee_cap = pcaps->eee_cap;
3177 cfg.eeer_value = pcaps->eeer_value;
3178 cfg.link_fec_opt = pcaps->link_fec_options;
3180 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3182 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3184 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3187 ice_free(hw, pcaps);
3192 ice_dev_set_link_up(struct rte_eth_dev *dev)
3194 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3196 return ice_force_phys_link_state(hw, true);
3200 ice_dev_set_link_down(struct rte_eth_dev *dev)
3202 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3204 return ice_force_phys_link_state(hw, false);
3208 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3210 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3211 struct rte_eth_dev_data *dev_data = pf->dev_data;
3212 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3214 /* check if mtu is within the allowed range */
3215 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3218 /* mtu setting is forbidden if port is start */
3219 if (dev_data->dev_started) {
3221 "port %d must be stopped before configuration",
3226 if (frame_size > RTE_ETHER_MAX_LEN)
3227 dev_data->dev_conf.rxmode.offloads |=
3228 DEV_RX_OFFLOAD_JUMBO_FRAME;
3230 dev_data->dev_conf.rxmode.offloads &=
3231 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3233 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3238 static int ice_macaddr_set(struct rte_eth_dev *dev,
3239 struct rte_ether_addr *mac_addr)
3241 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3242 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3243 struct ice_vsi *vsi = pf->main_vsi;
3244 struct ice_mac_filter *f;
3248 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3249 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3253 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3254 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3259 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3263 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3264 if (ret != ICE_SUCCESS) {
3265 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3268 ret = ice_add_mac_filter(vsi, mac_addr);
3269 if (ret != ICE_SUCCESS) {
3270 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3273 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
3275 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3276 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3277 if (ret != ICE_SUCCESS)
3278 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3283 /* Add a MAC address, and update filters */
3285 ice_macaddr_add(struct rte_eth_dev *dev,
3286 struct rte_ether_addr *mac_addr,
3287 __rte_unused uint32_t index,
3288 __rte_unused uint32_t pool)
3290 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3291 struct ice_vsi *vsi = pf->main_vsi;
3294 ret = ice_add_mac_filter(vsi, mac_addr);
3295 if (ret != ICE_SUCCESS) {
3296 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3303 /* Remove a MAC address, and update filters */
3305 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3307 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3308 struct ice_vsi *vsi = pf->main_vsi;
3309 struct rte_eth_dev_data *data = dev->data;
3310 struct rte_ether_addr *macaddr;
3313 macaddr = &data->mac_addrs[index];
3314 ret = ice_remove_mac_filter(vsi, macaddr);
3316 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3322 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3324 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3325 struct ice_vsi *vsi = pf->main_vsi;
3328 PMD_INIT_FUNC_TRACE();
3331 ret = ice_add_vlan_filter(vsi, vlan_id);
3333 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3337 ret = ice_remove_vlan_filter(vsi, vlan_id);
3339 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3347 /* Configure vlan filter on or off */
3349 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3351 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3352 struct ice_vsi_ctx ctxt;
3353 uint8_t sec_flags, sw_flags2;
3356 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3357 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3358 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3361 vsi->info.sec_flags |= sec_flags;
3362 vsi->info.sw_flags2 |= sw_flags2;
3364 vsi->info.sec_flags &= ~sec_flags;
3365 vsi->info.sw_flags2 &= ~sw_flags2;
3367 vsi->info.sw_id = hw->port_info->sw_id;
3368 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3369 ctxt.info.valid_sections =
3370 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3371 ICE_AQ_VSI_PROP_SECURITY_VALID);
3372 ctxt.vsi_num = vsi->vsi_id;
3374 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3376 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3377 on ? "enable" : "disable");
3380 vsi->info.valid_sections |=
3381 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3382 ICE_AQ_VSI_PROP_SECURITY_VALID);
3385 /* consist with other drivers, allow untagged packet when vlan filter on */
3387 ret = ice_add_vlan_filter(vsi, 0);
3389 ret = ice_remove_vlan_filter(vsi, 0);
3395 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3397 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3398 struct ice_vsi_ctx ctxt;
3402 /* Check if it has been already on or off */
3403 if (vsi->info.valid_sections &
3404 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3406 if ((vsi->info.vlan_flags &
3407 ICE_AQ_VSI_VLAN_EMOD_M) ==
3408 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3409 return 0; /* already on */
3411 if ((vsi->info.vlan_flags &
3412 ICE_AQ_VSI_VLAN_EMOD_M) ==
3413 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3414 return 0; /* already off */
3419 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3421 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3422 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3423 vsi->info.vlan_flags |= vlan_flags;
3424 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3425 ctxt.info.valid_sections =
3426 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3427 ctxt.vsi_num = vsi->vsi_id;
3428 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3430 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3431 on ? "enable" : "disable");
3435 vsi->info.valid_sections |=
3436 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3442 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3444 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3445 struct ice_vsi *vsi = pf->main_vsi;
3446 struct rte_eth_rxmode *rxmode;
3448 rxmode = &dev->data->dev_conf.rxmode;
3449 if (mask & ETH_VLAN_FILTER_MASK) {
3450 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3451 ice_vsi_config_vlan_filter(vsi, TRUE);
3453 ice_vsi_config_vlan_filter(vsi, FALSE);
3456 if (mask & ETH_VLAN_STRIP_MASK) {
3457 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3458 ice_vsi_config_vlan_stripping(vsi, TRUE);
3460 ice_vsi_config_vlan_stripping(vsi, FALSE);
3463 if (mask & ETH_VLAN_EXTEND_MASK) {
3464 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3465 ice_vsi_config_double_vlan(vsi, TRUE);
3467 ice_vsi_config_double_vlan(vsi, FALSE);
3474 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3476 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3477 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3483 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3484 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3485 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3487 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3491 uint64_t *lut_dw = (uint64_t *)lut;
3492 uint16_t i, lut_size_dw = lut_size / 4;
3494 for (i = 0; i < lut_size_dw; i++)
3495 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3502 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3511 pf = ICE_VSI_TO_PF(vsi);
3512 hw = ICE_VSI_TO_HW(vsi);
3514 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3515 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3516 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3518 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3522 uint64_t *lut_dw = (uint64_t *)lut;
3523 uint16_t i, lut_size_dw = lut_size / 4;
3525 for (i = 0; i < lut_size_dw; i++)
3526 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3535 ice_rss_reta_update(struct rte_eth_dev *dev,
3536 struct rte_eth_rss_reta_entry64 *reta_conf,
3539 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3540 uint16_t i, lut_size = pf->hash_lut_size;
3541 uint16_t idx, shift;
3545 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3546 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3547 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3549 "The size of hash lookup table configured (%d)"
3550 "doesn't match the number hardware can "
3551 "supported (128, 512, 2048)",
3556 /* It MUST use the current LUT size to get the RSS lookup table,
3557 * otherwise if will fail with -100 error code.
3559 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
3561 PMD_DRV_LOG(ERR, "No memory can be allocated");
3564 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3568 for (i = 0; i < reta_size; i++) {
3569 idx = i / RTE_RETA_GROUP_SIZE;
3570 shift = i % RTE_RETA_GROUP_SIZE;
3571 if (reta_conf[idx].mask & (1ULL << shift))
3572 lut[i] = reta_conf[idx].reta[shift];
3574 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3575 if (ret == 0 && lut_size != reta_size) {
3577 "The size of hash lookup table is changed from (%d) to (%d)",
3578 lut_size, reta_size);
3579 pf->hash_lut_size = reta_size;
3589 ice_rss_reta_query(struct rte_eth_dev *dev,
3590 struct rte_eth_rss_reta_entry64 *reta_conf,
3593 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3594 uint16_t i, lut_size = pf->hash_lut_size;
3595 uint16_t idx, shift;
3599 if (reta_size != lut_size) {
3601 "The size of hash lookup table configured (%d)"
3602 "doesn't match the number hardware can "
3604 reta_size, lut_size);
3608 lut = rte_zmalloc(NULL, reta_size, 0);
3610 PMD_DRV_LOG(ERR, "No memory can be allocated");
3614 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3618 for (i = 0; i < reta_size; i++) {
3619 idx = i / RTE_RETA_GROUP_SIZE;
3620 shift = i % RTE_RETA_GROUP_SIZE;
3621 if (reta_conf[idx].mask & (1ULL << shift))
3622 reta_conf[idx].reta[shift] = lut[i];
3632 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3634 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3637 if (!key || key_len == 0) {
3638 PMD_DRV_LOG(DEBUG, "No key to be configured");
3640 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3642 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3646 struct ice_aqc_get_set_rss_keys *key_dw =
3647 (struct ice_aqc_get_set_rss_keys *)key;
3649 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3651 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3659 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3661 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3664 if (!key || !key_len)
3667 ret = ice_aq_get_rss_key
3669 (struct ice_aqc_get_set_rss_keys *)key);
3671 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3674 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3680 ice_rss_hash_update(struct rte_eth_dev *dev,
3681 struct rte_eth_rss_conf *rss_conf)
3683 enum ice_status status = ICE_SUCCESS;
3684 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3685 struct ice_vsi *vsi = pf->main_vsi;
3688 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3692 /* TODO: hash enable config, ice_add_rss_cfg */
3697 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3698 struct rte_eth_rss_conf *rss_conf)
3700 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3701 struct ice_vsi *vsi = pf->main_vsi;
3703 ice_get_rss_key(vsi, rss_conf->rss_key,
3704 &rss_conf->rss_key_len);
3706 /* TODO: default set to 0 as hf config is not supported now */
3707 rss_conf->rss_hf = 0;
3712 ice_promisc_enable(struct rte_eth_dev *dev)
3714 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3715 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716 struct ice_vsi *vsi = pf->main_vsi;
3717 enum ice_status status;
3721 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3722 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3724 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3726 case ICE_ERR_ALREADY_EXISTS:
3727 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3731 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3739 ice_promisc_disable(struct rte_eth_dev *dev)
3741 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3742 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3743 struct ice_vsi *vsi = pf->main_vsi;
3744 enum ice_status status;
3748 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3749 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3751 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3752 if (status != ICE_SUCCESS) {
3753 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3761 ice_allmulti_enable(struct rte_eth_dev *dev)
3763 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3764 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3765 struct ice_vsi *vsi = pf->main_vsi;
3766 enum ice_status status;
3770 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3772 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3775 case ICE_ERR_ALREADY_EXISTS:
3776 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3780 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3788 ice_allmulti_disable(struct rte_eth_dev *dev)
3790 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3791 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3792 struct ice_vsi *vsi = pf->main_vsi;
3793 enum ice_status status;
3797 if (dev->data->promiscuous == 1)
3798 return 0; /* must remain in all_multicast mode */
3800 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3802 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3803 if (status != ICE_SUCCESS) {
3804 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3811 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3814 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3815 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3816 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3820 msix_intr = intr_handle->intr_vec[queue_id];
3822 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3823 GLINT_DYN_CTL_ITR_INDX_M;
3824 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3826 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3827 rte_intr_ack(&pci_dev->intr_handle);
3832 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3835 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3836 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3837 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3840 msix_intr = intr_handle->intr_vec[queue_id];
3842 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3848 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3850 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3856 full_ver = hw->nvm.oem_ver;
3857 ver = (u8)(full_ver >> 24);
3858 build = (u16)((full_ver >> 8) & 0xffff);
3859 patch = (u8)(full_ver & 0xff);
3861 ret = snprintf(fw_version, fw_size,
3862 "%d.%d%d 0x%08x %d.%d.%d",
3863 ((hw->nvm.ver >> 12) & 0xf),
3864 ((hw->nvm.ver >> 4) & 0xff),
3865 (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3868 /* add the size of '\0' */
3870 if (fw_size < (u32)ret)
3877 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3880 struct ice_vsi_ctx ctxt;
3881 uint8_t vlan_flags = 0;
3884 if (!vsi || !info) {
3885 PMD_DRV_LOG(ERR, "invalid parameters");
3890 vsi->info.pvid = info->config.pvid;
3892 * If insert pvid is enabled, only tagged pkts are
3893 * allowed to be sent out.
3895 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3896 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3899 if (info->config.reject.tagged == 0)
3900 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3902 if (info->config.reject.untagged == 0)
3903 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3905 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3906 ICE_AQ_VSI_VLAN_MODE_M);
3907 vsi->info.vlan_flags |= vlan_flags;
3908 memset(&ctxt, 0, sizeof(ctxt));
3909 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3910 ctxt.info.valid_sections =
3911 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3912 ctxt.vsi_num = vsi->vsi_id;
3914 hw = ICE_VSI_TO_HW(vsi);
3915 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3916 if (ret != ICE_SUCCESS) {
3918 "update VSI for VLAN insert failed, err %d",
3923 vsi->info.valid_sections |=
3924 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3930 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3932 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3933 struct ice_vsi *vsi = pf->main_vsi;
3934 struct rte_eth_dev_data *data = pf->dev_data;
3935 struct ice_vsi_vlan_pvid_info info;
3938 memset(&info, 0, sizeof(info));
3941 info.config.pvid = pvid;
3943 info.config.reject.tagged =
3944 data->dev_conf.txmode.hw_vlan_reject_tagged;
3945 info.config.reject.untagged =
3946 data->dev_conf.txmode.hw_vlan_reject_untagged;
3949 ret = ice_vsi_vlan_pvid_set(vsi, &info);
3951 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3959 ice_get_eeprom_length(struct rte_eth_dev *dev)
3961 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3963 /* Convert word count to byte count */
3964 return hw->nvm.sr_words << 1;
3968 ice_get_eeprom(struct rte_eth_dev *dev,
3969 struct rte_dev_eeprom_info *eeprom)
3971 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3972 uint16_t *data = eeprom->data;
3973 uint16_t first_word, last_word, nwords;
3974 enum ice_status status = ICE_SUCCESS;
3976 first_word = eeprom->offset >> 1;
3977 last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3978 nwords = last_word - first_word + 1;
3980 if (first_word >= hw->nvm.sr_words ||
3981 last_word >= hw->nvm.sr_words) {
3982 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3986 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3988 status = ice_read_sr_buf(hw, first_word, &nwords, data);
3990 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3991 eeprom->length = sizeof(uint16_t) * nwords;
3999 ice_stat_update_32(struct ice_hw *hw,
4007 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4011 if (new_data >= *offset)
4012 *stat = (uint64_t)(new_data - *offset);
4014 *stat = (uint64_t)((new_data +
4015 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4020 ice_stat_update_40(struct ice_hw *hw,
4029 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4030 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4036 if (new_data >= *offset)
4037 *stat = new_data - *offset;
4039 *stat = (uint64_t)((new_data +
4040 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4043 *stat &= ICE_40_BIT_MASK;
4046 /* Get all the statistics of a VSI */
4048 ice_update_vsi_stats(struct ice_vsi *vsi)
4050 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4051 struct ice_eth_stats *nes = &vsi->eth_stats;
4052 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4053 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4055 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4056 vsi->offset_loaded, &oes->rx_bytes,
4058 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4059 vsi->offset_loaded, &oes->rx_unicast,
4061 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4062 vsi->offset_loaded, &oes->rx_multicast,
4063 &nes->rx_multicast);
4064 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4065 vsi->offset_loaded, &oes->rx_broadcast,
4066 &nes->rx_broadcast);
4067 /* exclude CRC bytes */
4068 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4069 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4071 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4072 &oes->rx_discards, &nes->rx_discards);
4073 /* GLV_REPC not supported */
4074 /* GLV_RMPC not supported */
4075 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4076 &oes->rx_unknown_protocol,
4077 &nes->rx_unknown_protocol);
4078 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4079 vsi->offset_loaded, &oes->tx_bytes,
4081 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4082 vsi->offset_loaded, &oes->tx_unicast,
4084 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4085 vsi->offset_loaded, &oes->tx_multicast,
4086 &nes->tx_multicast);
4087 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4088 vsi->offset_loaded, &oes->tx_broadcast,
4089 &nes->tx_broadcast);
4090 /* GLV_TDPC not supported */
4091 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4092 &oes->tx_errors, &nes->tx_errors);
4093 vsi->offset_loaded = true;
4095 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4097 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4098 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4099 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4100 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4101 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4102 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4103 nes->rx_unknown_protocol);
4104 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4105 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4106 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4107 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4108 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4109 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4110 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4115 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4117 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4118 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4120 /* Get statistics of struct ice_eth_stats */
4121 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4122 GLPRT_GORCL(hw->port_info->lport),
4123 pf->offset_loaded, &os->eth.rx_bytes,
4125 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4126 GLPRT_UPRCL(hw->port_info->lport),
4127 pf->offset_loaded, &os->eth.rx_unicast,
4128 &ns->eth.rx_unicast);
4129 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4130 GLPRT_MPRCL(hw->port_info->lport),
4131 pf->offset_loaded, &os->eth.rx_multicast,
4132 &ns->eth.rx_multicast);
4133 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4134 GLPRT_BPRCL(hw->port_info->lport),
4135 pf->offset_loaded, &os->eth.rx_broadcast,
4136 &ns->eth.rx_broadcast);
4137 ice_stat_update_32(hw, PRTRPB_RDPC,
4138 pf->offset_loaded, &os->eth.rx_discards,
4139 &ns->eth.rx_discards);
4141 /* Workaround: CRC size should not be included in byte statistics,
4142 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4145 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4146 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4148 /* GLPRT_REPC not supported */
4149 /* GLPRT_RMPC not supported */
4150 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4152 &os->eth.rx_unknown_protocol,
4153 &ns->eth.rx_unknown_protocol);
4154 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4155 GLPRT_GOTCL(hw->port_info->lport),
4156 pf->offset_loaded, &os->eth.tx_bytes,
4158 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4159 GLPRT_UPTCL(hw->port_info->lport),
4160 pf->offset_loaded, &os->eth.tx_unicast,
4161 &ns->eth.tx_unicast);
4162 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4163 GLPRT_MPTCL(hw->port_info->lport),
4164 pf->offset_loaded, &os->eth.tx_multicast,
4165 &ns->eth.tx_multicast);
4166 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4167 GLPRT_BPTCL(hw->port_info->lport),
4168 pf->offset_loaded, &os->eth.tx_broadcast,
4169 &ns->eth.tx_broadcast);
4170 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4171 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4173 /* GLPRT_TEPC not supported */
4175 /* additional port specific stats */
4176 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4177 pf->offset_loaded, &os->tx_dropped_link_down,
4178 &ns->tx_dropped_link_down);
4179 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4180 pf->offset_loaded, &os->crc_errors,
4182 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4183 pf->offset_loaded, &os->illegal_bytes,
4184 &ns->illegal_bytes);
4185 /* GLPRT_ERRBC not supported */
4186 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4187 pf->offset_loaded, &os->mac_local_faults,
4188 &ns->mac_local_faults);
4189 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4190 pf->offset_loaded, &os->mac_remote_faults,
4191 &ns->mac_remote_faults);
4193 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4194 pf->offset_loaded, &os->rx_len_errors,
4195 &ns->rx_len_errors);
4197 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4198 pf->offset_loaded, &os->link_xon_rx,
4200 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4201 pf->offset_loaded, &os->link_xoff_rx,
4203 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4204 pf->offset_loaded, &os->link_xon_tx,
4206 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4207 pf->offset_loaded, &os->link_xoff_tx,
4209 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4210 GLPRT_PRC64L(hw->port_info->lport),
4211 pf->offset_loaded, &os->rx_size_64,
4213 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4214 GLPRT_PRC127L(hw->port_info->lport),
4215 pf->offset_loaded, &os->rx_size_127,
4217 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4218 GLPRT_PRC255L(hw->port_info->lport),
4219 pf->offset_loaded, &os->rx_size_255,
4221 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4222 GLPRT_PRC511L(hw->port_info->lport),
4223 pf->offset_loaded, &os->rx_size_511,
4225 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4226 GLPRT_PRC1023L(hw->port_info->lport),
4227 pf->offset_loaded, &os->rx_size_1023,
4229 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4230 GLPRT_PRC1522L(hw->port_info->lport),
4231 pf->offset_loaded, &os->rx_size_1522,
4233 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4234 GLPRT_PRC9522L(hw->port_info->lport),
4235 pf->offset_loaded, &os->rx_size_big,
4237 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4238 pf->offset_loaded, &os->rx_undersize,
4240 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4241 pf->offset_loaded, &os->rx_fragments,
4243 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4244 pf->offset_loaded, &os->rx_oversize,
4246 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4247 pf->offset_loaded, &os->rx_jabber,
4249 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4250 GLPRT_PTC64L(hw->port_info->lport),
4251 pf->offset_loaded, &os->tx_size_64,
4253 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4254 GLPRT_PTC127L(hw->port_info->lport),
4255 pf->offset_loaded, &os->tx_size_127,
4257 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4258 GLPRT_PTC255L(hw->port_info->lport),
4259 pf->offset_loaded, &os->tx_size_255,
4261 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4262 GLPRT_PTC511L(hw->port_info->lport),
4263 pf->offset_loaded, &os->tx_size_511,
4265 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4266 GLPRT_PTC1023L(hw->port_info->lport),
4267 pf->offset_loaded, &os->tx_size_1023,
4269 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4270 GLPRT_PTC1522L(hw->port_info->lport),
4271 pf->offset_loaded, &os->tx_size_1522,
4273 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4274 GLPRT_PTC9522L(hw->port_info->lport),
4275 pf->offset_loaded, &os->tx_size_big,
4278 /* GLPRT_MSPDC not supported */
4279 /* GLPRT_XEC not supported */
4281 pf->offset_loaded = true;
4284 ice_update_vsi_stats(pf->main_vsi);
4287 /* Get all statistics of a port */
4289 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4291 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4292 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4295 /* call read registers - updates values, now write them to struct */
4296 ice_read_stats_registers(pf, hw);
4298 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4299 pf->main_vsi->eth_stats.rx_multicast +
4300 pf->main_vsi->eth_stats.rx_broadcast -
4301 pf->main_vsi->eth_stats.rx_discards;
4302 stats->opackets = ns->eth.tx_unicast +
4303 ns->eth.tx_multicast +
4304 ns->eth.tx_broadcast;
4305 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
4306 stats->obytes = ns->eth.tx_bytes;
4307 stats->oerrors = ns->eth.tx_errors +
4308 pf->main_vsi->eth_stats.tx_errors;
4311 stats->imissed = ns->eth.rx_discards +
4312 pf->main_vsi->eth_stats.rx_discards;
4313 stats->ierrors = ns->crc_errors +
4315 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4317 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4318 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
4319 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4320 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4321 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4322 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4323 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4324 pf->main_vsi->eth_stats.rx_discards);
4325 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4326 ns->eth.rx_unknown_protocol);
4327 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
4328 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4329 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4330 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4331 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4332 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4333 pf->main_vsi->eth_stats.tx_discards);
4334 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
4336 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
4337 ns->tx_dropped_link_down);
4338 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4339 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
4341 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
4342 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
4343 ns->mac_local_faults);
4344 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
4345 ns->mac_remote_faults);
4346 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
4347 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
4348 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
4349 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
4350 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
4351 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
4352 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
4353 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
4354 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
4355 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
4356 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
4357 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
4358 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
4359 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
4360 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
4361 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
4362 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
4363 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
4364 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
4365 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
4366 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
4367 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
4368 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
4369 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4373 /* Reset the statistics */
4375 ice_stats_reset(struct rte_eth_dev *dev)
4377 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4378 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4380 /* Mark PF and VSI stats to update the offset, aka "reset" */
4381 pf->offset_loaded = false;
4383 pf->main_vsi->offset_loaded = false;
4385 /* read the stats, reading current register values into offset */
4386 ice_read_stats_registers(pf, hw);
4392 ice_xstats_calc_num(void)
4396 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4402 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4405 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4406 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4409 struct ice_hw_port_stats *hw_stats = &pf->stats;
4411 count = ice_xstats_calc_num();
4415 ice_read_stats_registers(pf, hw);
4422 /* Get stats from ice_eth_stats struct */
4423 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4424 xstats[count].value =
4425 *(uint64_t *)((char *)&hw_stats->eth +
4426 ice_stats_strings[i].offset);
4427 xstats[count].id = count;
4431 /* Get individiual stats from ice_hw_port struct */
4432 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4433 xstats[count].value =
4434 *(uint64_t *)((char *)hw_stats +
4435 ice_hw_port_strings[i].offset);
4436 xstats[count].id = count;
4443 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4444 struct rte_eth_xstat_name *xstats_names,
4445 __rte_unused unsigned int limit)
4447 unsigned int count = 0;
4451 return ice_xstats_calc_num();
4453 /* Note: limit checked in rte_eth_xstats_names() */
4455 /* Get stats from ice_eth_stats struct */
4456 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4457 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4458 sizeof(xstats_names[count].name));
4462 /* Get individiual stats from ice_hw_port struct */
4463 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4464 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4465 sizeof(xstats_names[count].name));
4473 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4474 enum rte_filter_type filter_type,
4475 enum rte_filter_op filter_op,
4483 switch (filter_type) {
4484 case RTE_ETH_FILTER_GENERIC:
4485 if (filter_op != RTE_ETH_FILTER_GET)
4487 *(const void **)arg = &ice_flow_ops;
4490 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4499 /* Add UDP tunneling port */
4501 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4502 struct rte_eth_udp_tunnel *udp_tunnel)
4505 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4507 if (udp_tunnel == NULL)
4510 switch (udp_tunnel->prot_type) {
4511 case RTE_TUNNEL_TYPE_VXLAN:
4512 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4515 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4523 /* Delete UDP tunneling port */
4525 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4526 struct rte_eth_udp_tunnel *udp_tunnel)
4529 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4531 if (udp_tunnel == NULL)
4534 switch (udp_tunnel->prot_type) {
4535 case RTE_TUNNEL_TYPE_VXLAN:
4536 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4539 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4548 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4549 struct rte_pci_device *pci_dev)
4551 return rte_eth_dev_pci_generic_probe(pci_dev,
4552 sizeof(struct ice_adapter),
4557 ice_pci_remove(struct rte_pci_device *pci_dev)
4559 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4562 static struct rte_pci_driver rte_ice_pmd = {
4563 .id_table = pci_id_ice_map,
4564 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4565 .probe = ice_pci_probe,
4566 .remove = ice_pci_remove,
4570 * Driver initialization routine.
4571 * Invoked once at EAL init time.
4572 * Register itself as the [Poll Mode] Driver of PCI devices.
4574 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4575 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4576 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4577 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4578 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4579 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4580 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
4581 ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
4583 RTE_INIT(ice_init_log)
4585 ice_logtype_init = rte_log_register("pmd.net.ice.init");
4586 if (ice_logtype_init >= 0)
4587 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4588 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4589 if (ice_logtype_driver >= 0)
4590 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4592 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4593 ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4594 if (ice_logtype_rx >= 0)
4595 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4598 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4599 ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4600 if (ice_logtype_tx >= 0)
4601 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4604 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4605 ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4606 if (ice_logtype_tx_free >= 0)
4607 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);