1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
18 #include "rte_pmd_ice.h"
19 #include "ice_ethdev.h"
21 #include "ice_generic_flow.h"
24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
26 #define ICE_FLOW_MARK_SUPPORT_ARG "flow-mark-support"
27 #define ICE_PROTO_XTR_ARG "proto_xtr"
29 static const char * const ice_valid_args[] = {
30 ICE_SAFE_MODE_SUPPORT_ARG,
31 ICE_PIPELINE_MODE_SUPPORT_ARG,
32 ICE_FLOW_MARK_SUPPORT_ARG,
37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
38 .name = "ice_dynfield_proto_xtr_metadata",
39 .size = sizeof(uint32_t),
40 .align = __alignof__(uint32_t),
44 struct proto_xtr_ol_flag {
45 const struct rte_mbuf_dynflag param;
50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
52 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
55 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
58 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
60 [PROTO_XTR_IPV6_FLOW] = {
61 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
64 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
68 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
70 /* DDP package search path */
71 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
72 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
73 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
74 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
76 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
77 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
78 #define ICE_MAX_PKG_FILENAME_SIZE 256
79 #define ICE_MAX_RES_DESC_NUM 1024
82 int ice_logtype_driver;
83 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
86 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
89 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
90 int ice_logtype_tx_free;
93 static int ice_dev_configure(struct rte_eth_dev *dev);
94 static int ice_dev_start(struct rte_eth_dev *dev);
95 static void ice_dev_stop(struct rte_eth_dev *dev);
96 static void ice_dev_close(struct rte_eth_dev *dev);
97 static int ice_dev_reset(struct rte_eth_dev *dev);
98 static int ice_dev_info_get(struct rte_eth_dev *dev,
99 struct rte_eth_dev_info *dev_info);
100 static int ice_link_update(struct rte_eth_dev *dev,
101 int wait_to_complete);
102 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
103 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
105 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
106 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
107 static int ice_rss_reta_update(struct rte_eth_dev *dev,
108 struct rte_eth_rss_reta_entry64 *reta_conf,
110 static int ice_rss_reta_query(struct rte_eth_dev *dev,
111 struct rte_eth_rss_reta_entry64 *reta_conf,
113 static int ice_rss_hash_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_conf *rss_conf);
115 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
116 struct rte_eth_rss_conf *rss_conf);
117 static int ice_promisc_enable(struct rte_eth_dev *dev);
118 static int ice_promisc_disable(struct rte_eth_dev *dev);
119 static int ice_allmulti_enable(struct rte_eth_dev *dev);
120 static int ice_allmulti_disable(struct rte_eth_dev *dev);
121 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
124 static int ice_macaddr_set(struct rte_eth_dev *dev,
125 struct rte_ether_addr *mac_addr);
126 static int ice_macaddr_add(struct rte_eth_dev *dev,
127 struct rte_ether_addr *mac_addr,
128 __rte_unused uint32_t index,
130 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
131 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
133 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
135 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
137 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
138 uint16_t pvid, int on);
139 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
140 static int ice_get_eeprom(struct rte_eth_dev *dev,
141 struct rte_dev_eeprom_info *eeprom);
142 static int ice_stats_get(struct rte_eth_dev *dev,
143 struct rte_eth_stats *stats);
144 static int ice_stats_reset(struct rte_eth_dev *dev);
145 static int ice_xstats_get(struct rte_eth_dev *dev,
146 struct rte_eth_xstat *xstats, unsigned int n);
147 static int ice_xstats_get_names(struct rte_eth_dev *dev,
148 struct rte_eth_xstat_name *xstats_names,
150 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
151 enum rte_filter_type filter_type,
152 enum rte_filter_op filter_op,
154 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
155 struct rte_eth_udp_tunnel *udp_tunnel);
156 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
157 struct rte_eth_udp_tunnel *udp_tunnel);
159 static const struct rte_pci_id pci_id_ice_map[] = {
160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
164 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
165 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
166 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_BACKPLANE) },
167 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_QSFP) },
168 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_SFP) },
169 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_10G_BASE_T) },
170 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_SGMII) },
171 { .vendor_id = 0, /* sentinel */ },
174 static const struct eth_dev_ops ice_eth_dev_ops = {
175 .dev_configure = ice_dev_configure,
176 .dev_start = ice_dev_start,
177 .dev_stop = ice_dev_stop,
178 .dev_close = ice_dev_close,
179 .dev_reset = ice_dev_reset,
180 .dev_set_link_up = ice_dev_set_link_up,
181 .dev_set_link_down = ice_dev_set_link_down,
182 .rx_queue_start = ice_rx_queue_start,
183 .rx_queue_stop = ice_rx_queue_stop,
184 .tx_queue_start = ice_tx_queue_start,
185 .tx_queue_stop = ice_tx_queue_stop,
186 .rx_queue_setup = ice_rx_queue_setup,
187 .rx_queue_release = ice_rx_queue_release,
188 .tx_queue_setup = ice_tx_queue_setup,
189 .tx_queue_release = ice_tx_queue_release,
190 .dev_infos_get = ice_dev_info_get,
191 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
192 .link_update = ice_link_update,
193 .mtu_set = ice_mtu_set,
194 .mac_addr_set = ice_macaddr_set,
195 .mac_addr_add = ice_macaddr_add,
196 .mac_addr_remove = ice_macaddr_remove,
197 .vlan_filter_set = ice_vlan_filter_set,
198 .vlan_offload_set = ice_vlan_offload_set,
199 .reta_update = ice_rss_reta_update,
200 .reta_query = ice_rss_reta_query,
201 .rss_hash_update = ice_rss_hash_update,
202 .rss_hash_conf_get = ice_rss_hash_conf_get,
203 .promiscuous_enable = ice_promisc_enable,
204 .promiscuous_disable = ice_promisc_disable,
205 .allmulticast_enable = ice_allmulti_enable,
206 .allmulticast_disable = ice_allmulti_disable,
207 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
208 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
209 .fw_version_get = ice_fw_version_get,
210 .vlan_pvid_set = ice_vlan_pvid_set,
211 .rxq_info_get = ice_rxq_info_get,
212 .txq_info_get = ice_txq_info_get,
213 .rx_burst_mode_get = ice_rx_burst_mode_get,
214 .tx_burst_mode_get = ice_tx_burst_mode_get,
215 .get_eeprom_length = ice_get_eeprom_length,
216 .get_eeprom = ice_get_eeprom,
217 .rx_queue_count = ice_rx_queue_count,
218 .rx_descriptor_status = ice_rx_descriptor_status,
219 .tx_descriptor_status = ice_tx_descriptor_status,
220 .stats_get = ice_stats_get,
221 .stats_reset = ice_stats_reset,
222 .xstats_get = ice_xstats_get,
223 .xstats_get_names = ice_xstats_get_names,
224 .xstats_reset = ice_stats_reset,
225 .filter_ctrl = ice_dev_filter_ctrl,
226 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
227 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
228 .tx_done_cleanup = ice_tx_done_cleanup,
231 /* store statistics names and its offset in stats structure */
232 struct ice_xstats_name_off {
233 char name[RTE_ETH_XSTATS_NAME_SIZE];
237 static const struct ice_xstats_name_off ice_stats_strings[] = {
238 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
239 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
240 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
241 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
242 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
243 rx_unknown_protocol)},
244 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
245 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
246 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
247 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
250 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
251 sizeof(ice_stats_strings[0]))
253 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
254 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
255 tx_dropped_link_down)},
256 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
257 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
259 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
260 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
262 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
264 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
266 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
267 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
268 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
269 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
270 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
271 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
273 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
275 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
277 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
279 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
281 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
283 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
285 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
287 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
288 mac_short_pkt_dropped)},
289 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
291 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
292 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
293 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
295 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
297 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
299 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
301 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
303 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
307 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
308 sizeof(ice_hw_port_strings[0]))
311 ice_init_controlq_parameter(struct ice_hw *hw)
313 /* fields for adminq */
314 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
315 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
316 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
317 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
319 /* fields for mailboxq, DPDK used as PF host */
320 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
321 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
322 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
323 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
327 lookup_proto_xtr_type(const char *xtr_name)
331 enum proto_xtr_type type;
333 { "vlan", PROTO_XTR_VLAN },
334 { "ipv4", PROTO_XTR_IPV4 },
335 { "ipv6", PROTO_XTR_IPV6 },
336 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
337 { "tcp", PROTO_XTR_TCP },
341 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
342 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
343 return xtr_type_map[i].type;
350 * Parse elem, the elem could be single number/range or '(' ')' group
351 * 1) A single number elem, it's just a simple digit. e.g. 9
352 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
353 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
354 * Within group elem, '-' used for a range separator;
355 * ',' used for a single number.
358 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
360 const char *str = input;
365 while (isblank(*str))
368 if (!isdigit(*str) && *str != '(')
371 /* process single number or single range of number */
374 idx = strtoul(str, &end, 10);
375 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
378 while (isblank(*end))
384 /* process single <number>-<number> */
387 while (isblank(*end))
393 idx = strtoul(end, &end, 10);
394 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
398 while (isblank(*end))
405 for (idx = RTE_MIN(min, max);
406 idx <= RTE_MAX(min, max); idx++)
407 devargs->proto_xtr[idx] = xtr_type;
412 /* process set within bracket */
414 while (isblank(*str))
419 min = ICE_MAX_QUEUE_NUM;
421 /* go ahead to the first digit */
422 while (isblank(*str))
427 /* get the digit value */
429 idx = strtoul(str, &end, 10);
430 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
433 /* go ahead to separator '-',',' and ')' */
434 while (isblank(*end))
437 if (min == ICE_MAX_QUEUE_NUM)
439 else /* avoid continuous '-' */
441 } else if (*end == ',' || *end == ')') {
443 if (min == ICE_MAX_QUEUE_NUM)
446 for (idx = RTE_MIN(min, max);
447 idx <= RTE_MAX(min, max); idx++)
448 devargs->proto_xtr[idx] = xtr_type;
450 min = ICE_MAX_QUEUE_NUM;
456 } while (*end != ')' && *end != '\0');
462 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
464 const char *queue_start;
469 while (isblank(*queues))
472 if (*queues != '[') {
473 xtr_type = lookup_proto_xtr_type(queues);
477 devargs->proto_xtr_dflt = xtr_type;
484 while (isblank(*queues))
489 queue_start = queues;
491 /* go across a complete bracket */
492 if (*queue_start == '(') {
493 queues += strcspn(queues, ")");
498 /* scan the separator ':' */
499 queues += strcspn(queues, ":");
500 if (*queues++ != ':')
502 while (isblank(*queues))
505 for (idx = 0; ; idx++) {
506 if (isblank(queues[idx]) ||
507 queues[idx] == ',' ||
508 queues[idx] == ']' ||
512 if (idx > sizeof(xtr_name) - 2)
515 xtr_name[idx] = queues[idx];
517 xtr_name[idx] = '\0';
518 xtr_type = lookup_proto_xtr_type(xtr_name);
524 while (isblank(*queues) || *queues == ',' || *queues == ']')
527 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
529 } while (*queues != '\0');
535 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
538 struct ice_devargs *devargs = extra_args;
540 if (value == NULL || extra_args == NULL)
543 if (parse_queue_proto_xtr(value, devargs) < 0) {
545 "The protocol extraction parameter is wrong : '%s'",
554 ice_proto_xtr_support(struct ice_hw *hw)
556 #define FLX_REG(val, fld, idx) \
557 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
558 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
564 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
565 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
566 ICE_PROT_IPV4_OF_OR_S },
567 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
568 ICE_PROT_IPV6_OF_OR_S },
569 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
570 ICE_PROT_IPV6_OF_OR_S },
571 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
575 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
576 uint32_t rxdid = xtr_sets[i].rxdid;
579 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
580 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
582 if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
583 FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
587 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
588 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
590 if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
591 FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
600 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
603 struct pool_entry *entry;
608 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
611 "Failed to allocate memory for resource pool");
615 /* queue heap initialize */
616 pool->num_free = num;
619 LIST_INIT(&pool->alloc_list);
620 LIST_INIT(&pool->free_list);
622 /* Initialize element */
626 LIST_INSERT_HEAD(&pool->free_list, entry, next);
631 ice_res_pool_alloc(struct ice_res_pool_info *pool,
634 struct pool_entry *entry, *valid_entry;
637 PMD_INIT_LOG(ERR, "Invalid parameter");
641 if (pool->num_free < num) {
642 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
643 num, pool->num_free);
648 /* Lookup in free list and find most fit one */
649 LIST_FOREACH(entry, &pool->free_list, next) {
650 if (entry->len >= num) {
652 if (entry->len == num) {
657 valid_entry->len > entry->len)
662 /* Not find one to satisfy the request, return */
664 PMD_INIT_LOG(ERR, "No valid entry found");
668 * The entry have equal queue number as requested,
669 * remove it from alloc_list.
671 if (valid_entry->len == num) {
672 LIST_REMOVE(valid_entry, next);
675 * The entry have more numbers than requested,
676 * create a new entry for alloc_list and minus its
677 * queue base and number in free_list.
679 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
682 "Failed to allocate memory for "
686 entry->base = valid_entry->base;
688 valid_entry->base += num;
689 valid_entry->len -= num;
693 /* Insert it into alloc list, not sorted */
694 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
696 pool->num_free -= valid_entry->len;
697 pool->num_alloc += valid_entry->len;
699 return valid_entry->base + pool->base;
703 ice_res_pool_destroy(struct ice_res_pool_info *pool)
705 struct pool_entry *entry, *next_entry;
710 for (entry = LIST_FIRST(&pool->alloc_list);
711 entry && (next_entry = LIST_NEXT(entry, next), 1);
712 entry = next_entry) {
713 LIST_REMOVE(entry, next);
717 for (entry = LIST_FIRST(&pool->free_list);
718 entry && (next_entry = LIST_NEXT(entry, next), 1);
719 entry = next_entry) {
720 LIST_REMOVE(entry, next);
727 LIST_INIT(&pool->alloc_list);
728 LIST_INIT(&pool->free_list);
732 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
734 /* Set VSI LUT selection */
735 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
736 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
737 /* Set Hash scheme */
738 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
739 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
741 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
744 static enum ice_status
745 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
746 struct ice_aqc_vsi_props *info,
747 uint8_t enabled_tcmap)
749 uint16_t bsf, qp_idx;
751 /* default tc 0 now. Multi-TC supporting need to be done later.
752 * Configure TC and queue mapping parameters, for enabled TC,
753 * allocate qpnum_per_tc queues to this traffic.
755 if (enabled_tcmap != 0x01) {
756 PMD_INIT_LOG(ERR, "only TC0 is supported");
760 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
761 bsf = rte_bsf32(vsi->nb_qps);
762 /* Adjust the queue number to actual queues that can be applied */
763 vsi->nb_qps = 0x1 << bsf;
766 /* Set tc and queue mapping with VSI */
767 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
768 ICE_AQ_VSI_TC_Q_OFFSET_S) |
769 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
771 /* Associate queue number with VSI */
772 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
773 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
774 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
775 info->valid_sections |=
776 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
777 /* Set the info.ingress_table and info.egress_table
778 * for UP translate table. Now just set it to 1:1 map by default
779 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
781 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
782 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
783 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
784 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
789 ice_init_mac_address(struct rte_eth_dev *dev)
791 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
793 if (!rte_is_unicast_ether_addr
794 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
795 PMD_INIT_LOG(ERR, "Invalid MAC address");
800 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
801 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
803 dev->data->mac_addrs =
804 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
805 if (!dev->data->mac_addrs) {
807 "Failed to allocate memory to store mac address");
810 /* store it to dev data */
812 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
813 &dev->data->mac_addrs[0]);
817 /* Find out specific MAC filter */
818 static struct ice_mac_filter *
819 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
821 struct ice_mac_filter *f;
823 TAILQ_FOREACH(f, &vsi->mac_list, next) {
824 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
832 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
834 struct ice_fltr_list_entry *m_list_itr = NULL;
835 struct ice_mac_filter *f;
836 struct LIST_HEAD_TYPE list_head;
837 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
840 /* If it's added and configured, return */
841 f = ice_find_mac_filter(vsi, mac_addr);
843 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
847 INIT_LIST_HEAD(&list_head);
849 m_list_itr = (struct ice_fltr_list_entry *)
850 ice_malloc(hw, sizeof(*m_list_itr));
855 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
856 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
857 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
858 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
859 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
860 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
861 m_list_itr->fltr_info.vsi_handle = vsi->idx;
863 LIST_ADD(&m_list_itr->list_entry, &list_head);
866 ret = ice_add_mac(hw, &list_head);
867 if (ret != ICE_SUCCESS) {
868 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
872 /* Add the mac addr into mac list */
873 f = rte_zmalloc(NULL, sizeof(*f), 0);
875 PMD_DRV_LOG(ERR, "failed to allocate memory");
879 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
880 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
886 rte_free(m_list_itr);
891 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
893 struct ice_fltr_list_entry *m_list_itr = NULL;
894 struct ice_mac_filter *f;
895 struct LIST_HEAD_TYPE list_head;
896 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
899 /* Can't find it, return an error */
900 f = ice_find_mac_filter(vsi, mac_addr);
904 INIT_LIST_HEAD(&list_head);
906 m_list_itr = (struct ice_fltr_list_entry *)
907 ice_malloc(hw, sizeof(*m_list_itr));
912 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
913 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
914 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
915 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
916 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
917 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
918 m_list_itr->fltr_info.vsi_handle = vsi->idx;
920 LIST_ADD(&m_list_itr->list_entry, &list_head);
922 /* remove the mac filter */
923 ret = ice_remove_mac(hw, &list_head);
924 if (ret != ICE_SUCCESS) {
925 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
930 /* Remove the mac addr from mac list */
931 TAILQ_REMOVE(&vsi->mac_list, f, next);
937 rte_free(m_list_itr);
941 /* Find out specific VLAN filter */
942 static struct ice_vlan_filter *
943 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
945 struct ice_vlan_filter *f;
947 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
948 if (vlan_id == f->vlan_info.vlan_id)
956 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
958 struct ice_fltr_list_entry *v_list_itr = NULL;
959 struct ice_vlan_filter *f;
960 struct LIST_HEAD_TYPE list_head;
964 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
967 hw = ICE_VSI_TO_HW(vsi);
969 /* If it's added and configured, return. */
970 f = ice_find_vlan_filter(vsi, vlan_id);
972 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
976 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
979 INIT_LIST_HEAD(&list_head);
981 v_list_itr = (struct ice_fltr_list_entry *)
982 ice_malloc(hw, sizeof(*v_list_itr));
987 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
988 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
989 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
990 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
991 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
992 v_list_itr->fltr_info.vsi_handle = vsi->idx;
994 LIST_ADD(&v_list_itr->list_entry, &list_head);
997 ret = ice_add_vlan(hw, &list_head);
998 if (ret != ICE_SUCCESS) {
999 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1004 /* Add vlan into vlan list */
1005 f = rte_zmalloc(NULL, sizeof(*f), 0);
1007 PMD_DRV_LOG(ERR, "failed to allocate memory");
1011 f->vlan_info.vlan_id = vlan_id;
1012 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1018 rte_free(v_list_itr);
1023 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1025 struct ice_fltr_list_entry *v_list_itr = NULL;
1026 struct ice_vlan_filter *f;
1027 struct LIST_HEAD_TYPE list_head;
1032 * Vlan 0 is the generic filter for untagged packets
1033 * and can't be removed.
1035 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1038 hw = ICE_VSI_TO_HW(vsi);
1040 /* Can't find it, return an error */
1041 f = ice_find_vlan_filter(vsi, vlan_id);
1045 INIT_LIST_HEAD(&list_head);
1047 v_list_itr = (struct ice_fltr_list_entry *)
1048 ice_malloc(hw, sizeof(*v_list_itr));
1054 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1055 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1056 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1057 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1058 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1059 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1061 LIST_ADD(&v_list_itr->list_entry, &list_head);
1063 /* remove the vlan filter */
1064 ret = ice_remove_vlan(hw, &list_head);
1065 if (ret != ICE_SUCCESS) {
1066 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1071 /* Remove the vlan id from vlan list */
1072 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1078 rte_free(v_list_itr);
1083 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1085 struct ice_mac_filter *m_f;
1086 struct ice_vlan_filter *v_f;
1089 if (!vsi || !vsi->mac_num)
1092 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1093 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1094 if (ret != ICE_SUCCESS) {
1100 if (vsi->vlan_num == 0)
1103 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1104 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1105 if (ret != ICE_SUCCESS) {
1116 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1118 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1119 struct ice_vsi_ctx ctxt;
1123 /* Check if it has been already on or off */
1124 if (vsi->info.valid_sections &
1125 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1127 if ((vsi->info.outer_tag_flags &
1128 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1129 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1130 return 0; /* already on */
1132 if (!(vsi->info.outer_tag_flags &
1133 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1134 return 0; /* already off */
1139 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1142 /* clear global insertion and use per packet insertion */
1143 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1144 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1145 vsi->info.outer_tag_flags |= qinq_flags;
1146 /* use default vlan type 0x8100 */
1147 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1148 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1149 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1150 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1151 ctxt.info.valid_sections =
1152 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1153 ctxt.vsi_num = vsi->vsi_id;
1154 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1157 "Update VSI failed to %s qinq stripping",
1158 on ? "enable" : "disable");
1162 vsi->info.valid_sections |=
1163 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1169 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1171 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1172 struct ice_vsi_ctx ctxt;
1176 /* Check if it has been already on or off */
1177 if (vsi->info.valid_sections &
1178 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1180 if ((vsi->info.outer_tag_flags &
1181 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1182 ICE_AQ_VSI_OUTER_TAG_COPY)
1183 return 0; /* already on */
1185 if ((vsi->info.outer_tag_flags &
1186 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1187 ICE_AQ_VSI_OUTER_TAG_NOTHING)
1188 return 0; /* already off */
1193 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1195 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1196 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1197 vsi->info.outer_tag_flags |= qinq_flags;
1198 /* use default vlan type 0x8100 */
1199 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1200 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1201 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1202 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1203 ctxt.info.valid_sections =
1204 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1205 ctxt.vsi_num = vsi->vsi_id;
1206 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1209 "Update VSI failed to %s qinq stripping",
1210 on ? "enable" : "disable");
1214 vsi->info.valid_sections |=
1215 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1221 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1225 ret = ice_vsi_config_qinq_stripping(vsi, on);
1227 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1229 ret = ice_vsi_config_qinq_insertion(vsi, on);
1231 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1238 ice_pf_enable_irq0(struct ice_hw *hw)
1240 /* reset the registers */
1241 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1242 ICE_READ_REG(hw, PFINT_OICR);
1245 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1246 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1247 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1249 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1250 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1251 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1252 PFINT_OICR_CTL_ITR_INDX_M) |
1253 PFINT_OICR_CTL_CAUSE_ENA_M);
1255 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1256 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1257 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1258 PFINT_FW_CTL_ITR_INDX_M) |
1259 PFINT_FW_CTL_CAUSE_ENA_M);
1261 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1264 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1265 GLINT_DYN_CTL_INTENA_M |
1266 GLINT_DYN_CTL_CLEARPBA_M |
1267 GLINT_DYN_CTL_ITR_INDX_M);
1274 ice_pf_disable_irq0(struct ice_hw *hw)
1276 /* Disable all interrupt types */
1277 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1283 ice_handle_aq_msg(struct rte_eth_dev *dev)
1285 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1286 struct ice_ctl_q_info *cq = &hw->adminq;
1287 struct ice_rq_event_info event;
1288 uint16_t pending, opcode;
1291 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1292 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1293 if (!event.msg_buf) {
1294 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1300 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1302 if (ret != ICE_SUCCESS) {
1304 "Failed to read msg from AdminQ, "
1306 hw->adminq.sq_last_status);
1309 opcode = rte_le_to_cpu_16(event.desc.opcode);
1312 case ice_aqc_opc_get_link_status:
1313 ret = ice_link_update(dev, 0);
1315 _rte_eth_dev_callback_process
1316 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1319 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1324 rte_free(event.msg_buf);
1329 * Interrupt handler triggered by NIC for handling
1330 * specific interrupt.
1333 * Pointer to interrupt handle.
1335 * The address of parameter (struct rte_eth_dev *) regsitered before.
1341 ice_interrupt_handler(void *param)
1343 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1344 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352 uint32_t int_fw_ctl;
1355 /* Disable interrupt */
1356 ice_pf_disable_irq0(hw);
1358 /* read out interrupt causes */
1359 oicr = ICE_READ_REG(hw, PFINT_OICR);
1361 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1364 /* No interrupt event indicated */
1365 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1366 PMD_DRV_LOG(INFO, "No interrupt event");
1371 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1372 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1373 ice_handle_aq_msg(dev);
1376 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1377 PMD_DRV_LOG(INFO, "OICR: link state change event");
1378 ret = ice_link_update(dev, 0);
1380 _rte_eth_dev_callback_process
1381 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1385 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1386 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1387 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1388 if (reg & GL_MDET_TX_PQM_VALID_M) {
1389 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1390 GL_MDET_TX_PQM_PF_NUM_S;
1391 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1392 GL_MDET_TX_PQM_MAL_TYPE_S;
1393 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1394 GL_MDET_TX_PQM_QNUM_S;
1396 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1397 "%d by PQM on TX queue %d PF# %d",
1398 event, queue, pf_num);
1401 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1402 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1403 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1404 GL_MDET_TX_TCLAN_PF_NUM_S;
1405 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1406 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1407 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1408 GL_MDET_TX_TCLAN_QNUM_S;
1410 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1411 "%d by TCLAN on TX queue %d PF# %d",
1412 event, queue, pf_num);
1416 /* Enable interrupt */
1417 ice_pf_enable_irq0(hw);
1418 rte_intr_ack(dev->intr_handle);
1422 ice_init_proto_xtr(struct rte_eth_dev *dev)
1424 struct ice_adapter *ad =
1425 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1426 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1428 const struct proto_xtr_ol_flag *ol_flag;
1429 bool proto_xtr_enable = false;
1433 if (!ice_proto_xtr_support(hw)) {
1434 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1438 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1439 if (unlikely(pf->proto_xtr == NULL)) {
1440 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1444 for (i = 0; i < pf->lan_nb_qps; i++) {
1445 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1446 ad->devargs.proto_xtr[i] :
1447 ad->devargs.proto_xtr_dflt;
1449 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1450 uint8_t type = pf->proto_xtr[i];
1452 ice_proto_xtr_ol_flag_params[type].required = true;
1453 proto_xtr_enable = true;
1457 if (likely(!proto_xtr_enable))
1460 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1461 if (unlikely(offset == -1)) {
1463 "Protocol extraction metadata is disabled in mbuf with error %d",
1469 "Protocol extraction metadata offset in mbuf is : %d",
1471 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1473 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1474 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1476 if (!ol_flag->required)
1479 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1480 if (unlikely(offset == -1)) {
1482 "Protocol extraction offload '%s' failed to register with error %d",
1483 ol_flag->param.name, -rte_errno);
1485 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1490 "Protocol extraction offload '%s' offset in mbuf is : %d",
1491 ol_flag->param.name, offset);
1492 *ol_flag->ol_flag = 1ULL << offset;
1496 /* Initialize SW parameters of PF */
1498 ice_pf_sw_init(struct rte_eth_dev *dev)
1500 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1501 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1504 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1505 hw->func_caps.common_cap.num_rxq);
1507 pf->lan_nb_qps = pf->lan_nb_qp_max;
1509 ice_init_proto_xtr(dev);
1511 if (hw->func_caps.fd_fltr_guar > 0 ||
1512 hw->func_caps.fd_fltr_best_effort > 0) {
1513 pf->flags |= ICE_FLAG_FDIR;
1514 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1515 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1517 pf->fdir_nb_qps = 0;
1519 pf->fdir_qp_offset = 0;
1525 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1527 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1528 struct ice_vsi *vsi = NULL;
1529 struct ice_vsi_ctx vsi_ctx;
1531 struct rte_ether_addr broadcast = {
1532 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1533 struct rte_ether_addr mac_addr;
1534 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1535 uint8_t tc_bitmap = 0x1;
1538 /* hw->num_lports = 1 in NIC mode */
1539 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1543 vsi->idx = pf->next_vsi_idx;
1546 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1547 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1548 vsi->vlan_anti_spoof_on = 0;
1549 vsi->vlan_filter_on = 1;
1550 TAILQ_INIT(&vsi->mac_list);
1551 TAILQ_INIT(&vsi->vlan_list);
1553 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1554 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1555 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1556 hw->func_caps.common_cap.rss_table_size;
1557 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1559 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1562 vsi->nb_qps = pf->lan_nb_qps;
1563 vsi->base_queue = 1;
1564 ice_vsi_config_default_rss(&vsi_ctx.info);
1565 vsi_ctx.alloc_from_pool = true;
1566 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1567 /* switch_id is queried by get_switch_config aq, which is done
1570 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1571 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1572 /* Allow all untagged or tagged packets */
1573 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1574 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1575 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1576 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1579 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1580 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1581 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1582 cfg = ICE_AQ_VSI_FD_ENABLE;
1583 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1584 vsi_ctx.info.max_fd_fltr_dedicated =
1585 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1586 vsi_ctx.info.max_fd_fltr_shared =
1587 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1589 /* Enable VLAN/UP trip */
1590 ret = ice_vsi_config_tc_queue_mapping(vsi,
1595 "tc queue mapping with vsi failed, "
1603 vsi->nb_qps = pf->fdir_nb_qps;
1604 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1605 vsi_ctx.alloc_from_pool = true;
1606 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1608 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1609 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1610 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1611 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1612 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1613 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1614 ret = ice_vsi_config_tc_queue_mapping(vsi,
1619 "tc queue mapping with vsi failed, "
1626 /* for other types of VSI */
1627 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1631 /* VF has MSIX interrupt in VF range, don't allocate here */
1632 if (type == ICE_VSI_PF) {
1633 ret = ice_res_pool_alloc(&pf->msix_pool,
1634 RTE_MIN(vsi->nb_qps,
1635 RTE_MAX_RXTX_INTR_VEC_ID));
1637 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1640 vsi->msix_intr = ret;
1641 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1642 } else if (type == ICE_VSI_CTRL) {
1643 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1645 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1648 vsi->msix_intr = ret;
1654 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1655 if (ret != ICE_SUCCESS) {
1656 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1659 /* store vsi information is SW structure */
1660 vsi->vsi_id = vsi_ctx.vsi_num;
1661 vsi->info = vsi_ctx.info;
1662 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1663 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1665 if (type == ICE_VSI_PF) {
1666 /* MAC configuration */
1667 rte_ether_addr_copy((struct rte_ether_addr *)
1668 hw->port_info->mac.perm_addr,
1671 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1672 ret = ice_add_mac_filter(vsi, &mac_addr);
1673 if (ret != ICE_SUCCESS)
1674 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1676 rte_ether_addr_copy(&broadcast, &mac_addr);
1677 ret = ice_add_mac_filter(vsi, &mac_addr);
1678 if (ret != ICE_SUCCESS)
1679 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1682 /* At the beginning, only TC0. */
1683 /* What we need here is the maximam number of the TX queues.
1684 * Currently vsi->nb_qps means it.
1685 * Correct it if any change.
1687 max_txqs[0] = vsi->nb_qps;
1688 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1689 tc_bitmap, max_txqs);
1690 if (ret != ICE_SUCCESS)
1691 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1701 ice_send_driver_ver(struct ice_hw *hw)
1703 struct ice_driver_ver dv;
1705 /* we don't have driver version use 0 for dummy */
1709 dv.subbuild_ver = 0;
1710 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1712 return ice_aq_send_driver_ver(hw, &dv, NULL);
1716 ice_pf_setup(struct ice_pf *pf)
1718 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1719 struct ice_vsi *vsi;
1722 /* Clear all stats counters */
1723 pf->offset_loaded = false;
1724 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1725 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1726 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1727 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1729 /* force guaranteed filter pool for PF */
1730 ice_alloc_fd_guar_item(hw, &unused,
1731 hw->func_caps.fd_fltr_guar);
1732 /* force shared filter pool for PF */
1733 ice_alloc_fd_shrd_item(hw, &unused,
1734 hw->func_caps.fd_fltr_best_effort);
1736 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1738 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1747 /* PCIe configuration space setting */
1748 #define PCI_CFG_SPACE_SIZE 256
1749 #define PCI_CFG_SPACE_EXP_SIZE 4096
1750 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
1751 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
1752 #define PCI_EXT_CAP_ID_DSN 0x03
1755 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1759 int pos = PCI_CFG_SPACE_SIZE;
1761 /* minimum 8 bytes per capability */
1762 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1764 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1765 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1770 * If we have no capabilities, this is indicated by cap ID,
1771 * cap version and next pointer all being 0.
1777 if (PCI_EXT_CAP_ID(header) == cap)
1780 pos = PCI_EXT_CAP_NEXT(header);
1782 if (pos < PCI_CFG_SPACE_SIZE)
1785 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1786 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1795 * Extract device serial number from PCIe Configuration Space and
1796 * determine the pkg file path according to the DSN.
1799 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1802 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1803 uint32_t dsn_low, dsn_high;
1804 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1806 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1809 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1810 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1811 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1812 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1814 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1818 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1819 ICE_MAX_PKG_FILENAME_SIZE);
1820 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1823 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1824 ICE_MAX_PKG_FILENAME_SIZE);
1825 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1829 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1830 if (!access(pkg_file, 0))
1832 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1836 static enum ice_pkg_type
1837 ice_load_pkg_type(struct ice_hw *hw)
1839 enum ice_pkg_type package_type;
1841 /* store the activated package type (OS default or Comms) */
1842 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1844 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1845 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1847 package_type = ICE_PKG_TYPE_COMMS;
1849 package_type = ICE_PKG_TYPE_UNKNOWN;
1851 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1852 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1853 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1854 hw->active_pkg_name);
1856 return package_type;
1859 static int ice_load_pkg(struct rte_eth_dev *dev)
1861 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1868 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1869 struct ice_adapter *ad =
1870 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1872 ice_pkg_file_search_path(pci_dev, pkg_file);
1874 file = fopen(pkg_file, "rb");
1876 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1880 err = stat(pkg_file, &fstat);
1882 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1887 buf_len = fstat.st_size;
1888 buf = rte_malloc(NULL, buf_len, 0);
1891 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1897 err = fread(buf, buf_len, 1, file);
1899 PMD_INIT_LOG(ERR, "failed to read package data\n");
1907 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1909 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1913 /* store the loaded pkg type info */
1914 ad->active_pkg_type = ice_load_pkg_type(hw);
1916 err = ice_init_hw_tbls(hw);
1918 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1919 goto fail_init_tbls;
1925 rte_free(hw->pkg_copy);
1932 ice_base_queue_get(struct ice_pf *pf)
1935 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1937 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1938 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1939 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1941 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1947 parse_bool(const char *key, const char *value, void *args)
1949 int *i = (int *)args;
1953 num = strtoul(value, &end, 10);
1955 if (num != 0 && num != 1) {
1956 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1957 "value must be 0 or 1",
1966 static int ice_parse_devargs(struct rte_eth_dev *dev)
1968 struct ice_adapter *ad =
1969 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1970 struct rte_devargs *devargs = dev->device->devargs;
1971 struct rte_kvargs *kvlist;
1974 if (devargs == NULL)
1977 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1978 if (kvlist == NULL) {
1979 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1983 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1984 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1985 sizeof(ad->devargs.proto_xtr));
1987 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1988 &handle_proto_xtr_arg, &ad->devargs);
1992 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1993 &parse_bool, &ad->devargs.safe_mode_support);
1997 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1998 &parse_bool, &ad->devargs.pipe_mode_support);
2002 ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
2003 &parse_bool, &ad->devargs.flow_mark_support);
2008 rte_kvargs_free(kvlist);
2012 /* Forward LLDP packets to default VSI by set switch rules */
2014 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
2016 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2017 struct ice_fltr_list_entry *s_list_itr = NULL;
2018 struct LIST_HEAD_TYPE list_head;
2021 INIT_LIST_HEAD(&list_head);
2023 s_list_itr = (struct ice_fltr_list_entry *)
2024 ice_malloc(hw, sizeof(*s_list_itr));
2027 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2028 s_list_itr->fltr_info.vsi_handle = vsi->idx;
2029 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2030 RTE_ETHER_TYPE_LLDP;
2031 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2032 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2033 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2034 LIST_ADD(&s_list_itr->list_entry, &list_head);
2036 ret = ice_add_eth_mac(hw, &list_head);
2038 ret = ice_remove_eth_mac(hw, &list_head);
2040 rte_free(s_list_itr);
2044 static enum ice_status
2045 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2046 uint16_t num, uint16_t desc_id,
2047 uint16_t *prof_buf, uint16_t *num_prof)
2049 struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2052 bool res_shared = 1;
2053 struct ice_aq_desc aq_desc;
2054 struct ice_sq_cd *cd = NULL;
2055 struct ice_aqc_get_allocd_res_desc *cmd =
2056 &aq_desc.params.get_res_desc;
2058 buf_len = sizeof(resp_buf->elem) * num;
2059 resp_buf = ice_malloc(hw, buf_len);
2063 ice_fill_dflt_direct_cmd_desc(&aq_desc,
2064 ice_aqc_opc_get_allocd_res_desc);
2066 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2067 ICE_AQC_RES_TYPE_M) | (res_shared ?
2068 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2069 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2071 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2073 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2077 ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2078 (*num_prof), ICE_NONDMA_TO_NONDMA);
2085 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2089 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2090 uint16_t first_desc = 1;
2091 uint16_t num_prof = 0;
2093 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2094 first_desc, prof_buf, &num_prof);
2096 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2100 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2101 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2103 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2111 ice_reset_fxp_resource(struct ice_hw *hw)
2115 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2117 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2121 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2123 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2131 ice_dev_init(struct rte_eth_dev *dev)
2133 struct rte_pci_device *pci_dev;
2134 struct rte_intr_handle *intr_handle;
2135 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2136 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2137 struct ice_adapter *ad =
2138 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2139 struct ice_vsi *vsi;
2142 dev->dev_ops = &ice_eth_dev_ops;
2143 dev->rx_pkt_burst = ice_recv_pkts;
2144 dev->tx_pkt_burst = ice_xmit_pkts;
2145 dev->tx_pkt_prepare = ice_prep_pkts;
2147 /* for secondary processes, we don't initialise any further as primary
2148 * has already done this work.
2150 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2151 ice_set_rx_function(dev);
2152 ice_set_tx_function(dev);
2156 ice_set_default_ptype_table(dev);
2157 pci_dev = RTE_DEV_TO_PCI(dev->device);
2158 intr_handle = &pci_dev->intr_handle;
2160 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2161 pf->adapter->eth_dev = dev;
2162 pf->dev_data = dev->data;
2163 hw->back = pf->adapter;
2164 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2165 hw->vendor_id = pci_dev->id.vendor_id;
2166 hw->device_id = pci_dev->id.device_id;
2167 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2168 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2169 hw->bus.device = pci_dev->addr.devid;
2170 hw->bus.func = pci_dev->addr.function;
2172 ret = ice_parse_devargs(dev);
2174 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2178 ice_init_controlq_parameter(hw);
2180 ret = ice_init_hw(hw);
2182 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2186 ret = ice_load_pkg(dev);
2188 if (ad->devargs.safe_mode_support == 0) {
2189 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2190 "Use safe-mode-support=1 to enter Safe Mode");
2194 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2195 "Entering Safe Mode");
2196 ad->is_safe_mode = 1;
2199 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2200 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2201 hw->api_maj_ver, hw->api_min_ver);
2203 ice_pf_sw_init(dev);
2204 ret = ice_init_mac_address(dev);
2206 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2210 /* Pass the information to the rte_eth_dev_close() that it should also
2211 * release the private port resources.
2213 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2215 ret = ice_res_pool_init(&pf->msix_pool, 1,
2216 hw->func_caps.common_cap.num_msix_vectors - 1);
2218 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2219 goto err_msix_pool_init;
2222 ret = ice_pf_setup(pf);
2224 PMD_INIT_LOG(ERR, "Failed to setup PF");
2228 ret = ice_send_driver_ver(hw);
2230 PMD_INIT_LOG(ERR, "Failed to send driver version");
2236 /* Disable double vlan by default */
2237 ice_vsi_config_double_vlan(vsi, false);
2239 ret = ice_aq_stop_lldp(hw, true, false, NULL);
2240 if (ret != ICE_SUCCESS)
2241 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2242 ret = ice_init_dcb(hw, true);
2243 if (ret != ICE_SUCCESS)
2244 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2245 /* Forward LLDP packets to default VSI */
2246 ret = ice_vsi_config_sw_lldp(vsi, true);
2247 if (ret != ICE_SUCCESS)
2248 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2249 /* register callback func to eal lib */
2250 rte_intr_callback_register(intr_handle,
2251 ice_interrupt_handler, dev);
2253 ice_pf_enable_irq0(hw);
2255 /* enable uio intr after callback register */
2256 rte_intr_enable(intr_handle);
2258 /* get base queue pairs index in the device */
2259 ice_base_queue_get(pf);
2261 if (!ad->is_safe_mode) {
2262 ret = ice_flow_init(ad);
2264 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2269 ret = ice_reset_fxp_resource(hw);
2271 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2278 ice_res_pool_destroy(&pf->msix_pool);
2280 rte_free(dev->data->mac_addrs);
2281 dev->data->mac_addrs = NULL;
2283 ice_sched_cleanup_all(hw);
2284 rte_free(hw->port_info);
2285 ice_shutdown_all_ctrlq(hw);
2286 rte_free(pf->proto_xtr);
2292 ice_release_vsi(struct ice_vsi *vsi)
2295 struct ice_vsi_ctx vsi_ctx;
2296 enum ice_status ret;
2301 hw = ICE_VSI_TO_HW(vsi);
2303 ice_remove_all_mac_vlan_filters(vsi);
2305 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2307 vsi_ctx.vsi_num = vsi->vsi_id;
2308 vsi_ctx.info = vsi->info;
2309 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2310 if (ret != ICE_SUCCESS) {
2311 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2321 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2323 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2324 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2325 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2326 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2327 uint16_t msix_intr, i;
2329 /* disable interrupt and also clear all the exist config */
2330 for (i = 0; i < vsi->nb_qps; i++) {
2331 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2332 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2336 if (rte_intr_allow_others(intr_handle))
2338 for (i = 0; i < vsi->nb_msix; i++) {
2339 msix_intr = vsi->msix_intr + i;
2340 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2341 GLINT_DYN_CTL_WB_ON_ITR_M);
2345 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2349 ice_dev_stop(struct rte_eth_dev *dev)
2351 struct rte_eth_dev_data *data = dev->data;
2352 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2353 struct ice_vsi *main_vsi = pf->main_vsi;
2354 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2355 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2358 /* avoid stopping again */
2359 if (pf->adapter_stopped)
2362 /* stop and clear all Rx queues */
2363 for (i = 0; i < data->nb_rx_queues; i++)
2364 ice_rx_queue_stop(dev, i);
2366 /* stop and clear all Tx queues */
2367 for (i = 0; i < data->nb_tx_queues; i++)
2368 ice_tx_queue_stop(dev, i);
2370 /* disable all queue interrupts */
2371 ice_vsi_disable_queues_intr(main_vsi);
2373 /* Clear all queues and release mbufs */
2374 ice_clear_queues(dev);
2376 if (pf->init_link_up)
2377 ice_dev_set_link_up(dev);
2379 ice_dev_set_link_down(dev);
2381 /* Clean datapath event and queue/vec mapping */
2382 rte_intr_efd_disable(intr_handle);
2383 if (intr_handle->intr_vec) {
2384 rte_free(intr_handle->intr_vec);
2385 intr_handle->intr_vec = NULL;
2388 pf->adapter_stopped = true;
2392 ice_dev_close(struct rte_eth_dev *dev)
2394 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2395 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2397 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2398 struct ice_adapter *ad =
2399 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2401 /* Since stop will make link down, then the link event will be
2402 * triggered, disable the irq firstly to avoid the port_infoe etc
2403 * resources deallocation causing the interrupt service thread
2406 ice_pf_disable_irq0(hw);
2410 if (!ad->is_safe_mode)
2411 ice_flow_uninit(ad);
2413 /* release all queue resource */
2414 ice_free_queues(dev);
2416 ice_res_pool_destroy(&pf->msix_pool);
2417 ice_release_vsi(pf->main_vsi);
2418 ice_sched_cleanup_all(hw);
2419 ice_free_hw_tbls(hw);
2420 rte_free(hw->port_info);
2421 hw->port_info = NULL;
2422 ice_shutdown_all_ctrlq(hw);
2423 rte_free(pf->proto_xtr);
2424 pf->proto_xtr = NULL;
2426 dev->dev_ops = NULL;
2427 dev->rx_pkt_burst = NULL;
2428 dev->tx_pkt_burst = NULL;
2430 rte_free(dev->data->mac_addrs);
2431 dev->data->mac_addrs = NULL;
2433 /* disable uio intr before callback unregister */
2434 rte_intr_disable(intr_handle);
2436 /* unregister callback func from eal lib */
2437 rte_intr_callback_unregister(intr_handle,
2438 ice_interrupt_handler, dev);
2442 ice_dev_uninit(struct rte_eth_dev *dev)
2450 ice_dev_configure(struct rte_eth_dev *dev)
2452 struct ice_adapter *ad =
2453 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2455 /* Initialize to TRUE. If any of Rx queues doesn't meet the
2456 * bulk allocation or vector Rx preconditions we will reset it.
2458 ad->rx_bulk_alloc_allowed = true;
2459 ad->tx_simple_allowed = true;
2461 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2462 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2467 static int ice_init_rss(struct ice_pf *pf)
2469 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2470 struct ice_vsi *vsi = pf->main_vsi;
2471 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2472 struct rte_eth_rss_conf *rss_conf;
2473 struct ice_aqc_get_set_rss_keys key;
2476 bool is_safe_mode = pf->adapter->is_safe_mode;
2479 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2480 nb_q = dev->data->nb_rx_queues;
2481 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2482 vsi->rss_lut_size = pf->hash_lut_size;
2485 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2490 vsi->rss_key = rte_zmalloc(NULL,
2491 vsi->rss_key_size, 0);
2493 vsi->rss_lut = rte_zmalloc(NULL,
2494 vsi->rss_lut_size, 0);
2496 /* configure RSS key */
2497 if (!rss_conf->rss_key) {
2498 /* Calculate the default hash key */
2499 for (i = 0; i <= vsi->rss_key_size; i++)
2500 vsi->rss_key[i] = (uint8_t)rte_rand();
2502 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2503 RTE_MIN(rss_conf->rss_key_len,
2504 vsi->rss_key_size));
2506 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2507 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2511 /* init RSS LUT table */
2512 for (i = 0; i < vsi->rss_lut_size; i++)
2513 vsi->rss_lut[i] = i % nb_q;
2515 ret = ice_aq_set_rss_lut(hw, vsi->idx,
2516 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2517 vsi->rss_lut, vsi->rss_lut_size);
2521 /* Enable registers for symmetric_toeplitz function. */
2522 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2523 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2524 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2525 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2527 /* configure RSS for IPv4 with input set IPv4 src/dst */
2528 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2529 ICE_FLOW_SEG_HDR_IPV4, 0);
2531 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2533 /* configure RSS for IPv6 with input set IPv6 src/dst */
2534 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2535 ICE_FLOW_SEG_HDR_IPV6, 0);
2537 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2539 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2540 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2541 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2543 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2545 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2546 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2547 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2549 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2551 /* configure RSS for sctp6 with input set IPv6 src/dst */
2552 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2553 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2555 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2558 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2559 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2560 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2562 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2564 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2565 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2566 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2568 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2570 /* configure RSS for sctp4 with input set IP src/dst */
2571 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2572 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2574 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2577 /* configure RSS for gtpu with input set TEID */
2578 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2579 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2581 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2585 * configure RSS for pppoe/pppod with input set
2586 * Source MAC and Session ID
2588 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2589 ICE_FLOW_SEG_HDR_PPPOE, 0);
2591 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2598 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2599 int base_queue, int nb_queue)
2601 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2602 uint32_t val, val_tx;
2605 for (i = 0; i < nb_queue; i++) {
2607 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2608 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2609 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2610 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2612 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2613 base_queue + i, msix_vect);
2614 /* set ITR0 value */
2615 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2616 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2617 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2622 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2624 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2625 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2626 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2627 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2628 uint16_t msix_vect = vsi->msix_intr;
2629 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2630 uint16_t queue_idx = 0;
2634 /* clear Rx/Tx queue interrupt */
2635 for (i = 0; i < vsi->nb_used_qps; i++) {
2636 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2637 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2640 /* PF bind interrupt */
2641 if (rte_intr_dp_is_en(intr_handle)) {
2646 for (i = 0; i < vsi->nb_used_qps; i++) {
2648 if (!rte_intr_allow_others(intr_handle))
2649 msix_vect = ICE_MISC_VEC_ID;
2651 /* uio mapping all queue to one msix_vect */
2652 __vsi_queues_bind_intr(vsi, msix_vect,
2653 vsi->base_queue + i,
2654 vsi->nb_used_qps - i);
2656 for (; !!record && i < vsi->nb_used_qps; i++)
2657 intr_handle->intr_vec[queue_idx + i] =
2662 /* vfio 1:1 queue/msix_vect mapping */
2663 __vsi_queues_bind_intr(vsi, msix_vect,
2664 vsi->base_queue + i, 1);
2667 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2675 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2677 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2678 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2679 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2680 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2681 uint16_t msix_intr, i;
2683 if (rte_intr_allow_others(intr_handle))
2684 for (i = 0; i < vsi->nb_used_qps; i++) {
2685 msix_intr = vsi->msix_intr + i;
2686 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2687 GLINT_DYN_CTL_INTENA_M |
2688 GLINT_DYN_CTL_CLEARPBA_M |
2689 GLINT_DYN_CTL_ITR_INDX_M |
2690 GLINT_DYN_CTL_WB_ON_ITR_M);
2693 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2694 GLINT_DYN_CTL_INTENA_M |
2695 GLINT_DYN_CTL_CLEARPBA_M |
2696 GLINT_DYN_CTL_ITR_INDX_M |
2697 GLINT_DYN_CTL_WB_ON_ITR_M);
2701 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2703 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2704 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2705 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2706 struct ice_vsi *vsi = pf->main_vsi;
2707 uint32_t intr_vector = 0;
2709 rte_intr_disable(intr_handle);
2711 /* check and configure queue intr-vector mapping */
2712 if ((rte_intr_cap_multiple(intr_handle) ||
2713 !RTE_ETH_DEV_SRIOV(dev).active) &&
2714 dev->data->dev_conf.intr_conf.rxq != 0) {
2715 intr_vector = dev->data->nb_rx_queues;
2716 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2717 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2718 ICE_MAX_INTR_QUEUE_NUM);
2721 if (rte_intr_efd_enable(intr_handle, intr_vector))
2725 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2726 intr_handle->intr_vec =
2727 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2729 if (!intr_handle->intr_vec) {
2731 "Failed to allocate %d rx_queues intr_vec",
2732 dev->data->nb_rx_queues);
2737 /* Map queues with MSIX interrupt */
2738 vsi->nb_used_qps = dev->data->nb_rx_queues;
2739 ice_vsi_queues_bind_intr(vsi);
2741 /* Enable interrupts for all the queues */
2742 ice_vsi_enable_queues_intr(vsi);
2744 rte_intr_enable(intr_handle);
2750 ice_get_init_link_status(struct rte_eth_dev *dev)
2752 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2753 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2754 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2755 struct ice_link_status link_status;
2758 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
2759 &link_status, NULL);
2760 if (ret != ICE_SUCCESS) {
2761 PMD_DRV_LOG(ERR, "Failed to get link info");
2762 pf->init_link_up = false;
2766 if (link_status.link_info & ICE_AQ_LINK_UP)
2767 pf->init_link_up = true;
2771 ice_dev_start(struct rte_eth_dev *dev)
2773 struct rte_eth_dev_data *data = dev->data;
2774 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2775 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2776 struct ice_vsi *vsi = pf->main_vsi;
2777 uint16_t nb_rxq = 0;
2779 uint16_t max_frame_size;
2782 /* program Tx queues' context in hardware */
2783 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2784 ret = ice_tx_queue_start(dev, nb_txq);
2786 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2791 /* program Rx queues' context in hardware*/
2792 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2793 ret = ice_rx_queue_start(dev, nb_rxq);
2795 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2800 ret = ice_init_rss(pf);
2802 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2806 ice_set_rx_function(dev);
2807 ice_set_tx_function(dev);
2809 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2810 ETH_VLAN_EXTEND_MASK;
2811 ret = ice_vlan_offload_set(dev, mask);
2813 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2817 /* enable Rx interrput and mapping Rx queue to interrupt vector */
2818 if (ice_rxq_intr_setup(dev))
2821 /* Enable receiving broadcast packets and transmitting packets */
2822 ret = ice_set_vsi_promisc(hw, vsi->idx,
2823 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2824 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2826 if (ret != ICE_SUCCESS)
2827 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2829 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2830 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2831 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2832 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2833 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2834 ICE_AQ_LINK_EVENT_AN_COMPLETED |
2835 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2837 if (ret != ICE_SUCCESS)
2838 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2840 ice_get_init_link_status(dev);
2842 ice_dev_set_link_up(dev);
2844 /* Call get_link_info aq commond to enable/disable LSE */
2845 ice_link_update(dev, 0);
2847 pf->adapter_stopped = false;
2849 /* Set the max frame size to default value*/
2850 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2851 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2854 /* Set the max frame size to HW*/
2855 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2859 /* stop the started queues if failed to start all queues */
2861 for (i = 0; i < nb_rxq; i++)
2862 ice_rx_queue_stop(dev, i);
2864 for (i = 0; i < nb_txq; i++)
2865 ice_tx_queue_stop(dev, i);
2871 ice_dev_reset(struct rte_eth_dev *dev)
2875 if (dev->data->sriov.active)
2878 ret = ice_dev_uninit(dev);
2880 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2884 ret = ice_dev_init(dev);
2886 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2894 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2896 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2897 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2898 struct ice_vsi *vsi = pf->main_vsi;
2899 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2900 bool is_safe_mode = pf->adapter->is_safe_mode;
2904 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2905 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2906 dev_info->max_rx_queues = vsi->nb_qps;
2907 dev_info->max_tx_queues = vsi->nb_qps;
2908 dev_info->max_mac_addrs = vsi->max_macaddrs;
2909 dev_info->max_vfs = pci_dev->max_vfs;
2910 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2911 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2913 dev_info->rx_offload_capa =
2914 DEV_RX_OFFLOAD_VLAN_STRIP |
2915 DEV_RX_OFFLOAD_JUMBO_FRAME |
2916 DEV_RX_OFFLOAD_KEEP_CRC |
2917 DEV_RX_OFFLOAD_SCATTER |
2918 DEV_RX_OFFLOAD_VLAN_FILTER;
2919 dev_info->tx_offload_capa =
2920 DEV_TX_OFFLOAD_VLAN_INSERT |
2921 DEV_TX_OFFLOAD_TCP_TSO |
2922 DEV_TX_OFFLOAD_MULTI_SEGS |
2923 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2924 dev_info->flow_type_rss_offloads = 0;
2926 if (!is_safe_mode) {
2927 dev_info->rx_offload_capa |=
2928 DEV_RX_OFFLOAD_IPV4_CKSUM |
2929 DEV_RX_OFFLOAD_UDP_CKSUM |
2930 DEV_RX_OFFLOAD_TCP_CKSUM |
2931 DEV_RX_OFFLOAD_QINQ_STRIP |
2932 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2933 DEV_RX_OFFLOAD_VLAN_EXTEND |
2934 DEV_RX_OFFLOAD_RSS_HASH;
2935 dev_info->tx_offload_capa |=
2936 DEV_TX_OFFLOAD_QINQ_INSERT |
2937 DEV_TX_OFFLOAD_IPV4_CKSUM |
2938 DEV_TX_OFFLOAD_UDP_CKSUM |
2939 DEV_TX_OFFLOAD_TCP_CKSUM |
2940 DEV_TX_OFFLOAD_SCTP_CKSUM |
2941 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2942 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2943 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2946 dev_info->rx_queue_offload_capa = 0;
2947 dev_info->tx_queue_offload_capa = 0;
2949 dev_info->reta_size = pf->hash_lut_size;
2950 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2952 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2954 .pthresh = ICE_DEFAULT_RX_PTHRESH,
2955 .hthresh = ICE_DEFAULT_RX_HTHRESH,
2956 .wthresh = ICE_DEFAULT_RX_WTHRESH,
2958 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2963 dev_info->default_txconf = (struct rte_eth_txconf) {
2965 .pthresh = ICE_DEFAULT_TX_PTHRESH,
2966 .hthresh = ICE_DEFAULT_TX_HTHRESH,
2967 .wthresh = ICE_DEFAULT_TX_WTHRESH,
2969 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2970 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2974 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2975 .nb_max = ICE_MAX_RING_DESC,
2976 .nb_min = ICE_MIN_RING_DESC,
2977 .nb_align = ICE_ALIGN_RING_DESC,
2980 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2981 .nb_max = ICE_MAX_RING_DESC,
2982 .nb_min = ICE_MIN_RING_DESC,
2983 .nb_align = ICE_ALIGN_RING_DESC,
2986 dev_info->speed_capa = ETH_LINK_SPEED_10M |
2987 ETH_LINK_SPEED_100M |
2989 ETH_LINK_SPEED_2_5G |
2991 ETH_LINK_SPEED_10G |
2992 ETH_LINK_SPEED_20G |
2995 phy_type_low = hw->port_info->phy.phy_type_low;
2996 phy_type_high = hw->port_info->phy.phy_type_high;
2998 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2999 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3001 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3002 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3003 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3005 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3006 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3008 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3009 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3010 dev_info->default_rxportconf.nb_queues = 1;
3011 dev_info->default_txportconf.nb_queues = 1;
3012 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3013 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3019 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3020 struct rte_eth_link *link)
3022 struct rte_eth_link *dst = link;
3023 struct rte_eth_link *src = &dev->data->dev_link;
3025 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3026 *(uint64_t *)src) == 0)
3033 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3034 struct rte_eth_link *link)
3036 struct rte_eth_link *dst = &dev->data->dev_link;
3037 struct rte_eth_link *src = link;
3039 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3040 *(uint64_t *)src) == 0)
3047 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3049 #define CHECK_INTERVAL 100 /* 100ms */
3050 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3051 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3052 struct ice_link_status link_status;
3053 struct rte_eth_link link, old;
3055 unsigned int rep_cnt = MAX_REPEAT_TIME;
3056 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3058 memset(&link, 0, sizeof(link));
3059 memset(&old, 0, sizeof(old));
3060 memset(&link_status, 0, sizeof(link_status));
3061 ice_atomic_read_link_status(dev, &old);
3064 /* Get link status information from hardware */
3065 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3066 &link_status, NULL);
3067 if (status != ICE_SUCCESS) {
3068 link.link_speed = ETH_SPEED_NUM_100M;
3069 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3070 PMD_DRV_LOG(ERR, "Failed to get link info");
3074 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3075 if (!wait_to_complete || link.link_status)
3078 rte_delay_ms(CHECK_INTERVAL);
3079 } while (--rep_cnt);
3081 if (!link.link_status)
3084 /* Full-duplex operation at all supported speeds */
3085 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3087 /* Parse the link status */
3088 switch (link_status.link_speed) {
3089 case ICE_AQ_LINK_SPEED_10MB:
3090 link.link_speed = ETH_SPEED_NUM_10M;
3092 case ICE_AQ_LINK_SPEED_100MB:
3093 link.link_speed = ETH_SPEED_NUM_100M;
3095 case ICE_AQ_LINK_SPEED_1000MB:
3096 link.link_speed = ETH_SPEED_NUM_1G;
3098 case ICE_AQ_LINK_SPEED_2500MB:
3099 link.link_speed = ETH_SPEED_NUM_2_5G;
3101 case ICE_AQ_LINK_SPEED_5GB:
3102 link.link_speed = ETH_SPEED_NUM_5G;
3104 case ICE_AQ_LINK_SPEED_10GB:
3105 link.link_speed = ETH_SPEED_NUM_10G;
3107 case ICE_AQ_LINK_SPEED_20GB:
3108 link.link_speed = ETH_SPEED_NUM_20G;
3110 case ICE_AQ_LINK_SPEED_25GB:
3111 link.link_speed = ETH_SPEED_NUM_25G;
3113 case ICE_AQ_LINK_SPEED_40GB:
3114 link.link_speed = ETH_SPEED_NUM_40G;
3116 case ICE_AQ_LINK_SPEED_50GB:
3117 link.link_speed = ETH_SPEED_NUM_50G;
3119 case ICE_AQ_LINK_SPEED_100GB:
3120 link.link_speed = ETH_SPEED_NUM_100G;
3122 case ICE_AQ_LINK_SPEED_UNKNOWN:
3124 PMD_DRV_LOG(ERR, "Unknown link speed");
3125 link.link_speed = ETH_SPEED_NUM_NONE;
3129 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3130 ETH_LINK_SPEED_FIXED);
3133 ice_atomic_write_link_status(dev, &link);
3134 if (link.link_status == old.link_status)
3140 /* Force the physical link state by getting the current PHY capabilities from
3141 * hardware and setting the PHY config based on the determined capabilities. If
3142 * link changes, link event will be triggered because both the Enable Automatic
3143 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3145 static enum ice_status
3146 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3148 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3149 struct ice_aqc_get_phy_caps_data *pcaps;
3150 struct ice_port_info *pi;
3151 enum ice_status status;
3153 if (!hw || !hw->port_info)
3154 return ICE_ERR_PARAM;
3158 pcaps = (struct ice_aqc_get_phy_caps_data *)
3159 ice_malloc(hw, sizeof(*pcaps));
3161 return ICE_ERR_NO_MEMORY;
3163 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3168 /* No change in link */
3169 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3170 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3173 cfg.phy_type_low = pcaps->phy_type_low;
3174 cfg.phy_type_high = pcaps->phy_type_high;
3175 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3176 cfg.low_power_ctrl = pcaps->low_power_ctrl;
3177 cfg.eee_cap = pcaps->eee_cap;
3178 cfg.eeer_value = pcaps->eeer_value;
3179 cfg.link_fec_opt = pcaps->link_fec_options;
3181 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3183 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3185 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3188 ice_free(hw, pcaps);
3193 ice_dev_set_link_up(struct rte_eth_dev *dev)
3195 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3197 return ice_force_phys_link_state(hw, true);
3201 ice_dev_set_link_down(struct rte_eth_dev *dev)
3203 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3205 return ice_force_phys_link_state(hw, false);
3209 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3211 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3212 struct rte_eth_dev_data *dev_data = pf->dev_data;
3213 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3215 /* check if mtu is within the allowed range */
3216 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3219 /* mtu setting is forbidden if port is start */
3220 if (dev_data->dev_started) {
3222 "port %d must be stopped before configuration",
3227 if (frame_size > RTE_ETHER_MAX_LEN)
3228 dev_data->dev_conf.rxmode.offloads |=
3229 DEV_RX_OFFLOAD_JUMBO_FRAME;
3231 dev_data->dev_conf.rxmode.offloads &=
3232 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3234 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3239 static int ice_macaddr_set(struct rte_eth_dev *dev,
3240 struct rte_ether_addr *mac_addr)
3242 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3243 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3244 struct ice_vsi *vsi = pf->main_vsi;
3245 struct ice_mac_filter *f;
3249 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3250 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3254 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3255 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3260 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3264 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3265 if (ret != ICE_SUCCESS) {
3266 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3269 ret = ice_add_mac_filter(vsi, mac_addr);
3270 if (ret != ICE_SUCCESS) {
3271 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3274 rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3276 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3277 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3278 if (ret != ICE_SUCCESS)
3279 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3284 /* Add a MAC address, and update filters */
3286 ice_macaddr_add(struct rte_eth_dev *dev,
3287 struct rte_ether_addr *mac_addr,
3288 __rte_unused uint32_t index,
3289 __rte_unused uint32_t pool)
3291 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3292 struct ice_vsi *vsi = pf->main_vsi;
3295 ret = ice_add_mac_filter(vsi, mac_addr);
3296 if (ret != ICE_SUCCESS) {
3297 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3304 /* Remove a MAC address, and update filters */
3306 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3308 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3309 struct ice_vsi *vsi = pf->main_vsi;
3310 struct rte_eth_dev_data *data = dev->data;
3311 struct rte_ether_addr *macaddr;
3314 macaddr = &data->mac_addrs[index];
3315 ret = ice_remove_mac_filter(vsi, macaddr);
3317 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3323 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3325 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3326 struct ice_vsi *vsi = pf->main_vsi;
3329 PMD_INIT_FUNC_TRACE();
3332 ret = ice_add_vlan_filter(vsi, vlan_id);
3334 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3338 ret = ice_remove_vlan_filter(vsi, vlan_id);
3340 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3348 /* Configure vlan filter on or off */
3350 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3352 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3353 struct ice_vsi_ctx ctxt;
3354 uint8_t sec_flags, sw_flags2;
3357 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3358 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3359 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3362 vsi->info.sec_flags |= sec_flags;
3363 vsi->info.sw_flags2 |= sw_flags2;
3365 vsi->info.sec_flags &= ~sec_flags;
3366 vsi->info.sw_flags2 &= ~sw_flags2;
3368 vsi->info.sw_id = hw->port_info->sw_id;
3369 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3370 ctxt.info.valid_sections =
3371 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3372 ICE_AQ_VSI_PROP_SECURITY_VALID);
3373 ctxt.vsi_num = vsi->vsi_id;
3375 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3377 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3378 on ? "enable" : "disable");
3381 vsi->info.valid_sections |=
3382 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3383 ICE_AQ_VSI_PROP_SECURITY_VALID);
3386 /* consist with other drivers, allow untagged packet when vlan filter on */
3388 ret = ice_add_vlan_filter(vsi, 0);
3390 ret = ice_remove_vlan_filter(vsi, 0);
3396 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3398 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3399 struct ice_vsi_ctx ctxt;
3403 /* Check if it has been already on or off */
3404 if (vsi->info.valid_sections &
3405 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3407 if ((vsi->info.vlan_flags &
3408 ICE_AQ_VSI_VLAN_EMOD_M) ==
3409 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3410 return 0; /* already on */
3412 if ((vsi->info.vlan_flags &
3413 ICE_AQ_VSI_VLAN_EMOD_M) ==
3414 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3415 return 0; /* already off */
3420 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3422 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3423 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3424 vsi->info.vlan_flags |= vlan_flags;
3425 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3426 ctxt.info.valid_sections =
3427 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3428 ctxt.vsi_num = vsi->vsi_id;
3429 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3431 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3432 on ? "enable" : "disable");
3436 vsi->info.valid_sections |=
3437 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3443 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3445 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3446 struct ice_vsi *vsi = pf->main_vsi;
3447 struct rte_eth_rxmode *rxmode;
3449 rxmode = &dev->data->dev_conf.rxmode;
3450 if (mask & ETH_VLAN_FILTER_MASK) {
3451 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3452 ice_vsi_config_vlan_filter(vsi, true);
3454 ice_vsi_config_vlan_filter(vsi, false);
3457 if (mask & ETH_VLAN_STRIP_MASK) {
3458 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3459 ice_vsi_config_vlan_stripping(vsi, true);
3461 ice_vsi_config_vlan_stripping(vsi, false);
3464 if (mask & ETH_VLAN_EXTEND_MASK) {
3465 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3466 ice_vsi_config_double_vlan(vsi, true);
3468 ice_vsi_config_double_vlan(vsi, false);
3475 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3477 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3478 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3484 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3485 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3486 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3488 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3492 uint64_t *lut_dw = (uint64_t *)lut;
3493 uint16_t i, lut_size_dw = lut_size / 4;
3495 for (i = 0; i < lut_size_dw; i++)
3496 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3503 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3512 pf = ICE_VSI_TO_PF(vsi);
3513 hw = ICE_VSI_TO_HW(vsi);
3515 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3516 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3517 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3519 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3523 uint64_t *lut_dw = (uint64_t *)lut;
3524 uint16_t i, lut_size_dw = lut_size / 4;
3526 for (i = 0; i < lut_size_dw; i++)
3527 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3536 ice_rss_reta_update(struct rte_eth_dev *dev,
3537 struct rte_eth_rss_reta_entry64 *reta_conf,
3540 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3541 uint16_t i, lut_size = pf->hash_lut_size;
3542 uint16_t idx, shift;
3546 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3547 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3548 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3550 "The size of hash lookup table configured (%d)"
3551 "doesn't match the number hardware can "
3552 "supported (128, 512, 2048)",
3557 /* It MUST use the current LUT size to get the RSS lookup table,
3558 * otherwise if will fail with -100 error code.
3560 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
3562 PMD_DRV_LOG(ERR, "No memory can be allocated");
3565 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3569 for (i = 0; i < reta_size; i++) {
3570 idx = i / RTE_RETA_GROUP_SIZE;
3571 shift = i % RTE_RETA_GROUP_SIZE;
3572 if (reta_conf[idx].mask & (1ULL << shift))
3573 lut[i] = reta_conf[idx].reta[shift];
3575 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3576 if (ret == 0 && lut_size != reta_size) {
3578 "The size of hash lookup table is changed from (%d) to (%d)",
3579 lut_size, reta_size);
3580 pf->hash_lut_size = reta_size;
3590 ice_rss_reta_query(struct rte_eth_dev *dev,
3591 struct rte_eth_rss_reta_entry64 *reta_conf,
3594 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3595 uint16_t i, lut_size = pf->hash_lut_size;
3596 uint16_t idx, shift;
3600 if (reta_size != lut_size) {
3602 "The size of hash lookup table configured (%d)"
3603 "doesn't match the number hardware can "
3605 reta_size, lut_size);
3609 lut = rte_zmalloc(NULL, reta_size, 0);
3611 PMD_DRV_LOG(ERR, "No memory can be allocated");
3615 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3619 for (i = 0; i < reta_size; i++) {
3620 idx = i / RTE_RETA_GROUP_SIZE;
3621 shift = i % RTE_RETA_GROUP_SIZE;
3622 if (reta_conf[idx].mask & (1ULL << shift))
3623 reta_conf[idx].reta[shift] = lut[i];
3633 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3635 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3638 if (!key || key_len == 0) {
3639 PMD_DRV_LOG(DEBUG, "No key to be configured");
3641 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3643 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3647 struct ice_aqc_get_set_rss_keys *key_dw =
3648 (struct ice_aqc_get_set_rss_keys *)key;
3650 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3652 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3660 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3662 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3665 if (!key || !key_len)
3668 ret = ice_aq_get_rss_key
3670 (struct ice_aqc_get_set_rss_keys *)key);
3672 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3675 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3681 ice_rss_hash_update(struct rte_eth_dev *dev,
3682 struct rte_eth_rss_conf *rss_conf)
3684 enum ice_status status = ICE_SUCCESS;
3685 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3686 struct ice_vsi *vsi = pf->main_vsi;
3689 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3693 /* TODO: hash enable config, ice_add_rss_cfg */
3698 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3699 struct rte_eth_rss_conf *rss_conf)
3701 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3702 struct ice_vsi *vsi = pf->main_vsi;
3704 ice_get_rss_key(vsi, rss_conf->rss_key,
3705 &rss_conf->rss_key_len);
3707 /* TODO: default set to 0 as hf config is not supported now */
3708 rss_conf->rss_hf = 0;
3713 ice_promisc_enable(struct rte_eth_dev *dev)
3715 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3716 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3717 struct ice_vsi *vsi = pf->main_vsi;
3718 enum ice_status status;
3722 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3723 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3725 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3727 case ICE_ERR_ALREADY_EXISTS:
3728 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3732 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3740 ice_promisc_disable(struct rte_eth_dev *dev)
3742 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3743 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3744 struct ice_vsi *vsi = pf->main_vsi;
3745 enum ice_status status;
3749 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3750 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3752 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3753 if (status != ICE_SUCCESS) {
3754 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3762 ice_allmulti_enable(struct rte_eth_dev *dev)
3764 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3765 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3766 struct ice_vsi *vsi = pf->main_vsi;
3767 enum ice_status status;
3771 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3773 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3776 case ICE_ERR_ALREADY_EXISTS:
3777 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3781 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3789 ice_allmulti_disable(struct rte_eth_dev *dev)
3791 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3792 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3793 struct ice_vsi *vsi = pf->main_vsi;
3794 enum ice_status status;
3798 if (dev->data->promiscuous == 1)
3799 return 0; /* must remain in all_multicast mode */
3801 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3803 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3804 if (status != ICE_SUCCESS) {
3805 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3812 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3815 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3816 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3817 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3821 msix_intr = intr_handle->intr_vec[queue_id];
3823 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3824 GLINT_DYN_CTL_ITR_INDX_M;
3825 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3827 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3828 rte_intr_ack(&pci_dev->intr_handle);
3833 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3836 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3837 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3838 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3841 msix_intr = intr_handle->intr_vec[queue_id];
3843 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3849 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3851 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3857 full_ver = hw->nvm.oem_ver;
3858 ver = (u8)(full_ver >> 24);
3859 build = (u16)((full_ver >> 8) & 0xffff);
3860 patch = (u8)(full_ver & 0xff);
3862 ret = snprintf(fw_version, fw_size,
3863 "%d.%d%d 0x%08x %d.%d.%d",
3864 ((hw->nvm.ver >> 12) & 0xf),
3865 ((hw->nvm.ver >> 4) & 0xff),
3866 (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3869 /* add the size of '\0' */
3871 if (fw_size < (u32)ret)
3878 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3881 struct ice_vsi_ctx ctxt;
3882 uint8_t vlan_flags = 0;
3885 if (!vsi || !info) {
3886 PMD_DRV_LOG(ERR, "invalid parameters");
3891 vsi->info.pvid = info->config.pvid;
3893 * If insert pvid is enabled, only tagged pkts are
3894 * allowed to be sent out.
3896 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3897 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3900 if (info->config.reject.tagged == 0)
3901 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3903 if (info->config.reject.untagged == 0)
3904 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3906 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3907 ICE_AQ_VSI_VLAN_MODE_M);
3908 vsi->info.vlan_flags |= vlan_flags;
3909 memset(&ctxt, 0, sizeof(ctxt));
3910 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3911 ctxt.info.valid_sections =
3912 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3913 ctxt.vsi_num = vsi->vsi_id;
3915 hw = ICE_VSI_TO_HW(vsi);
3916 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3917 if (ret != ICE_SUCCESS) {
3919 "update VSI for VLAN insert failed, err %d",
3924 vsi->info.valid_sections |=
3925 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3931 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3933 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3934 struct ice_vsi *vsi = pf->main_vsi;
3935 struct rte_eth_dev_data *data = pf->dev_data;
3936 struct ice_vsi_vlan_pvid_info info;
3939 memset(&info, 0, sizeof(info));
3942 info.config.pvid = pvid;
3944 info.config.reject.tagged =
3945 data->dev_conf.txmode.hw_vlan_reject_tagged;
3946 info.config.reject.untagged =
3947 data->dev_conf.txmode.hw_vlan_reject_untagged;
3950 ret = ice_vsi_vlan_pvid_set(vsi, &info);
3952 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3960 ice_get_eeprom_length(struct rte_eth_dev *dev)
3962 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3964 /* Convert word count to byte count */
3965 return hw->nvm.sr_words << 1;
3969 ice_get_eeprom(struct rte_eth_dev *dev,
3970 struct rte_dev_eeprom_info *eeprom)
3972 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3973 uint16_t *data = eeprom->data;
3974 uint16_t first_word, last_word, nwords;
3975 enum ice_status status = ICE_SUCCESS;
3977 first_word = eeprom->offset >> 1;
3978 last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3979 nwords = last_word - first_word + 1;
3981 if (first_word >= hw->nvm.sr_words ||
3982 last_word >= hw->nvm.sr_words) {
3983 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3987 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3989 status = ice_read_sr_buf(hw, first_word, &nwords, data);
3991 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3992 eeprom->length = sizeof(uint16_t) * nwords;
4000 ice_stat_update_32(struct ice_hw *hw,
4008 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4012 if (new_data >= *offset)
4013 *stat = (uint64_t)(new_data - *offset);
4015 *stat = (uint64_t)((new_data +
4016 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4021 ice_stat_update_40(struct ice_hw *hw,
4030 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4031 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4037 if (new_data >= *offset)
4038 *stat = new_data - *offset;
4040 *stat = (uint64_t)((new_data +
4041 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4044 *stat &= ICE_40_BIT_MASK;
4047 /* Get all the statistics of a VSI */
4049 ice_update_vsi_stats(struct ice_vsi *vsi)
4051 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4052 struct ice_eth_stats *nes = &vsi->eth_stats;
4053 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4054 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4056 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4057 vsi->offset_loaded, &oes->rx_bytes,
4059 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4060 vsi->offset_loaded, &oes->rx_unicast,
4062 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4063 vsi->offset_loaded, &oes->rx_multicast,
4064 &nes->rx_multicast);
4065 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4066 vsi->offset_loaded, &oes->rx_broadcast,
4067 &nes->rx_broadcast);
4068 /* exclude CRC bytes */
4069 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4070 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4072 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4073 &oes->rx_discards, &nes->rx_discards);
4074 /* GLV_REPC not supported */
4075 /* GLV_RMPC not supported */
4076 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4077 &oes->rx_unknown_protocol,
4078 &nes->rx_unknown_protocol);
4079 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4080 vsi->offset_loaded, &oes->tx_bytes,
4082 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4083 vsi->offset_loaded, &oes->tx_unicast,
4085 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4086 vsi->offset_loaded, &oes->tx_multicast,
4087 &nes->tx_multicast);
4088 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4089 vsi->offset_loaded, &oes->tx_broadcast,
4090 &nes->tx_broadcast);
4091 /* GLV_TDPC not supported */
4092 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4093 &oes->tx_errors, &nes->tx_errors);
4094 vsi->offset_loaded = true;
4096 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4098 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4099 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4100 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4101 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4102 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4103 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4104 nes->rx_unknown_protocol);
4105 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4106 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4107 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4108 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4109 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4110 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4111 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4116 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4118 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4119 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4121 /* Get statistics of struct ice_eth_stats */
4122 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4123 GLPRT_GORCL(hw->port_info->lport),
4124 pf->offset_loaded, &os->eth.rx_bytes,
4126 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4127 GLPRT_UPRCL(hw->port_info->lport),
4128 pf->offset_loaded, &os->eth.rx_unicast,
4129 &ns->eth.rx_unicast);
4130 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4131 GLPRT_MPRCL(hw->port_info->lport),
4132 pf->offset_loaded, &os->eth.rx_multicast,
4133 &ns->eth.rx_multicast);
4134 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4135 GLPRT_BPRCL(hw->port_info->lport),
4136 pf->offset_loaded, &os->eth.rx_broadcast,
4137 &ns->eth.rx_broadcast);
4138 ice_stat_update_32(hw, PRTRPB_RDPC,
4139 pf->offset_loaded, &os->eth.rx_discards,
4140 &ns->eth.rx_discards);
4142 /* Workaround: CRC size should not be included in byte statistics,
4143 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4146 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4147 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4149 /* GLPRT_REPC not supported */
4150 /* GLPRT_RMPC not supported */
4151 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4153 &os->eth.rx_unknown_protocol,
4154 &ns->eth.rx_unknown_protocol);
4155 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4156 GLPRT_GOTCL(hw->port_info->lport),
4157 pf->offset_loaded, &os->eth.tx_bytes,
4159 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4160 GLPRT_UPTCL(hw->port_info->lport),
4161 pf->offset_loaded, &os->eth.tx_unicast,
4162 &ns->eth.tx_unicast);
4163 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4164 GLPRT_MPTCL(hw->port_info->lport),
4165 pf->offset_loaded, &os->eth.tx_multicast,
4166 &ns->eth.tx_multicast);
4167 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4168 GLPRT_BPTCL(hw->port_info->lport),
4169 pf->offset_loaded, &os->eth.tx_broadcast,
4170 &ns->eth.tx_broadcast);
4171 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4172 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4174 /* GLPRT_TEPC not supported */
4176 /* additional port specific stats */
4177 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4178 pf->offset_loaded, &os->tx_dropped_link_down,
4179 &ns->tx_dropped_link_down);
4180 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4181 pf->offset_loaded, &os->crc_errors,
4183 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4184 pf->offset_loaded, &os->illegal_bytes,
4185 &ns->illegal_bytes);
4186 /* GLPRT_ERRBC not supported */
4187 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4188 pf->offset_loaded, &os->mac_local_faults,
4189 &ns->mac_local_faults);
4190 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4191 pf->offset_loaded, &os->mac_remote_faults,
4192 &ns->mac_remote_faults);
4194 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4195 pf->offset_loaded, &os->rx_len_errors,
4196 &ns->rx_len_errors);
4198 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4199 pf->offset_loaded, &os->link_xon_rx,
4201 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4202 pf->offset_loaded, &os->link_xoff_rx,
4204 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4205 pf->offset_loaded, &os->link_xon_tx,
4207 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4208 pf->offset_loaded, &os->link_xoff_tx,
4210 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4211 GLPRT_PRC64L(hw->port_info->lport),
4212 pf->offset_loaded, &os->rx_size_64,
4214 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4215 GLPRT_PRC127L(hw->port_info->lport),
4216 pf->offset_loaded, &os->rx_size_127,
4218 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4219 GLPRT_PRC255L(hw->port_info->lport),
4220 pf->offset_loaded, &os->rx_size_255,
4222 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4223 GLPRT_PRC511L(hw->port_info->lport),
4224 pf->offset_loaded, &os->rx_size_511,
4226 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4227 GLPRT_PRC1023L(hw->port_info->lport),
4228 pf->offset_loaded, &os->rx_size_1023,
4230 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4231 GLPRT_PRC1522L(hw->port_info->lport),
4232 pf->offset_loaded, &os->rx_size_1522,
4234 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4235 GLPRT_PRC9522L(hw->port_info->lport),
4236 pf->offset_loaded, &os->rx_size_big,
4238 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4239 pf->offset_loaded, &os->rx_undersize,
4241 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4242 pf->offset_loaded, &os->rx_fragments,
4244 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4245 pf->offset_loaded, &os->rx_oversize,
4247 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4248 pf->offset_loaded, &os->rx_jabber,
4250 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4251 GLPRT_PTC64L(hw->port_info->lport),
4252 pf->offset_loaded, &os->tx_size_64,
4254 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4255 GLPRT_PTC127L(hw->port_info->lport),
4256 pf->offset_loaded, &os->tx_size_127,
4258 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4259 GLPRT_PTC255L(hw->port_info->lport),
4260 pf->offset_loaded, &os->tx_size_255,
4262 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4263 GLPRT_PTC511L(hw->port_info->lport),
4264 pf->offset_loaded, &os->tx_size_511,
4266 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4267 GLPRT_PTC1023L(hw->port_info->lport),
4268 pf->offset_loaded, &os->tx_size_1023,
4270 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4271 GLPRT_PTC1522L(hw->port_info->lport),
4272 pf->offset_loaded, &os->tx_size_1522,
4274 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4275 GLPRT_PTC9522L(hw->port_info->lport),
4276 pf->offset_loaded, &os->tx_size_big,
4279 /* GLPRT_MSPDC not supported */
4280 /* GLPRT_XEC not supported */
4282 pf->offset_loaded = true;
4285 ice_update_vsi_stats(pf->main_vsi);
4288 /* Get all statistics of a port */
4290 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4292 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4293 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4294 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4296 /* call read registers - updates values, now write them to struct */
4297 ice_read_stats_registers(pf, hw);
4299 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4300 pf->main_vsi->eth_stats.rx_multicast +
4301 pf->main_vsi->eth_stats.rx_broadcast -
4302 pf->main_vsi->eth_stats.rx_discards;
4303 stats->opackets = ns->eth.tx_unicast +
4304 ns->eth.tx_multicast +
4305 ns->eth.tx_broadcast;
4306 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
4307 stats->obytes = ns->eth.tx_bytes;
4308 stats->oerrors = ns->eth.tx_errors +
4309 pf->main_vsi->eth_stats.tx_errors;
4312 stats->imissed = ns->eth.rx_discards +
4313 pf->main_vsi->eth_stats.rx_discards;
4314 stats->ierrors = ns->crc_errors +
4316 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4318 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4319 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
4320 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4321 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4322 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4323 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4324 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4325 pf->main_vsi->eth_stats.rx_discards);
4326 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4327 ns->eth.rx_unknown_protocol);
4328 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
4329 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4330 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4331 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4332 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4333 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4334 pf->main_vsi->eth_stats.tx_discards);
4335 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
4337 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
4338 ns->tx_dropped_link_down);
4339 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4340 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
4342 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
4343 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
4344 ns->mac_local_faults);
4345 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
4346 ns->mac_remote_faults);
4347 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
4348 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
4349 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
4350 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
4351 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
4352 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
4353 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
4354 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
4355 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
4356 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
4357 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
4358 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
4359 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
4360 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
4361 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
4362 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
4363 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
4364 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
4365 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
4366 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
4367 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
4368 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
4369 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
4370 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4374 /* Reset the statistics */
4376 ice_stats_reset(struct rte_eth_dev *dev)
4378 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4379 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4381 /* Mark PF and VSI stats to update the offset, aka "reset" */
4382 pf->offset_loaded = false;
4384 pf->main_vsi->offset_loaded = false;
4386 /* read the stats, reading current register values into offset */
4387 ice_read_stats_registers(pf, hw);
4393 ice_xstats_calc_num(void)
4397 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4403 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4406 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4407 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4410 struct ice_hw_port_stats *hw_stats = &pf->stats;
4412 count = ice_xstats_calc_num();
4416 ice_read_stats_registers(pf, hw);
4423 /* Get stats from ice_eth_stats struct */
4424 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4425 xstats[count].value =
4426 *(uint64_t *)((char *)&hw_stats->eth +
4427 ice_stats_strings[i].offset);
4428 xstats[count].id = count;
4432 /* Get individiual stats from ice_hw_port struct */
4433 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4434 xstats[count].value =
4435 *(uint64_t *)((char *)hw_stats +
4436 ice_hw_port_strings[i].offset);
4437 xstats[count].id = count;
4444 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4445 struct rte_eth_xstat_name *xstats_names,
4446 __rte_unused unsigned int limit)
4448 unsigned int count = 0;
4452 return ice_xstats_calc_num();
4454 /* Note: limit checked in rte_eth_xstats_names() */
4456 /* Get stats from ice_eth_stats struct */
4457 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4458 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4459 sizeof(xstats_names[count].name));
4463 /* Get individiual stats from ice_hw_port struct */
4464 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4465 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4466 sizeof(xstats_names[count].name));
4474 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4475 enum rte_filter_type filter_type,
4476 enum rte_filter_op filter_op,
4484 switch (filter_type) {
4485 case RTE_ETH_FILTER_GENERIC:
4486 if (filter_op != RTE_ETH_FILTER_GET)
4488 *(const void **)arg = &ice_flow_ops;
4491 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4500 /* Add UDP tunneling port */
4502 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4503 struct rte_eth_udp_tunnel *udp_tunnel)
4506 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4508 if (udp_tunnel == NULL)
4511 switch (udp_tunnel->prot_type) {
4512 case RTE_TUNNEL_TYPE_VXLAN:
4513 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4516 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4524 /* Delete UDP tunneling port */
4526 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4527 struct rte_eth_udp_tunnel *udp_tunnel)
4530 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4532 if (udp_tunnel == NULL)
4535 switch (udp_tunnel->prot_type) {
4536 case RTE_TUNNEL_TYPE_VXLAN:
4537 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4540 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4549 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4550 struct rte_pci_device *pci_dev)
4552 return rte_eth_dev_pci_generic_probe(pci_dev,
4553 sizeof(struct ice_adapter),
4558 ice_pci_remove(struct rte_pci_device *pci_dev)
4560 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4563 static struct rte_pci_driver rte_ice_pmd = {
4564 .id_table = pci_id_ice_map,
4565 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4566 .probe = ice_pci_probe,
4567 .remove = ice_pci_remove,
4571 * Driver initialization routine.
4572 * Invoked once at EAL init time.
4573 * Register itself as the [Poll Mode] Driver of PCI devices.
4575 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4576 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4577 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4578 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4579 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4580 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4581 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
4582 ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
4584 RTE_INIT(ice_init_log)
4586 ice_logtype_init = rte_log_register("pmd.net.ice.init");
4587 if (ice_logtype_init >= 0)
4588 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4589 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4590 if (ice_logtype_driver >= 0)
4591 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4593 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4594 ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4595 if (ice_logtype_rx >= 0)
4596 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4599 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4600 ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4601 if (ice_logtype_tx >= 0)
4602 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4605 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4606 ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4607 if (ice_logtype_tx_free >= 0)
4608 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);