1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
18 #include "rte_pmd_ice.h"
19 #include "ice_ethdev.h"
21 #include "ice_generic_flow.h"
24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
26 #define ICE_PROTO_XTR_ARG "proto_xtr"
28 static const char * const ice_valid_args[] = {
29 ICE_SAFE_MODE_SUPPORT_ARG,
30 ICE_PIPELINE_MODE_SUPPORT_ARG,
35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
36 .name = "intel_pmd_dynfield_proto_xtr_metadata",
37 .size = sizeof(uint32_t),
38 .align = __alignof__(uint32_t),
42 struct proto_xtr_ol_flag {
43 const struct rte_mbuf_dynflag param;
48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
52 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
55 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
58 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
60 [PROTO_XTR_IPV6_FLOW] = {
61 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
64 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
66 [PROTO_XTR_IP_OFFSET] = {
67 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
68 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
71 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
72 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
73 #define ICE_MAX_RES_DESC_NUM 1024
75 static int ice_dev_configure(struct rte_eth_dev *dev);
76 static int ice_dev_start(struct rte_eth_dev *dev);
77 static int ice_dev_stop(struct rte_eth_dev *dev);
78 static int ice_dev_close(struct rte_eth_dev *dev);
79 static int ice_dev_reset(struct rte_eth_dev *dev);
80 static int ice_dev_info_get(struct rte_eth_dev *dev,
81 struct rte_eth_dev_info *dev_info);
82 static int ice_link_update(struct rte_eth_dev *dev,
83 int wait_to_complete);
84 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
85 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
87 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
88 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
89 static int ice_rss_reta_update(struct rte_eth_dev *dev,
90 struct rte_eth_rss_reta_entry64 *reta_conf,
92 static int ice_rss_reta_query(struct rte_eth_dev *dev,
93 struct rte_eth_rss_reta_entry64 *reta_conf,
95 static int ice_rss_hash_update(struct rte_eth_dev *dev,
96 struct rte_eth_rss_conf *rss_conf);
97 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
98 struct rte_eth_rss_conf *rss_conf);
99 static int ice_promisc_enable(struct rte_eth_dev *dev);
100 static int ice_promisc_disable(struct rte_eth_dev *dev);
101 static int ice_allmulti_enable(struct rte_eth_dev *dev);
102 static int ice_allmulti_disable(struct rte_eth_dev *dev);
103 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
106 static int ice_macaddr_set(struct rte_eth_dev *dev,
107 struct rte_ether_addr *mac_addr);
108 static int ice_macaddr_add(struct rte_eth_dev *dev,
109 struct rte_ether_addr *mac_addr,
110 __rte_unused uint32_t index,
112 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
113 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
115 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
117 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
119 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
120 uint16_t pvid, int on);
121 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
122 static int ice_get_eeprom(struct rte_eth_dev *dev,
123 struct rte_dev_eeprom_info *eeprom);
124 static int ice_stats_get(struct rte_eth_dev *dev,
125 struct rte_eth_stats *stats);
126 static int ice_stats_reset(struct rte_eth_dev *dev);
127 static int ice_xstats_get(struct rte_eth_dev *dev,
128 struct rte_eth_xstat *xstats, unsigned int n);
129 static int ice_xstats_get_names(struct rte_eth_dev *dev,
130 struct rte_eth_xstat_name *xstats_names,
132 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
133 enum rte_filter_type filter_type,
134 enum rte_filter_op filter_op,
136 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
137 struct rte_eth_udp_tunnel *udp_tunnel);
138 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
139 struct rte_eth_udp_tunnel *udp_tunnel);
141 static const struct rte_pci_id pci_id_ice_map[] = {
142 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
143 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
144 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
145 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
146 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
147 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
148 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
149 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
150 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
157 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
159 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
164 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
165 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
166 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
167 { .vendor_id = 0, /* sentinel */ },
170 static const struct eth_dev_ops ice_eth_dev_ops = {
171 .dev_configure = ice_dev_configure,
172 .dev_start = ice_dev_start,
173 .dev_stop = ice_dev_stop,
174 .dev_close = ice_dev_close,
175 .dev_reset = ice_dev_reset,
176 .dev_set_link_up = ice_dev_set_link_up,
177 .dev_set_link_down = ice_dev_set_link_down,
178 .rx_queue_start = ice_rx_queue_start,
179 .rx_queue_stop = ice_rx_queue_stop,
180 .tx_queue_start = ice_tx_queue_start,
181 .tx_queue_stop = ice_tx_queue_stop,
182 .rx_queue_setup = ice_rx_queue_setup,
183 .rx_queue_release = ice_rx_queue_release,
184 .tx_queue_setup = ice_tx_queue_setup,
185 .tx_queue_release = ice_tx_queue_release,
186 .dev_infos_get = ice_dev_info_get,
187 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
188 .link_update = ice_link_update,
189 .mtu_set = ice_mtu_set,
190 .mac_addr_set = ice_macaddr_set,
191 .mac_addr_add = ice_macaddr_add,
192 .mac_addr_remove = ice_macaddr_remove,
193 .vlan_filter_set = ice_vlan_filter_set,
194 .vlan_offload_set = ice_vlan_offload_set,
195 .reta_update = ice_rss_reta_update,
196 .reta_query = ice_rss_reta_query,
197 .rss_hash_update = ice_rss_hash_update,
198 .rss_hash_conf_get = ice_rss_hash_conf_get,
199 .promiscuous_enable = ice_promisc_enable,
200 .promiscuous_disable = ice_promisc_disable,
201 .allmulticast_enable = ice_allmulti_enable,
202 .allmulticast_disable = ice_allmulti_disable,
203 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
204 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
205 .fw_version_get = ice_fw_version_get,
206 .vlan_pvid_set = ice_vlan_pvid_set,
207 .rxq_info_get = ice_rxq_info_get,
208 .txq_info_get = ice_txq_info_get,
209 .rx_burst_mode_get = ice_rx_burst_mode_get,
210 .tx_burst_mode_get = ice_tx_burst_mode_get,
211 .get_eeprom_length = ice_get_eeprom_length,
212 .get_eeprom = ice_get_eeprom,
213 .stats_get = ice_stats_get,
214 .stats_reset = ice_stats_reset,
215 .xstats_get = ice_xstats_get,
216 .xstats_get_names = ice_xstats_get_names,
217 .xstats_reset = ice_stats_reset,
218 .filter_ctrl = ice_dev_filter_ctrl,
219 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
220 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
221 .tx_done_cleanup = ice_tx_done_cleanup,
222 .get_monitor_addr = ice_get_monitor_addr,
225 /* store statistics names and its offset in stats structure */
226 struct ice_xstats_name_off {
227 char name[RTE_ETH_XSTATS_NAME_SIZE];
231 static const struct ice_xstats_name_off ice_stats_strings[] = {
232 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
233 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
234 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
235 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
236 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
237 rx_unknown_protocol)},
238 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
239 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
240 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
241 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
244 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
245 sizeof(ice_stats_strings[0]))
247 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
248 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
249 tx_dropped_link_down)},
250 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
251 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
253 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
254 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
256 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
258 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
260 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
261 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
262 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
263 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
264 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
265 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
267 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
269 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
271 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
273 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
275 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
277 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
279 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
281 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
282 mac_short_pkt_dropped)},
283 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
285 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
286 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
287 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
289 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
291 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
293 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
295 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
297 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
301 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
302 sizeof(ice_hw_port_strings[0]))
305 ice_init_controlq_parameter(struct ice_hw *hw)
307 /* fields for adminq */
308 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
309 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
310 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
311 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
313 /* fields for mailboxq, DPDK used as PF host */
314 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
315 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
316 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
317 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
321 lookup_proto_xtr_type(const char *xtr_name)
325 enum proto_xtr_type type;
327 { "vlan", PROTO_XTR_VLAN },
328 { "ipv4", PROTO_XTR_IPV4 },
329 { "ipv6", PROTO_XTR_IPV6 },
330 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
331 { "tcp", PROTO_XTR_TCP },
332 { "ip_offset", PROTO_XTR_IP_OFFSET },
336 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
337 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
338 return xtr_type_map[i].type;
345 * Parse elem, the elem could be single number/range or '(' ')' group
346 * 1) A single number elem, it's just a simple digit. e.g. 9
347 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
348 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
349 * Within group elem, '-' used for a range separator;
350 * ',' used for a single number.
353 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
355 const char *str = input;
360 while (isblank(*str))
363 if (!isdigit(*str) && *str != '(')
366 /* process single number or single range of number */
369 idx = strtoul(str, &end, 10);
370 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
373 while (isblank(*end))
379 /* process single <number>-<number> */
382 while (isblank(*end))
388 idx = strtoul(end, &end, 10);
389 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
393 while (isblank(*end))
400 for (idx = RTE_MIN(min, max);
401 idx <= RTE_MAX(min, max); idx++)
402 devargs->proto_xtr[idx] = xtr_type;
407 /* process set within bracket */
409 while (isblank(*str))
414 min = ICE_MAX_QUEUE_NUM;
416 /* go ahead to the first digit */
417 while (isblank(*str))
422 /* get the digit value */
424 idx = strtoul(str, &end, 10);
425 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
428 /* go ahead to separator '-',',' and ')' */
429 while (isblank(*end))
432 if (min == ICE_MAX_QUEUE_NUM)
434 else /* avoid continuous '-' */
436 } else if (*end == ',' || *end == ')') {
438 if (min == ICE_MAX_QUEUE_NUM)
441 for (idx = RTE_MIN(min, max);
442 idx <= RTE_MAX(min, max); idx++)
443 devargs->proto_xtr[idx] = xtr_type;
445 min = ICE_MAX_QUEUE_NUM;
451 } while (*end != ')' && *end != '\0');
457 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
459 const char *queue_start;
464 while (isblank(*queues))
467 if (*queues != '[') {
468 xtr_type = lookup_proto_xtr_type(queues);
472 devargs->proto_xtr_dflt = xtr_type;
479 while (isblank(*queues))
484 queue_start = queues;
486 /* go across a complete bracket */
487 if (*queue_start == '(') {
488 queues += strcspn(queues, ")");
493 /* scan the separator ':' */
494 queues += strcspn(queues, ":");
495 if (*queues++ != ':')
497 while (isblank(*queues))
500 for (idx = 0; ; idx++) {
501 if (isblank(queues[idx]) ||
502 queues[idx] == ',' ||
503 queues[idx] == ']' ||
507 if (idx > sizeof(xtr_name) - 2)
510 xtr_name[idx] = queues[idx];
512 xtr_name[idx] = '\0';
513 xtr_type = lookup_proto_xtr_type(xtr_name);
519 while (isblank(*queues) || *queues == ',' || *queues == ']')
522 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
524 } while (*queues != '\0');
530 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
533 struct ice_devargs *devargs = extra_args;
535 if (value == NULL || extra_args == NULL)
538 if (parse_queue_proto_xtr(value, devargs) < 0) {
540 "The protocol extraction parameter is wrong : '%s'",
549 ice_check_proto_xtr_support(struct ice_hw *hw)
551 #define FLX_REG(val, fld, idx) \
552 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
553 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
560 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
562 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
563 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
565 ICE_PROT_IPV4_OF_OR_S,
566 ICE_PROT_IPV4_OF_OR_S },
567 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
569 ICE_PROT_IPV6_OF_OR_S,
570 ICE_PROT_IPV6_OF_OR_S },
571 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
573 ICE_PROT_IPV6_OF_OR_S,
574 ICE_PROT_IPV6_OF_OR_S },
575 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
577 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
578 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
580 ICE_PROT_IPV4_OF_OR_S,
581 ICE_PROT_IPV6_OF_OR_S },
585 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
586 uint32_t rxdid = xtr_sets[i].rxdid;
589 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
590 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
592 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
593 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
594 ice_proto_xtr_hw_support[i] = true;
597 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
598 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
600 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
601 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
602 ice_proto_xtr_hw_support[i] = true;
608 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
611 struct pool_entry *entry;
616 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
619 "Failed to allocate memory for resource pool");
623 /* queue heap initialize */
624 pool->num_free = num;
627 LIST_INIT(&pool->alloc_list);
628 LIST_INIT(&pool->free_list);
630 /* Initialize element */
634 LIST_INSERT_HEAD(&pool->free_list, entry, next);
639 ice_res_pool_alloc(struct ice_res_pool_info *pool,
642 struct pool_entry *entry, *valid_entry;
645 PMD_INIT_LOG(ERR, "Invalid parameter");
649 if (pool->num_free < num) {
650 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
651 num, pool->num_free);
656 /* Lookup in free list and find most fit one */
657 LIST_FOREACH(entry, &pool->free_list, next) {
658 if (entry->len >= num) {
660 if (entry->len == num) {
665 valid_entry->len > entry->len)
670 /* Not find one to satisfy the request, return */
672 PMD_INIT_LOG(ERR, "No valid entry found");
676 * The entry have equal queue number as requested,
677 * remove it from alloc_list.
679 if (valid_entry->len == num) {
680 LIST_REMOVE(valid_entry, next);
683 * The entry have more numbers than requested,
684 * create a new entry for alloc_list and minus its
685 * queue base and number in free_list.
687 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
690 "Failed to allocate memory for "
694 entry->base = valid_entry->base;
696 valid_entry->base += num;
697 valid_entry->len -= num;
701 /* Insert it into alloc list, not sorted */
702 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
704 pool->num_free -= valid_entry->len;
705 pool->num_alloc += valid_entry->len;
707 return valid_entry->base + pool->base;
711 ice_res_pool_destroy(struct ice_res_pool_info *pool)
713 struct pool_entry *entry, *next_entry;
718 for (entry = LIST_FIRST(&pool->alloc_list);
719 entry && (next_entry = LIST_NEXT(entry, next), 1);
720 entry = next_entry) {
721 LIST_REMOVE(entry, next);
725 for (entry = LIST_FIRST(&pool->free_list);
726 entry && (next_entry = LIST_NEXT(entry, next), 1);
727 entry = next_entry) {
728 LIST_REMOVE(entry, next);
735 LIST_INIT(&pool->alloc_list);
736 LIST_INIT(&pool->free_list);
740 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
742 /* Set VSI LUT selection */
743 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
744 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
745 /* Set Hash scheme */
746 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
747 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
749 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
752 static enum ice_status
753 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
754 struct ice_aqc_vsi_props *info,
755 uint8_t enabled_tcmap)
757 uint16_t bsf, qp_idx;
759 /* default tc 0 now. Multi-TC supporting need to be done later.
760 * Configure TC and queue mapping parameters, for enabled TC,
761 * allocate qpnum_per_tc queues to this traffic.
763 if (enabled_tcmap != 0x01) {
764 PMD_INIT_LOG(ERR, "only TC0 is supported");
768 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
769 bsf = rte_bsf32(vsi->nb_qps);
770 /* Adjust the queue number to actual queues that can be applied */
771 vsi->nb_qps = 0x1 << bsf;
774 /* Set tc and queue mapping with VSI */
775 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
776 ICE_AQ_VSI_TC_Q_OFFSET_S) |
777 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
779 /* Associate queue number with VSI */
780 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
781 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
782 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
783 info->valid_sections |=
784 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
785 /* Set the info.ingress_table and info.egress_table
786 * for UP translate table. Now just set it to 1:1 map by default
787 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
789 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
790 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
791 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
792 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
797 ice_init_mac_address(struct rte_eth_dev *dev)
799 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
801 if (!rte_is_unicast_ether_addr
802 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
803 PMD_INIT_LOG(ERR, "Invalid MAC address");
808 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
809 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
811 dev->data->mac_addrs =
812 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
813 if (!dev->data->mac_addrs) {
815 "Failed to allocate memory to store mac address");
818 /* store it to dev data */
820 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
821 &dev->data->mac_addrs[0]);
825 /* Find out specific MAC filter */
826 static struct ice_mac_filter *
827 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
829 struct ice_mac_filter *f;
831 TAILQ_FOREACH(f, &vsi->mac_list, next) {
832 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
840 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
842 struct ice_fltr_list_entry *m_list_itr = NULL;
843 struct ice_mac_filter *f;
844 struct LIST_HEAD_TYPE list_head;
845 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
848 /* If it's added and configured, return */
849 f = ice_find_mac_filter(vsi, mac_addr);
851 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
855 INIT_LIST_HEAD(&list_head);
857 m_list_itr = (struct ice_fltr_list_entry *)
858 ice_malloc(hw, sizeof(*m_list_itr));
863 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
864 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
865 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
866 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
867 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
868 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
869 m_list_itr->fltr_info.vsi_handle = vsi->idx;
871 LIST_ADD(&m_list_itr->list_entry, &list_head);
874 ret = ice_add_mac(hw, &list_head);
875 if (ret != ICE_SUCCESS) {
876 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
880 /* Add the mac addr into mac list */
881 f = rte_zmalloc(NULL, sizeof(*f), 0);
883 PMD_DRV_LOG(ERR, "failed to allocate memory");
887 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
888 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
894 rte_free(m_list_itr);
899 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
901 struct ice_fltr_list_entry *m_list_itr = NULL;
902 struct ice_mac_filter *f;
903 struct LIST_HEAD_TYPE list_head;
904 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
907 /* Can't find it, return an error */
908 f = ice_find_mac_filter(vsi, mac_addr);
912 INIT_LIST_HEAD(&list_head);
914 m_list_itr = (struct ice_fltr_list_entry *)
915 ice_malloc(hw, sizeof(*m_list_itr));
920 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
921 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
922 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
923 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
924 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
925 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
926 m_list_itr->fltr_info.vsi_handle = vsi->idx;
928 LIST_ADD(&m_list_itr->list_entry, &list_head);
930 /* remove the mac filter */
931 ret = ice_remove_mac(hw, &list_head);
932 if (ret != ICE_SUCCESS) {
933 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
938 /* Remove the mac addr from mac list */
939 TAILQ_REMOVE(&vsi->mac_list, f, next);
945 rte_free(m_list_itr);
949 /* Find out specific VLAN filter */
950 static struct ice_vlan_filter *
951 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
953 struct ice_vlan_filter *f;
955 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
956 if (vlan->tpid == f->vlan_info.vlan.tpid &&
957 vlan->vid == f->vlan_info.vlan.vid)
965 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
967 struct ice_fltr_list_entry *v_list_itr = NULL;
968 struct ice_vlan_filter *f;
969 struct LIST_HEAD_TYPE list_head;
973 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
976 hw = ICE_VSI_TO_HW(vsi);
978 /* If it's added and configured, return. */
979 f = ice_find_vlan_filter(vsi, vlan);
981 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
985 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
988 INIT_LIST_HEAD(&list_head);
990 v_list_itr = (struct ice_fltr_list_entry *)
991 ice_malloc(hw, sizeof(*v_list_itr));
996 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
997 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
998 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
999 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1000 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1001 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1002 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1003 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1005 LIST_ADD(&v_list_itr->list_entry, &list_head);
1008 ret = ice_add_vlan(hw, &list_head);
1009 if (ret != ICE_SUCCESS) {
1010 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1015 /* Add vlan into vlan list */
1016 f = rte_zmalloc(NULL, sizeof(*f), 0);
1018 PMD_DRV_LOG(ERR, "failed to allocate memory");
1022 f->vlan_info.vlan.tpid = vlan->tpid;
1023 f->vlan_info.vlan.vid = vlan->vid;
1024 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1030 rte_free(v_list_itr);
1035 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1037 struct ice_fltr_list_entry *v_list_itr = NULL;
1038 struct ice_vlan_filter *f;
1039 struct LIST_HEAD_TYPE list_head;
1043 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1046 hw = ICE_VSI_TO_HW(vsi);
1048 /* Can't find it, return an error */
1049 f = ice_find_vlan_filter(vsi, vlan);
1053 INIT_LIST_HEAD(&list_head);
1055 v_list_itr = (struct ice_fltr_list_entry *)
1056 ice_malloc(hw, sizeof(*v_list_itr));
1062 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1063 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1064 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1065 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1066 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1067 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1068 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1069 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1071 LIST_ADD(&v_list_itr->list_entry, &list_head);
1073 /* remove the vlan filter */
1074 ret = ice_remove_vlan(hw, &list_head);
1075 if (ret != ICE_SUCCESS) {
1076 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1081 /* Remove the vlan id from vlan list */
1082 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1088 rte_free(v_list_itr);
1093 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1095 struct ice_mac_filter *m_f;
1096 struct ice_vlan_filter *v_f;
1099 if (!vsi || !vsi->mac_num)
1102 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1103 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1104 if (ret != ICE_SUCCESS) {
1110 if (vsi->vlan_num == 0)
1113 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1114 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1115 if (ret != ICE_SUCCESS) {
1127 ice_pf_enable_irq0(struct ice_hw *hw)
1129 /* reset the registers */
1130 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1131 ICE_READ_REG(hw, PFINT_OICR);
1134 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1135 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1136 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1138 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1139 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1140 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1141 PFINT_OICR_CTL_ITR_INDX_M) |
1142 PFINT_OICR_CTL_CAUSE_ENA_M);
1144 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1145 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1146 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1147 PFINT_FW_CTL_ITR_INDX_M) |
1148 PFINT_FW_CTL_CAUSE_ENA_M);
1150 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1153 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1154 GLINT_DYN_CTL_INTENA_M |
1155 GLINT_DYN_CTL_CLEARPBA_M |
1156 GLINT_DYN_CTL_ITR_INDX_M);
1163 ice_pf_disable_irq0(struct ice_hw *hw)
1165 /* Disable all interrupt types */
1166 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1172 ice_handle_aq_msg(struct rte_eth_dev *dev)
1174 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1175 struct ice_ctl_q_info *cq = &hw->adminq;
1176 struct ice_rq_event_info event;
1177 uint16_t pending, opcode;
1180 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1181 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1182 if (!event.msg_buf) {
1183 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1189 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1191 if (ret != ICE_SUCCESS) {
1193 "Failed to read msg from AdminQ, "
1195 hw->adminq.sq_last_status);
1198 opcode = rte_le_to_cpu_16(event.desc.opcode);
1201 case ice_aqc_opc_get_link_status:
1202 ret = ice_link_update(dev, 0);
1204 rte_eth_dev_callback_process
1205 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1208 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1213 rte_free(event.msg_buf);
1218 * Interrupt handler triggered by NIC for handling
1219 * specific interrupt.
1222 * Pointer to interrupt handle.
1224 * The address of parameter (struct rte_eth_dev *) regsitered before.
1230 ice_interrupt_handler(void *param)
1232 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1233 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1241 uint32_t int_fw_ctl;
1244 /* Disable interrupt */
1245 ice_pf_disable_irq0(hw);
1247 /* read out interrupt causes */
1248 oicr = ICE_READ_REG(hw, PFINT_OICR);
1250 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1253 /* No interrupt event indicated */
1254 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1255 PMD_DRV_LOG(INFO, "No interrupt event");
1260 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1261 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1262 ice_handle_aq_msg(dev);
1265 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1266 PMD_DRV_LOG(INFO, "OICR: link state change event");
1267 ret = ice_link_update(dev, 0);
1269 rte_eth_dev_callback_process
1270 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1274 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1275 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1276 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1277 if (reg & GL_MDET_TX_PQM_VALID_M) {
1278 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1279 GL_MDET_TX_PQM_PF_NUM_S;
1280 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1281 GL_MDET_TX_PQM_MAL_TYPE_S;
1282 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1283 GL_MDET_TX_PQM_QNUM_S;
1285 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1286 "%d by PQM on TX queue %d PF# %d",
1287 event, queue, pf_num);
1290 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1291 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1292 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1293 GL_MDET_TX_TCLAN_PF_NUM_S;
1294 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1295 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1296 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1297 GL_MDET_TX_TCLAN_QNUM_S;
1299 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1300 "%d by TCLAN on TX queue %d PF# %d",
1301 event, queue, pf_num);
1305 /* Enable interrupt */
1306 ice_pf_enable_irq0(hw);
1307 rte_intr_ack(dev->intr_handle);
1311 ice_init_proto_xtr(struct rte_eth_dev *dev)
1313 struct ice_adapter *ad =
1314 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1315 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1316 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1317 const struct proto_xtr_ol_flag *ol_flag;
1318 bool proto_xtr_enable = false;
1322 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1323 if (unlikely(pf->proto_xtr == NULL)) {
1324 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1328 for (i = 0; i < pf->lan_nb_qps; i++) {
1329 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1330 ad->devargs.proto_xtr[i] :
1331 ad->devargs.proto_xtr_dflt;
1333 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1334 uint8_t type = pf->proto_xtr[i];
1336 ice_proto_xtr_ol_flag_params[type].required = true;
1337 proto_xtr_enable = true;
1341 if (likely(!proto_xtr_enable))
1344 ice_check_proto_xtr_support(hw);
1346 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1347 if (unlikely(offset == -1)) {
1349 "Protocol extraction metadata is disabled in mbuf with error %d",
1355 "Protocol extraction metadata offset in mbuf is : %d",
1357 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1359 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1360 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1362 if (!ol_flag->required)
1365 if (!ice_proto_xtr_hw_support[i]) {
1367 "Protocol extraction type %u is not supported in hardware",
1369 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1373 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1374 if (unlikely(offset == -1)) {
1376 "Protocol extraction offload '%s' failed to register with error %d",
1377 ol_flag->param.name, -rte_errno);
1379 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1384 "Protocol extraction offload '%s' offset in mbuf is : %d",
1385 ol_flag->param.name, offset);
1386 *ol_flag->ol_flag = 1ULL << offset;
1390 /* Initialize SW parameters of PF */
1392 ice_pf_sw_init(struct rte_eth_dev *dev)
1394 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1395 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1398 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1399 hw->func_caps.common_cap.num_rxq);
1401 pf->lan_nb_qps = pf->lan_nb_qp_max;
1403 ice_init_proto_xtr(dev);
1405 if (hw->func_caps.fd_fltr_guar > 0 ||
1406 hw->func_caps.fd_fltr_best_effort > 0) {
1407 pf->flags |= ICE_FLAG_FDIR;
1408 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1409 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1411 pf->fdir_nb_qps = 0;
1413 pf->fdir_qp_offset = 0;
1419 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1421 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1422 struct ice_vsi *vsi = NULL;
1423 struct ice_vsi_ctx vsi_ctx;
1425 struct rte_ether_addr broadcast = {
1426 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1427 struct rte_ether_addr mac_addr;
1428 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1429 uint8_t tc_bitmap = 0x1;
1432 /* hw->num_lports = 1 in NIC mode */
1433 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1437 vsi->idx = pf->next_vsi_idx;
1440 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1441 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1442 vsi->vlan_anti_spoof_on = 0;
1443 vsi->vlan_filter_on = 1;
1444 TAILQ_INIT(&vsi->mac_list);
1445 TAILQ_INIT(&vsi->vlan_list);
1447 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1448 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1449 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1450 hw->func_caps.common_cap.rss_table_size;
1451 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1453 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1456 vsi->nb_qps = pf->lan_nb_qps;
1457 vsi->base_queue = 1;
1458 ice_vsi_config_default_rss(&vsi_ctx.info);
1459 vsi_ctx.alloc_from_pool = true;
1460 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1461 /* switch_id is queried by get_switch_config aq, which is done
1464 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1465 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1466 /* Allow all untagged or tagged packets */
1467 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1468 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1469 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1470 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1471 if (ice_is_dvm_ena(hw)) {
1472 vsi_ctx.info.outer_vlan_flags =
1473 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1474 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1475 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1476 vsi_ctx.info.outer_vlan_flags |=
1477 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1478 ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1479 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1483 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1484 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1485 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1486 cfg = ICE_AQ_VSI_FD_ENABLE;
1487 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1488 vsi_ctx.info.max_fd_fltr_dedicated =
1489 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1490 vsi_ctx.info.max_fd_fltr_shared =
1491 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1493 /* Enable VLAN/UP trip */
1494 ret = ice_vsi_config_tc_queue_mapping(vsi,
1499 "tc queue mapping with vsi failed, "
1507 vsi->nb_qps = pf->fdir_nb_qps;
1508 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1509 vsi_ctx.alloc_from_pool = true;
1510 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1512 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1513 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1514 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1515 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1516 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1517 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1518 ret = ice_vsi_config_tc_queue_mapping(vsi,
1523 "tc queue mapping with vsi failed, "
1530 /* for other types of VSI */
1531 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1535 /* VF has MSIX interrupt in VF range, don't allocate here */
1536 if (type == ICE_VSI_PF) {
1537 ret = ice_res_pool_alloc(&pf->msix_pool,
1538 RTE_MIN(vsi->nb_qps,
1539 RTE_MAX_RXTX_INTR_VEC_ID));
1541 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1544 vsi->msix_intr = ret;
1545 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1546 } else if (type == ICE_VSI_CTRL) {
1547 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1549 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1552 vsi->msix_intr = ret;
1558 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1559 if (ret != ICE_SUCCESS) {
1560 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1563 /* store vsi information is SW structure */
1564 vsi->vsi_id = vsi_ctx.vsi_num;
1565 vsi->info = vsi_ctx.info;
1566 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1567 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1569 if (type == ICE_VSI_PF) {
1570 /* MAC configuration */
1571 rte_ether_addr_copy((struct rte_ether_addr *)
1572 hw->port_info->mac.perm_addr,
1575 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1576 ret = ice_add_mac_filter(vsi, &mac_addr);
1577 if (ret != ICE_SUCCESS)
1578 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1580 rte_ether_addr_copy(&broadcast, &mac_addr);
1581 ret = ice_add_mac_filter(vsi, &mac_addr);
1582 if (ret != ICE_SUCCESS)
1583 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1586 /* At the beginning, only TC0. */
1587 /* What we need here is the maximam number of the TX queues.
1588 * Currently vsi->nb_qps means it.
1589 * Correct it if any change.
1591 max_txqs[0] = vsi->nb_qps;
1592 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1593 tc_bitmap, max_txqs);
1594 if (ret != ICE_SUCCESS)
1595 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1605 ice_send_driver_ver(struct ice_hw *hw)
1607 struct ice_driver_ver dv;
1609 /* we don't have driver version use 0 for dummy */
1613 dv.subbuild_ver = 0;
1614 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1616 return ice_aq_send_driver_ver(hw, &dv, NULL);
1620 ice_pf_setup(struct ice_pf *pf)
1622 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1623 struct ice_vsi *vsi;
1626 /* Clear all stats counters */
1627 pf->offset_loaded = false;
1628 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1629 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1630 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1631 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1633 /* force guaranteed filter pool for PF */
1634 ice_alloc_fd_guar_item(hw, &unused,
1635 hw->func_caps.fd_fltr_guar);
1636 /* force shared filter pool for PF */
1637 ice_alloc_fd_shrd_item(hw, &unused,
1638 hw->func_caps.fd_fltr_best_effort);
1640 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1642 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1652 * Extract device serial number from PCIe Configuration Space and
1653 * determine the pkg file path according to the DSN.
1656 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1659 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1660 uint32_t dsn_low, dsn_high;
1661 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1663 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1666 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0) {
1667 PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
1670 if (rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) {
1671 PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
1674 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1675 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1677 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1681 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1682 ICE_MAX_PKG_FILENAME_SIZE);
1683 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1686 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1687 ICE_MAX_PKG_FILENAME_SIZE);
1688 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1692 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1693 if (!access(pkg_file, 0))
1695 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1700 ice_load_pkg_type(struct ice_hw *hw)
1702 enum ice_pkg_type package_type;
1704 /* store the activated package type (OS default or Comms) */
1705 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1707 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1708 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1710 package_type = ICE_PKG_TYPE_COMMS;
1712 package_type = ICE_PKG_TYPE_UNKNOWN;
1714 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1715 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1716 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1717 hw->active_pkg_name,
1718 ice_is_dvm_ena(hw) ? "double" : "single");
1720 return package_type;
1723 static int ice_load_pkg(struct rte_eth_dev *dev)
1725 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1732 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1733 struct ice_adapter *ad =
1734 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1736 err = ice_pkg_file_search_path(pci_dev, pkg_file);
1738 PMD_INIT_LOG(ERR, "failed to search file path\n");
1742 file = fopen(pkg_file, "rb");
1744 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1748 err = stat(pkg_file, &fstat);
1750 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1755 buf_len = fstat.st_size;
1756 buf = rte_malloc(NULL, buf_len, 0);
1759 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1765 err = fread(buf, buf_len, 1, file);
1767 PMD_INIT_LOG(ERR, "failed to read package data\n");
1775 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1777 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1781 /* store the loaded pkg type info */
1782 ad->active_pkg_type = ice_load_pkg_type(hw);
1784 err = ice_init_hw_tbls(hw);
1786 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1787 goto fail_init_tbls;
1793 rte_free(hw->pkg_copy);
1800 ice_base_queue_get(struct ice_pf *pf)
1803 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1805 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1806 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1807 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1809 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1815 parse_bool(const char *key, const char *value, void *args)
1817 int *i = (int *)args;
1821 num = strtoul(value, &end, 10);
1823 if (num != 0 && num != 1) {
1824 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1825 "value must be 0 or 1",
1834 static int ice_parse_devargs(struct rte_eth_dev *dev)
1836 struct ice_adapter *ad =
1837 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1838 struct rte_devargs *devargs = dev->device->devargs;
1839 struct rte_kvargs *kvlist;
1842 if (devargs == NULL)
1845 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1846 if (kvlist == NULL) {
1847 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1851 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1852 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1853 sizeof(ad->devargs.proto_xtr));
1855 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1856 &handle_proto_xtr_arg, &ad->devargs);
1860 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1861 &parse_bool, &ad->devargs.safe_mode_support);
1865 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1866 &parse_bool, &ad->devargs.pipe_mode_support);
1871 rte_kvargs_free(kvlist);
1875 /* Forward LLDP packets to default VSI by set switch rules */
1877 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1879 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1880 struct ice_fltr_list_entry *s_list_itr = NULL;
1881 struct LIST_HEAD_TYPE list_head;
1884 INIT_LIST_HEAD(&list_head);
1886 s_list_itr = (struct ice_fltr_list_entry *)
1887 ice_malloc(hw, sizeof(*s_list_itr));
1890 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1891 s_list_itr->fltr_info.vsi_handle = vsi->idx;
1892 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1893 RTE_ETHER_TYPE_LLDP;
1894 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1895 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1896 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1897 LIST_ADD(&s_list_itr->list_entry, &list_head);
1899 ret = ice_add_eth_mac(hw, &list_head);
1901 ret = ice_remove_eth_mac(hw, &list_head);
1903 rte_free(s_list_itr);
1907 static enum ice_status
1908 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1909 uint16_t num, uint16_t desc_id,
1910 uint16_t *prof_buf, uint16_t *num_prof)
1912 struct ice_aqc_res_elem *resp_buf;
1915 bool res_shared = 1;
1916 struct ice_aq_desc aq_desc;
1917 struct ice_sq_cd *cd = NULL;
1918 struct ice_aqc_get_allocd_res_desc *cmd =
1919 &aq_desc.params.get_res_desc;
1921 buf_len = sizeof(*resp_buf) * num;
1922 resp_buf = ice_malloc(hw, buf_len);
1926 ice_fill_dflt_direct_cmd_desc(&aq_desc,
1927 ice_aqc_opc_get_allocd_res_desc);
1929 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1930 ICE_AQC_RES_TYPE_M) | (res_shared ?
1931 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1932 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1934 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1936 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1940 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
1941 (*num_prof), ICE_NONDMA_TO_NONDMA);
1948 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1952 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1953 uint16_t first_desc = 1;
1954 uint16_t num_prof = 0;
1956 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1957 first_desc, prof_buf, &num_prof);
1959 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
1963 for (prof_id = 0; prof_id < num_prof; prof_id++) {
1964 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
1966 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
1974 ice_reset_fxp_resource(struct ice_hw *hw)
1978 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
1980 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
1984 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
1986 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
1994 ice_rss_ctx_init(struct ice_pf *pf)
1996 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
2000 ice_get_supported_rxdid(struct ice_hw *hw)
2002 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2006 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2008 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2009 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2010 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2011 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2012 supported_rxdid |= BIT(i);
2014 return supported_rxdid;
2018 ice_dev_init(struct rte_eth_dev *dev)
2020 struct rte_pci_device *pci_dev;
2021 struct rte_intr_handle *intr_handle;
2022 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2024 struct ice_adapter *ad =
2025 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2026 struct ice_vsi *vsi;
2029 dev->dev_ops = &ice_eth_dev_ops;
2030 dev->rx_queue_count = ice_rx_queue_count;
2031 dev->rx_descriptor_status = ice_rx_descriptor_status;
2032 dev->tx_descriptor_status = ice_tx_descriptor_status;
2033 dev->rx_pkt_burst = ice_recv_pkts;
2034 dev->tx_pkt_burst = ice_xmit_pkts;
2035 dev->tx_pkt_prepare = ice_prep_pkts;
2037 /* for secondary processes, we don't initialise any further as primary
2038 * has already done this work.
2040 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2041 ice_set_rx_function(dev);
2042 ice_set_tx_function(dev);
2046 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2048 ice_set_default_ptype_table(dev);
2049 pci_dev = RTE_DEV_TO_PCI(dev->device);
2050 intr_handle = &pci_dev->intr_handle;
2052 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2053 pf->adapter->eth_dev = dev;
2054 pf->dev_data = dev->data;
2055 hw->back = pf->adapter;
2056 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2057 hw->vendor_id = pci_dev->id.vendor_id;
2058 hw->device_id = pci_dev->id.device_id;
2059 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2060 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2061 hw->bus.device = pci_dev->addr.devid;
2062 hw->bus.func = pci_dev->addr.function;
2064 ret = ice_parse_devargs(dev);
2066 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2070 ice_init_controlq_parameter(hw);
2072 ret = ice_init_hw(hw);
2074 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2078 ret = ice_load_pkg(dev);
2080 if (ad->devargs.safe_mode_support == 0) {
2081 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2082 "Use safe-mode-support=1 to enter Safe Mode");
2086 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2087 "Entering Safe Mode");
2088 ad->is_safe_mode = 1;
2091 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2092 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2093 hw->api_maj_ver, hw->api_min_ver);
2095 ice_pf_sw_init(dev);
2096 ret = ice_init_mac_address(dev);
2098 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2102 ret = ice_res_pool_init(&pf->msix_pool, 1,
2103 hw->func_caps.common_cap.num_msix_vectors - 1);
2105 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2106 goto err_msix_pool_init;
2109 ret = ice_pf_setup(pf);
2111 PMD_INIT_LOG(ERR, "Failed to setup PF");
2115 ret = ice_send_driver_ver(hw);
2117 PMD_INIT_LOG(ERR, "Failed to send driver version");
2123 ret = ice_aq_stop_lldp(hw, true, false, NULL);
2124 if (ret != ICE_SUCCESS)
2125 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2126 ret = ice_init_dcb(hw, true);
2127 if (ret != ICE_SUCCESS)
2128 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2129 /* Forward LLDP packets to default VSI */
2130 ret = ice_vsi_config_sw_lldp(vsi, true);
2131 if (ret != ICE_SUCCESS)
2132 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2133 /* register callback func to eal lib */
2134 rte_intr_callback_register(intr_handle,
2135 ice_interrupt_handler, dev);
2137 ice_pf_enable_irq0(hw);
2139 /* enable uio intr after callback register */
2140 rte_intr_enable(intr_handle);
2142 /* get base queue pairs index in the device */
2143 ice_base_queue_get(pf);
2145 /* Initialize RSS context for gtpu_eh */
2146 ice_rss_ctx_init(pf);
2148 if (!ad->is_safe_mode) {
2149 ret = ice_flow_init(ad);
2151 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2156 ret = ice_reset_fxp_resource(hw);
2158 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2162 pf->supported_rxdid = ice_get_supported_rxdid(hw);
2167 ice_res_pool_destroy(&pf->msix_pool);
2169 rte_free(dev->data->mac_addrs);
2170 dev->data->mac_addrs = NULL;
2172 ice_sched_cleanup_all(hw);
2173 rte_free(hw->port_info);
2174 ice_shutdown_all_ctrlq(hw);
2175 rte_free(pf->proto_xtr);
2181 ice_release_vsi(struct ice_vsi *vsi)
2184 struct ice_vsi_ctx vsi_ctx;
2185 enum ice_status ret;
2191 hw = ICE_VSI_TO_HW(vsi);
2193 ice_remove_all_mac_vlan_filters(vsi);
2195 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2197 vsi_ctx.vsi_num = vsi->vsi_id;
2198 vsi_ctx.info = vsi->info;
2199 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2200 if (ret != ICE_SUCCESS) {
2201 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2205 rte_free(vsi->rss_lut);
2206 rte_free(vsi->rss_key);
2212 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2214 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2215 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2216 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2217 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2218 uint16_t msix_intr, i;
2220 /* disable interrupt and also clear all the exist config */
2221 for (i = 0; i < vsi->nb_qps; i++) {
2222 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2223 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2227 if (rte_intr_allow_others(intr_handle))
2229 for (i = 0; i < vsi->nb_msix; i++) {
2230 msix_intr = vsi->msix_intr + i;
2231 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2232 GLINT_DYN_CTL_WB_ON_ITR_M);
2236 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2240 ice_dev_stop(struct rte_eth_dev *dev)
2242 struct rte_eth_dev_data *data = dev->data;
2243 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2244 struct ice_vsi *main_vsi = pf->main_vsi;
2245 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2246 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2249 /* avoid stopping again */
2250 if (pf->adapter_stopped)
2253 /* stop and clear all Rx queues */
2254 for (i = 0; i < data->nb_rx_queues; i++)
2255 ice_rx_queue_stop(dev, i);
2257 /* stop and clear all Tx queues */
2258 for (i = 0; i < data->nb_tx_queues; i++)
2259 ice_tx_queue_stop(dev, i);
2261 /* disable all queue interrupts */
2262 ice_vsi_disable_queues_intr(main_vsi);
2264 if (pf->init_link_up)
2265 ice_dev_set_link_up(dev);
2267 ice_dev_set_link_down(dev);
2269 /* Clean datapath event and queue/vec mapping */
2270 rte_intr_efd_disable(intr_handle);
2271 if (intr_handle->intr_vec) {
2272 rte_free(intr_handle->intr_vec);
2273 intr_handle->intr_vec = NULL;
2276 pf->adapter_stopped = true;
2277 dev->data->dev_started = 0;
2283 ice_dev_close(struct rte_eth_dev *dev)
2285 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2286 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2288 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2289 struct ice_adapter *ad =
2290 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2293 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2296 /* Since stop will make link down, then the link event will be
2297 * triggered, disable the irq firstly to avoid the port_infoe etc
2298 * resources deallocation causing the interrupt service thread
2301 ice_pf_disable_irq0(hw);
2303 ret = ice_dev_stop(dev);
2305 if (!ad->is_safe_mode)
2306 ice_flow_uninit(ad);
2308 /* release all queue resource */
2309 ice_free_queues(dev);
2311 ice_res_pool_destroy(&pf->msix_pool);
2312 ice_release_vsi(pf->main_vsi);
2313 ice_sched_cleanup_all(hw);
2314 ice_free_hw_tbls(hw);
2315 rte_free(hw->port_info);
2316 hw->port_info = NULL;
2317 ice_shutdown_all_ctrlq(hw);
2318 rte_free(pf->proto_xtr);
2319 pf->proto_xtr = NULL;
2321 /* disable uio intr before callback unregister */
2322 rte_intr_disable(intr_handle);
2324 /* unregister callback func from eal lib */
2325 rte_intr_callback_unregister(intr_handle,
2326 ice_interrupt_handler, dev);
2332 ice_dev_uninit(struct rte_eth_dev *dev)
2340 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2342 return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2346 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2351 cfg->hdr_type = ICE_RSS_ANY_HEADERS;
2355 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2357 enum ice_status status = ICE_SUCCESS;
2358 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2359 struct ice_vsi *vsi = pf->main_vsi;
2361 if (!is_hash_cfg_valid(cfg))
2364 status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2365 if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2367 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2376 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2378 enum ice_status status = ICE_SUCCESS;
2379 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2380 struct ice_vsi *vsi = pf->main_vsi;
2382 if (!is_hash_cfg_valid(cfg))
2385 status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2388 "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2397 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2401 ret = ice_hash_moveout(pf, cfg);
2402 if (ret && (ret != -ENOENT))
2405 hash_cfg_reset(cfg);
2411 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2417 case ICE_HASH_GTPU_CTX_EH_IP:
2418 ret = ice_hash_remove(pf,
2419 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2420 if (ret && (ret != -ENOENT))
2423 ret = ice_hash_remove(pf,
2424 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2425 if (ret && (ret != -ENOENT))
2428 ret = ice_hash_remove(pf,
2429 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2430 if (ret && (ret != -ENOENT))
2433 ret = ice_hash_remove(pf,
2434 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2435 if (ret && (ret != -ENOENT))
2438 ret = ice_hash_remove(pf,
2439 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2440 if (ret && (ret != -ENOENT))
2443 ret = ice_hash_remove(pf,
2444 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2445 if (ret && (ret != -ENOENT))
2448 ret = ice_hash_remove(pf,
2449 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2450 if (ret && (ret != -ENOENT))
2453 ret = ice_hash_remove(pf,
2454 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2455 if (ret && (ret != -ENOENT))
2459 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2460 ret = ice_hash_remove(pf,
2461 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2462 if (ret && (ret != -ENOENT))
2465 ret = ice_hash_remove(pf,
2466 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2467 if (ret && (ret != -ENOENT))
2470 ret = ice_hash_moveout(pf,
2471 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2472 if (ret && (ret != -ENOENT))
2475 ret = ice_hash_moveout(pf,
2476 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2477 if (ret && (ret != -ENOENT))
2480 ret = ice_hash_moveout(pf,
2481 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2482 if (ret && (ret != -ENOENT))
2485 ret = ice_hash_moveout(pf,
2486 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2487 if (ret && (ret != -ENOENT))
2491 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2492 ret = ice_hash_remove(pf,
2493 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2494 if (ret && (ret != -ENOENT))
2497 ret = ice_hash_remove(pf,
2498 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2499 if (ret && (ret != -ENOENT))
2502 ret = ice_hash_moveout(pf,
2503 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2504 if (ret && (ret != -ENOENT))
2507 ret = ice_hash_moveout(pf,
2508 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2509 if (ret && (ret != -ENOENT))
2512 ret = ice_hash_moveout(pf,
2513 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2514 if (ret && (ret != -ENOENT))
2517 ret = ice_hash_moveout(pf,
2518 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2519 if (ret && (ret != -ENOENT))
2523 case ICE_HASH_GTPU_CTX_UP_IP:
2524 ret = ice_hash_remove(pf,
2525 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2526 if (ret && (ret != -ENOENT))
2529 ret = ice_hash_remove(pf,
2530 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2531 if (ret && (ret != -ENOENT))
2534 ret = ice_hash_moveout(pf,
2535 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2536 if (ret && (ret != -ENOENT))
2539 ret = ice_hash_moveout(pf,
2540 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2541 if (ret && (ret != -ENOENT))
2544 ret = ice_hash_moveout(pf,
2545 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2546 if (ret && (ret != -ENOENT))
2550 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2551 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2552 ret = ice_hash_moveout(pf,
2553 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2554 if (ret && (ret != -ENOENT))
2557 ret = ice_hash_moveout(pf,
2558 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2559 if (ret && (ret != -ENOENT))
2562 ret = ice_hash_moveout(pf,
2563 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2564 if (ret && (ret != -ENOENT))
2568 case ICE_HASH_GTPU_CTX_DW_IP:
2569 ret = ice_hash_remove(pf,
2570 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2571 if (ret && (ret != -ENOENT))
2574 ret = ice_hash_remove(pf,
2575 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2576 if (ret && (ret != -ENOENT))
2579 ret = ice_hash_moveout(pf,
2580 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2581 if (ret && (ret != -ENOENT))
2584 ret = ice_hash_moveout(pf,
2585 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2586 if (ret && (ret != -ENOENT))
2589 ret = ice_hash_moveout(pf,
2590 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2591 if (ret && (ret != -ENOENT))
2595 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2596 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2597 ret = ice_hash_moveout(pf,
2598 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2599 if (ret && (ret != -ENOENT))
2602 ret = ice_hash_moveout(pf,
2603 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2604 if (ret && (ret != -ENOENT))
2607 ret = ice_hash_moveout(pf,
2608 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2609 if (ret && (ret != -ENOENT))
2620 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2624 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2626 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2628 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2631 return ICE_HASH_GTPU_CTX_MAX;
2634 if (hdr & ICE_FLOW_SEG_HDR_UDP)
2636 else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2639 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2640 return eh_idx * 3 + ip_idx;
2642 return ICE_HASH_GTPU_CTX_MAX;
2646 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2648 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2650 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2651 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2653 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2654 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2661 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2662 u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2666 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2667 ctx->ctx[ctx_idx] = *cfg;
2670 case ICE_HASH_GTPU_CTX_EH_IP:
2672 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2673 ret = ice_hash_moveback(pf,
2674 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2675 if (ret && (ret != -ENOENT))
2678 ret = ice_hash_moveback(pf,
2679 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2680 if (ret && (ret != -ENOENT))
2683 ret = ice_hash_moveback(pf,
2684 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2685 if (ret && (ret != -ENOENT))
2688 ret = ice_hash_moveback(pf,
2689 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2690 if (ret && (ret != -ENOENT))
2694 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2695 ret = ice_hash_moveback(pf,
2696 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2697 if (ret && (ret != -ENOENT))
2700 ret = ice_hash_moveback(pf,
2701 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2702 if (ret && (ret != -ENOENT))
2705 ret = ice_hash_moveback(pf,
2706 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2707 if (ret && (ret != -ENOENT))
2710 ret = ice_hash_moveback(pf,
2711 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2712 if (ret && (ret != -ENOENT))
2716 case ICE_HASH_GTPU_CTX_UP_IP:
2717 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2718 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2719 case ICE_HASH_GTPU_CTX_DW_IP:
2720 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2721 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2722 ret = ice_hash_moveback(pf,
2723 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2724 if (ret && (ret != -ENOENT))
2727 ret = ice_hash_moveback(pf,
2728 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2729 if (ret && (ret != -ENOENT))
2732 ret = ice_hash_moveback(pf,
2733 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2734 if (ret && (ret != -ENOENT))
2746 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2748 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2750 if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2751 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2753 else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2754 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2761 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2763 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2765 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2768 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2769 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2770 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2771 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2775 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2776 struct ice_rss_hash_cfg *cfg)
2778 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2781 ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2782 if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2783 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2785 ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2791 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2792 struct ice_rss_hash_cfg *cfg)
2794 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2797 ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2799 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2801 ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2803 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2805 ret = ice_add_rss_cfg_post(pf, cfg);
2807 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2813 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2815 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2816 struct ice_vsi *vsi = pf->main_vsi;
2817 struct ice_rss_hash_cfg cfg;
2820 #define ICE_RSS_HF_ALL ( \
2823 ETH_RSS_NONFRAG_IPV4_UDP | \
2824 ETH_RSS_NONFRAG_IPV6_UDP | \
2825 ETH_RSS_NONFRAG_IPV4_TCP | \
2826 ETH_RSS_NONFRAG_IPV6_TCP | \
2827 ETH_RSS_NONFRAG_IPV4_SCTP | \
2828 ETH_RSS_NONFRAG_IPV6_SCTP)
2830 ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2832 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2836 cfg.hdr_type = ICE_RSS_ANY_HEADERS;
2837 /* Configure RSS for IPv4 with src/dst addr as input set */
2838 if (rss_hf & ETH_RSS_IPV4) {
2839 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2840 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2841 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2843 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2847 /* Configure RSS for IPv6 with src/dst addr as input set */
2848 if (rss_hf & ETH_RSS_IPV6) {
2849 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2850 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2851 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2853 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2857 /* Configure RSS for udp4 with src/dst addr and port as input set */
2858 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2859 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2860 ICE_FLOW_SEG_HDR_IPV_OTHER;
2861 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2862 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2864 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2868 /* Configure RSS for udp6 with src/dst addr and port as input set */
2869 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2870 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
2871 ICE_FLOW_SEG_HDR_IPV_OTHER;
2872 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2873 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2875 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2879 /* Configure RSS for tcp4 with src/dst addr and port as input set */
2880 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2881 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
2882 ICE_FLOW_SEG_HDR_IPV_OTHER;
2883 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2884 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2886 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2890 /* Configure RSS for tcp6 with src/dst addr and port as input set */
2891 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2892 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
2893 ICE_FLOW_SEG_HDR_IPV_OTHER;
2894 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2895 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2897 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2901 /* Configure RSS for sctp4 with src/dst addr and port as input set */
2902 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2903 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
2904 ICE_FLOW_SEG_HDR_IPV_OTHER;
2905 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
2906 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2908 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2912 /* Configure RSS for sctp6 with src/dst addr and port as input set */
2913 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2914 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
2915 ICE_FLOW_SEG_HDR_IPV_OTHER;
2916 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
2917 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2919 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2923 if (rss_hf & ETH_RSS_IPV4) {
2924 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV4 |
2925 ICE_FLOW_SEG_HDR_IPV_OTHER;
2926 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2927 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2929 PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
2932 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV4 |
2933 ICE_FLOW_SEG_HDR_IPV_OTHER;
2934 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2936 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
2939 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
2940 ICE_FLOW_SEG_HDR_IPV_OTHER;
2941 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2943 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2947 if (rss_hf & ETH_RSS_IPV6) {
2948 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV6 |
2949 ICE_FLOW_SEG_HDR_IPV_OTHER;
2950 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2951 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2953 PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
2956 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV6 |
2957 ICE_FLOW_SEG_HDR_IPV_OTHER;
2958 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2960 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
2963 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
2964 ICE_FLOW_SEG_HDR_IPV_OTHER;
2965 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2967 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2971 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2972 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2973 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2974 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2975 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2977 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
2980 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
2981 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2982 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2984 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
2987 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2988 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2989 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2991 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2995 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2996 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2997 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2998 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2999 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3001 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
3004 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
3005 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3006 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3008 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
3011 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3012 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3013 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3015 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3019 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3020 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3021 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3022 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3023 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3025 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
3028 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3029 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3030 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3032 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
3035 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3036 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3037 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3039 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3043 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3044 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3045 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3046 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3047 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3049 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
3052 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3053 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3054 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3056 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
3059 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3060 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3061 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3063 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3067 pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3070 static int ice_init_rss(struct ice_pf *pf)
3072 struct ice_hw *hw = ICE_PF_TO_HW(pf);
3073 struct ice_vsi *vsi = pf->main_vsi;
3074 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3075 struct ice_aq_get_set_rss_lut_params lut_params;
3076 struct rte_eth_rss_conf *rss_conf;
3077 struct ice_aqc_get_set_rss_keys key;
3080 bool is_safe_mode = pf->adapter->is_safe_mode;
3083 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3084 nb_q = dev->data->nb_rx_queues;
3085 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3086 vsi->rss_lut_size = pf->hash_lut_size;
3089 PMD_DRV_LOG(WARNING,
3090 "RSS is not supported as rx queues number is zero\n");
3095 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3099 if (!vsi->rss_key) {
3100 vsi->rss_key = rte_zmalloc(NULL,
3101 vsi->rss_key_size, 0);
3102 if (vsi->rss_key == NULL) {
3103 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3107 if (!vsi->rss_lut) {
3108 vsi->rss_lut = rte_zmalloc(NULL,
3109 vsi->rss_lut_size, 0);
3110 if (vsi->rss_lut == NULL) {
3111 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3112 rte_free(vsi->rss_key);
3113 vsi->rss_key = NULL;
3117 /* configure RSS key */
3118 if (!rss_conf->rss_key) {
3119 /* Calculate the default hash key */
3120 for (i = 0; i <= vsi->rss_key_size; i++)
3121 vsi->rss_key[i] = (uint8_t)rte_rand();
3123 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3124 RTE_MIN(rss_conf->rss_key_len,
3125 vsi->rss_key_size));
3127 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3128 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3132 /* init RSS LUT table */
3133 for (i = 0; i < vsi->rss_lut_size; i++)
3134 vsi->rss_lut[i] = i % nb_q;
3136 lut_params.vsi_handle = vsi->idx;
3137 lut_params.lut_size = vsi->rss_lut_size;
3138 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3139 lut_params.lut = vsi->rss_lut;
3140 lut_params.global_lut_id = 0;
3141 ret = ice_aq_set_rss_lut(hw, &lut_params);
3145 /* Enable registers for symmetric_toeplitz function. */
3146 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3147 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3148 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3149 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3151 /* RSS hash configuration */
3152 ice_rss_hash_set(pf, rss_conf->rss_hf);
3156 rte_free(vsi->rss_key);
3157 vsi->rss_key = NULL;
3158 rte_free(vsi->rss_lut);
3159 vsi->rss_lut = NULL;
3164 ice_dev_configure(struct rte_eth_dev *dev)
3166 struct ice_adapter *ad =
3167 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3168 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3171 /* Initialize to TRUE. If any of Rx queues doesn't meet the
3172 * bulk allocation or vector Rx preconditions we will reset it.
3174 ad->rx_bulk_alloc_allowed = true;
3175 ad->tx_simple_allowed = true;
3177 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3178 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3180 if (dev->data->nb_rx_queues) {
3181 ret = ice_init_rss(pf);
3183 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3192 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3193 int base_queue, int nb_queue)
3195 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3196 uint32_t val, val_tx;
3199 for (i = 0; i < nb_queue; i++) {
3201 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3202 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3203 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3204 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3206 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3207 base_queue + i, msix_vect);
3208 /* set ITR0 value */
3209 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3210 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3211 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3216 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3218 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3219 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3220 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3221 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3222 uint16_t msix_vect = vsi->msix_intr;
3223 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3224 uint16_t queue_idx = 0;
3228 /* clear Rx/Tx queue interrupt */
3229 for (i = 0; i < vsi->nb_used_qps; i++) {
3230 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3231 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3234 /* PF bind interrupt */
3235 if (rte_intr_dp_is_en(intr_handle)) {
3240 for (i = 0; i < vsi->nb_used_qps; i++) {
3242 if (!rte_intr_allow_others(intr_handle))
3243 msix_vect = ICE_MISC_VEC_ID;
3245 /* uio mapping all queue to one msix_vect */
3246 __vsi_queues_bind_intr(vsi, msix_vect,
3247 vsi->base_queue + i,
3248 vsi->nb_used_qps - i);
3250 for (; !!record && i < vsi->nb_used_qps; i++)
3251 intr_handle->intr_vec[queue_idx + i] =
3256 /* vfio 1:1 queue/msix_vect mapping */
3257 __vsi_queues_bind_intr(vsi, msix_vect,
3258 vsi->base_queue + i, 1);
3261 intr_handle->intr_vec[queue_idx + i] = msix_vect;
3269 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3271 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3272 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3273 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3274 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3275 uint16_t msix_intr, i;
3277 if (rte_intr_allow_others(intr_handle))
3278 for (i = 0; i < vsi->nb_used_qps; i++) {
3279 msix_intr = vsi->msix_intr + i;
3280 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3281 GLINT_DYN_CTL_INTENA_M |
3282 GLINT_DYN_CTL_CLEARPBA_M |
3283 GLINT_DYN_CTL_ITR_INDX_M |
3284 GLINT_DYN_CTL_WB_ON_ITR_M);
3287 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3288 GLINT_DYN_CTL_INTENA_M |
3289 GLINT_DYN_CTL_CLEARPBA_M |
3290 GLINT_DYN_CTL_ITR_INDX_M |
3291 GLINT_DYN_CTL_WB_ON_ITR_M);
3295 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3297 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3298 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3299 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3300 struct ice_vsi *vsi = pf->main_vsi;
3301 uint32_t intr_vector = 0;
3303 rte_intr_disable(intr_handle);
3305 /* check and configure queue intr-vector mapping */
3306 if ((rte_intr_cap_multiple(intr_handle) ||
3307 !RTE_ETH_DEV_SRIOV(dev).active) &&
3308 dev->data->dev_conf.intr_conf.rxq != 0) {
3309 intr_vector = dev->data->nb_rx_queues;
3310 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3311 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3312 ICE_MAX_INTR_QUEUE_NUM);
3315 if (rte_intr_efd_enable(intr_handle, intr_vector))
3319 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3320 intr_handle->intr_vec =
3321 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3323 if (!intr_handle->intr_vec) {
3325 "Failed to allocate %d rx_queues intr_vec",
3326 dev->data->nb_rx_queues);
3331 /* Map queues with MSIX interrupt */
3332 vsi->nb_used_qps = dev->data->nb_rx_queues;
3333 ice_vsi_queues_bind_intr(vsi);
3335 /* Enable interrupts for all the queues */
3336 ice_vsi_enable_queues_intr(vsi);
3338 rte_intr_enable(intr_handle);
3344 ice_get_init_link_status(struct rte_eth_dev *dev)
3346 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3347 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3348 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3349 struct ice_link_status link_status;
3352 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3353 &link_status, NULL);
3354 if (ret != ICE_SUCCESS) {
3355 PMD_DRV_LOG(ERR, "Failed to get link info");
3356 pf->init_link_up = false;
3360 if (link_status.link_info & ICE_AQ_LINK_UP)
3361 pf->init_link_up = true;
3365 ice_dev_start(struct rte_eth_dev *dev)
3367 struct rte_eth_dev_data *data = dev->data;
3368 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3369 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3370 struct ice_vsi *vsi = pf->main_vsi;
3371 uint16_t nb_rxq = 0;
3373 uint16_t max_frame_size;
3376 /* program Tx queues' context in hardware */
3377 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3378 ret = ice_tx_queue_start(dev, nb_txq);
3380 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3385 /* program Rx queues' context in hardware*/
3386 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3387 ret = ice_rx_queue_start(dev, nb_rxq);
3389 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3394 ice_set_rx_function(dev);
3395 ice_set_tx_function(dev);
3397 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3398 ETH_VLAN_EXTEND_MASK;
3399 ret = ice_vlan_offload_set(dev, mask);
3401 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3405 /* enable Rx interrput and mapping Rx queue to interrupt vector */
3406 if (ice_rxq_intr_setup(dev))
3409 /* Enable receiving broadcast packets and transmitting packets */
3410 ret = ice_set_vsi_promisc(hw, vsi->idx,
3411 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3412 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3414 if (ret != ICE_SUCCESS)
3415 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3417 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3418 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3419 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3420 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3421 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3422 ICE_AQ_LINK_EVENT_AN_COMPLETED |
3423 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3425 if (ret != ICE_SUCCESS)
3426 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3428 ice_get_init_link_status(dev);
3430 ice_dev_set_link_up(dev);
3432 /* Call get_link_info aq commond to enable/disable LSE */
3433 ice_link_update(dev, 0);
3435 pf->adapter_stopped = false;
3437 /* Set the max frame size to default value*/
3438 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3439 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3442 /* Set the max frame size to HW*/
3443 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3447 /* stop the started queues if failed to start all queues */
3449 for (i = 0; i < nb_rxq; i++)
3450 ice_rx_queue_stop(dev, i);
3452 for (i = 0; i < nb_txq; i++)
3453 ice_tx_queue_stop(dev, i);
3459 ice_dev_reset(struct rte_eth_dev *dev)
3463 if (dev->data->sriov.active)
3466 ret = ice_dev_uninit(dev);
3468 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3472 ret = ice_dev_init(dev);
3474 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3482 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3484 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3485 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486 struct ice_vsi *vsi = pf->main_vsi;
3487 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3488 bool is_safe_mode = pf->adapter->is_safe_mode;
3492 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3493 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3494 dev_info->max_rx_queues = vsi->nb_qps;
3495 dev_info->max_tx_queues = vsi->nb_qps;
3496 dev_info->max_mac_addrs = vsi->max_macaddrs;
3497 dev_info->max_vfs = pci_dev->max_vfs;
3498 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3499 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3501 dev_info->rx_offload_capa =
3502 DEV_RX_OFFLOAD_VLAN_STRIP |
3503 DEV_RX_OFFLOAD_JUMBO_FRAME |
3504 DEV_RX_OFFLOAD_KEEP_CRC |
3505 DEV_RX_OFFLOAD_SCATTER |
3506 DEV_RX_OFFLOAD_VLAN_FILTER;
3507 dev_info->tx_offload_capa =
3508 DEV_TX_OFFLOAD_VLAN_INSERT |
3509 DEV_TX_OFFLOAD_TCP_TSO |
3510 DEV_TX_OFFLOAD_MULTI_SEGS |
3511 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3512 dev_info->flow_type_rss_offloads = 0;
3514 if (!is_safe_mode) {
3515 dev_info->rx_offload_capa |=
3516 DEV_RX_OFFLOAD_IPV4_CKSUM |
3517 DEV_RX_OFFLOAD_UDP_CKSUM |
3518 DEV_RX_OFFLOAD_TCP_CKSUM |
3519 DEV_RX_OFFLOAD_QINQ_STRIP |
3520 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3521 DEV_RX_OFFLOAD_VLAN_EXTEND |
3522 DEV_RX_OFFLOAD_RSS_HASH;
3523 dev_info->tx_offload_capa |=
3524 DEV_TX_OFFLOAD_QINQ_INSERT |
3525 DEV_TX_OFFLOAD_IPV4_CKSUM |
3526 DEV_TX_OFFLOAD_UDP_CKSUM |
3527 DEV_TX_OFFLOAD_TCP_CKSUM |
3528 DEV_TX_OFFLOAD_SCTP_CKSUM |
3529 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3530 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3531 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3534 dev_info->rx_queue_offload_capa = 0;
3535 dev_info->tx_queue_offload_capa = 0;
3537 dev_info->reta_size = pf->hash_lut_size;
3538 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3540 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3542 .pthresh = ICE_DEFAULT_RX_PTHRESH,
3543 .hthresh = ICE_DEFAULT_RX_HTHRESH,
3544 .wthresh = ICE_DEFAULT_RX_WTHRESH,
3546 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3551 dev_info->default_txconf = (struct rte_eth_txconf) {
3553 .pthresh = ICE_DEFAULT_TX_PTHRESH,
3554 .hthresh = ICE_DEFAULT_TX_HTHRESH,
3555 .wthresh = ICE_DEFAULT_TX_WTHRESH,
3557 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3558 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3562 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3563 .nb_max = ICE_MAX_RING_DESC,
3564 .nb_min = ICE_MIN_RING_DESC,
3565 .nb_align = ICE_ALIGN_RING_DESC,
3568 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3569 .nb_max = ICE_MAX_RING_DESC,
3570 .nb_min = ICE_MIN_RING_DESC,
3571 .nb_align = ICE_ALIGN_RING_DESC,
3574 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3575 ETH_LINK_SPEED_100M |
3577 ETH_LINK_SPEED_2_5G |
3579 ETH_LINK_SPEED_10G |
3580 ETH_LINK_SPEED_20G |
3583 phy_type_low = hw->port_info->phy.phy_type_low;
3584 phy_type_high = hw->port_info->phy.phy_type_high;
3586 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3587 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3589 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3590 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3591 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3593 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3594 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3596 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3597 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3598 dev_info->default_rxportconf.nb_queues = 1;
3599 dev_info->default_txportconf.nb_queues = 1;
3600 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3601 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3607 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3608 struct rte_eth_link *link)
3610 struct rte_eth_link *dst = link;
3611 struct rte_eth_link *src = &dev->data->dev_link;
3613 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3614 *(uint64_t *)src) == 0)
3621 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3622 struct rte_eth_link *link)
3624 struct rte_eth_link *dst = &dev->data->dev_link;
3625 struct rte_eth_link *src = link;
3627 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3628 *(uint64_t *)src) == 0)
3635 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3637 #define CHECK_INTERVAL 100 /* 100ms */
3638 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3639 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3640 struct ice_link_status link_status;
3641 struct rte_eth_link link, old;
3643 unsigned int rep_cnt = MAX_REPEAT_TIME;
3644 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3646 memset(&link, 0, sizeof(link));
3647 memset(&old, 0, sizeof(old));
3648 memset(&link_status, 0, sizeof(link_status));
3649 ice_atomic_read_link_status(dev, &old);
3652 /* Get link status information from hardware */
3653 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3654 &link_status, NULL);
3655 if (status != ICE_SUCCESS) {
3656 link.link_speed = ETH_SPEED_NUM_100M;
3657 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3658 PMD_DRV_LOG(ERR, "Failed to get link info");
3662 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3663 if (!wait_to_complete || link.link_status)
3666 rte_delay_ms(CHECK_INTERVAL);
3667 } while (--rep_cnt);
3669 if (!link.link_status)
3672 /* Full-duplex operation at all supported speeds */
3673 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3675 /* Parse the link status */
3676 switch (link_status.link_speed) {
3677 case ICE_AQ_LINK_SPEED_10MB:
3678 link.link_speed = ETH_SPEED_NUM_10M;
3680 case ICE_AQ_LINK_SPEED_100MB:
3681 link.link_speed = ETH_SPEED_NUM_100M;
3683 case ICE_AQ_LINK_SPEED_1000MB:
3684 link.link_speed = ETH_SPEED_NUM_1G;
3686 case ICE_AQ_LINK_SPEED_2500MB:
3687 link.link_speed = ETH_SPEED_NUM_2_5G;
3689 case ICE_AQ_LINK_SPEED_5GB:
3690 link.link_speed = ETH_SPEED_NUM_5G;
3692 case ICE_AQ_LINK_SPEED_10GB:
3693 link.link_speed = ETH_SPEED_NUM_10G;
3695 case ICE_AQ_LINK_SPEED_20GB:
3696 link.link_speed = ETH_SPEED_NUM_20G;
3698 case ICE_AQ_LINK_SPEED_25GB:
3699 link.link_speed = ETH_SPEED_NUM_25G;
3701 case ICE_AQ_LINK_SPEED_40GB:
3702 link.link_speed = ETH_SPEED_NUM_40G;
3704 case ICE_AQ_LINK_SPEED_50GB:
3705 link.link_speed = ETH_SPEED_NUM_50G;
3707 case ICE_AQ_LINK_SPEED_100GB:
3708 link.link_speed = ETH_SPEED_NUM_100G;
3710 case ICE_AQ_LINK_SPEED_UNKNOWN:
3711 PMD_DRV_LOG(ERR, "Unknown link speed");
3712 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3715 PMD_DRV_LOG(ERR, "None link speed");
3716 link.link_speed = ETH_SPEED_NUM_NONE;
3720 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3721 ETH_LINK_SPEED_FIXED);
3724 ice_atomic_write_link_status(dev, &link);
3725 if (link.link_status == old.link_status)
3731 /* Force the physical link state by getting the current PHY capabilities from
3732 * hardware and setting the PHY config based on the determined capabilities. If
3733 * link changes, link event will be triggered because both the Enable Automatic
3734 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3736 static enum ice_status
3737 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3739 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3740 struct ice_aqc_get_phy_caps_data *pcaps;
3741 struct ice_port_info *pi;
3742 enum ice_status status;
3744 if (!hw || !hw->port_info)
3745 return ICE_ERR_PARAM;
3749 pcaps = (struct ice_aqc_get_phy_caps_data *)
3750 ice_malloc(hw, sizeof(*pcaps));
3752 return ICE_ERR_NO_MEMORY;
3754 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3759 /* No change in link */
3760 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3761 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3764 cfg.phy_type_low = pcaps->phy_type_low;
3765 cfg.phy_type_high = pcaps->phy_type_high;
3766 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3767 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3768 cfg.eee_cap = pcaps->eee_cap;
3769 cfg.eeer_value = pcaps->eeer_value;
3770 cfg.link_fec_opt = pcaps->link_fec_options;
3772 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3774 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3776 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3779 ice_free(hw, pcaps);
3784 ice_dev_set_link_up(struct rte_eth_dev *dev)
3786 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3788 return ice_force_phys_link_state(hw, true);
3792 ice_dev_set_link_down(struct rte_eth_dev *dev)
3794 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796 return ice_force_phys_link_state(hw, false);
3800 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3802 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3803 struct rte_eth_dev_data *dev_data = pf->dev_data;
3804 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3806 /* check if mtu is within the allowed range */
3807 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3810 /* mtu setting is forbidden if port is start */
3811 if (dev_data->dev_started) {
3813 "port %d must be stopped before configuration",
3818 if (frame_size > ICE_ETH_MAX_LEN)
3819 dev_data->dev_conf.rxmode.offloads |=
3820 DEV_RX_OFFLOAD_JUMBO_FRAME;
3822 dev_data->dev_conf.rxmode.offloads &=
3823 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3825 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3830 static int ice_macaddr_set(struct rte_eth_dev *dev,
3831 struct rte_ether_addr *mac_addr)
3833 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3834 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3835 struct ice_vsi *vsi = pf->main_vsi;
3836 struct ice_mac_filter *f;
3840 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3841 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3845 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3846 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3851 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3855 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3856 if (ret != ICE_SUCCESS) {
3857 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3860 ret = ice_add_mac_filter(vsi, mac_addr);
3861 if (ret != ICE_SUCCESS) {
3862 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3865 rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3867 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3868 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3869 if (ret != ICE_SUCCESS)
3870 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3875 /* Add a MAC address, and update filters */
3877 ice_macaddr_add(struct rte_eth_dev *dev,
3878 struct rte_ether_addr *mac_addr,
3879 __rte_unused uint32_t index,
3880 __rte_unused uint32_t pool)
3882 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3883 struct ice_vsi *vsi = pf->main_vsi;
3886 ret = ice_add_mac_filter(vsi, mac_addr);
3887 if (ret != ICE_SUCCESS) {
3888 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3895 /* Remove a MAC address, and update filters */
3897 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3899 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3900 struct ice_vsi *vsi = pf->main_vsi;
3901 struct rte_eth_dev_data *data = dev->data;
3902 struct rte_ether_addr *macaddr;
3905 macaddr = &data->mac_addrs[index];
3906 ret = ice_remove_mac_filter(vsi, macaddr);
3908 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3914 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3916 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3917 struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
3918 struct ice_vsi *vsi = pf->main_vsi;
3921 PMD_INIT_FUNC_TRACE();
3924 * Vlan 0 is the generic filter for untagged packets
3925 * and can't be removed or added by user.
3931 ret = ice_add_vlan_filter(vsi, &vlan);
3933 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3937 ret = ice_remove_vlan_filter(vsi, &vlan);
3939 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3947 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
3948 * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
3949 * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
3950 * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
3952 * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
3953 * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
3954 * traffic in SVM, since the VLAN TPID isn't part of filtering.
3956 * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
3957 * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
3958 * part of filtering.
3961 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
3963 struct ice_vlan vlan;
3966 vlan = ICE_VLAN(0, 0);
3967 err = ice_add_vlan_filter(vsi, &vlan);
3969 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
3973 /* in SVM both VLAN 0 filters are identical */
3974 if (!ice_is_dvm_ena(&vsi->adapter->hw))
3977 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3978 err = ice_add_vlan_filter(vsi, &vlan);
3980 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
3988 * Delete the VLAN 0 filters in the same manner that they were added in
3989 * ice_vsi_add_vlan_zero.
3992 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
3994 struct ice_vlan vlan;
3997 vlan = ICE_VLAN(0, 0);
3998 err = ice_remove_vlan_filter(vsi, &vlan);
4000 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
4004 /* in SVM both VLAN 0 filters are identical */
4005 if (!ice_is_dvm_ena(&vsi->adapter->hw))
4008 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4009 err = ice_remove_vlan_filter(vsi, &vlan);
4011 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
4018 /* Configure vlan filter on or off */
4020 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4022 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4023 struct ice_vsi_ctx ctxt;
4027 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4030 vsi->info.sw_flags2 |= sw_flags2;
4032 vsi->info.sw_flags2 &= ~sw_flags2;
4034 vsi->info.sw_id = hw->port_info->sw_id;
4035 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4036 ctxt.info.valid_sections =
4037 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4038 ICE_AQ_VSI_PROP_SECURITY_VALID);
4039 ctxt.vsi_num = vsi->vsi_id;
4041 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4043 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4044 on ? "enable" : "disable");
4047 vsi->info.valid_sections |=
4048 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4049 ICE_AQ_VSI_PROP_SECURITY_VALID);
4052 /* consist with other drivers, allow untagged packet when vlan filter on */
4054 ret = ice_vsi_add_vlan_zero(vsi);
4056 ret = ice_vsi_del_vlan_zero(vsi);
4061 /* Manage VLAN stripping for the VSI for Rx */
4063 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4065 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4066 struct ice_vsi_ctx ctxt;
4067 enum ice_status status;
4070 /* do not allow modifying VLAN stripping when a port VLAN is configured
4073 if (vsi->info.port_based_inner_vlan)
4076 memset(&ctxt, 0, sizeof(ctxt));
4079 /* Strip VLAN tag from Rx packet and put it in the desc */
4080 ctxt.info.inner_vlan_flags =
4081 ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4083 /* Disable stripping. Leave tag in packet */
4084 ctxt.info.inner_vlan_flags =
4085 ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4087 /* Allow all packets untagged/tagged */
4088 ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4090 ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4092 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4094 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4095 ena ? "enable" : "disable");
4098 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4105 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4107 return ice_vsi_manage_vlan_stripping(vsi, true);
4111 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4113 return ice_vsi_manage_vlan_stripping(vsi, false);
4116 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4118 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4119 struct ice_vsi_ctx ctxt;
4120 enum ice_status status;
4123 /* do not allow modifying VLAN stripping when a port VLAN is configured
4126 if (vsi->info.port_based_outer_vlan)
4129 memset(&ctxt, 0, sizeof(ctxt));
4131 ctxt.info.valid_sections =
4132 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4133 /* clear current outer VLAN strip settings */
4134 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4135 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4136 ctxt.info.outer_vlan_flags |=
4137 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4138 ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4139 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4140 ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4142 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4144 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4147 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4154 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4156 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4157 struct ice_vsi_ctx ctxt;
4158 enum ice_status status;
4161 if (vsi->info.port_based_outer_vlan)
4164 memset(&ctxt, 0, sizeof(ctxt));
4166 ctxt.info.valid_sections =
4167 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4168 /* clear current outer VLAN strip settings */
4169 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4170 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4171 ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4172 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4174 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4176 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4179 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4186 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4188 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4191 if (ice_is_dvm_ena(hw)) {
4193 ret = ice_vsi_ena_outer_stripping(vsi);
4195 ret = ice_vsi_dis_outer_stripping(vsi);
4198 ret = ice_vsi_ena_inner_stripping(vsi);
4200 ret = ice_vsi_dis_inner_stripping(vsi);
4207 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4209 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4210 struct ice_vsi *vsi = pf->main_vsi;
4211 struct rte_eth_rxmode *rxmode;
4213 rxmode = &dev->data->dev_conf.rxmode;
4214 if (mask & ETH_VLAN_FILTER_MASK) {
4215 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4216 ice_vsi_config_vlan_filter(vsi, true);
4218 ice_vsi_config_vlan_filter(vsi, false);
4221 if (mask & ETH_VLAN_STRIP_MASK) {
4222 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4223 ice_vsi_config_vlan_stripping(vsi, true);
4225 ice_vsi_config_vlan_stripping(vsi, false);
4232 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4234 struct ice_aq_get_set_rss_lut_params lut_params;
4235 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4236 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4242 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4243 lut_params.vsi_handle = vsi->idx;
4244 lut_params.lut_size = lut_size;
4245 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4246 lut_params.lut = lut;
4247 lut_params.global_lut_id = 0;
4248 ret = ice_aq_get_rss_lut(hw, &lut_params);
4250 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4254 uint64_t *lut_dw = (uint64_t *)lut;
4255 uint16_t i, lut_size_dw = lut_size / 4;
4257 for (i = 0; i < lut_size_dw; i++)
4258 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4265 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4267 struct ice_aq_get_set_rss_lut_params lut_params;
4275 pf = ICE_VSI_TO_PF(vsi);
4276 hw = ICE_VSI_TO_HW(vsi);
4278 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4279 lut_params.vsi_handle = vsi->idx;
4280 lut_params.lut_size = lut_size;
4281 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4282 lut_params.lut = lut;
4283 lut_params.global_lut_id = 0;
4284 ret = ice_aq_set_rss_lut(hw, &lut_params);
4286 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4290 uint64_t *lut_dw = (uint64_t *)lut;
4291 uint16_t i, lut_size_dw = lut_size / 4;
4293 for (i = 0; i < lut_size_dw; i++)
4294 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4303 ice_rss_reta_update(struct rte_eth_dev *dev,
4304 struct rte_eth_rss_reta_entry64 *reta_conf,
4307 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4308 uint16_t i, lut_size = pf->hash_lut_size;
4309 uint16_t idx, shift;
4313 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4314 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4315 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4317 "The size of hash lookup table configured (%d)"
4318 "doesn't match the number hardware can "
4319 "supported (128, 512, 2048)",
4324 /* It MUST use the current LUT size to get the RSS lookup table,
4325 * otherwise if will fail with -100 error code.
4327 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
4329 PMD_DRV_LOG(ERR, "No memory can be allocated");
4332 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4336 for (i = 0; i < reta_size; i++) {
4337 idx = i / RTE_RETA_GROUP_SIZE;
4338 shift = i % RTE_RETA_GROUP_SIZE;
4339 if (reta_conf[idx].mask & (1ULL << shift))
4340 lut[i] = reta_conf[idx].reta[shift];
4342 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4343 if (ret == 0 && lut_size != reta_size) {
4345 "The size of hash lookup table is changed from (%d) to (%d)",
4346 lut_size, reta_size);
4347 pf->hash_lut_size = reta_size;
4357 ice_rss_reta_query(struct rte_eth_dev *dev,
4358 struct rte_eth_rss_reta_entry64 *reta_conf,
4361 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4362 uint16_t i, lut_size = pf->hash_lut_size;
4363 uint16_t idx, shift;
4367 if (reta_size != lut_size) {
4369 "The size of hash lookup table configured (%d)"
4370 "doesn't match the number hardware can "
4372 reta_size, lut_size);
4376 lut = rte_zmalloc(NULL, reta_size, 0);
4378 PMD_DRV_LOG(ERR, "No memory can be allocated");
4382 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4386 for (i = 0; i < reta_size; i++) {
4387 idx = i / RTE_RETA_GROUP_SIZE;
4388 shift = i % RTE_RETA_GROUP_SIZE;
4389 if (reta_conf[idx].mask & (1ULL << shift))
4390 reta_conf[idx].reta[shift] = lut[i];
4400 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4402 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4405 if (!key || key_len == 0) {
4406 PMD_DRV_LOG(DEBUG, "No key to be configured");
4408 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4410 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4414 struct ice_aqc_get_set_rss_keys *key_dw =
4415 (struct ice_aqc_get_set_rss_keys *)key;
4417 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4419 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4427 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4429 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4432 if (!key || !key_len)
4435 ret = ice_aq_get_rss_key
4437 (struct ice_aqc_get_set_rss_keys *)key);
4439 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4442 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4448 ice_rss_hash_update(struct rte_eth_dev *dev,
4449 struct rte_eth_rss_conf *rss_conf)
4451 enum ice_status status = ICE_SUCCESS;
4452 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4453 struct ice_vsi *vsi = pf->main_vsi;
4456 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4460 if (rss_conf->rss_hf == 0)
4463 /* RSS hash configuration */
4464 ice_rss_hash_set(pf, rss_conf->rss_hf);
4470 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4471 struct rte_eth_rss_conf *rss_conf)
4473 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4474 struct ice_vsi *vsi = pf->main_vsi;
4476 ice_get_rss_key(vsi, rss_conf->rss_key,
4477 &rss_conf->rss_key_len);
4479 rss_conf->rss_hf = pf->rss_hf;
4484 ice_promisc_enable(struct rte_eth_dev *dev)
4486 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4487 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4488 struct ice_vsi *vsi = pf->main_vsi;
4489 enum ice_status status;
4493 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4494 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4496 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4498 case ICE_ERR_ALREADY_EXISTS:
4499 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4503 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4511 ice_promisc_disable(struct rte_eth_dev *dev)
4513 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4514 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4515 struct ice_vsi *vsi = pf->main_vsi;
4516 enum ice_status status;
4520 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4521 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4523 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4524 if (status != ICE_SUCCESS) {
4525 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4533 ice_allmulti_enable(struct rte_eth_dev *dev)
4535 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4536 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4537 struct ice_vsi *vsi = pf->main_vsi;
4538 enum ice_status status;
4542 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4544 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4547 case ICE_ERR_ALREADY_EXISTS:
4548 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4552 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4560 ice_allmulti_disable(struct rte_eth_dev *dev)
4562 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4563 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4564 struct ice_vsi *vsi = pf->main_vsi;
4565 enum ice_status status;
4569 if (dev->data->promiscuous == 1)
4570 return 0; /* must remain in all_multicast mode */
4572 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4574 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4575 if (status != ICE_SUCCESS) {
4576 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4583 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4586 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4587 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4588 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4592 msix_intr = intr_handle->intr_vec[queue_id];
4594 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4595 GLINT_DYN_CTL_ITR_INDX_M;
4596 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4598 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4599 rte_intr_ack(&pci_dev->intr_handle);
4604 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4607 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4608 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4609 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4612 msix_intr = intr_handle->intr_vec[queue_id];
4614 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4620 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4622 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4627 ver = hw->flash.orom.major;
4628 patch = hw->flash.orom.patch;
4629 build = hw->flash.orom.build;
4631 ret = snprintf(fw_version, fw_size,
4632 "%x.%02x 0x%08x %d.%d.%d",
4633 hw->flash.nvm.major,
4634 hw->flash.nvm.minor,
4635 hw->flash.nvm.eetrack,
4638 /* add the size of '\0' */
4640 if (fw_size < (u32)ret)
4647 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4650 struct ice_vsi_ctx ctxt;
4651 uint8_t vlan_flags = 0;
4654 if (!vsi || !info) {
4655 PMD_DRV_LOG(ERR, "invalid parameters");
4660 vsi->info.port_based_inner_vlan = info->config.pvid;
4662 * If insert pvid is enabled, only tagged pkts are
4663 * allowed to be sent out.
4665 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4666 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4668 vsi->info.port_based_inner_vlan = 0;
4669 if (info->config.reject.tagged == 0)
4670 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4672 if (info->config.reject.untagged == 0)
4673 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4675 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4676 ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4677 vsi->info.inner_vlan_flags |= vlan_flags;
4678 memset(&ctxt, 0, sizeof(ctxt));
4679 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4680 ctxt.info.valid_sections =
4681 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4682 ctxt.vsi_num = vsi->vsi_id;
4684 hw = ICE_VSI_TO_HW(vsi);
4685 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4686 if (ret != ICE_SUCCESS) {
4688 "update VSI for VLAN insert failed, err %d",
4693 vsi->info.valid_sections |=
4694 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4700 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4702 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4703 struct ice_vsi *vsi = pf->main_vsi;
4704 struct rte_eth_dev_data *data = pf->dev_data;
4705 struct ice_vsi_vlan_pvid_info info;
4708 memset(&info, 0, sizeof(info));
4711 info.config.pvid = pvid;
4713 info.config.reject.tagged =
4714 data->dev_conf.txmode.hw_vlan_reject_tagged;
4715 info.config.reject.untagged =
4716 data->dev_conf.txmode.hw_vlan_reject_untagged;
4719 ret = ice_vsi_vlan_pvid_set(vsi, &info);
4721 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4729 ice_get_eeprom_length(struct rte_eth_dev *dev)
4731 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4733 return hw->flash.flash_size;
4737 ice_get_eeprom(struct rte_eth_dev *dev,
4738 struct rte_dev_eeprom_info *eeprom)
4740 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4741 enum ice_status status = ICE_SUCCESS;
4742 uint8_t *data = eeprom->data;
4744 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4746 status = ice_acquire_nvm(hw, ICE_RES_READ);
4748 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4752 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4755 ice_release_nvm(hw);
4758 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4766 ice_stat_update_32(struct ice_hw *hw,
4774 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4778 if (new_data >= *offset)
4779 *stat = (uint64_t)(new_data - *offset);
4781 *stat = (uint64_t)((new_data +
4782 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4787 ice_stat_update_40(struct ice_hw *hw,
4796 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4797 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4803 if (new_data >= *offset)
4804 *stat = new_data - *offset;
4806 *stat = (uint64_t)((new_data +
4807 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4810 *stat &= ICE_40_BIT_MASK;
4813 /* Get all the statistics of a VSI */
4815 ice_update_vsi_stats(struct ice_vsi *vsi)
4817 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4818 struct ice_eth_stats *nes = &vsi->eth_stats;
4819 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4820 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4822 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4823 vsi->offset_loaded, &oes->rx_bytes,
4825 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4826 vsi->offset_loaded, &oes->rx_unicast,
4828 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4829 vsi->offset_loaded, &oes->rx_multicast,
4830 &nes->rx_multicast);
4831 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4832 vsi->offset_loaded, &oes->rx_broadcast,
4833 &nes->rx_broadcast);
4834 /* enlarge the limitation when rx_bytes overflowed */
4835 if (vsi->offset_loaded) {
4836 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4837 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4838 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4840 vsi->old_rx_bytes = nes->rx_bytes;
4841 /* exclude CRC bytes */
4842 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4843 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4845 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4846 &oes->rx_discards, &nes->rx_discards);
4847 /* GLV_REPC not supported */
4848 /* GLV_RMPC not supported */
4849 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4850 &oes->rx_unknown_protocol,
4851 &nes->rx_unknown_protocol);
4852 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4853 vsi->offset_loaded, &oes->tx_bytes,
4855 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4856 vsi->offset_loaded, &oes->tx_unicast,
4858 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4859 vsi->offset_loaded, &oes->tx_multicast,
4860 &nes->tx_multicast);
4861 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4862 vsi->offset_loaded, &oes->tx_broadcast,
4863 &nes->tx_broadcast);
4864 /* GLV_TDPC not supported */
4865 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4866 &oes->tx_errors, &nes->tx_errors);
4867 /* enlarge the limitation when tx_bytes overflowed */
4868 if (vsi->offset_loaded) {
4869 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4870 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4871 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4873 vsi->old_tx_bytes = nes->tx_bytes;
4874 vsi->offset_loaded = true;
4876 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4878 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4879 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4880 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4881 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4882 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4883 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4884 nes->rx_unknown_protocol);
4885 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4886 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4887 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4888 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4889 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4890 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4891 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4896 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4898 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4899 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4901 /* Get statistics of struct ice_eth_stats */
4902 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4903 GLPRT_GORCL(hw->port_info->lport),
4904 pf->offset_loaded, &os->eth.rx_bytes,
4906 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4907 GLPRT_UPRCL(hw->port_info->lport),
4908 pf->offset_loaded, &os->eth.rx_unicast,
4909 &ns->eth.rx_unicast);
4910 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4911 GLPRT_MPRCL(hw->port_info->lport),
4912 pf->offset_loaded, &os->eth.rx_multicast,
4913 &ns->eth.rx_multicast);
4914 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4915 GLPRT_BPRCL(hw->port_info->lport),
4916 pf->offset_loaded, &os->eth.rx_broadcast,
4917 &ns->eth.rx_broadcast);
4918 ice_stat_update_32(hw, PRTRPB_RDPC,
4919 pf->offset_loaded, &os->eth.rx_discards,
4920 &ns->eth.rx_discards);
4921 /* enlarge the limitation when rx_bytes overflowed */
4922 if (pf->offset_loaded) {
4923 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4924 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4925 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4927 pf->old_rx_bytes = ns->eth.rx_bytes;
4929 /* Workaround: CRC size should not be included in byte statistics,
4930 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4933 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4934 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4936 /* GLPRT_REPC not supported */
4937 /* GLPRT_RMPC not supported */
4938 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4940 &os->eth.rx_unknown_protocol,
4941 &ns->eth.rx_unknown_protocol);
4942 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4943 GLPRT_GOTCL(hw->port_info->lport),
4944 pf->offset_loaded, &os->eth.tx_bytes,
4946 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4947 GLPRT_UPTCL(hw->port_info->lport),
4948 pf->offset_loaded, &os->eth.tx_unicast,
4949 &ns->eth.tx_unicast);
4950 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4951 GLPRT_MPTCL(hw->port_info->lport),
4952 pf->offset_loaded, &os->eth.tx_multicast,
4953 &ns->eth.tx_multicast);
4954 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4955 GLPRT_BPTCL(hw->port_info->lport),
4956 pf->offset_loaded, &os->eth.tx_broadcast,
4957 &ns->eth.tx_broadcast);
4958 /* enlarge the limitation when tx_bytes overflowed */
4959 if (pf->offset_loaded) {
4960 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4961 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4962 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4964 pf->old_tx_bytes = ns->eth.tx_bytes;
4965 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4966 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4968 /* GLPRT_TEPC not supported */
4970 /* additional port specific stats */
4971 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4972 pf->offset_loaded, &os->tx_dropped_link_down,
4973 &ns->tx_dropped_link_down);
4974 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4975 pf->offset_loaded, &os->crc_errors,
4977 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4978 pf->offset_loaded, &os->illegal_bytes,
4979 &ns->illegal_bytes);
4980 /* GLPRT_ERRBC not supported */
4981 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4982 pf->offset_loaded, &os->mac_local_faults,
4983 &ns->mac_local_faults);
4984 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4985 pf->offset_loaded, &os->mac_remote_faults,
4986 &ns->mac_remote_faults);
4988 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4989 pf->offset_loaded, &os->rx_len_errors,
4990 &ns->rx_len_errors);
4992 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4993 pf->offset_loaded, &os->link_xon_rx,
4995 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4996 pf->offset_loaded, &os->link_xoff_rx,
4998 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4999 pf->offset_loaded, &os->link_xon_tx,
5001 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
5002 pf->offset_loaded, &os->link_xoff_tx,
5004 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
5005 GLPRT_PRC64L(hw->port_info->lport),
5006 pf->offset_loaded, &os->rx_size_64,
5008 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
5009 GLPRT_PRC127L(hw->port_info->lport),
5010 pf->offset_loaded, &os->rx_size_127,
5012 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
5013 GLPRT_PRC255L(hw->port_info->lport),
5014 pf->offset_loaded, &os->rx_size_255,
5016 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
5017 GLPRT_PRC511L(hw->port_info->lport),
5018 pf->offset_loaded, &os->rx_size_511,
5020 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
5021 GLPRT_PRC1023L(hw->port_info->lport),
5022 pf->offset_loaded, &os->rx_size_1023,
5024 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
5025 GLPRT_PRC1522L(hw->port_info->lport),
5026 pf->offset_loaded, &os->rx_size_1522,
5028 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
5029 GLPRT_PRC9522L(hw->port_info->lport),
5030 pf->offset_loaded, &os->rx_size_big,
5032 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
5033 pf->offset_loaded, &os->rx_undersize,
5035 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
5036 pf->offset_loaded, &os->rx_fragments,
5038 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5039 pf->offset_loaded, &os->rx_oversize,
5041 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5042 pf->offset_loaded, &os->rx_jabber,
5044 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5045 GLPRT_PTC64L(hw->port_info->lport),
5046 pf->offset_loaded, &os->tx_size_64,
5048 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5049 GLPRT_PTC127L(hw->port_info->lport),
5050 pf->offset_loaded, &os->tx_size_127,
5052 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5053 GLPRT_PTC255L(hw->port_info->lport),
5054 pf->offset_loaded, &os->tx_size_255,
5056 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5057 GLPRT_PTC511L(hw->port_info->lport),
5058 pf->offset_loaded, &os->tx_size_511,
5060 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5061 GLPRT_PTC1023L(hw->port_info->lport),
5062 pf->offset_loaded, &os->tx_size_1023,
5064 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5065 GLPRT_PTC1522L(hw->port_info->lport),
5066 pf->offset_loaded, &os->tx_size_1522,
5068 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5069 GLPRT_PTC9522L(hw->port_info->lport),
5070 pf->offset_loaded, &os->tx_size_big,
5073 /* GLPRT_MSPDC not supported */
5074 /* GLPRT_XEC not supported */
5076 pf->offset_loaded = true;
5079 ice_update_vsi_stats(pf->main_vsi);
5082 /* Get all statistics of a port */
5084 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5086 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5087 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5088 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5090 /* call read registers - updates values, now write them to struct */
5091 ice_read_stats_registers(pf, hw);
5093 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5094 pf->main_vsi->eth_stats.rx_multicast +
5095 pf->main_vsi->eth_stats.rx_broadcast -
5096 pf->main_vsi->eth_stats.rx_discards;
5097 stats->opackets = ns->eth.tx_unicast +
5098 ns->eth.tx_multicast +
5099 ns->eth.tx_broadcast;
5100 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
5101 stats->obytes = ns->eth.tx_bytes;
5102 stats->oerrors = ns->eth.tx_errors +
5103 pf->main_vsi->eth_stats.tx_errors;
5106 stats->imissed = ns->eth.rx_discards +
5107 pf->main_vsi->eth_stats.rx_discards;
5108 stats->ierrors = ns->crc_errors +
5110 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5112 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5113 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
5114 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5115 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5116 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5117 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5118 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5119 pf->main_vsi->eth_stats.rx_discards);
5120 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5121 ns->eth.rx_unknown_protocol);
5122 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
5123 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5124 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5125 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5126 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5127 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5128 pf->main_vsi->eth_stats.tx_discards);
5129 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
5131 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
5132 ns->tx_dropped_link_down);
5133 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5134 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
5136 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
5137 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
5138 ns->mac_local_faults);
5139 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
5140 ns->mac_remote_faults);
5141 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
5142 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
5143 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
5144 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
5145 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
5146 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
5147 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
5148 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
5149 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
5150 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
5151 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
5152 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
5153 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
5154 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
5155 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
5156 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
5157 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
5158 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
5159 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
5160 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
5161 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
5162 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
5163 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
5164 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5168 /* Reset the statistics */
5170 ice_stats_reset(struct rte_eth_dev *dev)
5172 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5173 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5175 /* Mark PF and VSI stats to update the offset, aka "reset" */
5176 pf->offset_loaded = false;
5178 pf->main_vsi->offset_loaded = false;
5180 /* read the stats, reading current register values into offset */
5181 ice_read_stats_registers(pf, hw);
5187 ice_xstats_calc_num(void)
5191 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5197 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5200 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5201 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5204 struct ice_hw_port_stats *hw_stats = &pf->stats;
5206 count = ice_xstats_calc_num();
5210 ice_read_stats_registers(pf, hw);
5217 /* Get stats from ice_eth_stats struct */
5218 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5219 xstats[count].value =
5220 *(uint64_t *)((char *)&hw_stats->eth +
5221 ice_stats_strings[i].offset);
5222 xstats[count].id = count;
5226 /* Get individiual stats from ice_hw_port struct */
5227 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5228 xstats[count].value =
5229 *(uint64_t *)((char *)hw_stats +
5230 ice_hw_port_strings[i].offset);
5231 xstats[count].id = count;
5238 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5239 struct rte_eth_xstat_name *xstats_names,
5240 __rte_unused unsigned int limit)
5242 unsigned int count = 0;
5246 return ice_xstats_calc_num();
5248 /* Note: limit checked in rte_eth_xstats_names() */
5250 /* Get stats from ice_eth_stats struct */
5251 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5252 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5253 sizeof(xstats_names[count].name));
5257 /* Get individiual stats from ice_hw_port struct */
5258 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5259 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5260 sizeof(xstats_names[count].name));
5268 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
5269 enum rte_filter_type filter_type,
5270 enum rte_filter_op filter_op,
5278 switch (filter_type) {
5279 case RTE_ETH_FILTER_GENERIC:
5280 if (filter_op != RTE_ETH_FILTER_GET)
5282 *(const void **)arg = &ice_flow_ops;
5285 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5294 /* Add UDP tunneling port */
5296 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5297 struct rte_eth_udp_tunnel *udp_tunnel)
5300 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5302 if (udp_tunnel == NULL)
5305 switch (udp_tunnel->prot_type) {
5306 case RTE_TUNNEL_TYPE_VXLAN:
5307 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5310 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5318 /* Delete UDP tunneling port */
5320 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5321 struct rte_eth_udp_tunnel *udp_tunnel)
5324 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5326 if (udp_tunnel == NULL)
5329 switch (udp_tunnel->prot_type) {
5330 case RTE_TUNNEL_TYPE_VXLAN:
5331 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5334 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5343 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5344 struct rte_pci_device *pci_dev)
5346 return rte_eth_dev_pci_generic_probe(pci_dev,
5347 sizeof(struct ice_adapter),
5352 ice_pci_remove(struct rte_pci_device *pci_dev)
5354 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5357 static struct rte_pci_driver rte_ice_pmd = {
5358 .id_table = pci_id_ice_map,
5359 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5360 .probe = ice_pci_probe,
5361 .remove = ice_pci_remove,
5365 * Driver initialization routine.
5366 * Invoked once at EAL init time.
5367 * Register itself as the [Poll Mode] Driver of PCI devices.
5369 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5370 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5371 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5372 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5373 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5374 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5375 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5377 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5378 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5379 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5380 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5382 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5383 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5385 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5386 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);