1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "ice_ethdev.h"
18 #include "ice_switch_filter.h"
20 #define ICE_MAX_QP_NUM "max_queue_pair_num"
21 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
22 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg"
25 int ice_logtype_driver;
27 static int ice_dev_configure(struct rte_eth_dev *dev);
28 static int ice_dev_start(struct rte_eth_dev *dev);
29 static void ice_dev_stop(struct rte_eth_dev *dev);
30 static void ice_dev_close(struct rte_eth_dev *dev);
31 static int ice_dev_reset(struct rte_eth_dev *dev);
32 static void ice_dev_info_get(struct rte_eth_dev *dev,
33 struct rte_eth_dev_info *dev_info);
34 static int ice_link_update(struct rte_eth_dev *dev,
35 int wait_to_complete);
36 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
37 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
39 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
40 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
41 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
42 enum rte_vlan_type vlan_type,
44 static int ice_rss_reta_update(struct rte_eth_dev *dev,
45 struct rte_eth_rss_reta_entry64 *reta_conf,
47 static int ice_rss_reta_query(struct rte_eth_dev *dev,
48 struct rte_eth_rss_reta_entry64 *reta_conf,
50 static int ice_rss_hash_update(struct rte_eth_dev *dev,
51 struct rte_eth_rss_conf *rss_conf);
52 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
53 struct rte_eth_rss_conf *rss_conf);
54 static void ice_promisc_enable(struct rte_eth_dev *dev);
55 static void ice_promisc_disable(struct rte_eth_dev *dev);
56 static void ice_allmulti_enable(struct rte_eth_dev *dev);
57 static void ice_allmulti_disable(struct rte_eth_dev *dev);
58 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
61 static int ice_macaddr_set(struct rte_eth_dev *dev,
62 struct rte_ether_addr *mac_addr);
63 static int ice_macaddr_add(struct rte_eth_dev *dev,
64 struct rte_ether_addr *mac_addr,
65 __rte_unused uint32_t index,
67 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
68 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
70 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
72 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
74 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
75 uint16_t pvid, int on);
76 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
77 static int ice_get_eeprom(struct rte_eth_dev *dev,
78 struct rte_dev_eeprom_info *eeprom);
79 static int ice_stats_get(struct rte_eth_dev *dev,
80 struct rte_eth_stats *stats);
81 static void ice_stats_reset(struct rte_eth_dev *dev);
82 static int ice_xstats_get(struct rte_eth_dev *dev,
83 struct rte_eth_xstat *xstats, unsigned int n);
84 static int ice_xstats_get_names(struct rte_eth_dev *dev,
85 struct rte_eth_xstat_name *xstats_names,
87 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
88 enum rte_filter_type filter_type,
89 enum rte_filter_op filter_op,
91 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
92 struct rte_eth_udp_tunnel *udp_tunnel);
93 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
94 struct rte_eth_udp_tunnel *udp_tunnel);
96 static const struct rte_pci_id pci_id_ice_map[] = {
97 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
98 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
99 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
100 { .vendor_id = 0, /* sentinel */ },
103 static const struct eth_dev_ops ice_eth_dev_ops = {
104 .dev_configure = ice_dev_configure,
105 .dev_start = ice_dev_start,
106 .dev_stop = ice_dev_stop,
107 .dev_close = ice_dev_close,
108 .dev_reset = ice_dev_reset,
109 .dev_set_link_up = ice_dev_set_link_up,
110 .dev_set_link_down = ice_dev_set_link_down,
111 .rx_queue_start = ice_rx_queue_start,
112 .rx_queue_stop = ice_rx_queue_stop,
113 .tx_queue_start = ice_tx_queue_start,
114 .tx_queue_stop = ice_tx_queue_stop,
115 .rx_queue_setup = ice_rx_queue_setup,
116 .rx_queue_release = ice_rx_queue_release,
117 .tx_queue_setup = ice_tx_queue_setup,
118 .tx_queue_release = ice_tx_queue_release,
119 .dev_infos_get = ice_dev_info_get,
120 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
121 .link_update = ice_link_update,
122 .mtu_set = ice_mtu_set,
123 .mac_addr_set = ice_macaddr_set,
124 .mac_addr_add = ice_macaddr_add,
125 .mac_addr_remove = ice_macaddr_remove,
126 .vlan_filter_set = ice_vlan_filter_set,
127 .vlan_offload_set = ice_vlan_offload_set,
128 .vlan_tpid_set = ice_vlan_tpid_set,
129 .reta_update = ice_rss_reta_update,
130 .reta_query = ice_rss_reta_query,
131 .rss_hash_update = ice_rss_hash_update,
132 .rss_hash_conf_get = ice_rss_hash_conf_get,
133 .promiscuous_enable = ice_promisc_enable,
134 .promiscuous_disable = ice_promisc_disable,
135 .allmulticast_enable = ice_allmulti_enable,
136 .allmulticast_disable = ice_allmulti_disable,
137 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
138 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
139 .fw_version_get = ice_fw_version_get,
140 .vlan_pvid_set = ice_vlan_pvid_set,
141 .rxq_info_get = ice_rxq_info_get,
142 .txq_info_get = ice_txq_info_get,
143 .get_eeprom_length = ice_get_eeprom_length,
144 .get_eeprom = ice_get_eeprom,
145 .rx_queue_count = ice_rx_queue_count,
146 .rx_descriptor_status = ice_rx_descriptor_status,
147 .tx_descriptor_status = ice_tx_descriptor_status,
148 .stats_get = ice_stats_get,
149 .stats_reset = ice_stats_reset,
150 .xstats_get = ice_xstats_get,
151 .xstats_get_names = ice_xstats_get_names,
152 .xstats_reset = ice_stats_reset,
153 .filter_ctrl = ice_dev_filter_ctrl,
154 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
155 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
158 /* store statistics names and its offset in stats structure */
159 struct ice_xstats_name_off {
160 char name[RTE_ETH_XSTATS_NAME_SIZE];
164 static const struct ice_xstats_name_off ice_stats_strings[] = {
165 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
166 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
167 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
168 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
169 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
170 rx_unknown_protocol)},
171 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
172 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
173 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
174 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
177 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
178 sizeof(ice_stats_strings[0]))
180 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
181 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
182 tx_dropped_link_down)},
183 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
184 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
186 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
187 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
189 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
191 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
193 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
194 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
195 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
196 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
197 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
198 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
200 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
202 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
204 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
206 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
208 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
210 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
212 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
214 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
215 mac_short_pkt_dropped)},
216 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
218 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
219 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
220 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
222 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
224 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
226 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
228 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
230 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
234 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
235 sizeof(ice_hw_port_strings[0]))
238 ice_init_controlq_parameter(struct ice_hw *hw)
240 /* fields for adminq */
241 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
242 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
243 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
244 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
246 /* fields for mailboxq, DPDK used as PF host */
247 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
248 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
249 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
250 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
254 ice_check_qp_num(const char *key, const char *qp_value,
255 __rte_unused void *opaque)
260 while (isblank(*qp_value))
263 num = strtoul(qp_value, &end, 10);
265 if (!num || (*end == '-') || errno) {
266 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
276 ice_config_max_queue_pair_num(struct rte_devargs *devargs)
278 struct rte_kvargs *kvlist;
279 const char *queue_num_key = ICE_MAX_QP_NUM;
285 kvlist = rte_kvargs_parse(devargs->args, NULL);
289 if (!rte_kvargs_count(kvlist, queue_num_key)) {
290 rte_kvargs_free(kvlist);
294 if (rte_kvargs_process(kvlist, queue_num_key,
295 ice_check_qp_num, NULL) < 0) {
296 rte_kvargs_free(kvlist);
299 ret = rte_kvargs_process(kvlist, queue_num_key,
300 ice_check_qp_num, NULL);
301 rte_kvargs_free(kvlist);
307 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
310 struct pool_entry *entry;
315 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
318 "Failed to allocate memory for resource pool");
322 /* queue heap initialize */
323 pool->num_free = num;
326 LIST_INIT(&pool->alloc_list);
327 LIST_INIT(&pool->free_list);
329 /* Initialize element */
333 LIST_INSERT_HEAD(&pool->free_list, entry, next);
338 ice_res_pool_alloc(struct ice_res_pool_info *pool,
341 struct pool_entry *entry, *valid_entry;
344 PMD_INIT_LOG(ERR, "Invalid parameter");
348 if (pool->num_free < num) {
349 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
350 num, pool->num_free);
355 /* Lookup in free list and find most fit one */
356 LIST_FOREACH(entry, &pool->free_list, next) {
357 if (entry->len >= num) {
359 if (entry->len == num) {
364 valid_entry->len > entry->len)
369 /* Not find one to satisfy the request, return */
371 PMD_INIT_LOG(ERR, "No valid entry found");
375 * The entry have equal queue number as requested,
376 * remove it from alloc_list.
378 if (valid_entry->len == num) {
379 LIST_REMOVE(valid_entry, next);
382 * The entry have more numbers than requested,
383 * create a new entry for alloc_list and minus its
384 * queue base and number in free_list.
386 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
389 "Failed to allocate memory for "
393 entry->base = valid_entry->base;
395 valid_entry->base += num;
396 valid_entry->len -= num;
400 /* Insert it into alloc list, not sorted */
401 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
403 pool->num_free -= valid_entry->len;
404 pool->num_alloc += valid_entry->len;
406 return valid_entry->base + pool->base;
410 ice_res_pool_destroy(struct ice_res_pool_info *pool)
412 struct pool_entry *entry, *next_entry;
417 for (entry = LIST_FIRST(&pool->alloc_list);
418 entry && (next_entry = LIST_NEXT(entry, next), 1);
419 entry = next_entry) {
420 LIST_REMOVE(entry, next);
424 for (entry = LIST_FIRST(&pool->free_list);
425 entry && (next_entry = LIST_NEXT(entry, next), 1);
426 entry = next_entry) {
427 LIST_REMOVE(entry, next);
434 LIST_INIT(&pool->alloc_list);
435 LIST_INIT(&pool->free_list);
439 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
441 /* Set VSI LUT selection */
442 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
443 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
444 /* Set Hash scheme */
445 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
446 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
448 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
451 static enum ice_status
452 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
453 struct ice_aqc_vsi_props *info,
454 uint8_t enabled_tcmap)
456 uint16_t bsf, qp_idx;
458 /* default tc 0 now. Multi-TC supporting need to be done later.
459 * Configure TC and queue mapping parameters, for enabled TC,
460 * allocate qpnum_per_tc queues to this traffic.
462 if (enabled_tcmap != 0x01) {
463 PMD_INIT_LOG(ERR, "only TC0 is supported");
467 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
468 bsf = rte_bsf32(vsi->nb_qps);
469 /* Adjust the queue number to actual queues that can be applied */
470 vsi->nb_qps = 0x1 << bsf;
473 /* Set tc and queue mapping with VSI */
474 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
475 ICE_AQ_VSI_TC_Q_OFFSET_S) |
476 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
478 /* Associate queue number with VSI */
479 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
480 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
481 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
482 info->valid_sections |=
483 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
484 /* Set the info.ingress_table and info.egress_table
485 * for UP translate table. Now just set it to 1:1 map by default
486 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
488 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
489 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
490 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
491 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
496 ice_init_mac_address(struct rte_eth_dev *dev)
498 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
500 if (!rte_is_unicast_ether_addr
501 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
502 PMD_INIT_LOG(ERR, "Invalid MAC address");
507 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
508 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
510 dev->data->mac_addrs =
511 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
512 if (!dev->data->mac_addrs) {
514 "Failed to allocate memory to store mac address");
517 /* store it to dev data */
519 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
520 &dev->data->mac_addrs[0]);
524 /* Find out specific MAC filter */
525 static struct ice_mac_filter *
526 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
528 struct ice_mac_filter *f;
530 TAILQ_FOREACH(f, &vsi->mac_list, next) {
531 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
539 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
541 struct ice_fltr_list_entry *m_list_itr = NULL;
542 struct ice_mac_filter *f;
543 struct LIST_HEAD_TYPE list_head;
544 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
547 /* If it's added and configured, return */
548 f = ice_find_mac_filter(vsi, mac_addr);
550 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
554 INIT_LIST_HEAD(&list_head);
556 m_list_itr = (struct ice_fltr_list_entry *)
557 ice_malloc(hw, sizeof(*m_list_itr));
562 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
563 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
564 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
565 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
566 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
567 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
568 m_list_itr->fltr_info.vsi_handle = vsi->idx;
570 LIST_ADD(&m_list_itr->list_entry, &list_head);
573 ret = ice_add_mac(hw, &list_head);
574 if (ret != ICE_SUCCESS) {
575 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
579 /* Add the mac addr into mac list */
580 f = rte_zmalloc(NULL, sizeof(*f), 0);
582 PMD_DRV_LOG(ERR, "failed to allocate memory");
586 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
587 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
593 rte_free(m_list_itr);
598 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
600 struct ice_fltr_list_entry *m_list_itr = NULL;
601 struct ice_mac_filter *f;
602 struct LIST_HEAD_TYPE list_head;
603 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
606 /* Can't find it, return an error */
607 f = ice_find_mac_filter(vsi, mac_addr);
611 INIT_LIST_HEAD(&list_head);
613 m_list_itr = (struct ice_fltr_list_entry *)
614 ice_malloc(hw, sizeof(*m_list_itr));
619 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
620 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
621 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
622 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
623 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
624 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
625 m_list_itr->fltr_info.vsi_handle = vsi->idx;
627 LIST_ADD(&m_list_itr->list_entry, &list_head);
629 /* remove the mac filter */
630 ret = ice_remove_mac(hw, &list_head);
631 if (ret != ICE_SUCCESS) {
632 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
637 /* Remove the mac addr from mac list */
638 TAILQ_REMOVE(&vsi->mac_list, f, next);
644 rte_free(m_list_itr);
648 /* Find out specific VLAN filter */
649 static struct ice_vlan_filter *
650 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
652 struct ice_vlan_filter *f;
654 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
655 if (vlan_id == f->vlan_info.vlan_id)
663 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
665 struct ice_fltr_list_entry *v_list_itr = NULL;
666 struct ice_vlan_filter *f;
667 struct LIST_HEAD_TYPE list_head;
671 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
674 hw = ICE_VSI_TO_HW(vsi);
676 /* If it's added and configured, return. */
677 f = ice_find_vlan_filter(vsi, vlan_id);
679 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
683 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
686 INIT_LIST_HEAD(&list_head);
688 v_list_itr = (struct ice_fltr_list_entry *)
689 ice_malloc(hw, sizeof(*v_list_itr));
694 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
695 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
696 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
697 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
698 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
699 v_list_itr->fltr_info.vsi_handle = vsi->idx;
701 LIST_ADD(&v_list_itr->list_entry, &list_head);
704 ret = ice_add_vlan(hw, &list_head);
705 if (ret != ICE_SUCCESS) {
706 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
711 /* Add vlan into vlan list */
712 f = rte_zmalloc(NULL, sizeof(*f), 0);
714 PMD_DRV_LOG(ERR, "failed to allocate memory");
718 f->vlan_info.vlan_id = vlan_id;
719 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
725 rte_free(v_list_itr);
730 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
732 struct ice_fltr_list_entry *v_list_itr = NULL;
733 struct ice_vlan_filter *f;
734 struct LIST_HEAD_TYPE list_head;
739 * Vlan 0 is the generic filter for untagged packets
740 * and can't be removed.
742 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
745 hw = ICE_VSI_TO_HW(vsi);
747 /* Can't find it, return an error */
748 f = ice_find_vlan_filter(vsi, vlan_id);
752 INIT_LIST_HEAD(&list_head);
754 v_list_itr = (struct ice_fltr_list_entry *)
755 ice_malloc(hw, sizeof(*v_list_itr));
761 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
762 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
763 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
764 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
765 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
766 v_list_itr->fltr_info.vsi_handle = vsi->idx;
768 LIST_ADD(&v_list_itr->list_entry, &list_head);
770 /* remove the vlan filter */
771 ret = ice_remove_vlan(hw, &list_head);
772 if (ret != ICE_SUCCESS) {
773 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
778 /* Remove the vlan id from vlan list */
779 TAILQ_REMOVE(&vsi->vlan_list, f, next);
785 rte_free(v_list_itr);
790 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
792 struct ice_mac_filter *m_f;
793 struct ice_vlan_filter *v_f;
796 if (!vsi || !vsi->mac_num)
799 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
800 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
801 if (ret != ICE_SUCCESS) {
807 if (vsi->vlan_num == 0)
810 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
811 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
812 if (ret != ICE_SUCCESS) {
823 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
825 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
826 struct ice_vsi_ctx ctxt;
830 /* Check if it has been already on or off */
831 if (vsi->info.valid_sections &
832 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
834 if ((vsi->info.outer_tag_flags &
835 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
836 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
837 return 0; /* already on */
839 if (!(vsi->info.outer_tag_flags &
840 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
841 return 0; /* already off */
846 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
849 /* clear global insertion and use per packet insertion */
850 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
851 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
852 vsi->info.outer_tag_flags |= qinq_flags;
853 /* use default vlan type 0x8100 */
854 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
855 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
856 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
857 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
858 ctxt.info.valid_sections =
859 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
860 ctxt.vsi_num = vsi->vsi_id;
861 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
864 "Update VSI failed to %s qinq stripping",
865 on ? "enable" : "disable");
869 vsi->info.valid_sections |=
870 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
876 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
878 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
879 struct ice_vsi_ctx ctxt;
883 /* Check if it has been already on or off */
884 if (vsi->info.valid_sections &
885 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
887 if ((vsi->info.outer_tag_flags &
888 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
889 ICE_AQ_VSI_OUTER_TAG_COPY)
890 return 0; /* already on */
892 if ((vsi->info.outer_tag_flags &
893 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
894 ICE_AQ_VSI_OUTER_TAG_NOTHING)
895 return 0; /* already off */
900 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
902 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
903 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
904 vsi->info.outer_tag_flags |= qinq_flags;
905 /* use default vlan type 0x8100 */
906 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
907 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
908 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
909 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
910 ctxt.info.valid_sections =
911 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
912 ctxt.vsi_num = vsi->vsi_id;
913 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
916 "Update VSI failed to %s qinq stripping",
917 on ? "enable" : "disable");
921 vsi->info.valid_sections |=
922 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
928 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
932 ret = ice_vsi_config_qinq_stripping(vsi, on);
934 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
936 ret = ice_vsi_config_qinq_insertion(vsi, on);
938 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
945 ice_pf_enable_irq0(struct ice_hw *hw)
947 /* reset the registers */
948 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
949 ICE_READ_REG(hw, PFINT_OICR);
952 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
953 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
954 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
956 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
957 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
958 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
959 PFINT_OICR_CTL_ITR_INDX_M) |
960 PFINT_OICR_CTL_CAUSE_ENA_M);
962 ICE_WRITE_REG(hw, PFINT_FW_CTL,
963 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
964 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
965 PFINT_FW_CTL_ITR_INDX_M) |
966 PFINT_FW_CTL_CAUSE_ENA_M);
968 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
971 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
972 GLINT_DYN_CTL_INTENA_M |
973 GLINT_DYN_CTL_CLEARPBA_M |
974 GLINT_DYN_CTL_ITR_INDX_M);
981 ice_pf_disable_irq0(struct ice_hw *hw)
983 /* Disable all interrupt types */
984 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
990 ice_handle_aq_msg(struct rte_eth_dev *dev)
992 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
993 struct ice_ctl_q_info *cq = &hw->adminq;
994 struct ice_rq_event_info event;
995 uint16_t pending, opcode;
998 event.buf_len = ICE_AQ_MAX_BUF_LEN;
999 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1000 if (!event.msg_buf) {
1001 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1007 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1009 if (ret != ICE_SUCCESS) {
1011 "Failed to read msg from AdminQ, "
1013 hw->adminq.sq_last_status);
1016 opcode = rte_le_to_cpu_16(event.desc.opcode);
1019 case ice_aqc_opc_get_link_status:
1020 ret = ice_link_update(dev, 0);
1022 _rte_eth_dev_callback_process
1023 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1026 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1031 rte_free(event.msg_buf);
1036 * Interrupt handler triggered by NIC for handling
1037 * specific interrupt.
1040 * Pointer to interrupt handle.
1042 * The address of parameter (struct rte_eth_dev *) regsitered before.
1048 ice_interrupt_handler(void *param)
1050 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1051 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1058 uint32_t int_fw_ctl;
1061 /* Disable interrupt */
1062 ice_pf_disable_irq0(hw);
1064 /* read out interrupt causes */
1065 oicr = ICE_READ_REG(hw, PFINT_OICR);
1067 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1070 /* No interrupt event indicated */
1071 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1072 PMD_DRV_LOG(INFO, "No interrupt event");
1077 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1078 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1079 ice_handle_aq_msg(dev);
1082 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1083 PMD_DRV_LOG(INFO, "OICR: link state change event");
1084 ice_link_update(dev, 0);
1088 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1089 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1090 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1091 if (reg & GL_MDET_TX_PQM_VALID_M) {
1092 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1093 GL_MDET_TX_PQM_PF_NUM_S;
1094 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1095 GL_MDET_TX_PQM_MAL_TYPE_S;
1096 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1097 GL_MDET_TX_PQM_QNUM_S;
1099 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1100 "%d by PQM on TX queue %d PF# %d",
1101 event, queue, pf_num);
1104 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1105 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1106 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1107 GL_MDET_TX_TCLAN_PF_NUM_S;
1108 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1109 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1110 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1111 GL_MDET_TX_TCLAN_QNUM_S;
1113 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1114 "%d by TCLAN on TX queue %d PF# %d",
1115 event, queue, pf_num);
1119 /* Enable interrupt */
1120 ice_pf_enable_irq0(hw);
1121 rte_intr_enable(dev->intr_handle);
1124 /* Initialize SW parameters of PF */
1126 ice_pf_sw_init(struct rte_eth_dev *dev)
1128 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1129 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1131 if (ice_config_max_queue_pair_num(dev->device->devargs) > 0)
1133 ice_config_max_queue_pair_num(dev->device->devargs);
1136 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1137 hw->func_caps.common_cap.num_rxq);
1139 pf->lan_nb_qps = pf->lan_nb_qp_max;
1144 static struct ice_vsi *
1145 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1147 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1148 struct ice_vsi *vsi = NULL;
1149 struct ice_vsi_ctx vsi_ctx;
1151 struct rte_ether_addr broadcast = {
1152 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1153 struct rte_ether_addr mac_addr;
1154 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1155 uint8_t tc_bitmap = 0x1;
1157 /* hw->num_lports = 1 in NIC mode */
1158 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1162 vsi->idx = pf->next_vsi_idx;
1165 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1166 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1167 vsi->vlan_anti_spoof_on = 0;
1168 vsi->vlan_filter_on = 1;
1169 TAILQ_INIT(&vsi->mac_list);
1170 TAILQ_INIT(&vsi->vlan_list);
1172 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1173 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1174 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1175 hw->func_caps.common_cap.rss_table_size;
1176 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1178 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1179 /* base_queue in used in queue mapping of VSI add/update command.
1180 * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1181 * cases in the first stage. Only Main VSI.
1183 vsi->base_queue = 0;
1186 vsi->nb_qps = pf->lan_nb_qps;
1187 ice_vsi_config_default_rss(&vsi_ctx.info);
1188 vsi_ctx.alloc_from_pool = true;
1189 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1190 /* switch_id is queried by get_switch_config aq, which is done
1193 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1194 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1195 /* Allow all untagged or tagged packets */
1196 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1197 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1198 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1199 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1200 /* Enable VLAN/UP trip */
1201 ret = ice_vsi_config_tc_queue_mapping(vsi,
1206 "tc queue mapping with vsi failed, "
1214 /* for other types of VSI */
1215 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1219 /* VF has MSIX interrupt in VF range, don't allocate here */
1220 if (type == ICE_VSI_PF) {
1221 ret = ice_res_pool_alloc(&pf->msix_pool,
1222 RTE_MIN(vsi->nb_qps,
1223 RTE_MAX_RXTX_INTR_VEC_ID));
1225 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1228 vsi->msix_intr = ret;
1229 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1234 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1235 if (ret != ICE_SUCCESS) {
1236 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1239 /* store vsi information is SW structure */
1240 vsi->vsi_id = vsi_ctx.vsi_num;
1241 vsi->info = vsi_ctx.info;
1242 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1243 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1245 /* MAC configuration */
1246 rte_memcpy(pf->dev_addr.addr_bytes,
1247 hw->port_info->mac.perm_addr,
1250 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1251 ret = ice_add_mac_filter(vsi, &mac_addr);
1252 if (ret != ICE_SUCCESS)
1253 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1255 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1256 ret = ice_add_mac_filter(vsi, &mac_addr);
1257 if (ret != ICE_SUCCESS)
1258 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1260 /* At the beginning, only TC0. */
1261 /* What we need here is the maximam number of the TX queues.
1262 * Currently vsi->nb_qps means it.
1263 * Correct it if any change.
1265 max_txqs[0] = vsi->nb_qps;
1266 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1267 tc_bitmap, max_txqs);
1268 if (ret != ICE_SUCCESS)
1269 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1279 ice_send_driver_ver(struct ice_hw *hw)
1281 struct ice_driver_ver dv;
1283 /* we don't have driver version use 0 for dummy */
1287 dv.subbuild_ver = 0;
1288 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1290 return ice_aq_send_driver_ver(hw, &dv, NULL);
1294 ice_pf_setup(struct ice_pf *pf)
1296 struct ice_vsi *vsi;
1298 /* Clear all stats counters */
1299 pf->offset_loaded = FALSE;
1300 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1301 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1302 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1303 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1305 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1307 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1316 static int ice_load_pkg(struct rte_eth_dev *dev)
1318 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1319 const char *pkg_file = ICE_DFLT_PKG_FILE;
1326 file = fopen(pkg_file, "rb");
1328 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1332 err = stat(pkg_file, &fstat);
1334 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1339 buf_len = fstat.st_size;
1340 buf = rte_malloc(NULL, buf_len, 0);
1343 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1349 err = fread(buf, buf_len, 1, file);
1351 PMD_INIT_LOG(ERR, "failed to read package data\n");
1359 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1361 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1364 err = ice_init_hw_tbls(hw);
1366 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1367 goto fail_init_tbls;
1373 rte_free(hw->pkg_copy);
1380 ice_base_queue_get(struct ice_pf *pf)
1383 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1385 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1386 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1387 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1389 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1395 ice_dev_init(struct rte_eth_dev *dev)
1397 struct rte_pci_device *pci_dev;
1398 struct rte_intr_handle *intr_handle;
1399 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1401 struct ice_adapter *ad =
1402 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1403 struct ice_vsi *vsi;
1406 dev->dev_ops = &ice_eth_dev_ops;
1407 dev->rx_pkt_burst = ice_recv_pkts;
1408 dev->tx_pkt_burst = ice_xmit_pkts;
1409 dev->tx_pkt_prepare = ice_prep_pkts;
1411 ice_set_default_ptype_table(dev);
1412 pci_dev = RTE_DEV_TO_PCI(dev->device);
1413 intr_handle = &pci_dev->intr_handle;
1415 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1416 pf->adapter->eth_dev = dev;
1417 pf->dev_data = dev->data;
1418 hw->back = pf->adapter;
1419 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1420 hw->vendor_id = pci_dev->id.vendor_id;
1421 hw->device_id = pci_dev->id.device_id;
1422 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1423 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1424 hw->bus.device = pci_dev->addr.devid;
1425 hw->bus.func = pci_dev->addr.function;
1427 ice_init_controlq_parameter(hw);
1429 ret = ice_init_hw(hw);
1431 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1435 ret = ice_load_pkg(dev);
1437 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1438 "Entering Safe Mode");
1439 ad->is_safe_mode = 1;
1442 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1443 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1444 hw->api_maj_ver, hw->api_min_ver);
1446 ice_pf_sw_init(dev);
1447 ret = ice_init_mac_address(dev);
1449 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1453 ret = ice_res_pool_init(&pf->msix_pool, 1,
1454 hw->func_caps.common_cap.num_msix_vectors - 1);
1456 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1457 goto err_msix_pool_init;
1460 ret = ice_pf_setup(pf);
1462 PMD_INIT_LOG(ERR, "Failed to setup PF");
1466 ret = ice_send_driver_ver(hw);
1468 PMD_INIT_LOG(ERR, "Failed to send driver version");
1474 /* Disable double vlan by default */
1475 ice_vsi_config_double_vlan(vsi, FALSE);
1477 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1478 if (ret != ICE_SUCCESS)
1479 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1481 /* register callback func to eal lib */
1482 rte_intr_callback_register(intr_handle,
1483 ice_interrupt_handler, dev);
1485 ice_pf_enable_irq0(hw);
1487 /* enable uio intr after callback register */
1488 rte_intr_enable(intr_handle);
1490 /* get base queue pairs index in the device */
1491 ice_base_queue_get(pf);
1493 TAILQ_INIT(&pf->flow_list);
1498 ice_res_pool_destroy(&pf->msix_pool);
1500 rte_free(dev->data->mac_addrs);
1501 dev->data->mac_addrs = NULL;
1503 ice_sched_cleanup_all(hw);
1504 rte_free(hw->port_info);
1505 ice_shutdown_all_ctrlq(hw);
1511 ice_release_vsi(struct ice_vsi *vsi)
1514 struct ice_vsi_ctx vsi_ctx;
1515 enum ice_status ret;
1520 hw = ICE_VSI_TO_HW(vsi);
1522 ice_remove_all_mac_vlan_filters(vsi);
1524 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1526 vsi_ctx.vsi_num = vsi->vsi_id;
1527 vsi_ctx.info = vsi->info;
1528 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1529 if (ret != ICE_SUCCESS) {
1530 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1540 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1542 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1543 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1544 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1545 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1546 uint16_t msix_intr, i;
1548 /* disable interrupt and also clear all the exist config */
1549 for (i = 0; i < vsi->nb_qps; i++) {
1550 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1551 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1555 if (rte_intr_allow_others(intr_handle))
1557 for (i = 0; i < vsi->nb_msix; i++) {
1558 msix_intr = vsi->msix_intr + i;
1559 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1560 GLINT_DYN_CTL_WB_ON_ITR_M);
1564 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1568 ice_dev_stop(struct rte_eth_dev *dev)
1570 struct rte_eth_dev_data *data = dev->data;
1571 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1572 struct ice_vsi *main_vsi = pf->main_vsi;
1573 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1574 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1577 /* avoid stopping again */
1578 if (pf->adapter_stopped)
1581 /* stop and clear all Rx queues */
1582 for (i = 0; i < data->nb_rx_queues; i++)
1583 ice_rx_queue_stop(dev, i);
1585 /* stop and clear all Tx queues */
1586 for (i = 0; i < data->nb_tx_queues; i++)
1587 ice_tx_queue_stop(dev, i);
1589 /* disable all queue interrupts */
1590 ice_vsi_disable_queues_intr(main_vsi);
1592 /* Clear all queues and release mbufs */
1593 ice_clear_queues(dev);
1595 ice_dev_set_link_down(dev);
1597 /* Clean datapath event and queue/vec mapping */
1598 rte_intr_efd_disable(intr_handle);
1599 if (intr_handle->intr_vec) {
1600 rte_free(intr_handle->intr_vec);
1601 intr_handle->intr_vec = NULL;
1604 pf->adapter_stopped = true;
1608 ice_dev_close(struct rte_eth_dev *dev)
1610 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1611 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613 /* Since stop will make link down, then the link event will be
1614 * triggered, disable the irq firstly to avoid the port_infoe etc
1615 * resources deallocation causing the interrupt service thread
1618 ice_pf_disable_irq0(hw);
1622 /* release all queue resource */
1623 ice_free_queues(dev);
1625 ice_res_pool_destroy(&pf->msix_pool);
1626 ice_release_vsi(pf->main_vsi);
1627 ice_sched_cleanup_all(hw);
1628 rte_free(hw->port_info);
1629 hw->port_info = NULL;
1630 ice_shutdown_all_ctrlq(hw);
1634 ice_dev_uninit(struct rte_eth_dev *dev)
1636 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1637 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1638 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1639 struct rte_flow *p_flow;
1643 dev->dev_ops = NULL;
1644 dev->rx_pkt_burst = NULL;
1645 dev->tx_pkt_burst = NULL;
1647 rte_free(dev->data->mac_addrs);
1648 dev->data->mac_addrs = NULL;
1650 /* disable uio intr before callback unregister */
1651 rte_intr_disable(intr_handle);
1653 /* unregister callback func from eal lib */
1654 rte_intr_callback_unregister(intr_handle,
1655 ice_interrupt_handler, dev);
1657 /* Remove all flows */
1658 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1659 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1660 ice_free_switch_filter_rule(p_flow->rule);
1668 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1670 struct ice_adapter *ad =
1671 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1673 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1674 * bulk allocation or vector Rx preconditions we will reset it.
1676 ad->rx_bulk_alloc_allowed = true;
1677 ad->tx_simple_allowed = true;
1682 static int ice_init_rss(struct ice_pf *pf)
1684 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1685 struct ice_vsi *vsi = pf->main_vsi;
1686 struct rte_eth_dev *dev = pf->adapter->eth_dev;
1687 struct rte_eth_rss_conf *rss_conf;
1688 struct ice_aqc_get_set_rss_keys key;
1691 bool is_safe_mode = pf->adapter->is_safe_mode;
1693 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1694 nb_q = dev->data->nb_rx_queues;
1695 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1696 vsi->rss_lut_size = pf->hash_lut_size;
1699 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
1704 vsi->rss_key = rte_zmalloc(NULL,
1705 vsi->rss_key_size, 0);
1707 vsi->rss_lut = rte_zmalloc(NULL,
1708 vsi->rss_lut_size, 0);
1710 /* configure RSS key */
1711 if (!rss_conf->rss_key) {
1712 /* Calculate the default hash key */
1713 for (i = 0; i <= vsi->rss_key_size; i++)
1714 vsi->rss_key[i] = (uint8_t)rte_rand();
1716 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1717 RTE_MIN(rss_conf->rss_key_len,
1718 vsi->rss_key_size));
1720 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1721 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1725 /* init RSS LUT table */
1726 for (i = 0; i < vsi->rss_lut_size; i++)
1727 vsi->rss_lut[i] = i % nb_q;
1729 ret = ice_aq_set_rss_lut(hw, vsi->idx,
1730 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1731 vsi->rss_lut, vsi->rss_lut_size);
1735 /* configure RSS for IPv4 with input set IPv4 src/dst */
1736 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1737 ICE_FLOW_SEG_HDR_IPV4);
1739 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
1741 /* configure RSS for IPv6 with input set IPv6 src/dst */
1742 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1743 ICE_FLOW_SEG_HDR_IPV6);
1745 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
1747 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
1748 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
1749 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);
1751 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
1753 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
1754 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
1755 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);
1757 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
1759 /* configure RSS for sctp6 with input set IPv6 src/dst */
1760 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1761 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);
1763 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
1766 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
1767 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
1768 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);
1770 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
1772 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
1773 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
1774 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);
1776 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
1778 /* configure RSS for sctp4 with input set IP src/dst */
1779 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1780 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);
1782 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
1789 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1790 int base_queue, int nb_queue)
1792 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1793 uint32_t val, val_tx;
1796 for (i = 0; i < nb_queue; i++) {
1798 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1799 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1800 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1801 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1803 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1804 base_queue + i, msix_vect);
1805 /* set ITR0 value */
1806 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1807 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1808 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1813 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1815 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1816 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1817 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1818 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1819 uint16_t msix_vect = vsi->msix_intr;
1820 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1821 uint16_t queue_idx = 0;
1825 /* clear Rx/Tx queue interrupt */
1826 for (i = 0; i < vsi->nb_used_qps; i++) {
1827 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1828 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1831 /* PF bind interrupt */
1832 if (rte_intr_dp_is_en(intr_handle)) {
1837 for (i = 0; i < vsi->nb_used_qps; i++) {
1839 if (!rte_intr_allow_others(intr_handle))
1840 msix_vect = ICE_MISC_VEC_ID;
1842 /* uio mapping all queue to one msix_vect */
1843 __vsi_queues_bind_intr(vsi, msix_vect,
1844 vsi->base_queue + i,
1845 vsi->nb_used_qps - i);
1847 for (; !!record && i < vsi->nb_used_qps; i++)
1848 intr_handle->intr_vec[queue_idx + i] =
1853 /* vfio 1:1 queue/msix_vect mapping */
1854 __vsi_queues_bind_intr(vsi, msix_vect,
1855 vsi->base_queue + i, 1);
1858 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1866 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1868 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1869 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1870 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1871 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1872 uint16_t msix_intr, i;
1874 if (rte_intr_allow_others(intr_handle))
1875 for (i = 0; i < vsi->nb_used_qps; i++) {
1876 msix_intr = vsi->msix_intr + i;
1877 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1878 GLINT_DYN_CTL_INTENA_M |
1879 GLINT_DYN_CTL_CLEARPBA_M |
1880 GLINT_DYN_CTL_ITR_INDX_M |
1881 GLINT_DYN_CTL_WB_ON_ITR_M);
1884 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1885 GLINT_DYN_CTL_INTENA_M |
1886 GLINT_DYN_CTL_CLEARPBA_M |
1887 GLINT_DYN_CTL_ITR_INDX_M |
1888 GLINT_DYN_CTL_WB_ON_ITR_M);
1892 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1894 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1895 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1896 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1897 struct ice_vsi *vsi = pf->main_vsi;
1898 uint32_t intr_vector = 0;
1900 rte_intr_disable(intr_handle);
1902 /* check and configure queue intr-vector mapping */
1903 if ((rte_intr_cap_multiple(intr_handle) ||
1904 !RTE_ETH_DEV_SRIOV(dev).active) &&
1905 dev->data->dev_conf.intr_conf.rxq != 0) {
1906 intr_vector = dev->data->nb_rx_queues;
1907 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1908 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1909 ICE_MAX_INTR_QUEUE_NUM);
1912 if (rte_intr_efd_enable(intr_handle, intr_vector))
1916 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1917 intr_handle->intr_vec =
1918 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1920 if (!intr_handle->intr_vec) {
1922 "Failed to allocate %d rx_queues intr_vec",
1923 dev->data->nb_rx_queues);
1928 /* Map queues with MSIX interrupt */
1929 vsi->nb_used_qps = dev->data->nb_rx_queues;
1930 ice_vsi_queues_bind_intr(vsi);
1932 /* Enable interrupts for all the queues */
1933 ice_vsi_enable_queues_intr(vsi);
1935 rte_intr_enable(intr_handle);
1941 ice_dev_start(struct rte_eth_dev *dev)
1943 struct rte_eth_dev_data *data = dev->data;
1944 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1945 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1946 struct ice_vsi *vsi = pf->main_vsi;
1947 uint16_t nb_rxq = 0;
1951 /* program Tx queues' context in hardware */
1952 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1953 ret = ice_tx_queue_start(dev, nb_txq);
1955 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1960 /* program Rx queues' context in hardware*/
1961 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1962 ret = ice_rx_queue_start(dev, nb_rxq);
1964 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1969 ret = ice_init_rss(pf);
1971 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1975 ice_set_rx_function(dev);
1976 ice_set_tx_function(dev);
1978 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1979 ETH_VLAN_EXTEND_MASK;
1980 ret = ice_vlan_offload_set(dev, mask);
1982 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1986 /* enable Rx interrput and mapping Rx queue to interrupt vector */
1987 if (ice_rxq_intr_setup(dev))
1990 /* Enable receiving broadcast packets and transmitting packets */
1991 ret = ice_set_vsi_promisc(hw, vsi->idx,
1992 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
1993 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
1995 if (ret != ICE_SUCCESS)
1996 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1998 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
1999 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2000 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2001 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2002 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2003 ICE_AQ_LINK_EVENT_AN_COMPLETED |
2004 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2006 if (ret != ICE_SUCCESS)
2007 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2009 ice_dev_set_link_up(dev);
2011 /* Call get_link_info aq commond to enable/disable LSE */
2012 ice_link_update(dev, 0);
2014 pf->adapter_stopped = false;
2018 /* stop the started queues if failed to start all queues */
2020 for (i = 0; i < nb_rxq; i++)
2021 ice_rx_queue_stop(dev, i);
2023 for (i = 0; i < nb_txq; i++)
2024 ice_tx_queue_stop(dev, i);
2030 ice_dev_reset(struct rte_eth_dev *dev)
2034 if (dev->data->sriov.active)
2037 ret = ice_dev_uninit(dev);
2039 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2043 ret = ice_dev_init(dev);
2045 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2053 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2055 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2056 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057 struct ice_vsi *vsi = pf->main_vsi;
2058 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2059 bool is_safe_mode = pf->adapter->is_safe_mode;
2063 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2064 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2065 dev_info->max_rx_queues = vsi->nb_qps;
2066 dev_info->max_tx_queues = vsi->nb_qps;
2067 dev_info->max_mac_addrs = vsi->max_macaddrs;
2068 dev_info->max_vfs = pci_dev->max_vfs;
2069 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2070 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2072 dev_info->rx_offload_capa =
2073 DEV_RX_OFFLOAD_VLAN_STRIP |
2074 DEV_RX_OFFLOAD_JUMBO_FRAME |
2075 DEV_RX_OFFLOAD_KEEP_CRC |
2076 DEV_RX_OFFLOAD_SCATTER |
2077 DEV_RX_OFFLOAD_VLAN_FILTER;
2078 dev_info->tx_offload_capa =
2079 DEV_TX_OFFLOAD_VLAN_INSERT |
2080 DEV_TX_OFFLOAD_TCP_TSO |
2081 DEV_TX_OFFLOAD_MULTI_SEGS |
2082 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2083 dev_info->flow_type_rss_offloads = 0;
2085 if (!is_safe_mode) {
2086 dev_info->rx_offload_capa |=
2087 DEV_RX_OFFLOAD_IPV4_CKSUM |
2088 DEV_RX_OFFLOAD_UDP_CKSUM |
2089 DEV_RX_OFFLOAD_TCP_CKSUM |
2090 DEV_RX_OFFLOAD_QINQ_STRIP |
2091 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2092 DEV_RX_OFFLOAD_VLAN_EXTEND;
2093 dev_info->tx_offload_capa |=
2094 DEV_TX_OFFLOAD_QINQ_INSERT |
2095 DEV_TX_OFFLOAD_IPV4_CKSUM |
2096 DEV_TX_OFFLOAD_UDP_CKSUM |
2097 DEV_TX_OFFLOAD_TCP_CKSUM |
2098 DEV_TX_OFFLOAD_SCTP_CKSUM |
2099 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2100 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2101 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2104 dev_info->rx_queue_offload_capa = 0;
2105 dev_info->tx_queue_offload_capa = 0;
2107 dev_info->reta_size = pf->hash_lut_size;
2108 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2110 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2112 .pthresh = ICE_DEFAULT_RX_PTHRESH,
2113 .hthresh = ICE_DEFAULT_RX_HTHRESH,
2114 .wthresh = ICE_DEFAULT_RX_WTHRESH,
2116 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2121 dev_info->default_txconf = (struct rte_eth_txconf) {
2123 .pthresh = ICE_DEFAULT_TX_PTHRESH,
2124 .hthresh = ICE_DEFAULT_TX_HTHRESH,
2125 .wthresh = ICE_DEFAULT_TX_WTHRESH,
2127 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2128 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2132 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2133 .nb_max = ICE_MAX_RING_DESC,
2134 .nb_min = ICE_MIN_RING_DESC,
2135 .nb_align = ICE_ALIGN_RING_DESC,
2138 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2139 .nb_max = ICE_MAX_RING_DESC,
2140 .nb_min = ICE_MIN_RING_DESC,
2141 .nb_align = ICE_ALIGN_RING_DESC,
2144 dev_info->speed_capa = ETH_LINK_SPEED_10M |
2145 ETH_LINK_SPEED_100M |
2147 ETH_LINK_SPEED_2_5G |
2149 ETH_LINK_SPEED_10G |
2150 ETH_LINK_SPEED_20G |
2153 phy_type_low = hw->port_info->phy.phy_type_low;
2154 phy_type_high = hw->port_info->phy.phy_type_high;
2156 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2157 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2159 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2160 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2161 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2163 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2164 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2166 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2167 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2168 dev_info->default_rxportconf.nb_queues = 1;
2169 dev_info->default_txportconf.nb_queues = 1;
2170 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2171 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2175 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2176 struct rte_eth_link *link)
2178 struct rte_eth_link *dst = link;
2179 struct rte_eth_link *src = &dev->data->dev_link;
2181 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2182 *(uint64_t *)src) == 0)
2189 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2190 struct rte_eth_link *link)
2192 struct rte_eth_link *dst = &dev->data->dev_link;
2193 struct rte_eth_link *src = link;
2195 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2196 *(uint64_t *)src) == 0)
2203 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2205 #define CHECK_INTERVAL 100 /* 100ms */
2206 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2207 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2208 struct ice_link_status link_status;
2209 struct rte_eth_link link, old;
2211 unsigned int rep_cnt = MAX_REPEAT_TIME;
2212 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2214 memset(&link, 0, sizeof(link));
2215 memset(&old, 0, sizeof(old));
2216 memset(&link_status, 0, sizeof(link_status));
2217 ice_atomic_read_link_status(dev, &old);
2220 /* Get link status information from hardware */
2221 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2222 &link_status, NULL);
2223 if (status != ICE_SUCCESS) {
2224 link.link_speed = ETH_SPEED_NUM_100M;
2225 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2226 PMD_DRV_LOG(ERR, "Failed to get link info");
2230 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2231 if (!wait_to_complete || link.link_status)
2234 rte_delay_ms(CHECK_INTERVAL);
2235 } while (--rep_cnt);
2237 if (!link.link_status)
2240 /* Full-duplex operation at all supported speeds */
2241 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2243 /* Parse the link status */
2244 switch (link_status.link_speed) {
2245 case ICE_AQ_LINK_SPEED_10MB:
2246 link.link_speed = ETH_SPEED_NUM_10M;
2248 case ICE_AQ_LINK_SPEED_100MB:
2249 link.link_speed = ETH_SPEED_NUM_100M;
2251 case ICE_AQ_LINK_SPEED_1000MB:
2252 link.link_speed = ETH_SPEED_NUM_1G;
2254 case ICE_AQ_LINK_SPEED_2500MB:
2255 link.link_speed = ETH_SPEED_NUM_2_5G;
2257 case ICE_AQ_LINK_SPEED_5GB:
2258 link.link_speed = ETH_SPEED_NUM_5G;
2260 case ICE_AQ_LINK_SPEED_10GB:
2261 link.link_speed = ETH_SPEED_NUM_10G;
2263 case ICE_AQ_LINK_SPEED_20GB:
2264 link.link_speed = ETH_SPEED_NUM_20G;
2266 case ICE_AQ_LINK_SPEED_25GB:
2267 link.link_speed = ETH_SPEED_NUM_25G;
2269 case ICE_AQ_LINK_SPEED_40GB:
2270 link.link_speed = ETH_SPEED_NUM_40G;
2272 case ICE_AQ_LINK_SPEED_50GB:
2273 link.link_speed = ETH_SPEED_NUM_50G;
2275 case ICE_AQ_LINK_SPEED_100GB:
2276 link.link_speed = ETH_SPEED_NUM_100G;
2278 case ICE_AQ_LINK_SPEED_UNKNOWN:
2280 PMD_DRV_LOG(ERR, "Unknown link speed");
2281 link.link_speed = ETH_SPEED_NUM_NONE;
2285 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2286 ETH_LINK_SPEED_FIXED);
2289 ice_atomic_write_link_status(dev, &link);
2290 if (link.link_status == old.link_status)
2296 /* Force the physical link state by getting the current PHY capabilities from
2297 * hardware and setting the PHY config based on the determined capabilities. If
2298 * link changes, link event will be triggered because both the Enable Automatic
2299 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2301 static enum ice_status
2302 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2304 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2305 struct ice_aqc_get_phy_caps_data *pcaps;
2306 struct ice_port_info *pi;
2307 enum ice_status status;
2309 if (!hw || !hw->port_info)
2310 return ICE_ERR_PARAM;
2314 pcaps = (struct ice_aqc_get_phy_caps_data *)
2315 ice_malloc(hw, sizeof(*pcaps));
2317 return ICE_ERR_NO_MEMORY;
2319 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2324 /* No change in link */
2325 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2326 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2329 cfg.phy_type_low = pcaps->phy_type_low;
2330 cfg.phy_type_high = pcaps->phy_type_high;
2331 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2332 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2333 cfg.eee_cap = pcaps->eee_cap;
2334 cfg.eeer_value = pcaps->eeer_value;
2335 cfg.link_fec_opt = pcaps->link_fec_options;
2337 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2339 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2341 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2344 ice_free(hw, pcaps);
2349 ice_dev_set_link_up(struct rte_eth_dev *dev)
2351 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2353 return ice_force_phys_link_state(hw, true);
2357 ice_dev_set_link_down(struct rte_eth_dev *dev)
2359 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2361 return ice_force_phys_link_state(hw, false);
2365 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2367 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2368 struct rte_eth_dev_data *dev_data = pf->dev_data;
2369 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2371 /* check if mtu is within the allowed range */
2372 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2375 /* mtu setting is forbidden if port is start */
2376 if (dev_data->dev_started) {
2378 "port %d must be stopped before configuration",
2383 if (frame_size > RTE_ETHER_MAX_LEN)
2384 dev_data->dev_conf.rxmode.offloads |=
2385 DEV_RX_OFFLOAD_JUMBO_FRAME;
2387 dev_data->dev_conf.rxmode.offloads &=
2388 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2390 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2395 static int ice_macaddr_set(struct rte_eth_dev *dev,
2396 struct rte_ether_addr *mac_addr)
2398 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2400 struct ice_vsi *vsi = pf->main_vsi;
2401 struct ice_mac_filter *f;
2405 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2406 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2410 TAILQ_FOREACH(f, &vsi->mac_list, next) {
2411 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2416 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2420 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2421 if (ret != ICE_SUCCESS) {
2422 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2425 ret = ice_add_mac_filter(vsi, mac_addr);
2426 if (ret != ICE_SUCCESS) {
2427 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2430 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2432 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2433 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2434 if (ret != ICE_SUCCESS)
2435 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2440 /* Add a MAC address, and update filters */
2442 ice_macaddr_add(struct rte_eth_dev *dev,
2443 struct rte_ether_addr *mac_addr,
2444 __rte_unused uint32_t index,
2445 __rte_unused uint32_t pool)
2447 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2448 struct ice_vsi *vsi = pf->main_vsi;
2451 ret = ice_add_mac_filter(vsi, mac_addr);
2452 if (ret != ICE_SUCCESS) {
2453 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2460 /* Remove a MAC address, and update filters */
2462 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2464 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2465 struct ice_vsi *vsi = pf->main_vsi;
2466 struct rte_eth_dev_data *data = dev->data;
2467 struct rte_ether_addr *macaddr;
2470 macaddr = &data->mac_addrs[index];
2471 ret = ice_remove_mac_filter(vsi, macaddr);
2473 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2479 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2481 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2482 struct ice_vsi *vsi = pf->main_vsi;
2485 PMD_INIT_FUNC_TRACE();
2488 ret = ice_add_vlan_filter(vsi, vlan_id);
2490 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2494 ret = ice_remove_vlan_filter(vsi, vlan_id);
2496 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2504 /* Configure vlan filter on or off */
2506 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2508 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2509 struct ice_vsi_ctx ctxt;
2510 uint8_t sec_flags, sw_flags2;
2513 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2514 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2515 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2518 vsi->info.sec_flags |= sec_flags;
2519 vsi->info.sw_flags2 |= sw_flags2;
2521 vsi->info.sec_flags &= ~sec_flags;
2522 vsi->info.sw_flags2 &= ~sw_flags2;
2524 vsi->info.sw_id = hw->port_info->sw_id;
2525 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2526 ctxt.info.valid_sections =
2527 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2528 ICE_AQ_VSI_PROP_SECURITY_VALID);
2529 ctxt.vsi_num = vsi->vsi_id;
2531 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2533 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2534 on ? "enable" : "disable");
2537 vsi->info.valid_sections |=
2538 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2539 ICE_AQ_VSI_PROP_SECURITY_VALID);
2542 /* consist with other drivers, allow untagged packet when vlan filter on */
2544 ret = ice_add_vlan_filter(vsi, 0);
2546 ret = ice_remove_vlan_filter(vsi, 0);
2552 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2554 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2555 struct ice_vsi_ctx ctxt;
2559 /* Check if it has been already on or off */
2560 if (vsi->info.valid_sections &
2561 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2563 if ((vsi->info.vlan_flags &
2564 ICE_AQ_VSI_VLAN_EMOD_M) ==
2565 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2566 return 0; /* already on */
2568 if ((vsi->info.vlan_flags &
2569 ICE_AQ_VSI_VLAN_EMOD_M) ==
2570 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2571 return 0; /* already off */
2576 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2578 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2579 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2580 vsi->info.vlan_flags |= vlan_flags;
2581 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2582 ctxt.info.valid_sections =
2583 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2584 ctxt.vsi_num = vsi->vsi_id;
2585 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2587 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2588 on ? "enable" : "disable");
2592 vsi->info.valid_sections |=
2593 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2599 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2601 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2602 struct ice_vsi *vsi = pf->main_vsi;
2603 struct rte_eth_rxmode *rxmode;
2605 rxmode = &dev->data->dev_conf.rxmode;
2606 if (mask & ETH_VLAN_FILTER_MASK) {
2607 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2608 ice_vsi_config_vlan_filter(vsi, TRUE);
2610 ice_vsi_config_vlan_filter(vsi, FALSE);
2613 if (mask & ETH_VLAN_STRIP_MASK) {
2614 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2615 ice_vsi_config_vlan_stripping(vsi, TRUE);
2617 ice_vsi_config_vlan_stripping(vsi, FALSE);
2620 if (mask & ETH_VLAN_EXTEND_MASK) {
2621 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2622 ice_vsi_config_double_vlan(vsi, TRUE);
2624 ice_vsi_config_double_vlan(vsi, FALSE);
2631 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2632 enum rte_vlan_type vlan_type,
2635 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636 uint64_t reg_r = 0, reg_w = 0;
2637 uint16_t reg_id = 0;
2639 int qinq = dev->data->dev_conf.rxmode.offloads &
2640 DEV_RX_OFFLOAD_VLAN_EXTEND;
2642 switch (vlan_type) {
2643 case ETH_VLAN_TYPE_OUTER:
2649 case ETH_VLAN_TYPE_INNER:
2654 "Unsupported vlan type in single vlan.");
2659 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2662 reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2663 PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2664 "0x%08"PRIx64"", reg_id, reg_r);
2666 reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2667 reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2668 if (reg_r == reg_w) {
2669 PMD_DRV_LOG(DEBUG, "No need to write");
2673 ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2674 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2675 "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2681 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2683 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2684 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2690 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2691 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2694 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2698 uint64_t *lut_dw = (uint64_t *)lut;
2699 uint16_t i, lut_size_dw = lut_size / 4;
2701 for (i = 0; i < lut_size_dw; i++)
2702 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2709 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2718 pf = ICE_VSI_TO_PF(vsi);
2719 hw = ICE_VSI_TO_HW(vsi);
2721 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2722 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2725 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2729 uint64_t *lut_dw = (uint64_t *)lut;
2730 uint16_t i, lut_size_dw = lut_size / 4;
2732 for (i = 0; i < lut_size_dw; i++)
2733 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2742 ice_rss_reta_update(struct rte_eth_dev *dev,
2743 struct rte_eth_rss_reta_entry64 *reta_conf,
2746 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2747 uint16_t i, lut_size = pf->hash_lut_size;
2748 uint16_t idx, shift;
2752 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
2753 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
2754 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
2756 "The size of hash lookup table configured (%d)"
2757 "doesn't match the number hardware can "
2758 "supported (128, 512, 2048)",
2763 /* It MUST use the current LUT size to get the RSS lookup table,
2764 * otherwise if will fail with -100 error code.
2766 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
2768 PMD_DRV_LOG(ERR, "No memory can be allocated");
2771 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
2775 for (i = 0; i < reta_size; i++) {
2776 idx = i / RTE_RETA_GROUP_SIZE;
2777 shift = i % RTE_RETA_GROUP_SIZE;
2778 if (reta_conf[idx].mask & (1ULL << shift))
2779 lut[i] = reta_conf[idx].reta[shift];
2781 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2782 if (ret == 0 && lut_size != reta_size) {
2784 "The size of hash lookup table is changed from (%d) to (%d)",
2785 lut_size, reta_size);
2786 pf->hash_lut_size = reta_size;
2796 ice_rss_reta_query(struct rte_eth_dev *dev,
2797 struct rte_eth_rss_reta_entry64 *reta_conf,
2800 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2801 uint16_t i, lut_size = pf->hash_lut_size;
2802 uint16_t idx, shift;
2806 if (reta_size != lut_size) {
2808 "The size of hash lookup table configured (%d)"
2809 "doesn't match the number hardware can "
2811 reta_size, lut_size);
2815 lut = rte_zmalloc(NULL, reta_size, 0);
2817 PMD_DRV_LOG(ERR, "No memory can be allocated");
2821 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2825 for (i = 0; i < reta_size; i++) {
2826 idx = i / RTE_RETA_GROUP_SIZE;
2827 shift = i % RTE_RETA_GROUP_SIZE;
2828 if (reta_conf[idx].mask & (1ULL << shift))
2829 reta_conf[idx].reta[shift] = lut[i];
2839 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2841 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2844 if (!key || key_len == 0) {
2845 PMD_DRV_LOG(DEBUG, "No key to be configured");
2847 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2849 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2853 struct ice_aqc_get_set_rss_keys *key_dw =
2854 (struct ice_aqc_get_set_rss_keys *)key;
2856 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2858 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2866 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2868 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2871 if (!key || !key_len)
2874 ret = ice_aq_get_rss_key
2876 (struct ice_aqc_get_set_rss_keys *)key);
2878 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2881 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2887 ice_rss_hash_update(struct rte_eth_dev *dev,
2888 struct rte_eth_rss_conf *rss_conf)
2890 enum ice_status status = ICE_SUCCESS;
2891 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2892 struct ice_vsi *vsi = pf->main_vsi;
2895 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2899 /* TODO: hash enable config, ice_add_rss_cfg */
2904 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2905 struct rte_eth_rss_conf *rss_conf)
2907 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2908 struct ice_vsi *vsi = pf->main_vsi;
2910 ice_get_rss_key(vsi, rss_conf->rss_key,
2911 &rss_conf->rss_key_len);
2913 /* TODO: default set to 0 as hf config is not supported now */
2914 rss_conf->rss_hf = 0;
2919 ice_promisc_enable(struct rte_eth_dev *dev)
2921 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2922 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2923 struct ice_vsi *vsi = pf->main_vsi;
2924 enum ice_status status;
2927 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2928 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2930 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2931 if (status == ICE_ERR_ALREADY_EXISTS)
2932 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
2933 else if (status != ICE_SUCCESS)
2934 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
2938 ice_promisc_disable(struct rte_eth_dev *dev)
2940 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2941 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2942 struct ice_vsi *vsi = pf->main_vsi;
2943 enum ice_status status;
2946 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2947 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2949 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2950 if (status != ICE_SUCCESS)
2951 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
2955 ice_allmulti_enable(struct rte_eth_dev *dev)
2957 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2958 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2959 struct ice_vsi *vsi = pf->main_vsi;
2960 enum ice_status status;
2963 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2965 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2966 if (status != ICE_SUCCESS)
2967 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
2971 ice_allmulti_disable(struct rte_eth_dev *dev)
2973 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2974 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2975 struct ice_vsi *vsi = pf->main_vsi;
2976 enum ice_status status;
2979 if (dev->data->promiscuous == 1)
2980 return; /* must remain in all_multicast mode */
2982 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2984 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2985 if (status != ICE_SUCCESS)
2986 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
2989 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
2992 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2993 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2994 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2998 msix_intr = intr_handle->intr_vec[queue_id];
3000 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3001 GLINT_DYN_CTL_ITR_INDX_M;
3002 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3004 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3005 rte_intr_enable(&pci_dev->intr_handle);
3010 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3013 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3014 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3015 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018 msix_intr = intr_handle->intr_vec[queue_id];
3020 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3026 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3028 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3034 full_ver = hw->nvm.oem_ver;
3035 ver = (u8)(full_ver >> 24);
3036 build = (u16)((full_ver >> 8) & 0xffff);
3037 patch = (u8)(full_ver & 0xff);
3039 ret = snprintf(fw_version, fw_size,
3040 "%d.%d%d 0x%08x %d.%d.%d",
3041 ((hw->nvm.ver >> 12) & 0xf),
3042 ((hw->nvm.ver >> 4) & 0xff),
3043 (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3046 /* add the size of '\0' */
3048 if (fw_size < (u32)ret)
3055 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3058 struct ice_vsi_ctx ctxt;
3059 uint8_t vlan_flags = 0;
3062 if (!vsi || !info) {
3063 PMD_DRV_LOG(ERR, "invalid parameters");
3068 vsi->info.pvid = info->config.pvid;
3070 * If insert pvid is enabled, only tagged pkts are
3071 * allowed to be sent out.
3073 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3074 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3077 if (info->config.reject.tagged == 0)
3078 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3080 if (info->config.reject.untagged == 0)
3081 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3083 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3084 ICE_AQ_VSI_VLAN_MODE_M);
3085 vsi->info.vlan_flags |= vlan_flags;
3086 memset(&ctxt, 0, sizeof(ctxt));
3087 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3088 ctxt.info.valid_sections =
3089 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3090 ctxt.vsi_num = vsi->vsi_id;
3092 hw = ICE_VSI_TO_HW(vsi);
3093 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3094 if (ret != ICE_SUCCESS) {
3096 "update VSI for VLAN insert failed, err %d",
3101 vsi->info.valid_sections |=
3102 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3108 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3110 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3111 struct ice_vsi *vsi = pf->main_vsi;
3112 struct rte_eth_dev_data *data = pf->dev_data;
3113 struct ice_vsi_vlan_pvid_info info;
3116 memset(&info, 0, sizeof(info));
3119 info.config.pvid = pvid;
3121 info.config.reject.tagged =
3122 data->dev_conf.txmode.hw_vlan_reject_tagged;
3123 info.config.reject.untagged =
3124 data->dev_conf.txmode.hw_vlan_reject_untagged;
3127 ret = ice_vsi_vlan_pvid_set(vsi, &info);
3129 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3137 ice_get_eeprom_length(struct rte_eth_dev *dev)
3139 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3141 /* Convert word count to byte count */
3142 return hw->nvm.sr_words << 1;
3146 ice_get_eeprom(struct rte_eth_dev *dev,
3147 struct rte_dev_eeprom_info *eeprom)
3149 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3150 uint16_t *data = eeprom->data;
3151 uint16_t first_word, last_word, nwords;
3152 enum ice_status status = ICE_SUCCESS;
3154 first_word = eeprom->offset >> 1;
3155 last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3156 nwords = last_word - first_word + 1;
3158 if (first_word >= hw->nvm.sr_words ||
3159 last_word >= hw->nvm.sr_words) {
3160 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3164 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3166 status = ice_read_sr_buf(hw, first_word, &nwords, data);
3168 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3169 eeprom->length = sizeof(uint16_t) * nwords;
3177 ice_stat_update_32(struct ice_hw *hw,
3185 new_data = (uint64_t)ICE_READ_REG(hw, reg);
3189 if (new_data >= *offset)
3190 *stat = (uint64_t)(new_data - *offset);
3192 *stat = (uint64_t)((new_data +
3193 ((uint64_t)1 << ICE_32_BIT_WIDTH))
3198 ice_stat_update_40(struct ice_hw *hw,
3207 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3208 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3214 if (new_data >= *offset)
3215 *stat = new_data - *offset;
3217 *stat = (uint64_t)((new_data +
3218 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3221 *stat &= ICE_40_BIT_MASK;
3224 /* Get all the statistics of a VSI */
3226 ice_update_vsi_stats(struct ice_vsi *vsi)
3228 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3229 struct ice_eth_stats *nes = &vsi->eth_stats;
3230 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3231 int idx = rte_le_to_cpu_16(vsi->vsi_id);
3233 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3234 vsi->offset_loaded, &oes->rx_bytes,
3236 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3237 vsi->offset_loaded, &oes->rx_unicast,
3239 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3240 vsi->offset_loaded, &oes->rx_multicast,
3241 &nes->rx_multicast);
3242 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3243 vsi->offset_loaded, &oes->rx_broadcast,
3244 &nes->rx_broadcast);
3245 /* exclude CRC bytes */
3246 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3247 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3249 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3250 &oes->rx_discards, &nes->rx_discards);
3251 /* GLV_REPC not supported */
3252 /* GLV_RMPC not supported */
3253 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3254 &oes->rx_unknown_protocol,
3255 &nes->rx_unknown_protocol);
3256 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3257 vsi->offset_loaded, &oes->tx_bytes,
3259 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3260 vsi->offset_loaded, &oes->tx_unicast,
3262 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3263 vsi->offset_loaded, &oes->tx_multicast,
3264 &nes->tx_multicast);
3265 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3266 vsi->offset_loaded, &oes->tx_broadcast,
3267 &nes->tx_broadcast);
3268 /* GLV_TDPC not supported */
3269 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3270 &oes->tx_errors, &nes->tx_errors);
3271 vsi->offset_loaded = true;
3273 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3275 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3276 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3277 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3278 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3279 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3280 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3281 nes->rx_unknown_protocol);
3282 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3283 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3284 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3285 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3286 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3287 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3288 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3293 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3295 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3296 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3298 /* Get statistics of struct ice_eth_stats */
3299 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3300 GLPRT_GORCL(hw->port_info->lport),
3301 pf->offset_loaded, &os->eth.rx_bytes,
3303 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3304 GLPRT_UPRCL(hw->port_info->lport),
3305 pf->offset_loaded, &os->eth.rx_unicast,
3306 &ns->eth.rx_unicast);
3307 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3308 GLPRT_MPRCL(hw->port_info->lport),
3309 pf->offset_loaded, &os->eth.rx_multicast,
3310 &ns->eth.rx_multicast);
3311 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3312 GLPRT_BPRCL(hw->port_info->lport),
3313 pf->offset_loaded, &os->eth.rx_broadcast,
3314 &ns->eth.rx_broadcast);
3315 ice_stat_update_32(hw, PRTRPB_RDPC,
3316 pf->offset_loaded, &os->eth.rx_discards,
3317 &ns->eth.rx_discards);
3319 /* Workaround: CRC size should not be included in byte statistics,
3320 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3323 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3324 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3326 /* GLPRT_REPC not supported */
3327 /* GLPRT_RMPC not supported */
3328 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3330 &os->eth.rx_unknown_protocol,
3331 &ns->eth.rx_unknown_protocol);
3332 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3333 GLPRT_GOTCL(hw->port_info->lport),
3334 pf->offset_loaded, &os->eth.tx_bytes,
3336 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3337 GLPRT_UPTCL(hw->port_info->lport),
3338 pf->offset_loaded, &os->eth.tx_unicast,
3339 &ns->eth.tx_unicast);
3340 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3341 GLPRT_MPTCL(hw->port_info->lport),
3342 pf->offset_loaded, &os->eth.tx_multicast,
3343 &ns->eth.tx_multicast);
3344 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3345 GLPRT_BPTCL(hw->port_info->lport),
3346 pf->offset_loaded, &os->eth.tx_broadcast,
3347 &ns->eth.tx_broadcast);
3348 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3349 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3351 /* GLPRT_TEPC not supported */
3353 /* additional port specific stats */
3354 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3355 pf->offset_loaded, &os->tx_dropped_link_down,
3356 &ns->tx_dropped_link_down);
3357 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3358 pf->offset_loaded, &os->crc_errors,
3360 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3361 pf->offset_loaded, &os->illegal_bytes,
3362 &ns->illegal_bytes);
3363 /* GLPRT_ERRBC not supported */
3364 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3365 pf->offset_loaded, &os->mac_local_faults,
3366 &ns->mac_local_faults);
3367 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3368 pf->offset_loaded, &os->mac_remote_faults,
3369 &ns->mac_remote_faults);
3371 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3372 pf->offset_loaded, &os->rx_len_errors,
3373 &ns->rx_len_errors);
3375 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3376 pf->offset_loaded, &os->link_xon_rx,
3378 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3379 pf->offset_loaded, &os->link_xoff_rx,
3381 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3382 pf->offset_loaded, &os->link_xon_tx,
3384 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3385 pf->offset_loaded, &os->link_xoff_tx,
3387 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3388 GLPRT_PRC64L(hw->port_info->lport),
3389 pf->offset_loaded, &os->rx_size_64,
3391 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3392 GLPRT_PRC127L(hw->port_info->lport),
3393 pf->offset_loaded, &os->rx_size_127,
3395 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3396 GLPRT_PRC255L(hw->port_info->lport),
3397 pf->offset_loaded, &os->rx_size_255,
3399 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3400 GLPRT_PRC511L(hw->port_info->lport),
3401 pf->offset_loaded, &os->rx_size_511,
3403 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3404 GLPRT_PRC1023L(hw->port_info->lport),
3405 pf->offset_loaded, &os->rx_size_1023,
3407 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3408 GLPRT_PRC1522L(hw->port_info->lport),
3409 pf->offset_loaded, &os->rx_size_1522,
3411 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3412 GLPRT_PRC9522L(hw->port_info->lport),
3413 pf->offset_loaded, &os->rx_size_big,
3415 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3416 pf->offset_loaded, &os->rx_undersize,
3418 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3419 pf->offset_loaded, &os->rx_fragments,
3421 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3422 pf->offset_loaded, &os->rx_oversize,
3424 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3425 pf->offset_loaded, &os->rx_jabber,
3427 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3428 GLPRT_PTC64L(hw->port_info->lport),
3429 pf->offset_loaded, &os->tx_size_64,
3431 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3432 GLPRT_PTC127L(hw->port_info->lport),
3433 pf->offset_loaded, &os->tx_size_127,
3435 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3436 GLPRT_PTC255L(hw->port_info->lport),
3437 pf->offset_loaded, &os->tx_size_255,
3439 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3440 GLPRT_PTC511L(hw->port_info->lport),
3441 pf->offset_loaded, &os->tx_size_511,
3443 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3444 GLPRT_PTC1023L(hw->port_info->lport),
3445 pf->offset_loaded, &os->tx_size_1023,
3447 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3448 GLPRT_PTC1522L(hw->port_info->lport),
3449 pf->offset_loaded, &os->tx_size_1522,
3451 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3452 GLPRT_PTC9522L(hw->port_info->lport),
3453 pf->offset_loaded, &os->tx_size_big,
3456 /* GLPRT_MSPDC not supported */
3457 /* GLPRT_XEC not supported */
3459 pf->offset_loaded = true;
3462 ice_update_vsi_stats(pf->main_vsi);
3465 /* Get all statistics of a port */
3467 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3469 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3470 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3471 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3473 /* call read registers - updates values, now write them to struct */
3474 ice_read_stats_registers(pf, hw);
3476 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3477 pf->main_vsi->eth_stats.rx_multicast +
3478 pf->main_vsi->eth_stats.rx_broadcast -
3479 pf->main_vsi->eth_stats.rx_discards;
3480 stats->opackets = ns->eth.tx_unicast +
3481 ns->eth.tx_multicast +
3482 ns->eth.tx_broadcast;
3483 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3484 stats->obytes = ns->eth.tx_bytes;
3485 stats->oerrors = ns->eth.tx_errors +
3486 pf->main_vsi->eth_stats.tx_errors;
3489 stats->imissed = ns->eth.rx_discards +
3490 pf->main_vsi->eth_stats.rx_discards;
3491 stats->ierrors = ns->crc_errors +
3493 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3495 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3496 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3497 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3498 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3499 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3500 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3501 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3502 pf->main_vsi->eth_stats.rx_discards);
3503 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3504 ns->eth.rx_unknown_protocol);
3505 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3506 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3507 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3508 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3509 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3510 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3511 pf->main_vsi->eth_stats.tx_discards);
3512 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3514 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3515 ns->tx_dropped_link_down);
3516 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3517 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3519 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3520 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3521 ns->mac_local_faults);
3522 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3523 ns->mac_remote_faults);
3524 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3525 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3526 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3527 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3528 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3529 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3530 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3531 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3532 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3533 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3534 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3535 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3536 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3537 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3538 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3539 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3540 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3541 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3542 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3543 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3544 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3545 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3546 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
3547 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3551 /* Reset the statistics */
3553 ice_stats_reset(struct rte_eth_dev *dev)
3555 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3556 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3558 /* Mark PF and VSI stats to update the offset, aka "reset" */
3559 pf->offset_loaded = false;
3561 pf->main_vsi->offset_loaded = false;
3563 /* read the stats, reading current register values into offset */
3564 ice_read_stats_registers(pf, hw);
3568 ice_xstats_calc_num(void)
3572 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3578 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3581 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3582 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3585 struct ice_hw_port_stats *hw_stats = &pf->stats;
3587 count = ice_xstats_calc_num();
3591 ice_read_stats_registers(pf, hw);
3598 /* Get stats from ice_eth_stats struct */
3599 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3600 xstats[count].value =
3601 *(uint64_t *)((char *)&hw_stats->eth +
3602 ice_stats_strings[i].offset);
3603 xstats[count].id = count;
3607 /* Get individiual stats from ice_hw_port struct */
3608 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3609 xstats[count].value =
3610 *(uint64_t *)((char *)hw_stats +
3611 ice_hw_port_strings[i].offset);
3612 xstats[count].id = count;
3619 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3620 struct rte_eth_xstat_name *xstats_names,
3621 __rte_unused unsigned int limit)
3623 unsigned int count = 0;
3627 return ice_xstats_calc_num();
3629 /* Note: limit checked in rte_eth_xstats_names() */
3631 /* Get stats from ice_eth_stats struct */
3632 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3633 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
3634 sizeof(xstats_names[count].name));
3638 /* Get individiual stats from ice_hw_port struct */
3639 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3640 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
3641 sizeof(xstats_names[count].name));
3649 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
3650 enum rte_filter_type filter_type,
3651 enum rte_filter_op filter_op,
3659 switch (filter_type) {
3660 case RTE_ETH_FILTER_GENERIC:
3661 if (filter_op != RTE_ETH_FILTER_GET)
3663 *(const void **)arg = &ice_flow_ops;
3666 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3675 /* Add UDP tunneling port */
3677 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
3678 struct rte_eth_udp_tunnel *udp_tunnel)
3681 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3683 if (udp_tunnel == NULL)
3686 switch (udp_tunnel->prot_type) {
3687 case RTE_TUNNEL_TYPE_VXLAN:
3688 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
3691 PMD_DRV_LOG(ERR, "Invalid tunnel type");
3699 /* Delete UDP tunneling port */
3701 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
3702 struct rte_eth_udp_tunnel *udp_tunnel)
3705 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3707 if (udp_tunnel == NULL)
3710 switch (udp_tunnel->prot_type) {
3711 case RTE_TUNNEL_TYPE_VXLAN:
3712 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
3715 PMD_DRV_LOG(ERR, "Invalid tunnel type");
3724 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3725 struct rte_pci_device *pci_dev)
3727 return rte_eth_dev_pci_generic_probe(pci_dev,
3728 sizeof(struct ice_adapter),
3733 ice_pci_remove(struct rte_pci_device *pci_dev)
3735 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3738 static struct rte_pci_driver rte_ice_pmd = {
3739 .id_table = pci_id_ice_map,
3740 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3741 RTE_PCI_DRV_IOVA_AS_VA,
3742 .probe = ice_pci_probe,
3743 .remove = ice_pci_remove,
3747 * Driver initialization routine.
3748 * Invoked once at EAL init time.
3749 * Register itself as the [Poll Mode] Driver of PCI devices.
3751 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3752 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3753 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3754 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
3755 ICE_MAX_QP_NUM "=<int>");
3757 RTE_INIT(ice_init_log)
3759 ice_logtype_init = rte_log_register("pmd.net.ice.init");
3760 if (ice_logtype_init >= 0)
3761 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3762 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3763 if (ice_logtype_driver >= 0)
3764 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);