1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_ethdev_pci.h>
7 #include "base/ice_sched.h"
8 #include "ice_ethdev.h"
11 #define ICE_MAX_QP_NUM "max_queue_pair_num"
12 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
15 int ice_logtype_driver;
17 static int ice_dev_configure(struct rte_eth_dev *dev);
18 static int ice_dev_start(struct rte_eth_dev *dev);
19 static void ice_dev_stop(struct rte_eth_dev *dev);
20 static void ice_dev_close(struct rte_eth_dev *dev);
21 static int ice_dev_reset(struct rte_eth_dev *dev);
22 static void ice_dev_info_get(struct rte_eth_dev *dev,
23 struct rte_eth_dev_info *dev_info);
24 static int ice_link_update(struct rte_eth_dev *dev,
25 int wait_to_complete);
26 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
27 static int ice_macaddr_set(struct rte_eth_dev *dev,
28 struct ether_addr *mac_addr);
29 static int ice_macaddr_add(struct rte_eth_dev *dev,
30 struct ether_addr *mac_addr,
31 __rte_unused uint32_t index,
33 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
35 static const struct rte_pci_id pci_id_ice_map[] = {
36 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
37 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
38 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
39 { .vendor_id = 0, /* sentinel */ },
42 static const struct eth_dev_ops ice_eth_dev_ops = {
43 .dev_configure = ice_dev_configure,
44 .dev_start = ice_dev_start,
45 .dev_stop = ice_dev_stop,
46 .dev_close = ice_dev_close,
47 .dev_reset = ice_dev_reset,
48 .rx_queue_start = ice_rx_queue_start,
49 .rx_queue_stop = ice_rx_queue_stop,
50 .tx_queue_start = ice_tx_queue_start,
51 .tx_queue_stop = ice_tx_queue_stop,
52 .rx_queue_setup = ice_rx_queue_setup,
53 .rx_queue_release = ice_rx_queue_release,
54 .tx_queue_setup = ice_tx_queue_setup,
55 .tx_queue_release = ice_tx_queue_release,
56 .dev_infos_get = ice_dev_info_get,
57 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
58 .link_update = ice_link_update,
59 .mtu_set = ice_mtu_set,
60 .mac_addr_set = ice_macaddr_set,
61 .mac_addr_add = ice_macaddr_add,
62 .mac_addr_remove = ice_macaddr_remove,
63 .rxq_info_get = ice_rxq_info_get,
64 .txq_info_get = ice_txq_info_get,
65 .rx_queue_count = ice_rx_queue_count,
69 ice_init_controlq_parameter(struct ice_hw *hw)
71 /* fields for adminq */
72 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
73 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
74 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
75 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
77 /* fields for mailboxq, DPDK used as PF host */
78 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
79 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
80 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
81 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
85 ice_check_qp_num(const char *key, const char *qp_value,
86 __rte_unused void *opaque)
91 while (isblank(*qp_value))
94 num = strtoul(qp_value, &end, 10);
96 if (!num || (*end == '-') || errno) {
97 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
107 ice_config_max_queue_pair_num(struct rte_devargs *devargs)
109 struct rte_kvargs *kvlist;
110 const char *queue_num_key = ICE_MAX_QP_NUM;
116 kvlist = rte_kvargs_parse(devargs->args, NULL);
120 if (!rte_kvargs_count(kvlist, queue_num_key)) {
121 rte_kvargs_free(kvlist);
125 if (rte_kvargs_process(kvlist, queue_num_key,
126 ice_check_qp_num, NULL) < 0) {
127 rte_kvargs_free(kvlist);
130 ret = rte_kvargs_process(kvlist, queue_num_key,
131 ice_check_qp_num, NULL);
132 rte_kvargs_free(kvlist);
138 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
141 struct pool_entry *entry;
146 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
149 "Failed to allocate memory for resource pool");
153 /* queue heap initialize */
154 pool->num_free = num;
157 LIST_INIT(&pool->alloc_list);
158 LIST_INIT(&pool->free_list);
160 /* Initialize element */
164 LIST_INSERT_HEAD(&pool->free_list, entry, next);
169 ice_res_pool_alloc(struct ice_res_pool_info *pool,
172 struct pool_entry *entry, *valid_entry;
175 PMD_INIT_LOG(ERR, "Invalid parameter");
179 if (pool->num_free < num) {
180 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
181 num, pool->num_free);
186 /* Lookup in free list and find most fit one */
187 LIST_FOREACH(entry, &pool->free_list, next) {
188 if (entry->len >= num) {
190 if (entry->len == num) {
195 valid_entry->len > entry->len)
200 /* Not find one to satisfy the request, return */
202 PMD_INIT_LOG(ERR, "No valid entry found");
206 * The entry have equal queue number as requested,
207 * remove it from alloc_list.
209 if (valid_entry->len == num) {
210 LIST_REMOVE(valid_entry, next);
213 * The entry have more numbers than requested,
214 * create a new entry for alloc_list and minus its
215 * queue base and number in free_list.
217 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
220 "Failed to allocate memory for "
224 entry->base = valid_entry->base;
226 valid_entry->base += num;
227 valid_entry->len -= num;
231 /* Insert it into alloc list, not sorted */
232 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
234 pool->num_free -= valid_entry->len;
235 pool->num_alloc += valid_entry->len;
237 return valid_entry->base + pool->base;
241 ice_res_pool_destroy(struct ice_res_pool_info *pool)
243 struct pool_entry *entry, *next_entry;
248 for (entry = LIST_FIRST(&pool->alloc_list);
249 entry && (next_entry = LIST_NEXT(entry, next), 1);
250 entry = next_entry) {
251 LIST_REMOVE(entry, next);
255 for (entry = LIST_FIRST(&pool->free_list);
256 entry && (next_entry = LIST_NEXT(entry, next), 1);
257 entry = next_entry) {
258 LIST_REMOVE(entry, next);
265 LIST_INIT(&pool->alloc_list);
266 LIST_INIT(&pool->free_list);
270 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
272 /* Set VSI LUT selection */
273 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
274 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
275 /* Set Hash scheme */
276 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
277 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
279 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
282 static enum ice_status
283 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
284 struct ice_aqc_vsi_props *info,
285 uint8_t enabled_tcmap)
287 uint16_t bsf, qp_idx;
289 /* default tc 0 now. Multi-TC supporting need to be done later.
290 * Configure TC and queue mapping parameters, for enabled TC,
291 * allocate qpnum_per_tc queues to this traffic.
293 if (enabled_tcmap != 0x01) {
294 PMD_INIT_LOG(ERR, "only TC0 is supported");
298 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
299 bsf = rte_bsf32(vsi->nb_qps);
300 /* Adjust the queue number to actual queues that can be applied */
301 vsi->nb_qps = 0x1 << bsf;
304 /* Set tc and queue mapping with VSI */
305 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
306 ICE_AQ_VSI_TC_Q_OFFSET_S) |
307 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
309 /* Associate queue number with VSI */
310 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
311 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
312 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
313 info->valid_sections |=
314 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
315 /* Set the info.ingress_table and info.egress_table
316 * for UP translate table. Now just set it to 1:1 map by default
317 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
319 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
320 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
321 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
322 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
327 ice_init_mac_address(struct rte_eth_dev *dev)
329 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
331 if (!is_unicast_ether_addr
332 ((struct ether_addr *)hw->port_info[0].mac.lan_addr)) {
333 PMD_INIT_LOG(ERR, "Invalid MAC address");
337 ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.lan_addr,
338 (struct ether_addr *)hw->port_info[0].mac.perm_addr);
340 dev->data->mac_addrs = rte_zmalloc(NULL, sizeof(struct ether_addr), 0);
341 if (!dev->data->mac_addrs) {
343 "Failed to allocate memory to store mac address");
346 /* store it to dev data */
347 ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.perm_addr,
348 &dev->data->mac_addrs[0]);
352 /* Find out specific MAC filter */
353 static struct ice_mac_filter *
354 ice_find_mac_filter(struct ice_vsi *vsi, struct ether_addr *macaddr)
356 struct ice_mac_filter *f;
358 TAILQ_FOREACH(f, &vsi->mac_list, next) {
359 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
367 ice_add_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
369 struct ice_fltr_list_entry *m_list_itr = NULL;
370 struct ice_mac_filter *f;
371 struct LIST_HEAD_TYPE list_head;
372 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
375 /* If it's added and configured, return */
376 f = ice_find_mac_filter(vsi, mac_addr);
378 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
382 INIT_LIST_HEAD(&list_head);
384 m_list_itr = (struct ice_fltr_list_entry *)
385 ice_malloc(hw, sizeof(*m_list_itr));
390 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
391 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
392 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
393 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
394 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
395 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
396 m_list_itr->fltr_info.vsi_handle = vsi->idx;
398 LIST_ADD(&m_list_itr->list_entry, &list_head);
401 ret = ice_add_mac(hw, &list_head);
402 if (ret != ICE_SUCCESS) {
403 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
407 /* Add the mac addr into mac list */
408 f = rte_zmalloc(NULL, sizeof(*f), 0);
410 PMD_DRV_LOG(ERR, "failed to allocate memory");
414 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
415 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
421 rte_free(m_list_itr);
426 ice_remove_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
428 struct ice_fltr_list_entry *m_list_itr = NULL;
429 struct ice_mac_filter *f;
430 struct LIST_HEAD_TYPE list_head;
431 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
434 /* Can't find it, return an error */
435 f = ice_find_mac_filter(vsi, mac_addr);
439 INIT_LIST_HEAD(&list_head);
441 m_list_itr = (struct ice_fltr_list_entry *)
442 ice_malloc(hw, sizeof(*m_list_itr));
447 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
448 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
449 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
450 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
451 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
452 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
453 m_list_itr->fltr_info.vsi_handle = vsi->idx;
455 LIST_ADD(&m_list_itr->list_entry, &list_head);
457 /* remove the mac filter */
458 ret = ice_remove_mac(hw, &list_head);
459 if (ret != ICE_SUCCESS) {
460 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
465 /* Remove the mac addr from mac list */
466 TAILQ_REMOVE(&vsi->mac_list, f, next);
472 rte_free(m_list_itr);
478 ice_pf_enable_irq0(struct ice_hw *hw)
480 /* reset the registers */
481 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
482 ICE_READ_REG(hw, PFINT_OICR);
485 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
486 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
487 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
489 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
490 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
491 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
492 PFINT_OICR_CTL_ITR_INDX_M) |
493 PFINT_OICR_CTL_CAUSE_ENA_M);
495 ICE_WRITE_REG(hw, PFINT_FW_CTL,
496 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
497 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
498 PFINT_FW_CTL_ITR_INDX_M) |
499 PFINT_FW_CTL_CAUSE_ENA_M);
501 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
504 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
505 GLINT_DYN_CTL_INTENA_M |
506 GLINT_DYN_CTL_CLEARPBA_M |
507 GLINT_DYN_CTL_ITR_INDX_M);
514 ice_pf_disable_irq0(struct ice_hw *hw)
516 /* Disable all interrupt types */
517 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
523 ice_handle_aq_msg(struct rte_eth_dev *dev)
525 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
526 struct ice_ctl_q_info *cq = &hw->adminq;
527 struct ice_rq_event_info event;
528 uint16_t pending, opcode;
531 event.buf_len = ICE_AQ_MAX_BUF_LEN;
532 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
533 if (!event.msg_buf) {
534 PMD_DRV_LOG(ERR, "Failed to allocate mem");
540 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
542 if (ret != ICE_SUCCESS) {
544 "Failed to read msg from AdminQ, "
546 hw->adminq.sq_last_status);
549 opcode = rte_le_to_cpu_16(event.desc.opcode);
552 case ice_aqc_opc_get_link_status:
553 ret = ice_link_update(dev, 0);
555 _rte_eth_dev_callback_process
556 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
559 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
564 rte_free(event.msg_buf);
569 * Interrupt handler triggered by NIC for handling
570 * specific interrupt.
573 * Pointer to interrupt handle.
575 * The address of parameter (struct rte_eth_dev *) regsitered before.
581 ice_interrupt_handler(void *param)
583 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
584 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
594 /* Disable interrupt */
595 ice_pf_disable_irq0(hw);
597 /* read out interrupt causes */
598 oicr = ICE_READ_REG(hw, PFINT_OICR);
600 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
603 /* No interrupt event indicated */
604 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
605 PMD_DRV_LOG(INFO, "No interrupt event");
610 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
611 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
612 ice_handle_aq_msg(dev);
615 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
616 PMD_DRV_LOG(INFO, "OICR: link state change event");
617 ice_link_update(dev, 0);
621 if (oicr & PFINT_OICR_MAL_DETECT_M) {
622 PMD_DRV_LOG(WARNING, "OICR: MDD event");
623 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
624 if (reg & GL_MDET_TX_PQM_VALID_M) {
625 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
626 GL_MDET_TX_PQM_PF_NUM_S;
627 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
628 GL_MDET_TX_PQM_MAL_TYPE_S;
629 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
630 GL_MDET_TX_PQM_QNUM_S;
632 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
633 "%d by PQM on TX queue %d PF# %d",
634 event, queue, pf_num);
637 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
638 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
639 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
640 GL_MDET_TX_TCLAN_PF_NUM_S;
641 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
642 GL_MDET_TX_TCLAN_MAL_TYPE_S;
643 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
644 GL_MDET_TX_TCLAN_QNUM_S;
646 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
647 "%d by TCLAN on TX queue %d PF# %d",
648 event, queue, pf_num);
652 /* Enable interrupt */
653 ice_pf_enable_irq0(hw);
654 rte_intr_enable(dev->intr_handle);
657 /* Initialize SW parameters of PF */
659 ice_pf_sw_init(struct rte_eth_dev *dev)
661 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
662 struct ice_hw *hw = ICE_PF_TO_HW(pf);
664 if (ice_config_max_queue_pair_num(dev->device->devargs) > 0)
666 ice_config_max_queue_pair_num(dev->device->devargs);
669 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
670 hw->func_caps.common_cap.num_rxq);
672 pf->lan_nb_qps = pf->lan_nb_qp_max;
677 static struct ice_vsi *
678 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
680 struct ice_hw *hw = ICE_PF_TO_HW(pf);
681 struct ice_vsi *vsi = NULL;
682 struct ice_vsi_ctx vsi_ctx;
684 struct ether_addr broadcast = {
685 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
686 struct ether_addr mac_addr;
687 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
688 uint8_t tc_bitmap = 0x1;
690 /* hw->num_lports = 1 in NIC mode */
691 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
695 vsi->idx = pf->next_vsi_idx;
698 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
699 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
700 vsi->vlan_anti_spoof_on = 0;
701 vsi->vlan_filter_on = 1;
702 TAILQ_INIT(&vsi->mac_list);
703 TAILQ_INIT(&vsi->vlan_list);
705 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
706 /* base_queue in used in queue mapping of VSI add/update command.
707 * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
708 * cases in the first stage. Only Main VSI.
713 vsi->nb_qps = pf->lan_nb_qps;
714 ice_vsi_config_default_rss(&vsi_ctx.info);
715 vsi_ctx.alloc_from_pool = true;
716 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
717 /* switch_id is queried by get_switch_config aq, which is done
720 vsi_ctx.info.sw_id = hw->port_info->sw_id;
721 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
722 /* Allow all untagged or tagged packets */
723 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
724 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
725 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
726 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
727 /* Enable VLAN/UP trip */
728 ret = ice_vsi_config_tc_queue_mapping(vsi,
733 "tc queue mapping with vsi failed, "
741 /* for other types of VSI */
742 PMD_INIT_LOG(ERR, "other types of VSI not supported");
746 /* VF has MSIX interrupt in VF range, don't allocate here */
747 if (type == ICE_VSI_PF) {
748 ret = ice_res_pool_alloc(&pf->msix_pool,
750 RTE_MAX_RXTX_INTR_VEC_ID));
752 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
755 vsi->msix_intr = ret;
756 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
761 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
762 if (ret != ICE_SUCCESS) {
763 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
766 /* store vsi information is SW structure */
767 vsi->vsi_id = vsi_ctx.vsi_num;
768 vsi->info = vsi_ctx.info;
769 pf->vsis_allocated = vsi_ctx.vsis_allocd;
770 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
772 /* MAC configuration */
773 rte_memcpy(pf->dev_addr.addr_bytes,
774 hw->port_info->mac.perm_addr,
777 rte_memcpy(&mac_addr, &pf->dev_addr, ETHER_ADDR_LEN);
778 ret = ice_add_mac_filter(vsi, &mac_addr);
779 if (ret != ICE_SUCCESS)
780 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
782 rte_memcpy(&mac_addr, &broadcast, ETHER_ADDR_LEN);
783 ret = ice_add_mac_filter(vsi, &mac_addr);
784 if (ret != ICE_SUCCESS)
785 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
787 /* At the beginning, only TC0. */
788 /* What we need here is the maximam number of the TX queues.
789 * Currently vsi->nb_qps means it.
790 * Correct it if any change.
792 max_txqs[0] = vsi->nb_qps;
793 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
794 tc_bitmap, max_txqs);
795 if (ret != ICE_SUCCESS)
796 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
806 ice_pf_setup(struct ice_pf *pf)
810 /* Clear all stats counters */
811 pf->offset_loaded = FALSE;
812 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
813 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
814 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
815 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
817 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
819 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
829 ice_dev_init(struct rte_eth_dev *dev)
831 struct rte_pci_device *pci_dev;
832 struct rte_intr_handle *intr_handle;
833 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
834 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
837 dev->dev_ops = &ice_eth_dev_ops;
838 dev->rx_pkt_burst = ice_recv_pkts;
839 dev->tx_pkt_burst = ice_xmit_pkts;
840 dev->tx_pkt_prepare = ice_prep_pkts;
842 ice_set_default_ptype_table(dev);
843 pci_dev = RTE_DEV_TO_PCI(dev->device);
844 intr_handle = &pci_dev->intr_handle;
846 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
847 pf->adapter->eth_dev = dev;
848 pf->dev_data = dev->data;
849 hw->back = pf->adapter;
850 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
851 hw->vendor_id = pci_dev->id.vendor_id;
852 hw->device_id = pci_dev->id.device_id;
853 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
854 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
855 hw->bus.device = pci_dev->addr.devid;
856 hw->bus.func = pci_dev->addr.function;
858 ice_init_controlq_parameter(hw);
860 ret = ice_init_hw(hw);
862 PMD_INIT_LOG(ERR, "Failed to initialize HW");
866 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
867 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
868 hw->api_maj_ver, hw->api_min_ver);
871 ret = ice_init_mac_address(dev);
873 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
877 ret = ice_res_pool_init(&pf->msix_pool, 1,
878 hw->func_caps.common_cap.num_msix_vectors - 1);
880 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
881 goto err_msix_pool_init;
884 ret = ice_pf_setup(pf);
886 PMD_INIT_LOG(ERR, "Failed to setup PF");
890 /* register callback func to eal lib */
891 rte_intr_callback_register(intr_handle,
892 ice_interrupt_handler, dev);
894 ice_pf_enable_irq0(hw);
896 /* enable uio intr after callback register */
897 rte_intr_enable(intr_handle);
902 ice_res_pool_destroy(&pf->msix_pool);
904 rte_free(dev->data->mac_addrs);
906 ice_sched_cleanup_all(hw);
907 rte_free(hw->port_info);
908 ice_shutdown_all_ctrlq(hw);
914 ice_release_vsi(struct ice_vsi *vsi)
917 struct ice_vsi_ctx vsi_ctx;
923 hw = ICE_VSI_TO_HW(vsi);
925 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
927 vsi_ctx.vsi_num = vsi->vsi_id;
928 vsi_ctx.info = vsi->info;
929 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
930 if (ret != ICE_SUCCESS) {
931 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
941 ice_dev_stop(struct rte_eth_dev *dev)
943 struct rte_eth_dev_data *data = dev->data;
944 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
945 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
946 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
949 /* avoid stopping again */
950 if (pf->adapter_stopped)
953 /* stop and clear all Rx queues */
954 for (i = 0; i < data->nb_rx_queues; i++)
955 ice_rx_queue_stop(dev, i);
957 /* stop and clear all Tx queues */
958 for (i = 0; i < data->nb_tx_queues; i++)
959 ice_tx_queue_stop(dev, i);
961 /* Clear all queues and release mbufs */
962 ice_clear_queues(dev);
964 /* Clean datapath event and queue/vec mapping */
965 rte_intr_efd_disable(intr_handle);
966 if (intr_handle->intr_vec) {
967 rte_free(intr_handle->intr_vec);
968 intr_handle->intr_vec = NULL;
971 pf->adapter_stopped = true;
975 ice_dev_close(struct rte_eth_dev *dev)
977 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
978 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
982 /* release all queue resource */
983 ice_free_queues(dev);
985 ice_res_pool_destroy(&pf->msix_pool);
986 ice_release_vsi(pf->main_vsi);
988 ice_shutdown_all_ctrlq(hw);
992 ice_dev_uninit(struct rte_eth_dev *dev)
994 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
995 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
996 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
997 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1001 dev->dev_ops = NULL;
1002 dev->rx_pkt_burst = NULL;
1003 dev->tx_pkt_burst = NULL;
1005 rte_free(dev->data->mac_addrs);
1006 dev->data->mac_addrs = NULL;
1008 /* disable uio intr before callback unregister */
1009 rte_intr_disable(intr_handle);
1011 /* register callback func to eal lib */
1012 rte_intr_callback_unregister(intr_handle,
1013 ice_interrupt_handler, dev);
1015 ice_release_vsi(pf->main_vsi);
1016 ice_sched_cleanup_all(hw);
1017 rte_free(hw->port_info);
1018 ice_shutdown_all_ctrlq(hw);
1024 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1026 struct ice_adapter *ad =
1027 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1029 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1030 * bulk allocation or vector Rx preconditions we will reset it.
1032 ad->rx_bulk_alloc_allowed = true;
1033 ad->tx_simple_allowed = true;
1038 static int ice_init_rss(struct ice_pf *pf)
1040 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1041 struct ice_vsi *vsi = pf->main_vsi;
1042 struct rte_eth_dev *dev = pf->adapter->eth_dev;
1043 struct rte_eth_rss_conf *rss_conf;
1044 struct ice_aqc_get_set_rss_keys key;
1048 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1049 nb_q = dev->data->nb_rx_queues;
1050 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1051 vsi->rss_lut_size = hw->func_caps.common_cap.rss_table_size;
1054 vsi->rss_key = rte_zmalloc(NULL,
1055 vsi->rss_key_size, 0);
1057 vsi->rss_lut = rte_zmalloc(NULL,
1058 vsi->rss_lut_size, 0);
1060 /* configure RSS key */
1061 if (!rss_conf->rss_key) {
1062 /* Calculate the default hash key */
1063 for (i = 0; i <= vsi->rss_key_size; i++)
1064 vsi->rss_key[i] = (uint8_t)rte_rand();
1066 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1067 RTE_MIN(rss_conf->rss_key_len,
1068 vsi->rss_key_size));
1070 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1071 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1075 /* init RSS LUT table */
1076 for (i = 0; i < vsi->rss_lut_size; i++)
1077 vsi->rss_lut[i] = i % nb_q;
1079 ret = ice_aq_set_rss_lut(hw, vsi->idx,
1080 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1081 vsi->rss_lut, vsi->rss_lut_size);
1089 ice_dev_start(struct rte_eth_dev *dev)
1091 struct rte_eth_dev_data *data = dev->data;
1092 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1094 uint16_t nb_rxq = 0;
1098 /* program Tx queues' context in hardware */
1099 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1100 ret = ice_tx_queue_start(dev, nb_txq);
1102 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1107 /* program Rx queues' context in hardware*/
1108 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1109 ret = ice_rx_queue_start(dev, nb_rxq);
1111 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1116 ret = ice_init_rss(pf);
1118 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1122 ice_set_rx_function(dev);
1124 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
1125 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
1126 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
1127 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
1128 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
1129 ICE_AQ_LINK_EVENT_AN_COMPLETED |
1130 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
1132 if (ret != ICE_SUCCESS)
1133 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1135 /* Call get_link_info aq commond to enable/disable LSE */
1136 ice_link_update(dev, 0);
1138 pf->adapter_stopped = false;
1142 /* stop the started queues if failed to start all queues */
1144 for (i = 0; i < nb_rxq; i++)
1145 ice_rx_queue_stop(dev, i);
1147 for (i = 0; i < nb_txq; i++)
1148 ice_tx_queue_stop(dev, i);
1154 ice_dev_reset(struct rte_eth_dev *dev)
1158 if (dev->data->sriov.active)
1161 ret = ice_dev_uninit(dev);
1163 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
1167 ret = ice_dev_init(dev);
1169 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
1177 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1179 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1180 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1181 struct ice_vsi *vsi = pf->main_vsi;
1182 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1184 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
1185 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
1186 dev_info->max_rx_queues = vsi->nb_qps;
1187 dev_info->max_tx_queues = vsi->nb_qps;
1188 dev_info->max_mac_addrs = vsi->max_macaddrs;
1189 dev_info->max_vfs = pci_dev->max_vfs;
1191 dev_info->rx_offload_capa =
1192 DEV_RX_OFFLOAD_IPV4_CKSUM |
1193 DEV_RX_OFFLOAD_UDP_CKSUM |
1194 DEV_RX_OFFLOAD_TCP_CKSUM |
1195 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1196 DEV_RX_OFFLOAD_JUMBO_FRAME |
1197 DEV_RX_OFFLOAD_KEEP_CRC;
1198 dev_info->tx_offload_capa =
1199 DEV_TX_OFFLOAD_IPV4_CKSUM |
1200 DEV_TX_OFFLOAD_UDP_CKSUM |
1201 DEV_TX_OFFLOAD_TCP_CKSUM |
1202 DEV_TX_OFFLOAD_SCTP_CKSUM |
1203 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1204 DEV_TX_OFFLOAD_TCP_TSO |
1205 DEV_TX_OFFLOAD_MULTI_SEGS;
1206 dev_info->rx_queue_offload_capa = 0;
1207 dev_info->tx_queue_offload_capa = 0;
1209 dev_info->reta_size = hw->func_caps.common_cap.rss_table_size;
1210 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
1212 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1214 .pthresh = ICE_DEFAULT_RX_PTHRESH,
1215 .hthresh = ICE_DEFAULT_RX_HTHRESH,
1216 .wthresh = ICE_DEFAULT_RX_WTHRESH,
1218 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
1223 dev_info->default_txconf = (struct rte_eth_txconf) {
1225 .pthresh = ICE_DEFAULT_TX_PTHRESH,
1226 .hthresh = ICE_DEFAULT_TX_HTHRESH,
1227 .wthresh = ICE_DEFAULT_TX_WTHRESH,
1229 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
1230 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
1234 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1235 .nb_max = ICE_MAX_RING_DESC,
1236 .nb_min = ICE_MIN_RING_DESC,
1237 .nb_align = ICE_ALIGN_RING_DESC,
1240 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1241 .nb_max = ICE_MAX_RING_DESC,
1242 .nb_min = ICE_MIN_RING_DESC,
1243 .nb_align = ICE_ALIGN_RING_DESC,
1246 dev_info->speed_capa = ETH_LINK_SPEED_10M |
1247 ETH_LINK_SPEED_100M |
1249 ETH_LINK_SPEED_2_5G |
1251 ETH_LINK_SPEED_10G |
1252 ETH_LINK_SPEED_20G |
1253 ETH_LINK_SPEED_25G |
1256 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
1257 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
1259 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
1260 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
1261 dev_info->default_rxportconf.nb_queues = 1;
1262 dev_info->default_txportconf.nb_queues = 1;
1263 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
1264 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
1268 ice_atomic_read_link_status(struct rte_eth_dev *dev,
1269 struct rte_eth_link *link)
1271 struct rte_eth_link *dst = link;
1272 struct rte_eth_link *src = &dev->data->dev_link;
1274 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1275 *(uint64_t *)src) == 0)
1282 ice_atomic_write_link_status(struct rte_eth_dev *dev,
1283 struct rte_eth_link *link)
1285 struct rte_eth_link *dst = &dev->data->dev_link;
1286 struct rte_eth_link *src = link;
1288 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1289 *(uint64_t *)src) == 0)
1296 ice_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1298 #define CHECK_INTERVAL 100 /* 100ms */
1299 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1300 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301 struct ice_link_status link_status;
1302 struct rte_eth_link link, old;
1304 unsigned int rep_cnt = MAX_REPEAT_TIME;
1305 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
1307 memset(&link, 0, sizeof(link));
1308 memset(&old, 0, sizeof(old));
1309 memset(&link_status, 0, sizeof(link_status));
1310 ice_atomic_read_link_status(dev, &old);
1313 /* Get link status information from hardware */
1314 status = ice_aq_get_link_info(hw->port_info, enable_lse,
1315 &link_status, NULL);
1316 if (status != ICE_SUCCESS) {
1317 link.link_speed = ETH_SPEED_NUM_100M;
1318 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1319 PMD_DRV_LOG(ERR, "Failed to get link info");
1323 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
1324 if (!wait_to_complete || link.link_status)
1327 rte_delay_ms(CHECK_INTERVAL);
1328 } while (--rep_cnt);
1330 if (!link.link_status)
1333 /* Full-duplex operation at all supported speeds */
1334 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1336 /* Parse the link status */
1337 switch (link_status.link_speed) {
1338 case ICE_AQ_LINK_SPEED_10MB:
1339 link.link_speed = ETH_SPEED_NUM_10M;
1341 case ICE_AQ_LINK_SPEED_100MB:
1342 link.link_speed = ETH_SPEED_NUM_100M;
1344 case ICE_AQ_LINK_SPEED_1000MB:
1345 link.link_speed = ETH_SPEED_NUM_1G;
1347 case ICE_AQ_LINK_SPEED_2500MB:
1348 link.link_speed = ETH_SPEED_NUM_2_5G;
1350 case ICE_AQ_LINK_SPEED_5GB:
1351 link.link_speed = ETH_SPEED_NUM_5G;
1353 case ICE_AQ_LINK_SPEED_10GB:
1354 link.link_speed = ETH_SPEED_NUM_10G;
1356 case ICE_AQ_LINK_SPEED_20GB:
1357 link.link_speed = ETH_SPEED_NUM_20G;
1359 case ICE_AQ_LINK_SPEED_25GB:
1360 link.link_speed = ETH_SPEED_NUM_25G;
1362 case ICE_AQ_LINK_SPEED_40GB:
1363 link.link_speed = ETH_SPEED_NUM_40G;
1365 case ICE_AQ_LINK_SPEED_UNKNOWN:
1367 PMD_DRV_LOG(ERR, "Unknown link speed");
1368 link.link_speed = ETH_SPEED_NUM_NONE;
1372 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1373 ETH_LINK_SPEED_FIXED);
1376 ice_atomic_write_link_status(dev, &link);
1377 if (link.link_status == old.link_status)
1384 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1386 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1387 struct rte_eth_dev_data *dev_data = pf->dev_data;
1388 uint32_t frame_size = mtu + ETHER_HDR_LEN
1389 + ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE;
1391 /* check if mtu is within the allowed range */
1392 if (mtu < ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
1395 /* mtu setting is forbidden if port is start */
1396 if (dev_data->dev_started) {
1398 "port %d must be stopped before configuration",
1403 if (frame_size > ETHER_MAX_LEN)
1404 dev_data->dev_conf.rxmode.offloads |=
1405 DEV_RX_OFFLOAD_JUMBO_FRAME;
1407 dev_data->dev_conf.rxmode.offloads &=
1408 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1410 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1415 static int ice_macaddr_set(struct rte_eth_dev *dev,
1416 struct ether_addr *mac_addr)
1418 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1420 struct ice_vsi *vsi = pf->main_vsi;
1421 struct ice_mac_filter *f;
1425 if (!is_valid_assigned_ether_addr(mac_addr)) {
1426 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
1430 TAILQ_FOREACH(f, &vsi->mac_list, next) {
1431 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
1436 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
1440 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
1441 if (ret != ICE_SUCCESS) {
1442 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
1445 ret = ice_add_mac_filter(vsi, mac_addr);
1446 if (ret != ICE_SUCCESS) {
1447 PMD_DRV_LOG(ERR, "Failed to add mac filter");
1450 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
1452 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
1453 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
1454 if (ret != ICE_SUCCESS)
1455 PMD_DRV_LOG(ERR, "Failed to set manage mac");
1460 /* Add a MAC address, and update filters */
1462 ice_macaddr_add(struct rte_eth_dev *dev,
1463 struct ether_addr *mac_addr,
1464 __rte_unused uint32_t index,
1465 __rte_unused uint32_t pool)
1467 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1468 struct ice_vsi *vsi = pf->main_vsi;
1471 ret = ice_add_mac_filter(vsi, mac_addr);
1472 if (ret != ICE_SUCCESS) {
1473 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
1480 /* Remove a MAC address, and update filters */
1482 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1484 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1485 struct ice_vsi *vsi = pf->main_vsi;
1486 struct rte_eth_dev_data *data = dev->data;
1487 struct ether_addr *macaddr;
1490 macaddr = &data->mac_addrs[index];
1491 ret = ice_remove_mac_filter(vsi, macaddr);
1493 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
1499 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1500 struct rte_pci_device *pci_dev)
1502 return rte_eth_dev_pci_generic_probe(pci_dev,
1503 sizeof(struct ice_adapter),
1508 ice_pci_remove(struct rte_pci_device *pci_dev)
1510 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
1513 static struct rte_pci_driver rte_ice_pmd = {
1514 .id_table = pci_id_ice_map,
1515 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1516 RTE_PCI_DRV_IOVA_AS_VA,
1517 .probe = ice_pci_probe,
1518 .remove = ice_pci_remove,
1522 * Driver initialization routine.
1523 * Invoked once at EAL init time.
1524 * Register itself as the [Poll Mode] Driver of PCI devices.
1526 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
1527 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
1528 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
1529 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
1530 ICE_MAX_QP_NUM "=<int>");
1532 RTE_INIT(ice_init_log)
1534 ice_logtype_init = rte_log_register("pmd.net.ice.init");
1535 if (ice_logtype_init >= 0)
1536 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
1537 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
1538 if (ice_logtype_driver >= 0)
1539 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);