1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <ethdev_pci.h>
13 #include <rte_tailq.h>
15 #include "eal_firmware.h"
17 #include "base/ice_sched.h"
18 #include "base/ice_flow.h"
19 #include "base/ice_dcb.h"
20 #include "base/ice_common.h"
22 #include "rte_pmd_ice.h"
23 #include "ice_ethdev.h"
25 #include "ice_generic_flow.h"
28 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
29 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
30 #define ICE_PROTO_XTR_ARG "proto_xtr"
31 #define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask"
33 static const char * const ice_valid_args[] = {
34 ICE_SAFE_MODE_SUPPORT_ARG,
35 ICE_PIPELINE_MODE_SUPPORT_ARG,
37 ICE_HW_DEBUG_MASK_ARG,
41 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
42 .name = "intel_pmd_dynfield_proto_xtr_metadata",
43 .size = sizeof(uint32_t),
44 .align = __alignof__(uint32_t),
48 struct proto_xtr_ol_flag {
49 const struct rte_mbuf_dynflag param;
54 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
56 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
58 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
61 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
64 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
66 [PROTO_XTR_IPV6_FLOW] = {
67 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
68 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
70 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
71 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
72 [PROTO_XTR_IP_OFFSET] = {
73 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
74 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
77 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
78 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
79 #define ICE_MAX_RES_DESC_NUM 1024
81 static int ice_dev_configure(struct rte_eth_dev *dev);
82 static int ice_dev_start(struct rte_eth_dev *dev);
83 static int ice_dev_stop(struct rte_eth_dev *dev);
84 static int ice_dev_close(struct rte_eth_dev *dev);
85 static int ice_dev_reset(struct rte_eth_dev *dev);
86 static int ice_dev_info_get(struct rte_eth_dev *dev,
87 struct rte_eth_dev_info *dev_info);
88 static int ice_link_update(struct rte_eth_dev *dev,
89 int wait_to_complete);
90 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
91 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
93 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
94 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
95 static int ice_rss_reta_update(struct rte_eth_dev *dev,
96 struct rte_eth_rss_reta_entry64 *reta_conf,
98 static int ice_rss_reta_query(struct rte_eth_dev *dev,
99 struct rte_eth_rss_reta_entry64 *reta_conf,
101 static int ice_rss_hash_update(struct rte_eth_dev *dev,
102 struct rte_eth_rss_conf *rss_conf);
103 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
104 struct rte_eth_rss_conf *rss_conf);
105 static int ice_promisc_enable(struct rte_eth_dev *dev);
106 static int ice_promisc_disable(struct rte_eth_dev *dev);
107 static int ice_allmulti_enable(struct rte_eth_dev *dev);
108 static int ice_allmulti_disable(struct rte_eth_dev *dev);
109 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
112 static int ice_macaddr_set(struct rte_eth_dev *dev,
113 struct rte_ether_addr *mac_addr);
114 static int ice_macaddr_add(struct rte_eth_dev *dev,
115 struct rte_ether_addr *mac_addr,
116 __rte_unused uint32_t index,
118 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
119 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
121 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
123 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
125 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
126 uint16_t pvid, int on);
127 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
128 static int ice_get_eeprom(struct rte_eth_dev *dev,
129 struct rte_dev_eeprom_info *eeprom);
130 static int ice_stats_get(struct rte_eth_dev *dev,
131 struct rte_eth_stats *stats);
132 static int ice_stats_reset(struct rte_eth_dev *dev);
133 static int ice_xstats_get(struct rte_eth_dev *dev,
134 struct rte_eth_xstat *xstats, unsigned int n);
135 static int ice_xstats_get_names(struct rte_eth_dev *dev,
136 struct rte_eth_xstat_name *xstats_names,
138 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev,
139 const struct rte_flow_ops **ops);
140 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
141 struct rte_eth_udp_tunnel *udp_tunnel);
142 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
143 struct rte_eth_udp_tunnel *udp_tunnel);
145 static const struct rte_pci_id pci_id_ice_map[] = {
146 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
147 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
148 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
149 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
150 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
157 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
159 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
164 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
165 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
166 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
167 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
168 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
169 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
170 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
171 { .vendor_id = 0, /* sentinel */ },
174 static const struct eth_dev_ops ice_eth_dev_ops = {
175 .dev_configure = ice_dev_configure,
176 .dev_start = ice_dev_start,
177 .dev_stop = ice_dev_stop,
178 .dev_close = ice_dev_close,
179 .dev_reset = ice_dev_reset,
180 .dev_set_link_up = ice_dev_set_link_up,
181 .dev_set_link_down = ice_dev_set_link_down,
182 .rx_queue_start = ice_rx_queue_start,
183 .rx_queue_stop = ice_rx_queue_stop,
184 .tx_queue_start = ice_tx_queue_start,
185 .tx_queue_stop = ice_tx_queue_stop,
186 .rx_queue_setup = ice_rx_queue_setup,
187 .rx_queue_release = ice_rx_queue_release,
188 .tx_queue_setup = ice_tx_queue_setup,
189 .tx_queue_release = ice_tx_queue_release,
190 .dev_infos_get = ice_dev_info_get,
191 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
192 .link_update = ice_link_update,
193 .mtu_set = ice_mtu_set,
194 .mac_addr_set = ice_macaddr_set,
195 .mac_addr_add = ice_macaddr_add,
196 .mac_addr_remove = ice_macaddr_remove,
197 .vlan_filter_set = ice_vlan_filter_set,
198 .vlan_offload_set = ice_vlan_offload_set,
199 .reta_update = ice_rss_reta_update,
200 .reta_query = ice_rss_reta_query,
201 .rss_hash_update = ice_rss_hash_update,
202 .rss_hash_conf_get = ice_rss_hash_conf_get,
203 .promiscuous_enable = ice_promisc_enable,
204 .promiscuous_disable = ice_promisc_disable,
205 .allmulticast_enable = ice_allmulti_enable,
206 .allmulticast_disable = ice_allmulti_disable,
207 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
208 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
209 .fw_version_get = ice_fw_version_get,
210 .vlan_pvid_set = ice_vlan_pvid_set,
211 .rxq_info_get = ice_rxq_info_get,
212 .txq_info_get = ice_txq_info_get,
213 .rx_burst_mode_get = ice_rx_burst_mode_get,
214 .tx_burst_mode_get = ice_tx_burst_mode_get,
215 .get_eeprom_length = ice_get_eeprom_length,
216 .get_eeprom = ice_get_eeprom,
217 .stats_get = ice_stats_get,
218 .stats_reset = ice_stats_reset,
219 .xstats_get = ice_xstats_get,
220 .xstats_get_names = ice_xstats_get_names,
221 .xstats_reset = ice_stats_reset,
222 .flow_ops_get = ice_dev_flow_ops_get,
223 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
224 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
225 .tx_done_cleanup = ice_tx_done_cleanup,
226 .get_monitor_addr = ice_get_monitor_addr,
229 /* store statistics names and its offset in stats structure */
230 struct ice_xstats_name_off {
231 char name[RTE_ETH_XSTATS_NAME_SIZE];
235 static const struct ice_xstats_name_off ice_stats_strings[] = {
236 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
237 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
238 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
239 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
240 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
241 rx_unknown_protocol)},
242 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
243 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
244 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
245 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
248 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
249 sizeof(ice_stats_strings[0]))
251 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
252 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
253 tx_dropped_link_down)},
254 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
255 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
257 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
258 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
260 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
262 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
264 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
265 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
266 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
267 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
268 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
269 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
271 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
273 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
275 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
277 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
279 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
281 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
283 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
285 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
286 mac_short_pkt_dropped)},
287 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
289 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
290 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
291 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
293 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
295 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
297 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
299 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
301 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
305 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
306 sizeof(ice_hw_port_strings[0]))
309 ice_init_controlq_parameter(struct ice_hw *hw)
311 /* fields for adminq */
312 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
313 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
314 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
315 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
317 /* fields for mailboxq, DPDK used as PF host */
318 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
319 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
320 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
321 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
325 lookup_proto_xtr_type(const char *xtr_name)
329 enum proto_xtr_type type;
331 { "vlan", PROTO_XTR_VLAN },
332 { "ipv4", PROTO_XTR_IPV4 },
333 { "ipv6", PROTO_XTR_IPV6 },
334 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
335 { "tcp", PROTO_XTR_TCP },
336 { "ip_offset", PROTO_XTR_IP_OFFSET },
340 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
341 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
342 return xtr_type_map[i].type;
349 * Parse elem, the elem could be single number/range or '(' ')' group
350 * 1) A single number elem, it's just a simple digit. e.g. 9
351 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
352 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
353 * Within group elem, '-' used for a range separator;
354 * ',' used for a single number.
357 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
359 const char *str = input;
364 while (isblank(*str))
367 if (!isdigit(*str) && *str != '(')
370 /* process single number or single range of number */
373 idx = strtoul(str, &end, 10);
374 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
377 while (isblank(*end))
383 /* process single <number>-<number> */
386 while (isblank(*end))
392 idx = strtoul(end, &end, 10);
393 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
397 while (isblank(*end))
404 for (idx = RTE_MIN(min, max);
405 idx <= RTE_MAX(min, max); idx++)
406 devargs->proto_xtr[idx] = xtr_type;
411 /* process set within bracket */
413 while (isblank(*str))
418 min = ICE_MAX_QUEUE_NUM;
420 /* go ahead to the first digit */
421 while (isblank(*str))
426 /* get the digit value */
428 idx = strtoul(str, &end, 10);
429 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
432 /* go ahead to separator '-',',' and ')' */
433 while (isblank(*end))
436 if (min == ICE_MAX_QUEUE_NUM)
438 else /* avoid continuous '-' */
440 } else if (*end == ',' || *end == ')') {
442 if (min == ICE_MAX_QUEUE_NUM)
445 for (idx = RTE_MIN(min, max);
446 idx <= RTE_MAX(min, max); idx++)
447 devargs->proto_xtr[idx] = xtr_type;
449 min = ICE_MAX_QUEUE_NUM;
455 } while (*end != ')' && *end != '\0');
461 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
463 const char *queue_start;
468 while (isblank(*queues))
471 if (*queues != '[') {
472 xtr_type = lookup_proto_xtr_type(queues);
476 devargs->proto_xtr_dflt = xtr_type;
483 while (isblank(*queues))
488 queue_start = queues;
490 /* go across a complete bracket */
491 if (*queue_start == '(') {
492 queues += strcspn(queues, ")");
497 /* scan the separator ':' */
498 queues += strcspn(queues, ":");
499 if (*queues++ != ':')
501 while (isblank(*queues))
504 for (idx = 0; ; idx++) {
505 if (isblank(queues[idx]) ||
506 queues[idx] == ',' ||
507 queues[idx] == ']' ||
511 if (idx > sizeof(xtr_name) - 2)
514 xtr_name[idx] = queues[idx];
516 xtr_name[idx] = '\0';
517 xtr_type = lookup_proto_xtr_type(xtr_name);
523 while (isblank(*queues) || *queues == ',' || *queues == ']')
526 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
528 } while (*queues != '\0');
534 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
537 struct ice_devargs *devargs = extra_args;
539 if (value == NULL || extra_args == NULL)
542 if (parse_queue_proto_xtr(value, devargs) < 0) {
544 "The protocol extraction parameter is wrong : '%s'",
553 ice_check_proto_xtr_support(struct ice_hw *hw)
555 #define FLX_REG(val, fld, idx) \
556 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
557 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
564 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
566 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
567 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
569 ICE_PROT_IPV4_OF_OR_S,
570 ICE_PROT_IPV4_OF_OR_S },
571 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
573 ICE_PROT_IPV6_OF_OR_S,
574 ICE_PROT_IPV6_OF_OR_S },
575 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
577 ICE_PROT_IPV6_OF_OR_S,
578 ICE_PROT_IPV6_OF_OR_S },
579 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
581 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
582 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
584 ICE_PROT_IPV4_OF_OR_S,
585 ICE_PROT_IPV6_OF_OR_S },
589 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
590 uint32_t rxdid = xtr_sets[i].rxdid;
593 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
594 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
596 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
597 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
598 ice_proto_xtr_hw_support[i] = true;
601 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
602 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
604 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
605 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
606 ice_proto_xtr_hw_support[i] = true;
612 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
615 struct pool_entry *entry;
620 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
623 "Failed to allocate memory for resource pool");
627 /* queue heap initialize */
628 pool->num_free = num;
631 LIST_INIT(&pool->alloc_list);
632 LIST_INIT(&pool->free_list);
634 /* Initialize element */
638 LIST_INSERT_HEAD(&pool->free_list, entry, next);
643 ice_res_pool_alloc(struct ice_res_pool_info *pool,
646 struct pool_entry *entry, *valid_entry;
649 PMD_INIT_LOG(ERR, "Invalid parameter");
653 if (pool->num_free < num) {
654 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
655 num, pool->num_free);
660 /* Lookup in free list and find most fit one */
661 LIST_FOREACH(entry, &pool->free_list, next) {
662 if (entry->len >= num) {
664 if (entry->len == num) {
669 valid_entry->len > entry->len)
674 /* Not find one to satisfy the request, return */
676 PMD_INIT_LOG(ERR, "No valid entry found");
680 * The entry have equal queue number as requested,
681 * remove it from alloc_list.
683 if (valid_entry->len == num) {
684 LIST_REMOVE(valid_entry, next);
687 * The entry have more numbers than requested,
688 * create a new entry for alloc_list and minus its
689 * queue base and number in free_list.
691 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
694 "Failed to allocate memory for "
698 entry->base = valid_entry->base;
700 valid_entry->base += num;
701 valid_entry->len -= num;
705 /* Insert it into alloc list, not sorted */
706 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
708 pool->num_free -= valid_entry->len;
709 pool->num_alloc += valid_entry->len;
711 return valid_entry->base + pool->base;
715 ice_res_pool_destroy(struct ice_res_pool_info *pool)
717 struct pool_entry *entry, *next_entry;
722 for (entry = LIST_FIRST(&pool->alloc_list);
723 entry && (next_entry = LIST_NEXT(entry, next), 1);
724 entry = next_entry) {
725 LIST_REMOVE(entry, next);
729 for (entry = LIST_FIRST(&pool->free_list);
730 entry && (next_entry = LIST_NEXT(entry, next), 1);
731 entry = next_entry) {
732 LIST_REMOVE(entry, next);
739 LIST_INIT(&pool->alloc_list);
740 LIST_INIT(&pool->free_list);
744 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
746 /* Set VSI LUT selection */
747 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
748 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
749 /* Set Hash scheme */
750 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
751 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
753 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
756 static enum ice_status
757 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
758 struct ice_aqc_vsi_props *info,
759 uint8_t enabled_tcmap)
761 uint16_t bsf, qp_idx;
763 /* default tc 0 now. Multi-TC supporting need to be done later.
764 * Configure TC and queue mapping parameters, for enabled TC,
765 * allocate qpnum_per_tc queues to this traffic.
767 if (enabled_tcmap != 0x01) {
768 PMD_INIT_LOG(ERR, "only TC0 is supported");
772 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
773 bsf = rte_bsf32(vsi->nb_qps);
774 /* Adjust the queue number to actual queues that can be applied */
775 vsi->nb_qps = 0x1 << bsf;
778 /* Set tc and queue mapping with VSI */
779 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
780 ICE_AQ_VSI_TC_Q_OFFSET_S) |
781 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
783 /* Associate queue number with VSI */
784 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
785 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
786 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
787 info->valid_sections |=
788 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
789 /* Set the info.ingress_table and info.egress_table
790 * for UP translate table. Now just set it to 1:1 map by default
791 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
793 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
794 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
795 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
796 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
801 ice_init_mac_address(struct rte_eth_dev *dev)
803 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
805 if (!rte_is_unicast_ether_addr
806 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
807 PMD_INIT_LOG(ERR, "Invalid MAC address");
812 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
813 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
815 dev->data->mac_addrs =
816 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0);
817 if (!dev->data->mac_addrs) {
819 "Failed to allocate memory to store mac address");
822 /* store it to dev data */
824 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
825 &dev->data->mac_addrs[0]);
829 /* Find out specific MAC filter */
830 static struct ice_mac_filter *
831 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
833 struct ice_mac_filter *f;
835 TAILQ_FOREACH(f, &vsi->mac_list, next) {
836 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
844 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
846 struct ice_fltr_list_entry *m_list_itr = NULL;
847 struct ice_mac_filter *f;
848 struct LIST_HEAD_TYPE list_head;
849 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
852 /* If it's added and configured, return */
853 f = ice_find_mac_filter(vsi, mac_addr);
855 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
859 INIT_LIST_HEAD(&list_head);
861 m_list_itr = (struct ice_fltr_list_entry *)
862 ice_malloc(hw, sizeof(*m_list_itr));
867 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
868 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
869 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
870 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
871 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
872 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
873 m_list_itr->fltr_info.vsi_handle = vsi->idx;
875 LIST_ADD(&m_list_itr->list_entry, &list_head);
878 ret = ice_add_mac(hw, &list_head);
879 if (ret != ICE_SUCCESS) {
880 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
884 /* Add the mac addr into mac list */
885 f = rte_zmalloc(NULL, sizeof(*f), 0);
887 PMD_DRV_LOG(ERR, "failed to allocate memory");
891 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
892 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
898 rte_free(m_list_itr);
903 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
905 struct ice_fltr_list_entry *m_list_itr = NULL;
906 struct ice_mac_filter *f;
907 struct LIST_HEAD_TYPE list_head;
908 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
911 /* Can't find it, return an error */
912 f = ice_find_mac_filter(vsi, mac_addr);
916 INIT_LIST_HEAD(&list_head);
918 m_list_itr = (struct ice_fltr_list_entry *)
919 ice_malloc(hw, sizeof(*m_list_itr));
924 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
925 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
926 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
927 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
928 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
929 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
930 m_list_itr->fltr_info.vsi_handle = vsi->idx;
932 LIST_ADD(&m_list_itr->list_entry, &list_head);
934 /* remove the mac filter */
935 ret = ice_remove_mac(hw, &list_head);
936 if (ret != ICE_SUCCESS) {
937 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
942 /* Remove the mac addr from mac list */
943 TAILQ_REMOVE(&vsi->mac_list, f, next);
949 rte_free(m_list_itr);
953 /* Find out specific VLAN filter */
954 static struct ice_vlan_filter *
955 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
957 struct ice_vlan_filter *f;
959 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
960 if (vlan->tpid == f->vlan_info.vlan.tpid &&
961 vlan->vid == f->vlan_info.vlan.vid)
969 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
971 struct ice_fltr_list_entry *v_list_itr = NULL;
972 struct ice_vlan_filter *f;
973 struct LIST_HEAD_TYPE list_head;
977 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
980 hw = ICE_VSI_TO_HW(vsi);
982 /* If it's added and configured, return. */
983 f = ice_find_vlan_filter(vsi, vlan);
985 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
989 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
992 INIT_LIST_HEAD(&list_head);
994 v_list_itr = (struct ice_fltr_list_entry *)
995 ice_malloc(hw, sizeof(*v_list_itr));
1000 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1001 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1002 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1003 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1004 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1005 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1006 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1007 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1009 LIST_ADD(&v_list_itr->list_entry, &list_head);
1012 ret = ice_add_vlan(hw, &list_head);
1013 if (ret != ICE_SUCCESS) {
1014 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1019 /* Add vlan into vlan list */
1020 f = rte_zmalloc(NULL, sizeof(*f), 0);
1022 PMD_DRV_LOG(ERR, "failed to allocate memory");
1026 f->vlan_info.vlan.tpid = vlan->tpid;
1027 f->vlan_info.vlan.vid = vlan->vid;
1028 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1034 rte_free(v_list_itr);
1039 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1041 struct ice_fltr_list_entry *v_list_itr = NULL;
1042 struct ice_vlan_filter *f;
1043 struct LIST_HEAD_TYPE list_head;
1047 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1050 hw = ICE_VSI_TO_HW(vsi);
1052 /* Can't find it, return an error */
1053 f = ice_find_vlan_filter(vsi, vlan);
1057 INIT_LIST_HEAD(&list_head);
1059 v_list_itr = (struct ice_fltr_list_entry *)
1060 ice_malloc(hw, sizeof(*v_list_itr));
1066 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1067 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1068 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1069 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1070 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1071 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1072 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1073 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1075 LIST_ADD(&v_list_itr->list_entry, &list_head);
1077 /* remove the vlan filter */
1078 ret = ice_remove_vlan(hw, &list_head);
1079 if (ret != ICE_SUCCESS) {
1080 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1085 /* Remove the vlan id from vlan list */
1086 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1092 rte_free(v_list_itr);
1097 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1099 struct ice_mac_filter *m_f;
1100 struct ice_vlan_filter *v_f;
1104 if (!vsi || !vsi->mac_num)
1107 TAILQ_FOREACH_SAFE(m_f, &vsi->mac_list, next, temp) {
1108 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1109 if (ret != ICE_SUCCESS) {
1115 if (vsi->vlan_num == 0)
1118 TAILQ_FOREACH_SAFE(v_f, &vsi->vlan_list, next, temp) {
1119 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1120 if (ret != ICE_SUCCESS) {
1132 ice_pf_enable_irq0(struct ice_hw *hw)
1134 /* reset the registers */
1135 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1136 ICE_READ_REG(hw, PFINT_OICR);
1139 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1140 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1141 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1143 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1144 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1145 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1146 PFINT_OICR_CTL_ITR_INDX_M) |
1147 PFINT_OICR_CTL_CAUSE_ENA_M);
1149 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1150 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1151 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1152 PFINT_FW_CTL_ITR_INDX_M) |
1153 PFINT_FW_CTL_CAUSE_ENA_M);
1155 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1158 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1159 GLINT_DYN_CTL_INTENA_M |
1160 GLINT_DYN_CTL_CLEARPBA_M |
1161 GLINT_DYN_CTL_ITR_INDX_M);
1168 ice_pf_disable_irq0(struct ice_hw *hw)
1170 /* Disable all interrupt types */
1171 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1177 ice_handle_aq_msg(struct rte_eth_dev *dev)
1179 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1180 struct ice_ctl_q_info *cq = &hw->adminq;
1181 struct ice_rq_event_info event;
1182 uint16_t pending, opcode;
1185 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1186 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1187 if (!event.msg_buf) {
1188 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1194 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1196 if (ret != ICE_SUCCESS) {
1198 "Failed to read msg from AdminQ, "
1200 hw->adminq.sq_last_status);
1203 opcode = rte_le_to_cpu_16(event.desc.opcode);
1206 case ice_aqc_opc_get_link_status:
1207 ret = ice_link_update(dev, 0);
1209 rte_eth_dev_callback_process
1210 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1213 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1218 rte_free(event.msg_buf);
1223 * Interrupt handler triggered by NIC for handling
1224 * specific interrupt.
1227 * Pointer to interrupt handle.
1229 * The address of parameter (struct rte_eth_dev *) regsitered before.
1235 ice_interrupt_handler(void *param)
1237 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1238 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246 uint32_t int_fw_ctl;
1249 /* Disable interrupt */
1250 ice_pf_disable_irq0(hw);
1252 /* read out interrupt causes */
1253 oicr = ICE_READ_REG(hw, PFINT_OICR);
1255 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1258 /* No interrupt event indicated */
1259 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1260 PMD_DRV_LOG(INFO, "No interrupt event");
1265 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1266 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1267 ice_handle_aq_msg(dev);
1270 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1271 PMD_DRV_LOG(INFO, "OICR: link state change event");
1272 ret = ice_link_update(dev, 0);
1274 rte_eth_dev_callback_process
1275 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1279 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1280 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1281 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1282 if (reg & GL_MDET_TX_PQM_VALID_M) {
1283 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1284 GL_MDET_TX_PQM_PF_NUM_S;
1285 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1286 GL_MDET_TX_PQM_MAL_TYPE_S;
1287 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1288 GL_MDET_TX_PQM_QNUM_S;
1290 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1291 "%d by PQM on TX queue %d PF# %d",
1292 event, queue, pf_num);
1295 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1296 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1297 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1298 GL_MDET_TX_TCLAN_PF_NUM_S;
1299 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1300 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1301 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1302 GL_MDET_TX_TCLAN_QNUM_S;
1304 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1305 "%d by TCLAN on TX queue %d PF# %d",
1306 event, queue, pf_num);
1310 /* Enable interrupt */
1311 ice_pf_enable_irq0(hw);
1312 rte_intr_ack(dev->intr_handle);
1316 ice_init_proto_xtr(struct rte_eth_dev *dev)
1318 struct ice_adapter *ad =
1319 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1320 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1321 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1322 const struct proto_xtr_ol_flag *ol_flag;
1323 bool proto_xtr_enable = false;
1327 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1328 if (unlikely(pf->proto_xtr == NULL)) {
1329 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1333 for (i = 0; i < pf->lan_nb_qps; i++) {
1334 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1335 ad->devargs.proto_xtr[i] :
1336 ad->devargs.proto_xtr_dflt;
1338 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1339 uint8_t type = pf->proto_xtr[i];
1341 ice_proto_xtr_ol_flag_params[type].required = true;
1342 proto_xtr_enable = true;
1346 if (likely(!proto_xtr_enable))
1349 ice_check_proto_xtr_support(hw);
1351 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1352 if (unlikely(offset == -1)) {
1354 "Protocol extraction metadata is disabled in mbuf with error %d",
1360 "Protocol extraction metadata offset in mbuf is : %d",
1362 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1364 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1365 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1367 if (!ol_flag->required)
1370 if (!ice_proto_xtr_hw_support[i]) {
1372 "Protocol extraction type %u is not supported in hardware",
1374 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1378 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1379 if (unlikely(offset == -1)) {
1381 "Protocol extraction offload '%s' failed to register with error %d",
1382 ol_flag->param.name, -rte_errno);
1384 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1389 "Protocol extraction offload '%s' offset in mbuf is : %d",
1390 ol_flag->param.name, offset);
1391 *ol_flag->ol_flag = 1ULL << offset;
1395 /* Initialize SW parameters of PF */
1397 ice_pf_sw_init(struct rte_eth_dev *dev)
1399 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1400 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1403 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1404 hw->func_caps.common_cap.num_rxq);
1406 pf->lan_nb_qps = pf->lan_nb_qp_max;
1408 ice_init_proto_xtr(dev);
1410 if (hw->func_caps.fd_fltr_guar > 0 ||
1411 hw->func_caps.fd_fltr_best_effort > 0) {
1412 pf->flags |= ICE_FLAG_FDIR;
1413 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1414 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1416 pf->fdir_nb_qps = 0;
1418 pf->fdir_qp_offset = 0;
1424 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1426 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1427 struct ice_vsi *vsi = NULL;
1428 struct ice_vsi_ctx vsi_ctx;
1430 struct rte_ether_addr broadcast = {
1431 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1432 struct rte_ether_addr mac_addr;
1433 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1434 uint8_t tc_bitmap = 0x1;
1437 /* hw->num_lports = 1 in NIC mode */
1438 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1442 vsi->idx = pf->next_vsi_idx;
1445 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1446 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1447 vsi->vlan_anti_spoof_on = 0;
1448 vsi->vlan_filter_on = 1;
1449 TAILQ_INIT(&vsi->mac_list);
1450 TAILQ_INIT(&vsi->vlan_list);
1452 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1453 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1454 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1455 hw->func_caps.common_cap.rss_table_size;
1456 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1458 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1461 vsi->nb_qps = pf->lan_nb_qps;
1462 vsi->base_queue = 1;
1463 ice_vsi_config_default_rss(&vsi_ctx.info);
1464 vsi_ctx.alloc_from_pool = true;
1465 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1466 /* switch_id is queried by get_switch_config aq, which is done
1469 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1470 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1471 /* Allow all untagged or tagged packets */
1472 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1473 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1474 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1475 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1476 if (ice_is_dvm_ena(hw)) {
1477 vsi_ctx.info.outer_vlan_flags =
1478 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1479 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1480 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1481 vsi_ctx.info.outer_vlan_flags |=
1482 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1483 ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1484 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1488 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1489 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1490 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1491 cfg = ICE_AQ_VSI_FD_ENABLE;
1492 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1493 vsi_ctx.info.max_fd_fltr_dedicated =
1494 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1495 vsi_ctx.info.max_fd_fltr_shared =
1496 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1498 /* Enable VLAN/UP trip */
1499 ret = ice_vsi_config_tc_queue_mapping(vsi,
1504 "tc queue mapping with vsi failed, "
1512 vsi->nb_qps = pf->fdir_nb_qps;
1513 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1514 vsi_ctx.alloc_from_pool = true;
1515 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1517 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1518 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1519 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1520 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1521 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1522 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1523 ret = ice_vsi_config_tc_queue_mapping(vsi,
1528 "tc queue mapping with vsi failed, "
1535 /* for other types of VSI */
1536 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1540 /* VF has MSIX interrupt in VF range, don't allocate here */
1541 if (type == ICE_VSI_PF) {
1542 ret = ice_res_pool_alloc(&pf->msix_pool,
1543 RTE_MIN(vsi->nb_qps,
1544 RTE_MAX_RXTX_INTR_VEC_ID));
1546 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1549 vsi->msix_intr = ret;
1550 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1551 } else if (type == ICE_VSI_CTRL) {
1552 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1554 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1557 vsi->msix_intr = ret;
1563 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1564 if (ret != ICE_SUCCESS) {
1565 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1568 /* store vsi information is SW structure */
1569 vsi->vsi_id = vsi_ctx.vsi_num;
1570 vsi->info = vsi_ctx.info;
1571 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1572 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1574 if (type == ICE_VSI_PF) {
1575 /* MAC configuration */
1576 rte_ether_addr_copy((struct rte_ether_addr *)
1577 hw->port_info->mac.perm_addr,
1580 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1581 ret = ice_add_mac_filter(vsi, &mac_addr);
1582 if (ret != ICE_SUCCESS)
1583 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1585 rte_ether_addr_copy(&broadcast, &mac_addr);
1586 ret = ice_add_mac_filter(vsi, &mac_addr);
1587 if (ret != ICE_SUCCESS)
1588 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1591 /* At the beginning, only TC0. */
1592 /* What we need here is the maximam number of the TX queues.
1593 * Currently vsi->nb_qps means it.
1594 * Correct it if any change.
1596 max_txqs[0] = vsi->nb_qps;
1597 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1598 tc_bitmap, max_txqs);
1599 if (ret != ICE_SUCCESS)
1600 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1610 ice_send_driver_ver(struct ice_hw *hw)
1612 struct ice_driver_ver dv;
1614 /* we don't have driver version use 0 for dummy */
1618 dv.subbuild_ver = 0;
1619 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1621 return ice_aq_send_driver_ver(hw, &dv, NULL);
1625 ice_pf_setup(struct ice_pf *pf)
1627 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1628 struct ice_vsi *vsi;
1631 /* Clear all stats counters */
1632 pf->offset_loaded = false;
1633 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1634 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1635 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1636 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1638 /* force guaranteed filter pool for PF */
1639 ice_alloc_fd_guar_item(hw, &unused,
1640 hw->func_caps.fd_fltr_guar);
1641 /* force shared filter pool for PF */
1642 ice_alloc_fd_shrd_item(hw, &unused,
1643 hw->func_caps.fd_fltr_best_effort);
1645 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1647 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1656 static enum ice_pkg_type
1657 ice_load_pkg_type(struct ice_hw *hw)
1659 enum ice_pkg_type package_type;
1661 /* store the activated package type (OS default or Comms) */
1662 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1664 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1665 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1667 package_type = ICE_PKG_TYPE_COMMS;
1669 package_type = ICE_PKG_TYPE_UNKNOWN;
1671 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1672 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1673 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1674 hw->active_pkg_name,
1675 ice_is_dvm_ena(hw) ? "double" : "single");
1677 return package_type;
1680 int ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn)
1682 struct ice_hw *hw = &adapter->hw;
1683 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1684 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1692 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1693 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1694 "ice-%016" PRIx64 ".pkg", dsn);
1695 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1696 ICE_MAX_PKG_FILENAME_SIZE);
1697 strcat(pkg_file, opt_ddp_filename);
1698 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1701 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1702 ICE_MAX_PKG_FILENAME_SIZE);
1703 strcat(pkg_file, opt_ddp_filename);
1704 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1708 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1709 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1712 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1713 if (rte_firmware_read(pkg_file, &buf, &bufsz) < 0) {
1714 PMD_INIT_LOG(ERR, "failed to search file path\n");
1719 PMD_INIT_LOG(DEBUG, "DDP package name: %s", pkg_file);
1721 err = ice_copy_and_init_pkg(hw, buf, bufsz);
1723 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1727 /* store the loaded pkg type info */
1728 adapter->active_pkg_type = ice_load_pkg_type(hw);
1736 ice_base_queue_get(struct ice_pf *pf)
1739 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1741 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1742 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1743 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1745 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1751 parse_bool(const char *key, const char *value, void *args)
1753 int *i = (int *)args;
1757 num = strtoul(value, &end, 10);
1759 if (num != 0 && num != 1) {
1760 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1761 "value must be 0 or 1",
1771 parse_u64(const char *key, const char *value, void *args)
1773 u64 *num = (u64 *)args;
1777 tmp = strtoull(value, NULL, 16);
1779 PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u64",
1789 static int ice_parse_devargs(struct rte_eth_dev *dev)
1791 struct ice_adapter *ad =
1792 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1793 struct rte_devargs *devargs = dev->device->devargs;
1794 struct rte_kvargs *kvlist;
1797 if (devargs == NULL)
1800 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1801 if (kvlist == NULL) {
1802 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1806 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1807 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1808 sizeof(ad->devargs.proto_xtr));
1810 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1811 &handle_proto_xtr_arg, &ad->devargs);
1815 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1816 &parse_bool, &ad->devargs.safe_mode_support);
1820 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1821 &parse_bool, &ad->devargs.pipe_mode_support);
1825 ret = rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG,
1826 &parse_u64, &ad->hw.debug_mask);
1831 rte_kvargs_free(kvlist);
1835 /* Forward LLDP packets to default VSI by set switch rules */
1837 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1839 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1840 struct ice_fltr_list_entry *s_list_itr = NULL;
1841 struct LIST_HEAD_TYPE list_head;
1844 INIT_LIST_HEAD(&list_head);
1846 s_list_itr = (struct ice_fltr_list_entry *)
1847 ice_malloc(hw, sizeof(*s_list_itr));
1850 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1851 s_list_itr->fltr_info.vsi_handle = vsi->idx;
1852 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1853 RTE_ETHER_TYPE_LLDP;
1854 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1855 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1856 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1857 LIST_ADD(&s_list_itr->list_entry, &list_head);
1859 ret = ice_add_eth_mac(hw, &list_head);
1861 ret = ice_remove_eth_mac(hw, &list_head);
1863 rte_free(s_list_itr);
1867 static enum ice_status
1868 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1869 uint16_t num, uint16_t desc_id,
1870 uint16_t *prof_buf, uint16_t *num_prof)
1872 struct ice_aqc_res_elem *resp_buf;
1875 bool res_shared = 1;
1876 struct ice_aq_desc aq_desc;
1877 struct ice_sq_cd *cd = NULL;
1878 struct ice_aqc_get_allocd_res_desc *cmd =
1879 &aq_desc.params.get_res_desc;
1881 buf_len = sizeof(*resp_buf) * num;
1882 resp_buf = ice_malloc(hw, buf_len);
1886 ice_fill_dflt_direct_cmd_desc(&aq_desc,
1887 ice_aqc_opc_get_allocd_res_desc);
1889 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1890 ICE_AQC_RES_TYPE_M) | (res_shared ?
1891 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1892 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1894 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1896 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1900 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
1901 (*num_prof), ICE_NONDMA_TO_NONDMA);
1908 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1912 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1913 uint16_t first_desc = 1;
1914 uint16_t num_prof = 0;
1916 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1917 first_desc, prof_buf, &num_prof);
1919 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
1923 for (prof_id = 0; prof_id < num_prof; prof_id++) {
1924 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
1926 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
1934 ice_reset_fxp_resource(struct ice_hw *hw)
1938 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
1940 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
1944 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
1946 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
1954 ice_rss_ctx_init(struct ice_pf *pf)
1956 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
1960 ice_get_supported_rxdid(struct ice_hw *hw)
1962 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
1966 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
1968 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
1969 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
1970 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
1971 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
1972 supported_rxdid |= BIT(i);
1974 return supported_rxdid;
1978 ice_dev_init(struct rte_eth_dev *dev)
1980 struct rte_pci_device *pci_dev;
1981 struct rte_intr_handle *intr_handle;
1982 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1984 struct ice_adapter *ad =
1985 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1986 struct ice_vsi *vsi;
1988 #ifndef RTE_EXEC_ENV_WINDOWS
1990 uint32_t dsn_low, dsn_high;
1995 dev->dev_ops = &ice_eth_dev_ops;
1996 dev->rx_queue_count = ice_rx_queue_count;
1997 dev->rx_descriptor_status = ice_rx_descriptor_status;
1998 dev->tx_descriptor_status = ice_tx_descriptor_status;
1999 dev->rx_pkt_burst = ice_recv_pkts;
2000 dev->tx_pkt_burst = ice_xmit_pkts;
2001 dev->tx_pkt_prepare = ice_prep_pkts;
2003 /* for secondary processes, we don't initialise any further as primary
2004 * has already done this work.
2006 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2007 ice_set_rx_function(dev);
2008 ice_set_tx_function(dev);
2012 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2014 ice_set_default_ptype_table(dev);
2015 pci_dev = RTE_DEV_TO_PCI(dev->device);
2016 intr_handle = &pci_dev->intr_handle;
2018 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2019 pf->dev_data = dev->data;
2020 hw->back = pf->adapter;
2021 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2022 hw->vendor_id = pci_dev->id.vendor_id;
2023 hw->device_id = pci_dev->id.device_id;
2024 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2025 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2026 hw->bus.device = pci_dev->addr.devid;
2027 hw->bus.func = pci_dev->addr.function;
2029 ret = ice_parse_devargs(dev);
2031 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2035 ice_init_controlq_parameter(hw);
2037 ret = ice_init_hw(hw);
2039 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2043 #ifndef RTE_EXEC_ENV_WINDOWS
2046 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
2048 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0 ||
2049 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) {
2050 PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
2053 dsn = (uint64_t)dsn_high << 32 | dsn_low;
2056 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
2059 ret = ice_load_pkg(pf->adapter, use_dsn, dsn);
2061 ret = ice_init_hw_tbls(hw);
2063 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", ret);
2064 rte_free(hw->pkg_copy);
2069 if (ad->devargs.safe_mode_support == 0) {
2070 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2071 "Use safe-mode-support=1 to enter Safe Mode");
2075 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2076 "Entering Safe Mode");
2077 ad->is_safe_mode = 1;
2081 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2082 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2083 hw->api_maj_ver, hw->api_min_ver);
2085 ice_pf_sw_init(dev);
2086 ret = ice_init_mac_address(dev);
2088 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2092 ret = ice_res_pool_init(&pf->msix_pool, 1,
2093 hw->func_caps.common_cap.num_msix_vectors - 1);
2095 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2096 goto err_msix_pool_init;
2099 ret = ice_pf_setup(pf);
2101 PMD_INIT_LOG(ERR, "Failed to setup PF");
2105 ret = ice_send_driver_ver(hw);
2107 PMD_INIT_LOG(ERR, "Failed to send driver version");
2113 ret = ice_aq_stop_lldp(hw, true, false, NULL);
2114 if (ret != ICE_SUCCESS)
2115 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2116 ret = ice_init_dcb(hw, true);
2117 if (ret != ICE_SUCCESS)
2118 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2119 /* Forward LLDP packets to default VSI */
2120 ret = ice_vsi_config_sw_lldp(vsi, true);
2121 if (ret != ICE_SUCCESS)
2122 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2123 /* register callback func to eal lib */
2124 rte_intr_callback_register(intr_handle,
2125 ice_interrupt_handler, dev);
2127 ice_pf_enable_irq0(hw);
2129 /* enable uio intr after callback register */
2130 rte_intr_enable(intr_handle);
2132 /* get base queue pairs index in the device */
2133 ice_base_queue_get(pf);
2135 /* Initialize RSS context for gtpu_eh */
2136 ice_rss_ctx_init(pf);
2138 if (!ad->is_safe_mode) {
2139 ret = ice_flow_init(ad);
2141 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2146 ret = ice_reset_fxp_resource(hw);
2148 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2152 pf->supported_rxdid = ice_get_supported_rxdid(hw);
2157 ice_res_pool_destroy(&pf->msix_pool);
2159 rte_free(dev->data->mac_addrs);
2160 dev->data->mac_addrs = NULL;
2162 ice_sched_cleanup_all(hw);
2163 rte_free(hw->port_info);
2164 ice_shutdown_all_ctrlq(hw);
2165 rte_free(pf->proto_xtr);
2171 ice_release_vsi(struct ice_vsi *vsi)
2174 struct ice_vsi_ctx vsi_ctx;
2175 enum ice_status ret;
2181 hw = ICE_VSI_TO_HW(vsi);
2183 ice_remove_all_mac_vlan_filters(vsi);
2185 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2187 vsi_ctx.vsi_num = vsi->vsi_id;
2188 vsi_ctx.info = vsi->info;
2189 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2190 if (ret != ICE_SUCCESS) {
2191 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2195 rte_free(vsi->rss_lut);
2196 rte_free(vsi->rss_key);
2202 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2204 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
2205 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2207 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2208 uint16_t msix_intr, i;
2210 /* disable interrupt and also clear all the exist config */
2211 for (i = 0; i < vsi->nb_qps; i++) {
2212 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2213 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2217 if (rte_intr_allow_others(intr_handle))
2219 for (i = 0; i < vsi->nb_msix; i++) {
2220 msix_intr = vsi->msix_intr + i;
2221 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2222 GLINT_DYN_CTL_WB_ON_ITR_M);
2226 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2230 ice_dev_stop(struct rte_eth_dev *dev)
2232 struct rte_eth_dev_data *data = dev->data;
2233 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2234 struct ice_vsi *main_vsi = pf->main_vsi;
2235 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2236 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2239 /* avoid stopping again */
2240 if (pf->adapter_stopped)
2243 /* stop and clear all Rx queues */
2244 for (i = 0; i < data->nb_rx_queues; i++)
2245 ice_rx_queue_stop(dev, i);
2247 /* stop and clear all Tx queues */
2248 for (i = 0; i < data->nb_tx_queues; i++)
2249 ice_tx_queue_stop(dev, i);
2251 /* disable all queue interrupts */
2252 ice_vsi_disable_queues_intr(main_vsi);
2254 if (pf->init_link_up)
2255 ice_dev_set_link_up(dev);
2257 ice_dev_set_link_down(dev);
2259 /* Clean datapath event and queue/vec mapping */
2260 rte_intr_efd_disable(intr_handle);
2261 if (intr_handle->intr_vec) {
2262 rte_free(intr_handle->intr_vec);
2263 intr_handle->intr_vec = NULL;
2266 pf->adapter_stopped = true;
2267 dev->data->dev_started = 0;
2273 ice_dev_close(struct rte_eth_dev *dev)
2275 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2276 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2278 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2279 struct ice_adapter *ad =
2280 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2283 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2286 /* Since stop will make link down, then the link event will be
2287 * triggered, disable the irq firstly to avoid the port_infoe etc
2288 * resources deallocation causing the interrupt service thread
2291 ice_pf_disable_irq0(hw);
2293 ret = ice_dev_stop(dev);
2295 if (!ad->is_safe_mode)
2296 ice_flow_uninit(ad);
2298 /* release all queue resource */
2299 ice_free_queues(dev);
2301 ice_res_pool_destroy(&pf->msix_pool);
2302 ice_release_vsi(pf->main_vsi);
2303 ice_sched_cleanup_all(hw);
2304 ice_free_hw_tbls(hw);
2305 rte_free(hw->port_info);
2306 hw->port_info = NULL;
2307 ice_shutdown_all_ctrlq(hw);
2308 rte_free(pf->proto_xtr);
2309 pf->proto_xtr = NULL;
2311 /* disable uio intr before callback unregister */
2312 rte_intr_disable(intr_handle);
2314 /* unregister callback func from eal lib */
2315 rte_intr_callback_unregister(intr_handle,
2316 ice_interrupt_handler, dev);
2322 ice_dev_uninit(struct rte_eth_dev *dev)
2330 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2332 return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2336 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2341 cfg->hdr_type = ICE_RSS_OUTER_HEADERS;
2345 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2347 enum ice_status status = ICE_SUCCESS;
2348 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2349 struct ice_vsi *vsi = pf->main_vsi;
2351 if (!is_hash_cfg_valid(cfg))
2354 status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2355 if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2357 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2366 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2368 enum ice_status status = ICE_SUCCESS;
2369 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2370 struct ice_vsi *vsi = pf->main_vsi;
2372 if (!is_hash_cfg_valid(cfg))
2375 status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2378 "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2387 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2391 ret = ice_hash_moveout(pf, cfg);
2392 if (ret && (ret != -ENOENT))
2395 hash_cfg_reset(cfg);
2401 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2407 case ICE_HASH_GTPU_CTX_EH_IP:
2408 ret = ice_hash_remove(pf,
2409 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2410 if (ret && (ret != -ENOENT))
2413 ret = ice_hash_remove(pf,
2414 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2415 if (ret && (ret != -ENOENT))
2418 ret = ice_hash_remove(pf,
2419 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2420 if (ret && (ret != -ENOENT))
2423 ret = ice_hash_remove(pf,
2424 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2425 if (ret && (ret != -ENOENT))
2428 ret = ice_hash_remove(pf,
2429 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2430 if (ret && (ret != -ENOENT))
2433 ret = ice_hash_remove(pf,
2434 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2435 if (ret && (ret != -ENOENT))
2438 ret = ice_hash_remove(pf,
2439 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2440 if (ret && (ret != -ENOENT))
2443 ret = ice_hash_remove(pf,
2444 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2445 if (ret && (ret != -ENOENT))
2449 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2450 ret = ice_hash_remove(pf,
2451 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2452 if (ret && (ret != -ENOENT))
2455 ret = ice_hash_remove(pf,
2456 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2457 if (ret && (ret != -ENOENT))
2460 ret = ice_hash_moveout(pf,
2461 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2462 if (ret && (ret != -ENOENT))
2465 ret = ice_hash_moveout(pf,
2466 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2467 if (ret && (ret != -ENOENT))
2470 ret = ice_hash_moveout(pf,
2471 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2472 if (ret && (ret != -ENOENT))
2475 ret = ice_hash_moveout(pf,
2476 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2477 if (ret && (ret != -ENOENT))
2481 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2482 ret = ice_hash_remove(pf,
2483 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2484 if (ret && (ret != -ENOENT))
2487 ret = ice_hash_remove(pf,
2488 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2489 if (ret && (ret != -ENOENT))
2492 ret = ice_hash_moveout(pf,
2493 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2494 if (ret && (ret != -ENOENT))
2497 ret = ice_hash_moveout(pf,
2498 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2499 if (ret && (ret != -ENOENT))
2502 ret = ice_hash_moveout(pf,
2503 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2504 if (ret && (ret != -ENOENT))
2507 ret = ice_hash_moveout(pf,
2508 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2509 if (ret && (ret != -ENOENT))
2513 case ICE_HASH_GTPU_CTX_UP_IP:
2514 ret = ice_hash_remove(pf,
2515 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2516 if (ret && (ret != -ENOENT))
2519 ret = ice_hash_remove(pf,
2520 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2521 if (ret && (ret != -ENOENT))
2524 ret = ice_hash_moveout(pf,
2525 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2526 if (ret && (ret != -ENOENT))
2529 ret = ice_hash_moveout(pf,
2530 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2531 if (ret && (ret != -ENOENT))
2534 ret = ice_hash_moveout(pf,
2535 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2536 if (ret && (ret != -ENOENT))
2540 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2541 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2542 ret = ice_hash_moveout(pf,
2543 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2544 if (ret && (ret != -ENOENT))
2547 ret = ice_hash_moveout(pf,
2548 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2549 if (ret && (ret != -ENOENT))
2552 ret = ice_hash_moveout(pf,
2553 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2554 if (ret && (ret != -ENOENT))
2558 case ICE_HASH_GTPU_CTX_DW_IP:
2559 ret = ice_hash_remove(pf,
2560 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2561 if (ret && (ret != -ENOENT))
2564 ret = ice_hash_remove(pf,
2565 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2566 if (ret && (ret != -ENOENT))
2569 ret = ice_hash_moveout(pf,
2570 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2571 if (ret && (ret != -ENOENT))
2574 ret = ice_hash_moveout(pf,
2575 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2576 if (ret && (ret != -ENOENT))
2579 ret = ice_hash_moveout(pf,
2580 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2581 if (ret && (ret != -ENOENT))
2585 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2586 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2587 ret = ice_hash_moveout(pf,
2588 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2589 if (ret && (ret != -ENOENT))
2592 ret = ice_hash_moveout(pf,
2593 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2594 if (ret && (ret != -ENOENT))
2597 ret = ice_hash_moveout(pf,
2598 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2599 if (ret && (ret != -ENOENT))
2610 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2614 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2616 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2618 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2621 return ICE_HASH_GTPU_CTX_MAX;
2624 if (hdr & ICE_FLOW_SEG_HDR_UDP)
2626 else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2629 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2630 return eh_idx * 3 + ip_idx;
2632 return ICE_HASH_GTPU_CTX_MAX;
2636 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2638 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2640 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2641 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2643 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2644 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2651 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2652 u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2656 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2657 ctx->ctx[ctx_idx] = *cfg;
2660 case ICE_HASH_GTPU_CTX_EH_IP:
2662 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2663 ret = ice_hash_moveback(pf,
2664 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2665 if (ret && (ret != -ENOENT))
2668 ret = ice_hash_moveback(pf,
2669 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2670 if (ret && (ret != -ENOENT))
2673 ret = ice_hash_moveback(pf,
2674 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2675 if (ret && (ret != -ENOENT))
2678 ret = ice_hash_moveback(pf,
2679 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2680 if (ret && (ret != -ENOENT))
2684 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2685 ret = ice_hash_moveback(pf,
2686 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2687 if (ret && (ret != -ENOENT))
2690 ret = ice_hash_moveback(pf,
2691 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2692 if (ret && (ret != -ENOENT))
2695 ret = ice_hash_moveback(pf,
2696 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2697 if (ret && (ret != -ENOENT))
2700 ret = ice_hash_moveback(pf,
2701 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2702 if (ret && (ret != -ENOENT))
2706 case ICE_HASH_GTPU_CTX_UP_IP:
2707 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2708 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2709 case ICE_HASH_GTPU_CTX_DW_IP:
2710 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2711 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2712 ret = ice_hash_moveback(pf,
2713 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2714 if (ret && (ret != -ENOENT))
2717 ret = ice_hash_moveback(pf,
2718 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2719 if (ret && (ret != -ENOENT))
2722 ret = ice_hash_moveback(pf,
2723 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2724 if (ret && (ret != -ENOENT))
2736 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2738 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2740 if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2741 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2743 else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2744 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2751 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2753 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2755 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2758 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2759 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2760 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2761 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2765 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2766 struct ice_rss_hash_cfg *cfg)
2768 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2771 ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2772 if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2773 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2775 ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2781 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2782 struct ice_rss_hash_cfg *cfg)
2784 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2787 ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2789 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2791 ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2793 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2795 ret = ice_add_rss_cfg_post(pf, cfg);
2797 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2803 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2805 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2806 struct ice_vsi *vsi = pf->main_vsi;
2807 struct ice_rss_hash_cfg cfg;
2810 #define ICE_RSS_HF_ALL ( \
2813 ETH_RSS_NONFRAG_IPV4_UDP | \
2814 ETH_RSS_NONFRAG_IPV6_UDP | \
2815 ETH_RSS_NONFRAG_IPV4_TCP | \
2816 ETH_RSS_NONFRAG_IPV6_TCP | \
2817 ETH_RSS_NONFRAG_IPV4_SCTP | \
2818 ETH_RSS_NONFRAG_IPV6_SCTP | \
2819 ETH_RSS_FRAG_IPV4 | \
2822 ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2824 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2828 cfg.hdr_type = ICE_RSS_OUTER_HEADERS;
2829 /* Configure RSS for IPv4 with src/dst addr as input set */
2830 if (rss_hf & ETH_RSS_IPV4) {
2831 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2832 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2833 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2835 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2839 /* Configure RSS for IPv6 with src/dst addr as input set */
2840 if (rss_hf & ETH_RSS_IPV6) {
2841 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2842 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2843 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2845 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2849 /* Configure RSS for udp4 with src/dst addr and port as input set */
2850 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2851 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2852 ICE_FLOW_SEG_HDR_IPV_OTHER;
2853 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2854 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2856 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2860 /* Configure RSS for udp6 with src/dst addr and port as input set */
2861 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2862 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
2863 ICE_FLOW_SEG_HDR_IPV_OTHER;
2864 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2865 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2867 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2871 /* Configure RSS for tcp4 with src/dst addr and port as input set */
2872 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2873 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
2874 ICE_FLOW_SEG_HDR_IPV_OTHER;
2875 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2876 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2878 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2882 /* Configure RSS for tcp6 with src/dst addr and port as input set */
2883 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2884 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
2885 ICE_FLOW_SEG_HDR_IPV_OTHER;
2886 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2887 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2889 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2893 /* Configure RSS for sctp4 with src/dst addr and port as input set */
2894 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2895 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
2896 ICE_FLOW_SEG_HDR_IPV_OTHER;
2897 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
2898 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2900 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2904 /* Configure RSS for sctp6 with src/dst addr and port as input set */
2905 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2906 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
2907 ICE_FLOW_SEG_HDR_IPV_OTHER;
2908 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
2909 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2911 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2915 if (rss_hf & ETH_RSS_IPV4) {
2916 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
2917 ICE_FLOW_SEG_HDR_IPV_OTHER;
2918 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2919 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2921 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2925 if (rss_hf & ETH_RSS_IPV6) {
2926 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
2927 ICE_FLOW_SEG_HDR_IPV_OTHER;
2928 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2929 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2931 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2935 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2936 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2937 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2938 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2939 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2941 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2945 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2946 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2947 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2948 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2949 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2951 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
2955 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2956 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
2957 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2958 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2959 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2961 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
2965 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2966 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
2967 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2968 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2969 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2971 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
2975 if (rss_hf & ETH_RSS_FRAG_IPV4) {
2976 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_FRAG;
2977 cfg.hash_flds = ICE_FLOW_HASH_IPV4 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_ID);
2978 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2980 PMD_DRV_LOG(ERR, "%s IPV4_FRAG rss flow fail %d",
2984 if (rss_hf & ETH_RSS_FRAG_IPV6) {
2985 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_FRAG;
2986 cfg.hash_flds = ICE_FLOW_HASH_IPV6 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_ID);
2987 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2989 PMD_DRV_LOG(ERR, "%s IPV6_FRAG rss flow fail %d",
2993 pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
2997 ice_get_default_rss_key(uint8_t *rss_key, uint32_t rss_key_size)
2999 static struct ice_aqc_get_set_rss_keys default_key;
3000 static bool default_key_done;
3001 uint8_t *key = (uint8_t *)&default_key;
3004 if (rss_key_size > sizeof(default_key)) {
3005 PMD_DRV_LOG(WARNING,
3006 "requested size %u is larger than default %zu, "
3007 "only %zu bytes are gotten for key\n",
3008 rss_key_size, sizeof(default_key),
3009 sizeof(default_key));
3012 if (!default_key_done) {
3013 /* Calculate the default hash key */
3014 for (i = 0; i < sizeof(default_key); i++)
3015 key[i] = (uint8_t)rte_rand();
3016 default_key_done = true;
3018 rte_memcpy(rss_key, key, RTE_MIN(rss_key_size, sizeof(default_key)));
3021 static int ice_init_rss(struct ice_pf *pf)
3023 struct ice_hw *hw = ICE_PF_TO_HW(pf);
3024 struct ice_vsi *vsi = pf->main_vsi;
3025 struct rte_eth_dev_data *dev_data = pf->dev_data;
3026 struct ice_aq_get_set_rss_lut_params lut_params;
3027 struct rte_eth_rss_conf *rss_conf;
3028 struct ice_aqc_get_set_rss_keys key;
3031 bool is_safe_mode = pf->adapter->is_safe_mode;
3034 rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf;
3035 nb_q = dev_data->nb_rx_queues;
3036 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3037 vsi->rss_lut_size = pf->hash_lut_size;
3040 PMD_DRV_LOG(WARNING,
3041 "RSS is not supported as rx queues number is zero\n");
3046 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3050 if (!vsi->rss_key) {
3051 vsi->rss_key = rte_zmalloc(NULL,
3052 vsi->rss_key_size, 0);
3053 if (vsi->rss_key == NULL) {
3054 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3058 if (!vsi->rss_lut) {
3059 vsi->rss_lut = rte_zmalloc(NULL,
3060 vsi->rss_lut_size, 0);
3061 if (vsi->rss_lut == NULL) {
3062 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3063 rte_free(vsi->rss_key);
3064 vsi->rss_key = NULL;
3068 /* configure RSS key */
3069 if (!rss_conf->rss_key)
3070 ice_get_default_rss_key(vsi->rss_key, vsi->rss_key_size);
3072 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3073 RTE_MIN(rss_conf->rss_key_len,
3074 vsi->rss_key_size));
3076 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3077 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3081 /* init RSS LUT table */
3082 for (i = 0; i < vsi->rss_lut_size; i++)
3083 vsi->rss_lut[i] = i % nb_q;
3085 lut_params.vsi_handle = vsi->idx;
3086 lut_params.lut_size = vsi->rss_lut_size;
3087 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3088 lut_params.lut = vsi->rss_lut;
3089 lut_params.global_lut_id = 0;
3090 ret = ice_aq_set_rss_lut(hw, &lut_params);
3094 /* Enable registers for symmetric_toeplitz function. */
3095 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3096 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3097 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3098 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3100 /* RSS hash configuration */
3101 ice_rss_hash_set(pf, rss_conf->rss_hf);
3105 rte_free(vsi->rss_key);
3106 vsi->rss_key = NULL;
3107 rte_free(vsi->rss_lut);
3108 vsi->rss_lut = NULL;
3113 ice_dev_configure(struct rte_eth_dev *dev)
3115 struct ice_adapter *ad =
3116 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3117 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3120 /* Initialize to TRUE. If any of Rx queues doesn't meet the
3121 * bulk allocation or vector Rx preconditions we will reset it.
3123 ad->rx_bulk_alloc_allowed = true;
3124 ad->tx_simple_allowed = true;
3126 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3127 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3129 if (dev->data->nb_rx_queues) {
3130 ret = ice_init_rss(pf);
3132 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3141 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3142 int base_queue, int nb_queue)
3144 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3145 uint32_t val, val_tx;
3148 for (i = 0; i < nb_queue; i++) {
3150 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3151 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3152 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3153 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3155 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3156 base_queue + i, msix_vect);
3157 /* set ITR0 value */
3158 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3159 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3160 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3165 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3167 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3168 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3169 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3170 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3171 uint16_t msix_vect = vsi->msix_intr;
3172 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3173 uint16_t queue_idx = 0;
3177 /* clear Rx/Tx queue interrupt */
3178 for (i = 0; i < vsi->nb_used_qps; i++) {
3179 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3180 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3183 /* PF bind interrupt */
3184 if (rte_intr_dp_is_en(intr_handle)) {
3189 for (i = 0; i < vsi->nb_used_qps; i++) {
3191 if (!rte_intr_allow_others(intr_handle))
3192 msix_vect = ICE_MISC_VEC_ID;
3194 /* uio mapping all queue to one msix_vect */
3195 __vsi_queues_bind_intr(vsi, msix_vect,
3196 vsi->base_queue + i,
3197 vsi->nb_used_qps - i);
3199 for (; !!record && i < vsi->nb_used_qps; i++)
3200 intr_handle->intr_vec[queue_idx + i] =
3205 /* vfio 1:1 queue/msix_vect mapping */
3206 __vsi_queues_bind_intr(vsi, msix_vect,
3207 vsi->base_queue + i, 1);
3210 intr_handle->intr_vec[queue_idx + i] = msix_vect;
3218 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3220 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3221 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3222 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3223 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3224 uint16_t msix_intr, i;
3226 if (rte_intr_allow_others(intr_handle))
3227 for (i = 0; i < vsi->nb_used_qps; i++) {
3228 msix_intr = vsi->msix_intr + i;
3229 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3230 GLINT_DYN_CTL_INTENA_M |
3231 GLINT_DYN_CTL_CLEARPBA_M |
3232 GLINT_DYN_CTL_ITR_INDX_M |
3233 GLINT_DYN_CTL_WB_ON_ITR_M);
3236 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3237 GLINT_DYN_CTL_INTENA_M |
3238 GLINT_DYN_CTL_CLEARPBA_M |
3239 GLINT_DYN_CTL_ITR_INDX_M |
3240 GLINT_DYN_CTL_WB_ON_ITR_M);
3244 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3246 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3247 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3248 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3249 struct ice_vsi *vsi = pf->main_vsi;
3250 uint32_t intr_vector = 0;
3252 rte_intr_disable(intr_handle);
3254 /* check and configure queue intr-vector mapping */
3255 if ((rte_intr_cap_multiple(intr_handle) ||
3256 !RTE_ETH_DEV_SRIOV(dev).active) &&
3257 dev->data->dev_conf.intr_conf.rxq != 0) {
3258 intr_vector = dev->data->nb_rx_queues;
3259 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3260 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3261 ICE_MAX_INTR_QUEUE_NUM);
3264 if (rte_intr_efd_enable(intr_handle, intr_vector))
3268 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3269 intr_handle->intr_vec =
3270 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3272 if (!intr_handle->intr_vec) {
3274 "Failed to allocate %d rx_queues intr_vec",
3275 dev->data->nb_rx_queues);
3280 /* Map queues with MSIX interrupt */
3281 vsi->nb_used_qps = dev->data->nb_rx_queues;
3282 ice_vsi_queues_bind_intr(vsi);
3284 /* Enable interrupts for all the queues */
3285 ice_vsi_enable_queues_intr(vsi);
3287 rte_intr_enable(intr_handle);
3293 ice_get_init_link_status(struct rte_eth_dev *dev)
3295 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3297 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3298 struct ice_link_status link_status;
3301 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3302 &link_status, NULL);
3303 if (ret != ICE_SUCCESS) {
3304 PMD_DRV_LOG(ERR, "Failed to get link info");
3305 pf->init_link_up = false;
3309 if (link_status.link_info & ICE_AQ_LINK_UP)
3310 pf->init_link_up = true;
3314 ice_dev_start(struct rte_eth_dev *dev)
3316 struct rte_eth_dev_data *data = dev->data;
3317 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3318 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3319 struct ice_vsi *vsi = pf->main_vsi;
3320 uint16_t nb_rxq = 0;
3322 uint16_t max_frame_size;
3325 /* program Tx queues' context in hardware */
3326 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3327 ret = ice_tx_queue_start(dev, nb_txq);
3329 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3334 /* program Rx queues' context in hardware*/
3335 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3336 ret = ice_rx_queue_start(dev, nb_rxq);
3338 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3343 ice_set_rx_function(dev);
3344 ice_set_tx_function(dev);
3346 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3347 ETH_VLAN_EXTEND_MASK;
3348 ret = ice_vlan_offload_set(dev, mask);
3350 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3354 /* enable Rx interrput and mapping Rx queue to interrupt vector */
3355 if (ice_rxq_intr_setup(dev))
3358 /* Enable receiving broadcast packets and transmitting packets */
3359 ret = ice_set_vsi_promisc(hw, vsi->idx,
3360 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3361 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3363 if (ret != ICE_SUCCESS)
3364 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3366 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3367 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3368 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3369 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3370 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3371 ICE_AQ_LINK_EVENT_AN_COMPLETED |
3372 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3374 if (ret != ICE_SUCCESS)
3375 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3377 ice_get_init_link_status(dev);
3379 ice_dev_set_link_up(dev);
3381 /* Call get_link_info aq commond to enable/disable LSE */
3382 ice_link_update(dev, 0);
3384 pf->adapter_stopped = false;
3386 /* Set the max frame size to default value*/
3387 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3388 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3391 /* Set the max frame size to HW*/
3392 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3396 /* stop the started queues if failed to start all queues */
3398 for (i = 0; i < nb_rxq; i++)
3399 ice_rx_queue_stop(dev, i);
3401 for (i = 0; i < nb_txq; i++)
3402 ice_tx_queue_stop(dev, i);
3408 ice_dev_reset(struct rte_eth_dev *dev)
3412 if (dev->data->sriov.active)
3415 ret = ice_dev_uninit(dev);
3417 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3421 ret = ice_dev_init(dev);
3423 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3431 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3433 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3434 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3435 struct ice_vsi *vsi = pf->main_vsi;
3436 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3437 bool is_safe_mode = pf->adapter->is_safe_mode;
3441 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3442 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3443 dev_info->max_rx_queues = vsi->nb_qps;
3444 dev_info->max_tx_queues = vsi->nb_qps;
3445 dev_info->max_mac_addrs = vsi->max_macaddrs;
3446 dev_info->max_vfs = pci_dev->max_vfs;
3447 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3448 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3450 dev_info->rx_offload_capa =
3451 DEV_RX_OFFLOAD_VLAN_STRIP |
3452 DEV_RX_OFFLOAD_JUMBO_FRAME |
3453 DEV_RX_OFFLOAD_KEEP_CRC |
3454 DEV_RX_OFFLOAD_SCATTER |
3455 DEV_RX_OFFLOAD_VLAN_FILTER;
3456 dev_info->tx_offload_capa =
3457 DEV_TX_OFFLOAD_VLAN_INSERT |
3458 DEV_TX_OFFLOAD_TCP_TSO |
3459 DEV_TX_OFFLOAD_MULTI_SEGS |
3460 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3461 dev_info->flow_type_rss_offloads = 0;
3463 if (!is_safe_mode) {
3464 dev_info->rx_offload_capa |=
3465 DEV_RX_OFFLOAD_IPV4_CKSUM |
3466 DEV_RX_OFFLOAD_UDP_CKSUM |
3467 DEV_RX_OFFLOAD_TCP_CKSUM |
3468 DEV_RX_OFFLOAD_QINQ_STRIP |
3469 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3470 DEV_RX_OFFLOAD_VLAN_EXTEND |
3471 DEV_RX_OFFLOAD_RSS_HASH;
3472 dev_info->tx_offload_capa |=
3473 DEV_TX_OFFLOAD_QINQ_INSERT |
3474 DEV_TX_OFFLOAD_IPV4_CKSUM |
3475 DEV_TX_OFFLOAD_UDP_CKSUM |
3476 DEV_TX_OFFLOAD_TCP_CKSUM |
3477 DEV_TX_OFFLOAD_SCTP_CKSUM |
3478 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3479 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3480 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3483 dev_info->rx_queue_offload_capa = 0;
3484 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3486 dev_info->reta_size = pf->hash_lut_size;
3487 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3489 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3491 .pthresh = ICE_DEFAULT_RX_PTHRESH,
3492 .hthresh = ICE_DEFAULT_RX_HTHRESH,
3493 .wthresh = ICE_DEFAULT_RX_WTHRESH,
3495 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3500 dev_info->default_txconf = (struct rte_eth_txconf) {
3502 .pthresh = ICE_DEFAULT_TX_PTHRESH,
3503 .hthresh = ICE_DEFAULT_TX_HTHRESH,
3504 .wthresh = ICE_DEFAULT_TX_WTHRESH,
3506 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3507 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3511 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3512 .nb_max = ICE_MAX_RING_DESC,
3513 .nb_min = ICE_MIN_RING_DESC,
3514 .nb_align = ICE_ALIGN_RING_DESC,
3517 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3518 .nb_max = ICE_MAX_RING_DESC,
3519 .nb_min = ICE_MIN_RING_DESC,
3520 .nb_align = ICE_ALIGN_RING_DESC,
3523 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3524 ETH_LINK_SPEED_100M |
3526 ETH_LINK_SPEED_2_5G |
3528 ETH_LINK_SPEED_10G |
3529 ETH_LINK_SPEED_20G |
3532 phy_type_low = hw->port_info->phy.phy_type_low;
3533 phy_type_high = hw->port_info->phy.phy_type_high;
3535 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3536 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3538 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3539 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3540 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3542 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3543 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3545 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3546 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3547 dev_info->default_rxportconf.nb_queues = 1;
3548 dev_info->default_txportconf.nb_queues = 1;
3549 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3550 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3556 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3557 struct rte_eth_link *link)
3559 struct rte_eth_link *dst = link;
3560 struct rte_eth_link *src = &dev->data->dev_link;
3562 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3563 *(uint64_t *)src) == 0)
3570 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3571 struct rte_eth_link *link)
3573 struct rte_eth_link *dst = &dev->data->dev_link;
3574 struct rte_eth_link *src = link;
3576 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3577 *(uint64_t *)src) == 0)
3584 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3586 #define CHECK_INTERVAL 100 /* 100ms */
3587 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3588 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3589 struct ice_link_status link_status;
3590 struct rte_eth_link link, old;
3592 unsigned int rep_cnt = MAX_REPEAT_TIME;
3593 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3595 memset(&link, 0, sizeof(link));
3596 memset(&old, 0, sizeof(old));
3597 memset(&link_status, 0, sizeof(link_status));
3598 ice_atomic_read_link_status(dev, &old);
3601 /* Get link status information from hardware */
3602 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3603 &link_status, NULL);
3604 if (status != ICE_SUCCESS) {
3605 link.link_speed = ETH_SPEED_NUM_100M;
3606 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3607 PMD_DRV_LOG(ERR, "Failed to get link info");
3611 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3612 if (!wait_to_complete || link.link_status)
3615 rte_delay_ms(CHECK_INTERVAL);
3616 } while (--rep_cnt);
3618 if (!link.link_status)
3621 /* Full-duplex operation at all supported speeds */
3622 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3624 /* Parse the link status */
3625 switch (link_status.link_speed) {
3626 case ICE_AQ_LINK_SPEED_10MB:
3627 link.link_speed = ETH_SPEED_NUM_10M;
3629 case ICE_AQ_LINK_SPEED_100MB:
3630 link.link_speed = ETH_SPEED_NUM_100M;
3632 case ICE_AQ_LINK_SPEED_1000MB:
3633 link.link_speed = ETH_SPEED_NUM_1G;
3635 case ICE_AQ_LINK_SPEED_2500MB:
3636 link.link_speed = ETH_SPEED_NUM_2_5G;
3638 case ICE_AQ_LINK_SPEED_5GB:
3639 link.link_speed = ETH_SPEED_NUM_5G;
3641 case ICE_AQ_LINK_SPEED_10GB:
3642 link.link_speed = ETH_SPEED_NUM_10G;
3644 case ICE_AQ_LINK_SPEED_20GB:
3645 link.link_speed = ETH_SPEED_NUM_20G;
3647 case ICE_AQ_LINK_SPEED_25GB:
3648 link.link_speed = ETH_SPEED_NUM_25G;
3650 case ICE_AQ_LINK_SPEED_40GB:
3651 link.link_speed = ETH_SPEED_NUM_40G;
3653 case ICE_AQ_LINK_SPEED_50GB:
3654 link.link_speed = ETH_SPEED_NUM_50G;
3656 case ICE_AQ_LINK_SPEED_100GB:
3657 link.link_speed = ETH_SPEED_NUM_100G;
3659 case ICE_AQ_LINK_SPEED_UNKNOWN:
3660 PMD_DRV_LOG(ERR, "Unknown link speed");
3661 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3664 PMD_DRV_LOG(ERR, "None link speed");
3665 link.link_speed = ETH_SPEED_NUM_NONE;
3669 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3670 ETH_LINK_SPEED_FIXED);
3673 ice_atomic_write_link_status(dev, &link);
3674 if (link.link_status == old.link_status)
3680 /* Force the physical link state by getting the current PHY capabilities from
3681 * hardware and setting the PHY config based on the determined capabilities. If
3682 * link changes, link event will be triggered because both the Enable Automatic
3683 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3685 static enum ice_status
3686 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3688 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3689 struct ice_aqc_get_phy_caps_data *pcaps;
3690 struct ice_port_info *pi;
3691 enum ice_status status;
3693 if (!hw || !hw->port_info)
3694 return ICE_ERR_PARAM;
3698 pcaps = (struct ice_aqc_get_phy_caps_data *)
3699 ice_malloc(hw, sizeof(*pcaps));
3701 return ICE_ERR_NO_MEMORY;
3703 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3708 /* No change in link */
3709 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3710 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3713 cfg.phy_type_low = pcaps->phy_type_low;
3714 cfg.phy_type_high = pcaps->phy_type_high;
3715 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3716 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3717 cfg.eee_cap = pcaps->eee_cap;
3718 cfg.eeer_value = pcaps->eeer_value;
3719 cfg.link_fec_opt = pcaps->link_fec_options;
3721 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3723 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3725 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3728 ice_free(hw, pcaps);
3733 ice_dev_set_link_up(struct rte_eth_dev *dev)
3735 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737 return ice_force_phys_link_state(hw, true);
3741 ice_dev_set_link_down(struct rte_eth_dev *dev)
3743 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3745 return ice_force_phys_link_state(hw, false);
3749 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3751 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3752 struct rte_eth_dev_data *dev_data = pf->dev_data;
3753 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3755 /* check if mtu is within the allowed range */
3756 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3759 /* mtu setting is forbidden if port is start */
3760 if (dev_data->dev_started) {
3762 "port %d must be stopped before configuration",
3767 if (frame_size > ICE_ETH_MAX_LEN)
3768 dev_data->dev_conf.rxmode.offloads |=
3769 DEV_RX_OFFLOAD_JUMBO_FRAME;
3771 dev_data->dev_conf.rxmode.offloads &=
3772 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3774 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3779 static int ice_macaddr_set(struct rte_eth_dev *dev,
3780 struct rte_ether_addr *mac_addr)
3782 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3783 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3784 struct ice_vsi *vsi = pf->main_vsi;
3785 struct ice_mac_filter *f;
3789 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3790 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3794 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3795 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3800 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3804 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3805 if (ret != ICE_SUCCESS) {
3806 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3809 ret = ice_add_mac_filter(vsi, mac_addr);
3810 if (ret != ICE_SUCCESS) {
3811 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3814 rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3816 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3817 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3818 if (ret != ICE_SUCCESS)
3819 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3824 /* Add a MAC address, and update filters */
3826 ice_macaddr_add(struct rte_eth_dev *dev,
3827 struct rte_ether_addr *mac_addr,
3828 __rte_unused uint32_t index,
3829 __rte_unused uint32_t pool)
3831 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3832 struct ice_vsi *vsi = pf->main_vsi;
3835 ret = ice_add_mac_filter(vsi, mac_addr);
3836 if (ret != ICE_SUCCESS) {
3837 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3844 /* Remove a MAC address, and update filters */
3846 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3848 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3849 struct ice_vsi *vsi = pf->main_vsi;
3850 struct rte_eth_dev_data *data = dev->data;
3851 struct rte_ether_addr *macaddr;
3854 macaddr = &data->mac_addrs[index];
3855 ret = ice_remove_mac_filter(vsi, macaddr);
3857 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3863 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3865 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3866 struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
3867 struct ice_vsi *vsi = pf->main_vsi;
3870 PMD_INIT_FUNC_TRACE();
3873 * Vlan 0 is the generic filter for untagged packets
3874 * and can't be removed or added by user.
3880 ret = ice_add_vlan_filter(vsi, &vlan);
3882 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3886 ret = ice_remove_vlan_filter(vsi, &vlan);
3888 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3896 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
3897 * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
3898 * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
3899 * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
3901 * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
3902 * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
3903 * traffic in SVM, since the VLAN TPID isn't part of filtering.
3905 * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
3906 * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
3907 * part of filtering.
3910 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
3912 struct ice_vlan vlan;
3915 vlan = ICE_VLAN(0, 0);
3916 err = ice_add_vlan_filter(vsi, &vlan);
3918 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
3922 /* in SVM both VLAN 0 filters are identical */
3923 if (!ice_is_dvm_ena(&vsi->adapter->hw))
3926 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3927 err = ice_add_vlan_filter(vsi, &vlan);
3929 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
3937 * Delete the VLAN 0 filters in the same manner that they were added in
3938 * ice_vsi_add_vlan_zero.
3941 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
3943 struct ice_vlan vlan;
3946 vlan = ICE_VLAN(0, 0);
3947 err = ice_remove_vlan_filter(vsi, &vlan);
3949 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
3953 /* in SVM both VLAN 0 filters are identical */
3954 if (!ice_is_dvm_ena(&vsi->adapter->hw))
3957 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3958 err = ice_remove_vlan_filter(vsi, &vlan);
3960 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
3967 /* Configure vlan filter on or off */
3969 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3971 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3972 struct ice_vsi_ctx ctxt;
3976 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3979 vsi->info.sw_flags2 |= sw_flags2;
3981 vsi->info.sw_flags2 &= ~sw_flags2;
3983 vsi->info.sw_id = hw->port_info->sw_id;
3984 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3985 ctxt.info.valid_sections =
3986 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3987 ICE_AQ_VSI_PROP_SECURITY_VALID);
3988 ctxt.vsi_num = vsi->vsi_id;
3990 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3992 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3993 on ? "enable" : "disable");
3996 vsi->info.valid_sections |=
3997 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3998 ICE_AQ_VSI_PROP_SECURITY_VALID);
4001 /* consist with other drivers, allow untagged packet when vlan filter on */
4003 ret = ice_vsi_add_vlan_zero(vsi);
4005 ret = ice_vsi_del_vlan_zero(vsi);
4010 /* Manage VLAN stripping for the VSI for Rx */
4012 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4014 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4015 struct ice_vsi_ctx ctxt;
4016 enum ice_status status;
4019 /* do not allow modifying VLAN stripping when a port VLAN is configured
4022 if (vsi->info.port_based_inner_vlan)
4025 memset(&ctxt, 0, sizeof(ctxt));
4028 /* Strip VLAN tag from Rx packet and put it in the desc */
4029 ctxt.info.inner_vlan_flags =
4030 ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4032 /* Disable stripping. Leave tag in packet */
4033 ctxt.info.inner_vlan_flags =
4034 ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4036 /* Allow all packets untagged/tagged */
4037 ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4039 ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4041 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4043 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4044 ena ? "enable" : "disable");
4047 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4054 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4056 return ice_vsi_manage_vlan_stripping(vsi, true);
4060 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4062 return ice_vsi_manage_vlan_stripping(vsi, false);
4065 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4067 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4068 struct ice_vsi_ctx ctxt;
4069 enum ice_status status;
4072 /* do not allow modifying VLAN stripping when a port VLAN is configured
4075 if (vsi->info.port_based_outer_vlan)
4078 memset(&ctxt, 0, sizeof(ctxt));
4080 ctxt.info.valid_sections =
4081 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4082 /* clear current outer VLAN strip settings */
4083 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4084 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4085 ctxt.info.outer_vlan_flags |=
4086 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4087 ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4088 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4089 ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4091 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4093 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4096 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4103 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4105 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4106 struct ice_vsi_ctx ctxt;
4107 enum ice_status status;
4110 if (vsi->info.port_based_outer_vlan)
4113 memset(&ctxt, 0, sizeof(ctxt));
4115 ctxt.info.valid_sections =
4116 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4117 /* clear current outer VLAN strip settings */
4118 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4119 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4120 ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4121 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4123 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4125 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4128 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4135 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4137 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4140 if (ice_is_dvm_ena(hw)) {
4142 ret = ice_vsi_ena_outer_stripping(vsi);
4144 ret = ice_vsi_dis_outer_stripping(vsi);
4147 ret = ice_vsi_ena_inner_stripping(vsi);
4149 ret = ice_vsi_dis_inner_stripping(vsi);
4156 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4158 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4159 struct ice_vsi *vsi = pf->main_vsi;
4160 struct rte_eth_rxmode *rxmode;
4162 rxmode = &dev->data->dev_conf.rxmode;
4163 if (mask & ETH_VLAN_FILTER_MASK) {
4164 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4165 ice_vsi_config_vlan_filter(vsi, true);
4167 ice_vsi_config_vlan_filter(vsi, false);
4170 if (mask & ETH_VLAN_STRIP_MASK) {
4171 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4172 ice_vsi_config_vlan_stripping(vsi, true);
4174 ice_vsi_config_vlan_stripping(vsi, false);
4181 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4183 struct ice_aq_get_set_rss_lut_params lut_params;
4184 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4185 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4191 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4192 lut_params.vsi_handle = vsi->idx;
4193 lut_params.lut_size = lut_size;
4194 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4195 lut_params.lut = lut;
4196 lut_params.global_lut_id = 0;
4197 ret = ice_aq_get_rss_lut(hw, &lut_params);
4199 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4203 uint64_t *lut_dw = (uint64_t *)lut;
4204 uint16_t i, lut_size_dw = lut_size / 4;
4206 for (i = 0; i < lut_size_dw; i++)
4207 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4214 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4216 struct ice_aq_get_set_rss_lut_params lut_params;
4224 pf = ICE_VSI_TO_PF(vsi);
4225 hw = ICE_VSI_TO_HW(vsi);
4227 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4228 lut_params.vsi_handle = vsi->idx;
4229 lut_params.lut_size = lut_size;
4230 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4231 lut_params.lut = lut;
4232 lut_params.global_lut_id = 0;
4233 ret = ice_aq_set_rss_lut(hw, &lut_params);
4235 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4239 uint64_t *lut_dw = (uint64_t *)lut;
4240 uint16_t i, lut_size_dw = lut_size / 4;
4242 for (i = 0; i < lut_size_dw; i++)
4243 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4252 ice_rss_reta_update(struct rte_eth_dev *dev,
4253 struct rte_eth_rss_reta_entry64 *reta_conf,
4256 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4257 uint16_t i, lut_size = pf->hash_lut_size;
4258 uint16_t idx, shift;
4262 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4263 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4264 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4266 "The size of hash lookup table configured (%d)"
4267 "doesn't match the number hardware can "
4268 "supported (128, 512, 2048)",
4273 /* It MUST use the current LUT size to get the RSS lookup table,
4274 * otherwise if will fail with -100 error code.
4276 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
4278 PMD_DRV_LOG(ERR, "No memory can be allocated");
4281 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4285 for (i = 0; i < reta_size; i++) {
4286 idx = i / RTE_RETA_GROUP_SIZE;
4287 shift = i % RTE_RETA_GROUP_SIZE;
4288 if (reta_conf[idx].mask & (1ULL << shift))
4289 lut[i] = reta_conf[idx].reta[shift];
4291 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4292 if (ret == 0 && lut_size != reta_size) {
4294 "The size of hash lookup table is changed from (%d) to (%d)",
4295 lut_size, reta_size);
4296 pf->hash_lut_size = reta_size;
4306 ice_rss_reta_query(struct rte_eth_dev *dev,
4307 struct rte_eth_rss_reta_entry64 *reta_conf,
4310 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4311 uint16_t i, lut_size = pf->hash_lut_size;
4312 uint16_t idx, shift;
4316 if (reta_size != lut_size) {
4318 "The size of hash lookup table configured (%d)"
4319 "doesn't match the number hardware can "
4321 reta_size, lut_size);
4325 lut = rte_zmalloc(NULL, reta_size, 0);
4327 PMD_DRV_LOG(ERR, "No memory can be allocated");
4331 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4335 for (i = 0; i < reta_size; i++) {
4336 idx = i / RTE_RETA_GROUP_SIZE;
4337 shift = i % RTE_RETA_GROUP_SIZE;
4338 if (reta_conf[idx].mask & (1ULL << shift))
4339 reta_conf[idx].reta[shift] = lut[i];
4349 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4351 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4354 if (!key || key_len == 0) {
4355 PMD_DRV_LOG(DEBUG, "No key to be configured");
4357 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4359 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4363 struct ice_aqc_get_set_rss_keys *key_dw =
4364 (struct ice_aqc_get_set_rss_keys *)key;
4366 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4368 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4376 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4378 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4381 if (!key || !key_len)
4384 ret = ice_aq_get_rss_key
4386 (struct ice_aqc_get_set_rss_keys *)key);
4388 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4391 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4397 ice_rss_hash_update(struct rte_eth_dev *dev,
4398 struct rte_eth_rss_conf *rss_conf)
4400 enum ice_status status = ICE_SUCCESS;
4401 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4402 struct ice_vsi *vsi = pf->main_vsi;
4405 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4409 if (rss_conf->rss_hf == 0) {
4414 /* RSS hash configuration */
4415 ice_rss_hash_set(pf, rss_conf->rss_hf);
4421 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4422 struct rte_eth_rss_conf *rss_conf)
4424 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4425 struct ice_vsi *vsi = pf->main_vsi;
4427 ice_get_rss_key(vsi, rss_conf->rss_key,
4428 &rss_conf->rss_key_len);
4430 rss_conf->rss_hf = pf->rss_hf;
4435 ice_promisc_enable(struct rte_eth_dev *dev)
4437 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4438 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4439 struct ice_vsi *vsi = pf->main_vsi;
4440 enum ice_status status;
4444 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4445 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4447 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4449 case ICE_ERR_ALREADY_EXISTS:
4450 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4454 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4462 ice_promisc_disable(struct rte_eth_dev *dev)
4464 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4465 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4466 struct ice_vsi *vsi = pf->main_vsi;
4467 enum ice_status status;
4471 if (dev->data->all_multicast == 1)
4472 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX;
4474 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4475 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4477 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4478 if (status != ICE_SUCCESS) {
4479 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4487 ice_allmulti_enable(struct rte_eth_dev *dev)
4489 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4490 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4491 struct ice_vsi *vsi = pf->main_vsi;
4492 enum ice_status status;
4496 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4498 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4501 case ICE_ERR_ALREADY_EXISTS:
4502 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4506 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4514 ice_allmulti_disable(struct rte_eth_dev *dev)
4516 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4517 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4518 struct ice_vsi *vsi = pf->main_vsi;
4519 enum ice_status status;
4523 if (dev->data->promiscuous == 1)
4524 return 0; /* must remain in all_multicast mode */
4526 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4528 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4529 if (status != ICE_SUCCESS) {
4530 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4537 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4540 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4541 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4542 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4546 msix_intr = intr_handle->intr_vec[queue_id];
4548 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4549 GLINT_DYN_CTL_ITR_INDX_M;
4550 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4552 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4553 rte_intr_ack(&pci_dev->intr_handle);
4558 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4561 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4562 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4563 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4566 msix_intr = intr_handle->intr_vec[queue_id];
4568 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4574 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4576 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4581 ver = hw->flash.orom.major;
4582 patch = hw->flash.orom.patch;
4583 build = hw->flash.orom.build;
4585 ret = snprintf(fw_version, fw_size,
4586 "%x.%02x 0x%08x %d.%d.%d",
4587 hw->flash.nvm.major,
4588 hw->flash.nvm.minor,
4589 hw->flash.nvm.eetrack,
4594 /* add the size of '\0' */
4596 if (fw_size < (size_t)ret)
4603 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4606 struct ice_vsi_ctx ctxt;
4607 uint8_t vlan_flags = 0;
4610 if (!vsi || !info) {
4611 PMD_DRV_LOG(ERR, "invalid parameters");
4616 vsi->info.port_based_inner_vlan = info->config.pvid;
4618 * If insert pvid is enabled, only tagged pkts are
4619 * allowed to be sent out.
4621 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4622 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4624 vsi->info.port_based_inner_vlan = 0;
4625 if (info->config.reject.tagged == 0)
4626 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4628 if (info->config.reject.untagged == 0)
4629 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4631 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4632 ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4633 vsi->info.inner_vlan_flags |= vlan_flags;
4634 memset(&ctxt, 0, sizeof(ctxt));
4635 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4636 ctxt.info.valid_sections =
4637 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4638 ctxt.vsi_num = vsi->vsi_id;
4640 hw = ICE_VSI_TO_HW(vsi);
4641 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4642 if (ret != ICE_SUCCESS) {
4644 "update VSI for VLAN insert failed, err %d",
4649 vsi->info.valid_sections |=
4650 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4656 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4658 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4659 struct ice_vsi *vsi = pf->main_vsi;
4660 struct rte_eth_dev_data *data = pf->dev_data;
4661 struct ice_vsi_vlan_pvid_info info;
4664 memset(&info, 0, sizeof(info));
4667 info.config.pvid = pvid;
4669 info.config.reject.tagged =
4670 data->dev_conf.txmode.hw_vlan_reject_tagged;
4671 info.config.reject.untagged =
4672 data->dev_conf.txmode.hw_vlan_reject_untagged;
4675 ret = ice_vsi_vlan_pvid_set(vsi, &info);
4677 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4685 ice_get_eeprom_length(struct rte_eth_dev *dev)
4687 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4689 return hw->flash.flash_size;
4693 ice_get_eeprom(struct rte_eth_dev *dev,
4694 struct rte_dev_eeprom_info *eeprom)
4696 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4697 enum ice_status status = ICE_SUCCESS;
4698 uint8_t *data = eeprom->data;
4700 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4702 status = ice_acquire_nvm(hw, ICE_RES_READ);
4704 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4708 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4711 ice_release_nvm(hw);
4714 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4722 ice_stat_update_32(struct ice_hw *hw,
4730 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4734 if (new_data >= *offset)
4735 *stat = (uint64_t)(new_data - *offset);
4737 *stat = (uint64_t)((new_data +
4738 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4743 ice_stat_update_40(struct ice_hw *hw,
4752 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4753 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4759 if (new_data >= *offset)
4760 *stat = new_data - *offset;
4762 *stat = (uint64_t)((new_data +
4763 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4766 *stat &= ICE_40_BIT_MASK;
4769 /* Get all the statistics of a VSI */
4771 ice_update_vsi_stats(struct ice_vsi *vsi)
4773 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4774 struct ice_eth_stats *nes = &vsi->eth_stats;
4775 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4776 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4778 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4779 vsi->offset_loaded, &oes->rx_bytes,
4781 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4782 vsi->offset_loaded, &oes->rx_unicast,
4784 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4785 vsi->offset_loaded, &oes->rx_multicast,
4786 &nes->rx_multicast);
4787 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4788 vsi->offset_loaded, &oes->rx_broadcast,
4789 &nes->rx_broadcast);
4790 /* enlarge the limitation when rx_bytes overflowed */
4791 if (vsi->offset_loaded) {
4792 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4793 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4794 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4796 vsi->old_rx_bytes = nes->rx_bytes;
4797 /* exclude CRC bytes */
4798 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4799 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4801 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4802 &oes->rx_discards, &nes->rx_discards);
4803 /* GLV_REPC not supported */
4804 /* GLV_RMPC not supported */
4805 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4806 &oes->rx_unknown_protocol,
4807 &nes->rx_unknown_protocol);
4808 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4809 vsi->offset_loaded, &oes->tx_bytes,
4811 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4812 vsi->offset_loaded, &oes->tx_unicast,
4814 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4815 vsi->offset_loaded, &oes->tx_multicast,
4816 &nes->tx_multicast);
4817 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4818 vsi->offset_loaded, &oes->tx_broadcast,
4819 &nes->tx_broadcast);
4820 /* GLV_TDPC not supported */
4821 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4822 &oes->tx_errors, &nes->tx_errors);
4823 /* enlarge the limitation when tx_bytes overflowed */
4824 if (vsi->offset_loaded) {
4825 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4826 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4827 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4829 vsi->old_tx_bytes = nes->tx_bytes;
4830 vsi->offset_loaded = true;
4832 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4834 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4835 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4836 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4837 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4838 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4839 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4840 nes->rx_unknown_protocol);
4841 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4842 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4843 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4844 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4845 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4846 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4847 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4852 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4854 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4855 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4857 /* Get statistics of struct ice_eth_stats */
4858 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4859 GLPRT_GORCL(hw->port_info->lport),
4860 pf->offset_loaded, &os->eth.rx_bytes,
4862 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4863 GLPRT_UPRCL(hw->port_info->lport),
4864 pf->offset_loaded, &os->eth.rx_unicast,
4865 &ns->eth.rx_unicast);
4866 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4867 GLPRT_MPRCL(hw->port_info->lport),
4868 pf->offset_loaded, &os->eth.rx_multicast,
4869 &ns->eth.rx_multicast);
4870 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4871 GLPRT_BPRCL(hw->port_info->lport),
4872 pf->offset_loaded, &os->eth.rx_broadcast,
4873 &ns->eth.rx_broadcast);
4874 ice_stat_update_32(hw, PRTRPB_RDPC,
4875 pf->offset_loaded, &os->eth.rx_discards,
4876 &ns->eth.rx_discards);
4877 /* enlarge the limitation when rx_bytes overflowed */
4878 if (pf->offset_loaded) {
4879 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4880 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4881 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4883 pf->old_rx_bytes = ns->eth.rx_bytes;
4885 /* Workaround: CRC size should not be included in byte statistics,
4886 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4889 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4890 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4892 /* GLPRT_REPC not supported */
4893 /* GLPRT_RMPC not supported */
4894 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4896 &os->eth.rx_unknown_protocol,
4897 &ns->eth.rx_unknown_protocol);
4898 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4899 GLPRT_GOTCL(hw->port_info->lport),
4900 pf->offset_loaded, &os->eth.tx_bytes,
4902 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4903 GLPRT_UPTCL(hw->port_info->lport),
4904 pf->offset_loaded, &os->eth.tx_unicast,
4905 &ns->eth.tx_unicast);
4906 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4907 GLPRT_MPTCL(hw->port_info->lport),
4908 pf->offset_loaded, &os->eth.tx_multicast,
4909 &ns->eth.tx_multicast);
4910 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4911 GLPRT_BPTCL(hw->port_info->lport),
4912 pf->offset_loaded, &os->eth.tx_broadcast,
4913 &ns->eth.tx_broadcast);
4914 /* enlarge the limitation when tx_bytes overflowed */
4915 if (pf->offset_loaded) {
4916 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4917 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4918 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4920 pf->old_tx_bytes = ns->eth.tx_bytes;
4921 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4922 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4924 /* GLPRT_TEPC not supported */
4926 /* additional port specific stats */
4927 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4928 pf->offset_loaded, &os->tx_dropped_link_down,
4929 &ns->tx_dropped_link_down);
4930 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4931 pf->offset_loaded, &os->crc_errors,
4933 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4934 pf->offset_loaded, &os->illegal_bytes,
4935 &ns->illegal_bytes);
4936 /* GLPRT_ERRBC not supported */
4937 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4938 pf->offset_loaded, &os->mac_local_faults,
4939 &ns->mac_local_faults);
4940 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4941 pf->offset_loaded, &os->mac_remote_faults,
4942 &ns->mac_remote_faults);
4944 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4945 pf->offset_loaded, &os->rx_len_errors,
4946 &ns->rx_len_errors);
4948 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4949 pf->offset_loaded, &os->link_xon_rx,
4951 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4952 pf->offset_loaded, &os->link_xoff_rx,
4954 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4955 pf->offset_loaded, &os->link_xon_tx,
4957 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4958 pf->offset_loaded, &os->link_xoff_tx,
4960 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4961 GLPRT_PRC64L(hw->port_info->lport),
4962 pf->offset_loaded, &os->rx_size_64,
4964 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4965 GLPRT_PRC127L(hw->port_info->lport),
4966 pf->offset_loaded, &os->rx_size_127,
4968 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4969 GLPRT_PRC255L(hw->port_info->lport),
4970 pf->offset_loaded, &os->rx_size_255,
4972 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4973 GLPRT_PRC511L(hw->port_info->lport),
4974 pf->offset_loaded, &os->rx_size_511,
4976 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4977 GLPRT_PRC1023L(hw->port_info->lport),
4978 pf->offset_loaded, &os->rx_size_1023,
4980 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4981 GLPRT_PRC1522L(hw->port_info->lport),
4982 pf->offset_loaded, &os->rx_size_1522,
4984 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4985 GLPRT_PRC9522L(hw->port_info->lport),
4986 pf->offset_loaded, &os->rx_size_big,
4988 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4989 pf->offset_loaded, &os->rx_undersize,
4991 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4992 pf->offset_loaded, &os->rx_fragments,
4994 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4995 pf->offset_loaded, &os->rx_oversize,
4997 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4998 pf->offset_loaded, &os->rx_jabber,
5000 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5001 GLPRT_PTC64L(hw->port_info->lport),
5002 pf->offset_loaded, &os->tx_size_64,
5004 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5005 GLPRT_PTC127L(hw->port_info->lport),
5006 pf->offset_loaded, &os->tx_size_127,
5008 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5009 GLPRT_PTC255L(hw->port_info->lport),
5010 pf->offset_loaded, &os->tx_size_255,
5012 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5013 GLPRT_PTC511L(hw->port_info->lport),
5014 pf->offset_loaded, &os->tx_size_511,
5016 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5017 GLPRT_PTC1023L(hw->port_info->lport),
5018 pf->offset_loaded, &os->tx_size_1023,
5020 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5021 GLPRT_PTC1522L(hw->port_info->lport),
5022 pf->offset_loaded, &os->tx_size_1522,
5024 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5025 GLPRT_PTC9522L(hw->port_info->lport),
5026 pf->offset_loaded, &os->tx_size_big,
5029 /* GLPRT_MSPDC not supported */
5030 /* GLPRT_XEC not supported */
5032 pf->offset_loaded = true;
5035 ice_update_vsi_stats(pf->main_vsi);
5038 /* Get all statistics of a port */
5040 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5042 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5043 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5044 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5046 /* call read registers - updates values, now write them to struct */
5047 ice_read_stats_registers(pf, hw);
5049 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5050 pf->main_vsi->eth_stats.rx_multicast +
5051 pf->main_vsi->eth_stats.rx_broadcast -
5052 pf->main_vsi->eth_stats.rx_discards;
5053 stats->opackets = ns->eth.tx_unicast +
5054 ns->eth.tx_multicast +
5055 ns->eth.tx_broadcast;
5056 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
5057 stats->obytes = ns->eth.tx_bytes;
5058 stats->oerrors = ns->eth.tx_errors +
5059 pf->main_vsi->eth_stats.tx_errors;
5062 stats->imissed = ns->eth.rx_discards +
5063 pf->main_vsi->eth_stats.rx_discards;
5064 stats->ierrors = ns->crc_errors +
5066 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5068 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5069 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
5070 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5071 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5072 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5073 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5074 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5075 pf->main_vsi->eth_stats.rx_discards);
5076 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5077 ns->eth.rx_unknown_protocol);
5078 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
5079 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5080 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5081 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5082 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5083 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5084 pf->main_vsi->eth_stats.tx_discards);
5085 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
5087 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
5088 ns->tx_dropped_link_down);
5089 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5090 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
5092 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
5093 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
5094 ns->mac_local_faults);
5095 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
5096 ns->mac_remote_faults);
5097 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
5098 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
5099 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
5100 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
5101 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
5102 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
5103 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
5104 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
5105 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
5106 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
5107 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
5108 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
5109 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
5110 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
5111 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
5112 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
5113 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
5114 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
5115 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
5116 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
5117 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
5118 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
5119 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
5120 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5124 /* Reset the statistics */
5126 ice_stats_reset(struct rte_eth_dev *dev)
5128 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5129 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131 /* Mark PF and VSI stats to update the offset, aka "reset" */
5132 pf->offset_loaded = false;
5134 pf->main_vsi->offset_loaded = false;
5136 /* read the stats, reading current register values into offset */
5137 ice_read_stats_registers(pf, hw);
5143 ice_xstats_calc_num(void)
5147 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5153 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5156 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5157 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5160 struct ice_hw_port_stats *hw_stats = &pf->stats;
5162 count = ice_xstats_calc_num();
5166 ice_read_stats_registers(pf, hw);
5173 /* Get stats from ice_eth_stats struct */
5174 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5175 xstats[count].value =
5176 *(uint64_t *)((char *)&hw_stats->eth +
5177 ice_stats_strings[i].offset);
5178 xstats[count].id = count;
5182 /* Get individiual stats from ice_hw_port struct */
5183 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5184 xstats[count].value =
5185 *(uint64_t *)((char *)hw_stats +
5186 ice_hw_port_strings[i].offset);
5187 xstats[count].id = count;
5194 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5195 struct rte_eth_xstat_name *xstats_names,
5196 __rte_unused unsigned int limit)
5198 unsigned int count = 0;
5202 return ice_xstats_calc_num();
5204 /* Note: limit checked in rte_eth_xstats_names() */
5206 /* Get stats from ice_eth_stats struct */
5207 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5208 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5209 sizeof(xstats_names[count].name));
5213 /* Get individiual stats from ice_hw_port struct */
5214 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5215 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5216 sizeof(xstats_names[count].name));
5224 ice_dev_flow_ops_get(struct rte_eth_dev *dev,
5225 const struct rte_flow_ops **ops)
5230 *ops = &ice_flow_ops;
5234 /* Add UDP tunneling port */
5236 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5237 struct rte_eth_udp_tunnel *udp_tunnel)
5240 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5242 if (udp_tunnel == NULL)
5245 switch (udp_tunnel->prot_type) {
5246 case RTE_TUNNEL_TYPE_VXLAN:
5247 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5250 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5258 /* Delete UDP tunneling port */
5260 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5261 struct rte_eth_udp_tunnel *udp_tunnel)
5264 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5266 if (udp_tunnel == NULL)
5269 switch (udp_tunnel->prot_type) {
5270 case RTE_TUNNEL_TYPE_VXLAN:
5271 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5274 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5283 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5284 struct rte_pci_device *pci_dev)
5286 return rte_eth_dev_pci_generic_probe(pci_dev,
5287 sizeof(struct ice_adapter),
5292 ice_pci_remove(struct rte_pci_device *pci_dev)
5294 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5297 static struct rte_pci_driver rte_ice_pmd = {
5298 .id_table = pci_id_ice_map,
5299 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5300 .probe = ice_pci_probe,
5301 .remove = ice_pci_remove,
5305 * Driver initialization routine.
5306 * Invoked once at EAL init time.
5307 * Register itself as the [Poll Mode] Driver of PCI devices.
5309 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5310 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5311 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5312 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5313 ICE_HW_DEBUG_MASK_ARG "=0xXXX"
5314 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5315 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5316 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5318 RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE);
5319 RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE);
5320 #ifdef RTE_ETHDEV_DEBUG_RX
5321 RTE_LOG_REGISTER_SUFFIX(ice_logtype_rx, rx, DEBUG);
5323 #ifdef RTE_ETHDEV_DEBUG_TX
5324 RTE_LOG_REGISTER_SUFFIX(ice_logtype_tx, tx, DEBUG);