1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
18 #include "rte_pmd_ice.h"
19 #include "ice_ethdev.h"
21 #include "ice_generic_flow.h"
24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
26 #define ICE_PROTO_XTR_ARG "proto_xtr"
28 static const char * const ice_valid_args[] = {
29 ICE_SAFE_MODE_SUPPORT_ARG,
30 ICE_PIPELINE_MODE_SUPPORT_ARG,
35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
36 .name = "intel_pmd_dynfield_proto_xtr_metadata",
37 .size = sizeof(uint32_t),
38 .align = __alignof__(uint32_t),
42 struct proto_xtr_ol_flag {
43 const struct rte_mbuf_dynflag param;
48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
52 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
55 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
58 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
60 [PROTO_XTR_IPV6_FLOW] = {
61 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
64 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
66 [PROTO_XTR_IP_OFFSET] = {
67 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
68 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
71 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
73 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
74 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
75 #define ICE_MAX_RES_DESC_NUM 1024
77 static int ice_dev_configure(struct rte_eth_dev *dev);
78 static int ice_dev_start(struct rte_eth_dev *dev);
79 static int ice_dev_stop(struct rte_eth_dev *dev);
80 static int ice_dev_close(struct rte_eth_dev *dev);
81 static int ice_dev_reset(struct rte_eth_dev *dev);
82 static int ice_dev_info_get(struct rte_eth_dev *dev,
83 struct rte_eth_dev_info *dev_info);
84 static int ice_link_update(struct rte_eth_dev *dev,
85 int wait_to_complete);
86 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
87 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
89 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
90 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
91 static int ice_rss_reta_update(struct rte_eth_dev *dev,
92 struct rte_eth_rss_reta_entry64 *reta_conf,
94 static int ice_rss_reta_query(struct rte_eth_dev *dev,
95 struct rte_eth_rss_reta_entry64 *reta_conf,
97 static int ice_rss_hash_update(struct rte_eth_dev *dev,
98 struct rte_eth_rss_conf *rss_conf);
99 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
100 struct rte_eth_rss_conf *rss_conf);
101 static int ice_promisc_enable(struct rte_eth_dev *dev);
102 static int ice_promisc_disable(struct rte_eth_dev *dev);
103 static int ice_allmulti_enable(struct rte_eth_dev *dev);
104 static int ice_allmulti_disable(struct rte_eth_dev *dev);
105 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
108 static int ice_macaddr_set(struct rte_eth_dev *dev,
109 struct rte_ether_addr *mac_addr);
110 static int ice_macaddr_add(struct rte_eth_dev *dev,
111 struct rte_ether_addr *mac_addr,
112 __rte_unused uint32_t index,
114 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
115 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
117 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
119 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
121 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
122 uint16_t pvid, int on);
123 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
124 static int ice_get_eeprom(struct rte_eth_dev *dev,
125 struct rte_dev_eeprom_info *eeprom);
126 static int ice_stats_get(struct rte_eth_dev *dev,
127 struct rte_eth_stats *stats);
128 static int ice_stats_reset(struct rte_eth_dev *dev);
129 static int ice_xstats_get(struct rte_eth_dev *dev,
130 struct rte_eth_xstat *xstats, unsigned int n);
131 static int ice_xstats_get_names(struct rte_eth_dev *dev,
132 struct rte_eth_xstat_name *xstats_names,
134 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
135 enum rte_filter_type filter_type,
136 enum rte_filter_op filter_op,
138 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
139 struct rte_eth_udp_tunnel *udp_tunnel);
140 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
141 struct rte_eth_udp_tunnel *udp_tunnel);
143 static const struct rte_pci_id pci_id_ice_map[] = {
144 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
145 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
146 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
147 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
148 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
149 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
150 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
157 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
159 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
164 { .vendor_id = 0, /* sentinel */ },
167 static const struct eth_dev_ops ice_eth_dev_ops = {
168 .dev_configure = ice_dev_configure,
169 .dev_start = ice_dev_start,
170 .dev_stop = ice_dev_stop,
171 .dev_close = ice_dev_close,
172 .dev_reset = ice_dev_reset,
173 .dev_set_link_up = ice_dev_set_link_up,
174 .dev_set_link_down = ice_dev_set_link_down,
175 .rx_queue_start = ice_rx_queue_start,
176 .rx_queue_stop = ice_rx_queue_stop,
177 .tx_queue_start = ice_tx_queue_start,
178 .tx_queue_stop = ice_tx_queue_stop,
179 .rx_queue_setup = ice_rx_queue_setup,
180 .rx_queue_release = ice_rx_queue_release,
181 .tx_queue_setup = ice_tx_queue_setup,
182 .tx_queue_release = ice_tx_queue_release,
183 .dev_infos_get = ice_dev_info_get,
184 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
185 .link_update = ice_link_update,
186 .mtu_set = ice_mtu_set,
187 .mac_addr_set = ice_macaddr_set,
188 .mac_addr_add = ice_macaddr_add,
189 .mac_addr_remove = ice_macaddr_remove,
190 .vlan_filter_set = ice_vlan_filter_set,
191 .vlan_offload_set = ice_vlan_offload_set,
192 .reta_update = ice_rss_reta_update,
193 .reta_query = ice_rss_reta_query,
194 .rss_hash_update = ice_rss_hash_update,
195 .rss_hash_conf_get = ice_rss_hash_conf_get,
196 .promiscuous_enable = ice_promisc_enable,
197 .promiscuous_disable = ice_promisc_disable,
198 .allmulticast_enable = ice_allmulti_enable,
199 .allmulticast_disable = ice_allmulti_disable,
200 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
201 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
202 .fw_version_get = ice_fw_version_get,
203 .vlan_pvid_set = ice_vlan_pvid_set,
204 .rxq_info_get = ice_rxq_info_get,
205 .txq_info_get = ice_txq_info_get,
206 .rx_burst_mode_get = ice_rx_burst_mode_get,
207 .tx_burst_mode_get = ice_tx_burst_mode_get,
208 .get_eeprom_length = ice_get_eeprom_length,
209 .get_eeprom = ice_get_eeprom,
210 .stats_get = ice_stats_get,
211 .stats_reset = ice_stats_reset,
212 .xstats_get = ice_xstats_get,
213 .xstats_get_names = ice_xstats_get_names,
214 .xstats_reset = ice_stats_reset,
215 .filter_ctrl = ice_dev_filter_ctrl,
216 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
217 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
218 .tx_done_cleanup = ice_tx_done_cleanup,
219 .get_monitor_addr = ice_get_monitor_addr,
222 /* store statistics names and its offset in stats structure */
223 struct ice_xstats_name_off {
224 char name[RTE_ETH_XSTATS_NAME_SIZE];
228 static const struct ice_xstats_name_off ice_stats_strings[] = {
229 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
230 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
231 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
232 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
233 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
234 rx_unknown_protocol)},
235 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
236 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
237 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
238 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
241 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
242 sizeof(ice_stats_strings[0]))
244 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
245 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
246 tx_dropped_link_down)},
247 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
248 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
250 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
251 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
253 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
255 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
257 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
258 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
259 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
260 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
261 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
262 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
264 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
266 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
268 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
270 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
272 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
274 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
276 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
278 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
279 mac_short_pkt_dropped)},
280 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
282 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
283 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
284 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
286 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
288 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
290 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
292 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
294 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
298 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
299 sizeof(ice_hw_port_strings[0]))
302 ice_init_controlq_parameter(struct ice_hw *hw)
304 /* fields for adminq */
305 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
306 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
307 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
308 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
310 /* fields for mailboxq, DPDK used as PF host */
311 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
312 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
313 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
314 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
318 lookup_proto_xtr_type(const char *xtr_name)
322 enum proto_xtr_type type;
324 { "vlan", PROTO_XTR_VLAN },
325 { "ipv4", PROTO_XTR_IPV4 },
326 { "ipv6", PROTO_XTR_IPV6 },
327 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
328 { "tcp", PROTO_XTR_TCP },
329 { "ip_offset", PROTO_XTR_IP_OFFSET },
333 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
334 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
335 return xtr_type_map[i].type;
342 * Parse elem, the elem could be single number/range or '(' ')' group
343 * 1) A single number elem, it's just a simple digit. e.g. 9
344 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
345 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
346 * Within group elem, '-' used for a range separator;
347 * ',' used for a single number.
350 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
352 const char *str = input;
357 while (isblank(*str))
360 if (!isdigit(*str) && *str != '(')
363 /* process single number or single range of number */
366 idx = strtoul(str, &end, 10);
367 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
370 while (isblank(*end))
376 /* process single <number>-<number> */
379 while (isblank(*end))
385 idx = strtoul(end, &end, 10);
386 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
390 while (isblank(*end))
397 for (idx = RTE_MIN(min, max);
398 idx <= RTE_MAX(min, max); idx++)
399 devargs->proto_xtr[idx] = xtr_type;
404 /* process set within bracket */
406 while (isblank(*str))
411 min = ICE_MAX_QUEUE_NUM;
413 /* go ahead to the first digit */
414 while (isblank(*str))
419 /* get the digit value */
421 idx = strtoul(str, &end, 10);
422 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
425 /* go ahead to separator '-',',' and ')' */
426 while (isblank(*end))
429 if (min == ICE_MAX_QUEUE_NUM)
431 else /* avoid continuous '-' */
433 } else if (*end == ',' || *end == ')') {
435 if (min == ICE_MAX_QUEUE_NUM)
438 for (idx = RTE_MIN(min, max);
439 idx <= RTE_MAX(min, max); idx++)
440 devargs->proto_xtr[idx] = xtr_type;
442 min = ICE_MAX_QUEUE_NUM;
448 } while (*end != ')' && *end != '\0');
454 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
456 const char *queue_start;
461 while (isblank(*queues))
464 if (*queues != '[') {
465 xtr_type = lookup_proto_xtr_type(queues);
469 devargs->proto_xtr_dflt = xtr_type;
476 while (isblank(*queues))
481 queue_start = queues;
483 /* go across a complete bracket */
484 if (*queue_start == '(') {
485 queues += strcspn(queues, ")");
490 /* scan the separator ':' */
491 queues += strcspn(queues, ":");
492 if (*queues++ != ':')
494 while (isblank(*queues))
497 for (idx = 0; ; idx++) {
498 if (isblank(queues[idx]) ||
499 queues[idx] == ',' ||
500 queues[idx] == ']' ||
504 if (idx > sizeof(xtr_name) - 2)
507 xtr_name[idx] = queues[idx];
509 xtr_name[idx] = '\0';
510 xtr_type = lookup_proto_xtr_type(xtr_name);
516 while (isblank(*queues) || *queues == ',' || *queues == ']')
519 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
521 } while (*queues != '\0');
527 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
530 struct ice_devargs *devargs = extra_args;
532 if (value == NULL || extra_args == NULL)
535 if (parse_queue_proto_xtr(value, devargs) < 0) {
537 "The protocol extraction parameter is wrong : '%s'",
546 ice_check_proto_xtr_support(struct ice_hw *hw)
548 #define FLX_REG(val, fld, idx) \
549 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
550 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
557 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
559 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
560 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
562 ICE_PROT_IPV4_OF_OR_S,
563 ICE_PROT_IPV4_OF_OR_S },
564 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
566 ICE_PROT_IPV6_OF_OR_S,
567 ICE_PROT_IPV6_OF_OR_S },
568 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
570 ICE_PROT_IPV6_OF_OR_S,
571 ICE_PROT_IPV6_OF_OR_S },
572 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
574 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
575 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
577 ICE_PROT_IPV4_OF_OR_S,
578 ICE_PROT_IPV6_OF_OR_S },
582 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
583 uint32_t rxdid = xtr_sets[i].rxdid;
586 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
587 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
589 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
590 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
591 ice_proto_xtr_hw_support[i] = true;
594 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
595 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
597 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
598 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
599 ice_proto_xtr_hw_support[i] = true;
605 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
608 struct pool_entry *entry;
613 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
616 "Failed to allocate memory for resource pool");
620 /* queue heap initialize */
621 pool->num_free = num;
624 LIST_INIT(&pool->alloc_list);
625 LIST_INIT(&pool->free_list);
627 /* Initialize element */
631 LIST_INSERT_HEAD(&pool->free_list, entry, next);
636 ice_res_pool_alloc(struct ice_res_pool_info *pool,
639 struct pool_entry *entry, *valid_entry;
642 PMD_INIT_LOG(ERR, "Invalid parameter");
646 if (pool->num_free < num) {
647 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
648 num, pool->num_free);
653 /* Lookup in free list and find most fit one */
654 LIST_FOREACH(entry, &pool->free_list, next) {
655 if (entry->len >= num) {
657 if (entry->len == num) {
662 valid_entry->len > entry->len)
667 /* Not find one to satisfy the request, return */
669 PMD_INIT_LOG(ERR, "No valid entry found");
673 * The entry have equal queue number as requested,
674 * remove it from alloc_list.
676 if (valid_entry->len == num) {
677 LIST_REMOVE(valid_entry, next);
680 * The entry have more numbers than requested,
681 * create a new entry for alloc_list and minus its
682 * queue base and number in free_list.
684 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
687 "Failed to allocate memory for "
691 entry->base = valid_entry->base;
693 valid_entry->base += num;
694 valid_entry->len -= num;
698 /* Insert it into alloc list, not sorted */
699 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
701 pool->num_free -= valid_entry->len;
702 pool->num_alloc += valid_entry->len;
704 return valid_entry->base + pool->base;
708 ice_res_pool_destroy(struct ice_res_pool_info *pool)
710 struct pool_entry *entry, *next_entry;
715 for (entry = LIST_FIRST(&pool->alloc_list);
716 entry && (next_entry = LIST_NEXT(entry, next), 1);
717 entry = next_entry) {
718 LIST_REMOVE(entry, next);
722 for (entry = LIST_FIRST(&pool->free_list);
723 entry && (next_entry = LIST_NEXT(entry, next), 1);
724 entry = next_entry) {
725 LIST_REMOVE(entry, next);
732 LIST_INIT(&pool->alloc_list);
733 LIST_INIT(&pool->free_list);
737 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
739 /* Set VSI LUT selection */
740 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
741 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
742 /* Set Hash scheme */
743 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
744 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
746 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
749 static enum ice_status
750 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
751 struct ice_aqc_vsi_props *info,
752 uint8_t enabled_tcmap)
754 uint16_t bsf, qp_idx;
756 /* default tc 0 now. Multi-TC supporting need to be done later.
757 * Configure TC and queue mapping parameters, for enabled TC,
758 * allocate qpnum_per_tc queues to this traffic.
760 if (enabled_tcmap != 0x01) {
761 PMD_INIT_LOG(ERR, "only TC0 is supported");
765 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
766 bsf = rte_bsf32(vsi->nb_qps);
767 /* Adjust the queue number to actual queues that can be applied */
768 vsi->nb_qps = 0x1 << bsf;
771 /* Set tc and queue mapping with VSI */
772 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
773 ICE_AQ_VSI_TC_Q_OFFSET_S) |
774 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
776 /* Associate queue number with VSI */
777 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
778 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
779 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
780 info->valid_sections |=
781 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
782 /* Set the info.ingress_table and info.egress_table
783 * for UP translate table. Now just set it to 1:1 map by default
784 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
786 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
787 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
788 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
789 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
794 ice_init_mac_address(struct rte_eth_dev *dev)
796 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
798 if (!rte_is_unicast_ether_addr
799 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
800 PMD_INIT_LOG(ERR, "Invalid MAC address");
805 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
806 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
808 dev->data->mac_addrs =
809 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
810 if (!dev->data->mac_addrs) {
812 "Failed to allocate memory to store mac address");
815 /* store it to dev data */
817 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
818 &dev->data->mac_addrs[0]);
822 /* Find out specific MAC filter */
823 static struct ice_mac_filter *
824 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
826 struct ice_mac_filter *f;
828 TAILQ_FOREACH(f, &vsi->mac_list, next) {
829 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
837 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
839 struct ice_fltr_list_entry *m_list_itr = NULL;
840 struct ice_mac_filter *f;
841 struct LIST_HEAD_TYPE list_head;
842 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
845 /* If it's added and configured, return */
846 f = ice_find_mac_filter(vsi, mac_addr);
848 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
852 INIT_LIST_HEAD(&list_head);
854 m_list_itr = (struct ice_fltr_list_entry *)
855 ice_malloc(hw, sizeof(*m_list_itr));
860 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
861 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
862 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
863 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
864 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
865 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
866 m_list_itr->fltr_info.vsi_handle = vsi->idx;
868 LIST_ADD(&m_list_itr->list_entry, &list_head);
871 ret = ice_add_mac(hw, &list_head);
872 if (ret != ICE_SUCCESS) {
873 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
877 /* Add the mac addr into mac list */
878 f = rte_zmalloc(NULL, sizeof(*f), 0);
880 PMD_DRV_LOG(ERR, "failed to allocate memory");
884 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
885 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
891 rte_free(m_list_itr);
896 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
898 struct ice_fltr_list_entry *m_list_itr = NULL;
899 struct ice_mac_filter *f;
900 struct LIST_HEAD_TYPE list_head;
901 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
904 /* Can't find it, return an error */
905 f = ice_find_mac_filter(vsi, mac_addr);
909 INIT_LIST_HEAD(&list_head);
911 m_list_itr = (struct ice_fltr_list_entry *)
912 ice_malloc(hw, sizeof(*m_list_itr));
917 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
918 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
919 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
920 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
921 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
922 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
923 m_list_itr->fltr_info.vsi_handle = vsi->idx;
925 LIST_ADD(&m_list_itr->list_entry, &list_head);
927 /* remove the mac filter */
928 ret = ice_remove_mac(hw, &list_head);
929 if (ret != ICE_SUCCESS) {
930 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
935 /* Remove the mac addr from mac list */
936 TAILQ_REMOVE(&vsi->mac_list, f, next);
942 rte_free(m_list_itr);
946 /* Find out specific VLAN filter */
947 static struct ice_vlan_filter *
948 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
950 struct ice_vlan_filter *f;
952 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
953 if (vlan_id == f->vlan_info.vlan_id)
961 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
963 struct ice_fltr_list_entry *v_list_itr = NULL;
964 struct ice_vlan_filter *f;
965 struct LIST_HEAD_TYPE list_head;
969 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
972 hw = ICE_VSI_TO_HW(vsi);
974 /* If it's added and configured, return. */
975 f = ice_find_vlan_filter(vsi, vlan_id);
977 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
981 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
984 INIT_LIST_HEAD(&list_head);
986 v_list_itr = (struct ice_fltr_list_entry *)
987 ice_malloc(hw, sizeof(*v_list_itr));
992 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
993 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
994 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
995 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
996 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
997 v_list_itr->fltr_info.vsi_handle = vsi->idx;
999 LIST_ADD(&v_list_itr->list_entry, &list_head);
1002 ret = ice_add_vlan(hw, &list_head);
1003 if (ret != ICE_SUCCESS) {
1004 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1009 /* Add vlan into vlan list */
1010 f = rte_zmalloc(NULL, sizeof(*f), 0);
1012 PMD_DRV_LOG(ERR, "failed to allocate memory");
1016 f->vlan_info.vlan_id = vlan_id;
1017 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1023 rte_free(v_list_itr);
1028 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1030 struct ice_fltr_list_entry *v_list_itr = NULL;
1031 struct ice_vlan_filter *f;
1032 struct LIST_HEAD_TYPE list_head;
1037 * Vlan 0 is the generic filter for untagged packets
1038 * and can't be removed.
1040 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1043 hw = ICE_VSI_TO_HW(vsi);
1045 /* Can't find it, return an error */
1046 f = ice_find_vlan_filter(vsi, vlan_id);
1050 INIT_LIST_HEAD(&list_head);
1052 v_list_itr = (struct ice_fltr_list_entry *)
1053 ice_malloc(hw, sizeof(*v_list_itr));
1059 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1060 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1061 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1062 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1063 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1064 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1066 LIST_ADD(&v_list_itr->list_entry, &list_head);
1068 /* remove the vlan filter */
1069 ret = ice_remove_vlan(hw, &list_head);
1070 if (ret != ICE_SUCCESS) {
1071 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1076 /* Remove the vlan id from vlan list */
1077 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1083 rte_free(v_list_itr);
1088 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1090 struct ice_mac_filter *m_f;
1091 struct ice_vlan_filter *v_f;
1094 if (!vsi || !vsi->mac_num)
1097 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1098 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1099 if (ret != ICE_SUCCESS) {
1105 if (vsi->vlan_num == 0)
1108 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1109 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1110 if (ret != ICE_SUCCESS) {
1121 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1123 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1124 struct ice_vsi_ctx ctxt;
1128 /* Check if it has been already on or off */
1129 if (vsi->info.valid_sections &
1130 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1132 if ((vsi->info.outer_vlan_flags &
1133 ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST) ==
1134 ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST)
1135 return 0; /* already on */
1137 if (!(vsi->info.outer_vlan_flags &
1138 ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST))
1139 return 0; /* already off */
1144 qinq_flags = ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST;
1147 /* clear global insertion and use per packet insertion */
1148 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT);
1149 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST);
1150 vsi->info.outer_vlan_flags |= qinq_flags;
1151 /* use default vlan type 0x8100 */
1152 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1153 vsi->info.outer_vlan_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1154 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1155 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1156 ctxt.info.valid_sections =
1157 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1158 ctxt.vsi_num = vsi->vsi_id;
1159 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1162 "Update VSI failed to %s qinq stripping",
1163 on ? "enable" : "disable");
1167 vsi->info.valid_sections |=
1168 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1174 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1176 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1177 struct ice_vsi_ctx ctxt;
1181 /* Check if it has been already on or off */
1182 if (vsi->info.valid_sections &
1183 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1185 if ((vsi->info.outer_vlan_flags &
1186 ICE_AQ_VSI_OUTER_VLAN_EMODE_M) ==
1187 ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW)
1188 return 0; /* already on */
1190 if ((vsi->info.outer_vlan_flags &
1191 ICE_AQ_VSI_OUTER_VLAN_EMODE_M) ==
1192 ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH)
1193 return 0; /* already off */
1198 qinq_flags = ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW;
1200 qinq_flags = ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH;
1201 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M);
1202 vsi->info.outer_vlan_flags |= qinq_flags;
1203 /* use default vlan type 0x8100 */
1204 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1205 vsi->info.outer_vlan_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1206 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1207 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1208 ctxt.info.valid_sections =
1209 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1210 ctxt.vsi_num = vsi->vsi_id;
1211 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1214 "Update VSI failed to %s qinq stripping",
1215 on ? "enable" : "disable");
1219 vsi->info.valid_sections |=
1220 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1226 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1230 ret = ice_vsi_config_qinq_stripping(vsi, on);
1232 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1234 ret = ice_vsi_config_qinq_insertion(vsi, on);
1236 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1243 ice_pf_enable_irq0(struct ice_hw *hw)
1245 /* reset the registers */
1246 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1247 ICE_READ_REG(hw, PFINT_OICR);
1250 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1251 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1252 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1254 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1255 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1256 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1257 PFINT_OICR_CTL_ITR_INDX_M) |
1258 PFINT_OICR_CTL_CAUSE_ENA_M);
1260 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1261 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1262 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1263 PFINT_FW_CTL_ITR_INDX_M) |
1264 PFINT_FW_CTL_CAUSE_ENA_M);
1266 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1269 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1270 GLINT_DYN_CTL_INTENA_M |
1271 GLINT_DYN_CTL_CLEARPBA_M |
1272 GLINT_DYN_CTL_ITR_INDX_M);
1279 ice_pf_disable_irq0(struct ice_hw *hw)
1281 /* Disable all interrupt types */
1282 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1288 ice_handle_aq_msg(struct rte_eth_dev *dev)
1290 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1291 struct ice_ctl_q_info *cq = &hw->adminq;
1292 struct ice_rq_event_info event;
1293 uint16_t pending, opcode;
1296 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1297 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1298 if (!event.msg_buf) {
1299 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1305 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1307 if (ret != ICE_SUCCESS) {
1309 "Failed to read msg from AdminQ, "
1311 hw->adminq.sq_last_status);
1314 opcode = rte_le_to_cpu_16(event.desc.opcode);
1317 case ice_aqc_opc_get_link_status:
1318 ret = ice_link_update(dev, 0);
1320 rte_eth_dev_callback_process
1321 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1324 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1329 rte_free(event.msg_buf);
1334 * Interrupt handler triggered by NIC for handling
1335 * specific interrupt.
1338 * Pointer to interrupt handle.
1340 * The address of parameter (struct rte_eth_dev *) regsitered before.
1346 ice_interrupt_handler(void *param)
1348 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1349 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357 uint32_t int_fw_ctl;
1360 /* Disable interrupt */
1361 ice_pf_disable_irq0(hw);
1363 /* read out interrupt causes */
1364 oicr = ICE_READ_REG(hw, PFINT_OICR);
1366 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1369 /* No interrupt event indicated */
1370 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1371 PMD_DRV_LOG(INFO, "No interrupt event");
1376 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1377 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1378 ice_handle_aq_msg(dev);
1381 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1382 PMD_DRV_LOG(INFO, "OICR: link state change event");
1383 ret = ice_link_update(dev, 0);
1385 rte_eth_dev_callback_process
1386 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1390 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1391 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1392 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1393 if (reg & GL_MDET_TX_PQM_VALID_M) {
1394 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1395 GL_MDET_TX_PQM_PF_NUM_S;
1396 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1397 GL_MDET_TX_PQM_MAL_TYPE_S;
1398 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1399 GL_MDET_TX_PQM_QNUM_S;
1401 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1402 "%d by PQM on TX queue %d PF# %d",
1403 event, queue, pf_num);
1406 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1407 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1408 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1409 GL_MDET_TX_TCLAN_PF_NUM_S;
1410 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1411 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1412 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1413 GL_MDET_TX_TCLAN_QNUM_S;
1415 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1416 "%d by TCLAN on TX queue %d PF# %d",
1417 event, queue, pf_num);
1421 /* Enable interrupt */
1422 ice_pf_enable_irq0(hw);
1423 rte_intr_ack(dev->intr_handle);
1427 ice_init_proto_xtr(struct rte_eth_dev *dev)
1429 struct ice_adapter *ad =
1430 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1431 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1432 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1433 const struct proto_xtr_ol_flag *ol_flag;
1434 bool proto_xtr_enable = false;
1438 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1439 if (unlikely(pf->proto_xtr == NULL)) {
1440 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1444 for (i = 0; i < pf->lan_nb_qps; i++) {
1445 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1446 ad->devargs.proto_xtr[i] :
1447 ad->devargs.proto_xtr_dflt;
1449 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1450 uint8_t type = pf->proto_xtr[i];
1452 ice_proto_xtr_ol_flag_params[type].required = true;
1453 proto_xtr_enable = true;
1457 if (likely(!proto_xtr_enable))
1460 ice_check_proto_xtr_support(hw);
1462 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1463 if (unlikely(offset == -1)) {
1465 "Protocol extraction metadata is disabled in mbuf with error %d",
1471 "Protocol extraction metadata offset in mbuf is : %d",
1473 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1475 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1476 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1478 if (!ol_flag->required)
1481 if (!ice_proto_xtr_hw_support[i]) {
1483 "Protocol extraction type %u is not supported in hardware",
1485 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1489 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1490 if (unlikely(offset == -1)) {
1492 "Protocol extraction offload '%s' failed to register with error %d",
1493 ol_flag->param.name, -rte_errno);
1495 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1500 "Protocol extraction offload '%s' offset in mbuf is : %d",
1501 ol_flag->param.name, offset);
1502 *ol_flag->ol_flag = 1ULL << offset;
1506 /* Initialize SW parameters of PF */
1508 ice_pf_sw_init(struct rte_eth_dev *dev)
1510 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1511 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1514 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1515 hw->func_caps.common_cap.num_rxq);
1517 pf->lan_nb_qps = pf->lan_nb_qp_max;
1519 ice_init_proto_xtr(dev);
1521 if (hw->func_caps.fd_fltr_guar > 0 ||
1522 hw->func_caps.fd_fltr_best_effort > 0) {
1523 pf->flags |= ICE_FLAG_FDIR;
1524 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1525 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1527 pf->fdir_nb_qps = 0;
1529 pf->fdir_qp_offset = 0;
1535 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1537 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1538 struct ice_vsi *vsi = NULL;
1539 struct ice_vsi_ctx vsi_ctx;
1541 struct rte_ether_addr broadcast = {
1542 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1543 struct rte_ether_addr mac_addr;
1544 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1545 uint8_t tc_bitmap = 0x1;
1548 /* hw->num_lports = 1 in NIC mode */
1549 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1553 vsi->idx = pf->next_vsi_idx;
1556 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1557 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1558 vsi->vlan_anti_spoof_on = 0;
1559 vsi->vlan_filter_on = 1;
1560 TAILQ_INIT(&vsi->mac_list);
1561 TAILQ_INIT(&vsi->vlan_list);
1563 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1564 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1565 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1566 hw->func_caps.common_cap.rss_table_size;
1567 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1569 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1572 vsi->nb_qps = pf->lan_nb_qps;
1573 vsi->base_queue = 1;
1574 ice_vsi_config_default_rss(&vsi_ctx.info);
1575 vsi_ctx.alloc_from_pool = true;
1576 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1577 /* switch_id is queried by get_switch_config aq, which is done
1580 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1581 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1582 /* Allow all untagged or tagged packets */
1583 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1584 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1585 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1586 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1589 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1590 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1591 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1592 cfg = ICE_AQ_VSI_FD_ENABLE;
1593 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1594 vsi_ctx.info.max_fd_fltr_dedicated =
1595 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1596 vsi_ctx.info.max_fd_fltr_shared =
1597 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1599 /* Enable VLAN/UP trip */
1600 ret = ice_vsi_config_tc_queue_mapping(vsi,
1605 "tc queue mapping with vsi failed, "
1613 vsi->nb_qps = pf->fdir_nb_qps;
1614 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1615 vsi_ctx.alloc_from_pool = true;
1616 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1618 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1619 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1620 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1621 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1622 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1623 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1624 ret = ice_vsi_config_tc_queue_mapping(vsi,
1629 "tc queue mapping with vsi failed, "
1636 /* for other types of VSI */
1637 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1641 /* VF has MSIX interrupt in VF range, don't allocate here */
1642 if (type == ICE_VSI_PF) {
1643 ret = ice_res_pool_alloc(&pf->msix_pool,
1644 RTE_MIN(vsi->nb_qps,
1645 RTE_MAX_RXTX_INTR_VEC_ID));
1647 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1650 vsi->msix_intr = ret;
1651 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1652 } else if (type == ICE_VSI_CTRL) {
1653 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1655 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1658 vsi->msix_intr = ret;
1664 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1665 if (ret != ICE_SUCCESS) {
1666 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1669 /* store vsi information is SW structure */
1670 vsi->vsi_id = vsi_ctx.vsi_num;
1671 vsi->info = vsi_ctx.info;
1672 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1673 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1675 if (type == ICE_VSI_PF) {
1676 /* MAC configuration */
1677 rte_ether_addr_copy((struct rte_ether_addr *)
1678 hw->port_info->mac.perm_addr,
1681 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1682 ret = ice_add_mac_filter(vsi, &mac_addr);
1683 if (ret != ICE_SUCCESS)
1684 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1686 rte_ether_addr_copy(&broadcast, &mac_addr);
1687 ret = ice_add_mac_filter(vsi, &mac_addr);
1688 if (ret != ICE_SUCCESS)
1689 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1692 /* At the beginning, only TC0. */
1693 /* What we need here is the maximam number of the TX queues.
1694 * Currently vsi->nb_qps means it.
1695 * Correct it if any change.
1697 max_txqs[0] = vsi->nb_qps;
1698 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1699 tc_bitmap, max_txqs);
1700 if (ret != ICE_SUCCESS)
1701 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1711 ice_send_driver_ver(struct ice_hw *hw)
1713 struct ice_driver_ver dv;
1715 /* we don't have driver version use 0 for dummy */
1719 dv.subbuild_ver = 0;
1720 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1722 return ice_aq_send_driver_ver(hw, &dv, NULL);
1726 ice_pf_setup(struct ice_pf *pf)
1728 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1729 struct ice_vsi *vsi;
1732 /* Clear all stats counters */
1733 pf->offset_loaded = false;
1734 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1735 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1736 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1737 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1739 /* force guaranteed filter pool for PF */
1740 ice_alloc_fd_guar_item(hw, &unused,
1741 hw->func_caps.fd_fltr_guar);
1742 /* force shared filter pool for PF */
1743 ice_alloc_fd_shrd_item(hw, &unused,
1744 hw->func_caps.fd_fltr_best_effort);
1746 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1748 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1758 * Extract device serial number from PCIe Configuration Space and
1759 * determine the pkg file path according to the DSN.
1762 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1765 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1766 uint32_t dsn_low, dsn_high;
1767 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1769 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1772 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1773 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1774 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1775 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1777 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1781 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1782 ICE_MAX_PKG_FILENAME_SIZE);
1783 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1786 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1787 ICE_MAX_PKG_FILENAME_SIZE);
1788 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1792 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1793 if (!access(pkg_file, 0))
1795 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1800 ice_load_pkg_type(struct ice_hw *hw)
1802 enum ice_pkg_type package_type;
1804 /* store the activated package type (OS default or Comms) */
1805 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1807 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1808 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1810 package_type = ICE_PKG_TYPE_COMMS;
1812 package_type = ICE_PKG_TYPE_UNKNOWN;
1814 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1815 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1816 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1817 hw->active_pkg_name);
1819 return package_type;
1822 static int ice_load_pkg(struct rte_eth_dev *dev)
1824 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1831 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1832 struct ice_adapter *ad =
1833 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1835 ice_pkg_file_search_path(pci_dev, pkg_file);
1837 file = fopen(pkg_file, "rb");
1839 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1843 err = stat(pkg_file, &fstat);
1845 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1850 buf_len = fstat.st_size;
1851 buf = rte_malloc(NULL, buf_len, 0);
1854 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1860 err = fread(buf, buf_len, 1, file);
1862 PMD_INIT_LOG(ERR, "failed to read package data\n");
1870 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1872 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1876 /* store the loaded pkg type info */
1877 ad->active_pkg_type = ice_load_pkg_type(hw);
1879 err = ice_init_hw_tbls(hw);
1881 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1882 goto fail_init_tbls;
1888 rte_free(hw->pkg_copy);
1895 ice_base_queue_get(struct ice_pf *pf)
1898 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1900 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1901 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1902 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1904 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1910 parse_bool(const char *key, const char *value, void *args)
1912 int *i = (int *)args;
1916 num = strtoul(value, &end, 10);
1918 if (num != 0 && num != 1) {
1919 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1920 "value must be 0 or 1",
1929 static int ice_parse_devargs(struct rte_eth_dev *dev)
1931 struct ice_adapter *ad =
1932 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1933 struct rte_devargs *devargs = dev->device->devargs;
1934 struct rte_kvargs *kvlist;
1937 if (devargs == NULL)
1940 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1941 if (kvlist == NULL) {
1942 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1946 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1947 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1948 sizeof(ad->devargs.proto_xtr));
1950 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1951 &handle_proto_xtr_arg, &ad->devargs);
1955 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1956 &parse_bool, &ad->devargs.safe_mode_support);
1960 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1961 &parse_bool, &ad->devargs.pipe_mode_support);
1966 rte_kvargs_free(kvlist);
1970 /* Forward LLDP packets to default VSI by set switch rules */
1972 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1974 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1975 struct ice_fltr_list_entry *s_list_itr = NULL;
1976 struct LIST_HEAD_TYPE list_head;
1979 INIT_LIST_HEAD(&list_head);
1981 s_list_itr = (struct ice_fltr_list_entry *)
1982 ice_malloc(hw, sizeof(*s_list_itr));
1985 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1986 s_list_itr->fltr_info.vsi_handle = vsi->idx;
1987 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1988 RTE_ETHER_TYPE_LLDP;
1989 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1990 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1991 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1992 LIST_ADD(&s_list_itr->list_entry, &list_head);
1994 ret = ice_add_eth_mac(hw, &list_head);
1996 ret = ice_remove_eth_mac(hw, &list_head);
1998 rte_free(s_list_itr);
2002 static enum ice_status
2003 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2004 uint16_t num, uint16_t desc_id,
2005 uint16_t *prof_buf, uint16_t *num_prof)
2007 struct ice_aqc_res_elem *resp_buf;
2010 bool res_shared = 1;
2011 struct ice_aq_desc aq_desc;
2012 struct ice_sq_cd *cd = NULL;
2013 struct ice_aqc_get_allocd_res_desc *cmd =
2014 &aq_desc.params.get_res_desc;
2016 buf_len = sizeof(*resp_buf) * num;
2017 resp_buf = ice_malloc(hw, buf_len);
2021 ice_fill_dflt_direct_cmd_desc(&aq_desc,
2022 ice_aqc_opc_get_allocd_res_desc);
2024 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2025 ICE_AQC_RES_TYPE_M) | (res_shared ?
2026 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2027 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2029 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2031 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2035 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
2036 (*num_prof), ICE_NONDMA_TO_NONDMA);
2043 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2047 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2048 uint16_t first_desc = 1;
2049 uint16_t num_prof = 0;
2051 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2052 first_desc, prof_buf, &num_prof);
2054 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2058 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2059 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2061 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2069 ice_reset_fxp_resource(struct ice_hw *hw)
2073 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2075 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2079 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2081 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2089 ice_rss_ctx_init(struct ice_pf *pf)
2091 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
2095 ice_get_supported_rxdid(struct ice_hw *hw)
2097 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2101 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2103 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2104 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2105 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2106 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2107 supported_rxdid |= BIT(i);
2109 return supported_rxdid;
2113 ice_dev_init(struct rte_eth_dev *dev)
2115 struct rte_pci_device *pci_dev;
2116 struct rte_intr_handle *intr_handle;
2117 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2118 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2119 struct ice_adapter *ad =
2120 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2121 struct ice_vsi *vsi;
2124 dev->dev_ops = &ice_eth_dev_ops;
2125 dev->rx_queue_count = ice_rx_queue_count;
2126 dev->rx_descriptor_status = ice_rx_descriptor_status;
2127 dev->tx_descriptor_status = ice_tx_descriptor_status;
2128 dev->rx_pkt_burst = ice_recv_pkts;
2129 dev->tx_pkt_burst = ice_xmit_pkts;
2130 dev->tx_pkt_prepare = ice_prep_pkts;
2132 /* for secondary processes, we don't initialise any further as primary
2133 * has already done this work.
2135 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2136 ice_set_rx_function(dev);
2137 ice_set_tx_function(dev);
2141 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2143 ice_set_default_ptype_table(dev);
2144 pci_dev = RTE_DEV_TO_PCI(dev->device);
2145 intr_handle = &pci_dev->intr_handle;
2147 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2148 pf->adapter->eth_dev = dev;
2149 pf->dev_data = dev->data;
2150 hw->back = pf->adapter;
2151 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2152 hw->vendor_id = pci_dev->id.vendor_id;
2153 hw->device_id = pci_dev->id.device_id;
2154 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2155 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2156 hw->bus.device = pci_dev->addr.devid;
2157 hw->bus.func = pci_dev->addr.function;
2159 ret = ice_parse_devargs(dev);
2161 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2165 ice_init_controlq_parameter(hw);
2167 ret = ice_init_hw(hw);
2169 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2173 ret = ice_load_pkg(dev);
2175 if (ad->devargs.safe_mode_support == 0) {
2176 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2177 "Use safe-mode-support=1 to enter Safe Mode");
2181 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2182 "Entering Safe Mode");
2183 ad->is_safe_mode = 1;
2186 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2187 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2188 hw->api_maj_ver, hw->api_min_ver);
2190 ice_pf_sw_init(dev);
2191 ret = ice_init_mac_address(dev);
2193 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2197 ret = ice_res_pool_init(&pf->msix_pool, 1,
2198 hw->func_caps.common_cap.num_msix_vectors - 1);
2200 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2201 goto err_msix_pool_init;
2204 ret = ice_pf_setup(pf);
2206 PMD_INIT_LOG(ERR, "Failed to setup PF");
2210 ret = ice_send_driver_ver(hw);
2212 PMD_INIT_LOG(ERR, "Failed to send driver version");
2218 /* Disable double vlan by default */
2219 ice_vsi_config_double_vlan(vsi, false);
2221 ret = ice_aq_stop_lldp(hw, true, false, NULL);
2222 if (ret != ICE_SUCCESS)
2223 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2224 ret = ice_init_dcb(hw, true);
2225 if (ret != ICE_SUCCESS)
2226 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2227 /* Forward LLDP packets to default VSI */
2228 ret = ice_vsi_config_sw_lldp(vsi, true);
2229 if (ret != ICE_SUCCESS)
2230 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2231 /* register callback func to eal lib */
2232 rte_intr_callback_register(intr_handle,
2233 ice_interrupt_handler, dev);
2235 ice_pf_enable_irq0(hw);
2237 /* enable uio intr after callback register */
2238 rte_intr_enable(intr_handle);
2240 /* get base queue pairs index in the device */
2241 ice_base_queue_get(pf);
2243 /* Initialize RSS context for gtpu_eh */
2244 ice_rss_ctx_init(pf);
2246 if (!ad->is_safe_mode) {
2247 ret = ice_flow_init(ad);
2249 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2254 ret = ice_reset_fxp_resource(hw);
2256 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2260 pf->supported_rxdid = ice_get_supported_rxdid(hw);
2265 ice_res_pool_destroy(&pf->msix_pool);
2267 rte_free(dev->data->mac_addrs);
2268 dev->data->mac_addrs = NULL;
2270 ice_sched_cleanup_all(hw);
2271 rte_free(hw->port_info);
2272 ice_shutdown_all_ctrlq(hw);
2273 rte_free(pf->proto_xtr);
2279 ice_release_vsi(struct ice_vsi *vsi)
2282 struct ice_vsi_ctx vsi_ctx;
2283 enum ice_status ret;
2289 hw = ICE_VSI_TO_HW(vsi);
2291 ice_remove_all_mac_vlan_filters(vsi);
2293 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2295 vsi_ctx.vsi_num = vsi->vsi_id;
2296 vsi_ctx.info = vsi->info;
2297 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2298 if (ret != ICE_SUCCESS) {
2299 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2303 rte_free(vsi->rss_lut);
2304 rte_free(vsi->rss_key);
2310 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2312 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2313 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2314 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2315 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2316 uint16_t msix_intr, i;
2318 /* disable interrupt and also clear all the exist config */
2319 for (i = 0; i < vsi->nb_qps; i++) {
2320 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2321 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2325 if (rte_intr_allow_others(intr_handle))
2327 for (i = 0; i < vsi->nb_msix; i++) {
2328 msix_intr = vsi->msix_intr + i;
2329 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2330 GLINT_DYN_CTL_WB_ON_ITR_M);
2334 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2338 ice_dev_stop(struct rte_eth_dev *dev)
2340 struct rte_eth_dev_data *data = dev->data;
2341 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2342 struct ice_vsi *main_vsi = pf->main_vsi;
2343 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2344 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2347 /* avoid stopping again */
2348 if (pf->adapter_stopped)
2351 /* stop and clear all Rx queues */
2352 for (i = 0; i < data->nb_rx_queues; i++)
2353 ice_rx_queue_stop(dev, i);
2355 /* stop and clear all Tx queues */
2356 for (i = 0; i < data->nb_tx_queues; i++)
2357 ice_tx_queue_stop(dev, i);
2359 /* disable all queue interrupts */
2360 ice_vsi_disable_queues_intr(main_vsi);
2362 if (pf->init_link_up)
2363 ice_dev_set_link_up(dev);
2365 ice_dev_set_link_down(dev);
2367 /* Clean datapath event and queue/vec mapping */
2368 rte_intr_efd_disable(intr_handle);
2369 if (intr_handle->intr_vec) {
2370 rte_free(intr_handle->intr_vec);
2371 intr_handle->intr_vec = NULL;
2374 pf->adapter_stopped = true;
2375 dev->data->dev_started = 0;
2381 ice_dev_close(struct rte_eth_dev *dev)
2383 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2384 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2385 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2386 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2387 struct ice_adapter *ad =
2388 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2391 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2394 /* Since stop will make link down, then the link event will be
2395 * triggered, disable the irq firstly to avoid the port_infoe etc
2396 * resources deallocation causing the interrupt service thread
2399 ice_pf_disable_irq0(hw);
2401 ret = ice_dev_stop(dev);
2403 if (!ad->is_safe_mode)
2404 ice_flow_uninit(ad);
2406 /* release all queue resource */
2407 ice_free_queues(dev);
2409 ice_res_pool_destroy(&pf->msix_pool);
2410 ice_release_vsi(pf->main_vsi);
2411 ice_sched_cleanup_all(hw);
2412 ice_free_hw_tbls(hw);
2413 rte_free(hw->port_info);
2414 hw->port_info = NULL;
2415 ice_shutdown_all_ctrlq(hw);
2416 rte_free(pf->proto_xtr);
2417 pf->proto_xtr = NULL;
2419 /* disable uio intr before callback unregister */
2420 rte_intr_disable(intr_handle);
2422 /* unregister callback func from eal lib */
2423 rte_intr_callback_unregister(intr_handle,
2424 ice_interrupt_handler, dev);
2430 ice_dev_uninit(struct rte_eth_dev *dev)
2438 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2440 return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2444 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2449 cfg->hdr_type = ICE_RSS_ANY_HEADERS;
2453 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2455 enum ice_status status = ICE_SUCCESS;
2456 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2457 struct ice_vsi *vsi = pf->main_vsi;
2459 if (!is_hash_cfg_valid(cfg))
2462 status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2463 if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2465 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2474 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2476 enum ice_status status = ICE_SUCCESS;
2477 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2478 struct ice_vsi *vsi = pf->main_vsi;
2480 if (!is_hash_cfg_valid(cfg))
2483 status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2486 "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2495 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2499 ret = ice_hash_moveout(pf, cfg);
2500 if (ret && (ret != -ENOENT))
2503 hash_cfg_reset(cfg);
2509 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2515 case ICE_HASH_GTPU_CTX_EH_IP:
2516 ret = ice_hash_remove(pf,
2517 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2518 if (ret && (ret != -ENOENT))
2521 ret = ice_hash_remove(pf,
2522 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2523 if (ret && (ret != -ENOENT))
2526 ret = ice_hash_remove(pf,
2527 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2528 if (ret && (ret != -ENOENT))
2531 ret = ice_hash_remove(pf,
2532 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2533 if (ret && (ret != -ENOENT))
2536 ret = ice_hash_remove(pf,
2537 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2538 if (ret && (ret != -ENOENT))
2541 ret = ice_hash_remove(pf,
2542 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2543 if (ret && (ret != -ENOENT))
2546 ret = ice_hash_remove(pf,
2547 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2548 if (ret && (ret != -ENOENT))
2551 ret = ice_hash_remove(pf,
2552 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2553 if (ret && (ret != -ENOENT))
2557 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2558 ret = ice_hash_remove(pf,
2559 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2560 if (ret && (ret != -ENOENT))
2563 ret = ice_hash_remove(pf,
2564 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2565 if (ret && (ret != -ENOENT))
2568 ret = ice_hash_moveout(pf,
2569 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2570 if (ret && (ret != -ENOENT))
2573 ret = ice_hash_moveout(pf,
2574 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2575 if (ret && (ret != -ENOENT))
2578 ret = ice_hash_moveout(pf,
2579 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2580 if (ret && (ret != -ENOENT))
2583 ret = ice_hash_moveout(pf,
2584 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2585 if (ret && (ret != -ENOENT))
2589 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2590 ret = ice_hash_remove(pf,
2591 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2592 if (ret && (ret != -ENOENT))
2595 ret = ice_hash_remove(pf,
2596 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2597 if (ret && (ret != -ENOENT))
2600 ret = ice_hash_moveout(pf,
2601 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2602 if (ret && (ret != -ENOENT))
2605 ret = ice_hash_moveout(pf,
2606 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2607 if (ret && (ret != -ENOENT))
2610 ret = ice_hash_moveout(pf,
2611 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2612 if (ret && (ret != -ENOENT))
2615 ret = ice_hash_moveout(pf,
2616 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2617 if (ret && (ret != -ENOENT))
2621 case ICE_HASH_GTPU_CTX_UP_IP:
2622 ret = ice_hash_remove(pf,
2623 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2624 if (ret && (ret != -ENOENT))
2627 ret = ice_hash_remove(pf,
2628 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2629 if (ret && (ret != -ENOENT))
2632 ret = ice_hash_moveout(pf,
2633 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2634 if (ret && (ret != -ENOENT))
2637 ret = ice_hash_moveout(pf,
2638 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2639 if (ret && (ret != -ENOENT))
2642 ret = ice_hash_moveout(pf,
2643 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2644 if (ret && (ret != -ENOENT))
2648 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2649 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2650 ret = ice_hash_moveout(pf,
2651 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2652 if (ret && (ret != -ENOENT))
2655 ret = ice_hash_moveout(pf,
2656 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2657 if (ret && (ret != -ENOENT))
2660 ret = ice_hash_moveout(pf,
2661 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2662 if (ret && (ret != -ENOENT))
2666 case ICE_HASH_GTPU_CTX_DW_IP:
2667 ret = ice_hash_remove(pf,
2668 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2669 if (ret && (ret != -ENOENT))
2672 ret = ice_hash_remove(pf,
2673 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2674 if (ret && (ret != -ENOENT))
2677 ret = ice_hash_moveout(pf,
2678 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2679 if (ret && (ret != -ENOENT))
2682 ret = ice_hash_moveout(pf,
2683 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2684 if (ret && (ret != -ENOENT))
2687 ret = ice_hash_moveout(pf,
2688 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2689 if (ret && (ret != -ENOENT))
2693 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2694 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2695 ret = ice_hash_moveout(pf,
2696 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2697 if (ret && (ret != -ENOENT))
2700 ret = ice_hash_moveout(pf,
2701 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2702 if (ret && (ret != -ENOENT))
2705 ret = ice_hash_moveout(pf,
2706 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2707 if (ret && (ret != -ENOENT))
2718 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2722 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2724 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2726 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2729 return ICE_HASH_GTPU_CTX_MAX;
2732 if (hdr & ICE_FLOW_SEG_HDR_UDP)
2734 else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2737 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2738 return eh_idx * 3 + ip_idx;
2740 return ICE_HASH_GTPU_CTX_MAX;
2744 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2746 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2748 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2749 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2751 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2752 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2759 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2760 u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2764 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2765 ctx->ctx[ctx_idx] = *cfg;
2768 case ICE_HASH_GTPU_CTX_EH_IP:
2770 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2771 ret = ice_hash_moveback(pf,
2772 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2773 if (ret && (ret != -ENOENT))
2776 ret = ice_hash_moveback(pf,
2777 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2778 if (ret && (ret != -ENOENT))
2781 ret = ice_hash_moveback(pf,
2782 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2783 if (ret && (ret != -ENOENT))
2786 ret = ice_hash_moveback(pf,
2787 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2788 if (ret && (ret != -ENOENT))
2792 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2793 ret = ice_hash_moveback(pf,
2794 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2795 if (ret && (ret != -ENOENT))
2798 ret = ice_hash_moveback(pf,
2799 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2800 if (ret && (ret != -ENOENT))
2803 ret = ice_hash_moveback(pf,
2804 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2805 if (ret && (ret != -ENOENT))
2808 ret = ice_hash_moveback(pf,
2809 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2810 if (ret && (ret != -ENOENT))
2814 case ICE_HASH_GTPU_CTX_UP_IP:
2815 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2816 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2817 case ICE_HASH_GTPU_CTX_DW_IP:
2818 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2819 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2820 ret = ice_hash_moveback(pf,
2821 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2822 if (ret && (ret != -ENOENT))
2825 ret = ice_hash_moveback(pf,
2826 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2827 if (ret && (ret != -ENOENT))
2830 ret = ice_hash_moveback(pf,
2831 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2832 if (ret && (ret != -ENOENT))
2844 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2846 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2848 if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2849 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2851 else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2852 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2859 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2861 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2863 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2866 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2867 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2868 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2869 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2873 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2874 struct ice_rss_hash_cfg *cfg)
2876 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2879 ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2880 if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2881 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2883 ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2889 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2890 struct ice_rss_hash_cfg *cfg)
2892 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2895 ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2897 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2899 ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2901 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2903 ret = ice_add_rss_cfg_post(pf, cfg);
2905 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2911 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2913 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2914 struct ice_vsi *vsi = pf->main_vsi;
2915 struct ice_rss_hash_cfg cfg;
2918 #define ICE_RSS_HF_ALL ( \
2921 ETH_RSS_NONFRAG_IPV4_UDP | \
2922 ETH_RSS_NONFRAG_IPV6_UDP | \
2923 ETH_RSS_NONFRAG_IPV4_TCP | \
2924 ETH_RSS_NONFRAG_IPV6_TCP | \
2925 ETH_RSS_NONFRAG_IPV4_SCTP | \
2926 ETH_RSS_NONFRAG_IPV6_SCTP)
2928 ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2930 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2934 cfg.hdr_type = ICE_RSS_ANY_HEADERS;
2935 /* Configure RSS for IPv4 with src/dst addr as input set */
2936 if (rss_hf & ETH_RSS_IPV4) {
2937 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2938 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2939 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2941 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2945 /* Configure RSS for IPv6 with src/dst addr as input set */
2946 if (rss_hf & ETH_RSS_IPV6) {
2947 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2948 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2949 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2951 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2955 /* Configure RSS for udp4 with src/dst addr and port as input set */
2956 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2957 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2958 ICE_FLOW_SEG_HDR_IPV_OTHER;
2959 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2960 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2962 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2966 /* Configure RSS for udp6 with src/dst addr and port as input set */
2967 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2968 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
2969 ICE_FLOW_SEG_HDR_IPV_OTHER;
2970 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2971 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2973 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2977 /* Configure RSS for tcp4 with src/dst addr and port as input set */
2978 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2979 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
2980 ICE_FLOW_SEG_HDR_IPV_OTHER;
2981 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2982 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2984 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2988 /* Configure RSS for tcp6 with src/dst addr and port as input set */
2989 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2990 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
2991 ICE_FLOW_SEG_HDR_IPV_OTHER;
2992 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2993 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2995 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2999 /* Configure RSS for sctp4 with src/dst addr and port as input set */
3000 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
3001 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
3002 ICE_FLOW_SEG_HDR_IPV_OTHER;
3003 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
3004 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3006 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
3010 /* Configure RSS for sctp6 with src/dst addr and port as input set */
3011 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
3012 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
3013 ICE_FLOW_SEG_HDR_IPV_OTHER;
3014 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
3015 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3017 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
3021 if (rss_hf & ETH_RSS_IPV4) {
3022 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV4 |
3023 ICE_FLOW_SEG_HDR_IPV_OTHER;
3024 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
3025 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3027 PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
3030 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV4 |
3031 ICE_FLOW_SEG_HDR_IPV_OTHER;
3032 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3034 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
3037 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
3038 ICE_FLOW_SEG_HDR_IPV_OTHER;
3039 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3041 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
3045 if (rss_hf & ETH_RSS_IPV6) {
3046 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV6 |
3047 ICE_FLOW_SEG_HDR_IPV_OTHER;
3048 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
3049 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3051 PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
3054 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV6 |
3055 ICE_FLOW_SEG_HDR_IPV_OTHER;
3056 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3058 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
3061 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
3062 ICE_FLOW_SEG_HDR_IPV_OTHER;
3063 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3065 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
3069 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
3070 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
3071 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3072 cfg.hash_flds = ICE_HASH_UDP_IPV4;
3073 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3075 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
3078 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
3079 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3080 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3082 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
3085 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3086 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3087 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3089 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
3093 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
3094 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
3095 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3096 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3097 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3099 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
3102 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
3103 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3104 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3106 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
3109 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3110 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3111 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3113 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3117 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3118 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3119 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3120 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3121 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3123 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
3126 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3127 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3128 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3130 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
3133 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3134 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3135 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3137 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3141 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3142 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3143 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3144 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3145 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3147 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
3150 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3151 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3152 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3154 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
3157 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3158 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3159 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3161 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3165 pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3168 static int ice_init_rss(struct ice_pf *pf)
3170 struct ice_hw *hw = ICE_PF_TO_HW(pf);
3171 struct ice_vsi *vsi = pf->main_vsi;
3172 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3173 struct ice_aq_get_set_rss_lut_params lut_params;
3174 struct rte_eth_rss_conf *rss_conf;
3175 struct ice_aqc_get_set_rss_keys key;
3178 bool is_safe_mode = pf->adapter->is_safe_mode;
3181 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3182 nb_q = dev->data->nb_rx_queues;
3183 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3184 vsi->rss_lut_size = pf->hash_lut_size;
3187 PMD_DRV_LOG(WARNING,
3188 "RSS is not supported as rx queues number is zero\n");
3193 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3197 if (!vsi->rss_key) {
3198 vsi->rss_key = rte_zmalloc(NULL,
3199 vsi->rss_key_size, 0);
3200 if (vsi->rss_key == NULL) {
3201 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3205 if (!vsi->rss_lut) {
3206 vsi->rss_lut = rte_zmalloc(NULL,
3207 vsi->rss_lut_size, 0);
3208 if (vsi->rss_lut == NULL) {
3209 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3210 rte_free(vsi->rss_key);
3211 vsi->rss_key = NULL;
3215 /* configure RSS key */
3216 if (!rss_conf->rss_key) {
3217 /* Calculate the default hash key */
3218 for (i = 0; i <= vsi->rss_key_size; i++)
3219 vsi->rss_key[i] = (uint8_t)rte_rand();
3221 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3222 RTE_MIN(rss_conf->rss_key_len,
3223 vsi->rss_key_size));
3225 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3226 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3230 /* init RSS LUT table */
3231 for (i = 0; i < vsi->rss_lut_size; i++)
3232 vsi->rss_lut[i] = i % nb_q;
3234 lut_params.vsi_handle = vsi->idx;
3235 lut_params.lut_size = vsi->rss_lut_size;
3236 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3237 lut_params.lut = vsi->rss_lut;
3238 lut_params.global_lut_id = 0;
3239 ret = ice_aq_set_rss_lut(hw, &lut_params);
3243 /* Enable registers for symmetric_toeplitz function. */
3244 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3245 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3246 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3247 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3249 /* RSS hash configuration */
3250 ice_rss_hash_set(pf, rss_conf->rss_hf);
3254 rte_free(vsi->rss_key);
3255 vsi->rss_key = NULL;
3256 rte_free(vsi->rss_lut);
3257 vsi->rss_lut = NULL;
3262 ice_dev_configure(struct rte_eth_dev *dev)
3264 struct ice_adapter *ad =
3265 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3266 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3269 /* Initialize to TRUE. If any of Rx queues doesn't meet the
3270 * bulk allocation or vector Rx preconditions we will reset it.
3272 ad->rx_bulk_alloc_allowed = true;
3273 ad->tx_simple_allowed = true;
3275 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3276 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3278 if (dev->data->nb_rx_queues) {
3279 ret = ice_init_rss(pf);
3281 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3290 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3291 int base_queue, int nb_queue)
3293 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3294 uint32_t val, val_tx;
3297 for (i = 0; i < nb_queue; i++) {
3299 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3300 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3301 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3302 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3304 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3305 base_queue + i, msix_vect);
3306 /* set ITR0 value */
3307 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3308 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3309 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3314 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3316 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3317 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3318 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3319 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3320 uint16_t msix_vect = vsi->msix_intr;
3321 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3322 uint16_t queue_idx = 0;
3326 /* clear Rx/Tx queue interrupt */
3327 for (i = 0; i < vsi->nb_used_qps; i++) {
3328 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3329 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3332 /* PF bind interrupt */
3333 if (rte_intr_dp_is_en(intr_handle)) {
3338 for (i = 0; i < vsi->nb_used_qps; i++) {
3340 if (!rte_intr_allow_others(intr_handle))
3341 msix_vect = ICE_MISC_VEC_ID;
3343 /* uio mapping all queue to one msix_vect */
3344 __vsi_queues_bind_intr(vsi, msix_vect,
3345 vsi->base_queue + i,
3346 vsi->nb_used_qps - i);
3348 for (; !!record && i < vsi->nb_used_qps; i++)
3349 intr_handle->intr_vec[queue_idx + i] =
3354 /* vfio 1:1 queue/msix_vect mapping */
3355 __vsi_queues_bind_intr(vsi, msix_vect,
3356 vsi->base_queue + i, 1);
3359 intr_handle->intr_vec[queue_idx + i] = msix_vect;
3367 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3369 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3370 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3371 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3372 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3373 uint16_t msix_intr, i;
3375 if (rte_intr_allow_others(intr_handle))
3376 for (i = 0; i < vsi->nb_used_qps; i++) {
3377 msix_intr = vsi->msix_intr + i;
3378 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3379 GLINT_DYN_CTL_INTENA_M |
3380 GLINT_DYN_CTL_CLEARPBA_M |
3381 GLINT_DYN_CTL_ITR_INDX_M |
3382 GLINT_DYN_CTL_WB_ON_ITR_M);
3385 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3386 GLINT_DYN_CTL_INTENA_M |
3387 GLINT_DYN_CTL_CLEARPBA_M |
3388 GLINT_DYN_CTL_ITR_INDX_M |
3389 GLINT_DYN_CTL_WB_ON_ITR_M);
3393 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3395 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3396 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3397 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3398 struct ice_vsi *vsi = pf->main_vsi;
3399 uint32_t intr_vector = 0;
3401 rte_intr_disable(intr_handle);
3403 /* check and configure queue intr-vector mapping */
3404 if ((rte_intr_cap_multiple(intr_handle) ||
3405 !RTE_ETH_DEV_SRIOV(dev).active) &&
3406 dev->data->dev_conf.intr_conf.rxq != 0) {
3407 intr_vector = dev->data->nb_rx_queues;
3408 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3409 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3410 ICE_MAX_INTR_QUEUE_NUM);
3413 if (rte_intr_efd_enable(intr_handle, intr_vector))
3417 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3418 intr_handle->intr_vec =
3419 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3421 if (!intr_handle->intr_vec) {
3423 "Failed to allocate %d rx_queues intr_vec",
3424 dev->data->nb_rx_queues);
3429 /* Map queues with MSIX interrupt */
3430 vsi->nb_used_qps = dev->data->nb_rx_queues;
3431 ice_vsi_queues_bind_intr(vsi);
3433 /* Enable interrupts for all the queues */
3434 ice_vsi_enable_queues_intr(vsi);
3436 rte_intr_enable(intr_handle);
3442 ice_get_init_link_status(struct rte_eth_dev *dev)
3444 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3446 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3447 struct ice_link_status link_status;
3450 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3451 &link_status, NULL);
3452 if (ret != ICE_SUCCESS) {
3453 PMD_DRV_LOG(ERR, "Failed to get link info");
3454 pf->init_link_up = false;
3458 if (link_status.link_info & ICE_AQ_LINK_UP)
3459 pf->init_link_up = true;
3463 ice_dev_start(struct rte_eth_dev *dev)
3465 struct rte_eth_dev_data *data = dev->data;
3466 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3467 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3468 struct ice_vsi *vsi = pf->main_vsi;
3469 uint16_t nb_rxq = 0;
3471 uint16_t max_frame_size;
3474 /* program Tx queues' context in hardware */
3475 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3476 ret = ice_tx_queue_start(dev, nb_txq);
3478 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3483 /* program Rx queues' context in hardware*/
3484 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3485 ret = ice_rx_queue_start(dev, nb_rxq);
3487 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3492 ice_set_rx_function(dev);
3493 ice_set_tx_function(dev);
3495 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3496 ETH_VLAN_EXTEND_MASK;
3497 ret = ice_vlan_offload_set(dev, mask);
3499 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3503 /* enable Rx interrput and mapping Rx queue to interrupt vector */
3504 if (ice_rxq_intr_setup(dev))
3507 /* Enable receiving broadcast packets and transmitting packets */
3508 ret = ice_set_vsi_promisc(hw, vsi->idx,
3509 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3510 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3512 if (ret != ICE_SUCCESS)
3513 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3515 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3516 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3517 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3518 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3519 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3520 ICE_AQ_LINK_EVENT_AN_COMPLETED |
3521 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3523 if (ret != ICE_SUCCESS)
3524 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3526 ice_get_init_link_status(dev);
3528 ice_dev_set_link_up(dev);
3530 /* Call get_link_info aq commond to enable/disable LSE */
3531 ice_link_update(dev, 0);
3533 pf->adapter_stopped = false;
3535 /* Set the max frame size to default value*/
3536 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3537 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3540 /* Set the max frame size to HW*/
3541 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3545 /* stop the started queues if failed to start all queues */
3547 for (i = 0; i < nb_rxq; i++)
3548 ice_rx_queue_stop(dev, i);
3550 for (i = 0; i < nb_txq; i++)
3551 ice_tx_queue_stop(dev, i);
3557 ice_dev_reset(struct rte_eth_dev *dev)
3561 if (dev->data->sriov.active)
3564 ret = ice_dev_uninit(dev);
3566 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3570 ret = ice_dev_init(dev);
3572 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3580 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3582 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3583 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3584 struct ice_vsi *vsi = pf->main_vsi;
3585 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3586 bool is_safe_mode = pf->adapter->is_safe_mode;
3590 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3591 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3592 dev_info->max_rx_queues = vsi->nb_qps;
3593 dev_info->max_tx_queues = vsi->nb_qps;
3594 dev_info->max_mac_addrs = vsi->max_macaddrs;
3595 dev_info->max_vfs = pci_dev->max_vfs;
3596 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3597 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3599 dev_info->rx_offload_capa =
3600 DEV_RX_OFFLOAD_VLAN_STRIP |
3601 DEV_RX_OFFLOAD_JUMBO_FRAME |
3602 DEV_RX_OFFLOAD_KEEP_CRC |
3603 DEV_RX_OFFLOAD_SCATTER |
3604 DEV_RX_OFFLOAD_VLAN_FILTER;
3605 dev_info->tx_offload_capa =
3606 DEV_TX_OFFLOAD_VLAN_INSERT |
3607 DEV_TX_OFFLOAD_TCP_TSO |
3608 DEV_TX_OFFLOAD_MULTI_SEGS |
3609 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3610 dev_info->flow_type_rss_offloads = 0;
3612 if (!is_safe_mode) {
3613 dev_info->rx_offload_capa |=
3614 DEV_RX_OFFLOAD_IPV4_CKSUM |
3615 DEV_RX_OFFLOAD_UDP_CKSUM |
3616 DEV_RX_OFFLOAD_TCP_CKSUM |
3617 DEV_RX_OFFLOAD_QINQ_STRIP |
3618 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3619 DEV_RX_OFFLOAD_VLAN_EXTEND |
3620 DEV_RX_OFFLOAD_RSS_HASH;
3621 dev_info->tx_offload_capa |=
3622 DEV_TX_OFFLOAD_QINQ_INSERT |
3623 DEV_TX_OFFLOAD_IPV4_CKSUM |
3624 DEV_TX_OFFLOAD_UDP_CKSUM |
3625 DEV_TX_OFFLOAD_TCP_CKSUM |
3626 DEV_TX_OFFLOAD_SCTP_CKSUM |
3627 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3628 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3629 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3632 dev_info->rx_queue_offload_capa = 0;
3633 dev_info->tx_queue_offload_capa = 0;
3635 dev_info->reta_size = pf->hash_lut_size;
3636 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3638 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3640 .pthresh = ICE_DEFAULT_RX_PTHRESH,
3641 .hthresh = ICE_DEFAULT_RX_HTHRESH,
3642 .wthresh = ICE_DEFAULT_RX_WTHRESH,
3644 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3649 dev_info->default_txconf = (struct rte_eth_txconf) {
3651 .pthresh = ICE_DEFAULT_TX_PTHRESH,
3652 .hthresh = ICE_DEFAULT_TX_HTHRESH,
3653 .wthresh = ICE_DEFAULT_TX_WTHRESH,
3655 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3656 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3660 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3661 .nb_max = ICE_MAX_RING_DESC,
3662 .nb_min = ICE_MIN_RING_DESC,
3663 .nb_align = ICE_ALIGN_RING_DESC,
3666 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3667 .nb_max = ICE_MAX_RING_DESC,
3668 .nb_min = ICE_MIN_RING_DESC,
3669 .nb_align = ICE_ALIGN_RING_DESC,
3672 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3673 ETH_LINK_SPEED_100M |
3675 ETH_LINK_SPEED_2_5G |
3677 ETH_LINK_SPEED_10G |
3678 ETH_LINK_SPEED_20G |
3681 phy_type_low = hw->port_info->phy.phy_type_low;
3682 phy_type_high = hw->port_info->phy.phy_type_high;
3684 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3685 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3687 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3688 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3689 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3691 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3692 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3694 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3695 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3696 dev_info->default_rxportconf.nb_queues = 1;
3697 dev_info->default_txportconf.nb_queues = 1;
3698 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3699 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3705 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3706 struct rte_eth_link *link)
3708 struct rte_eth_link *dst = link;
3709 struct rte_eth_link *src = &dev->data->dev_link;
3711 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3712 *(uint64_t *)src) == 0)
3719 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3720 struct rte_eth_link *link)
3722 struct rte_eth_link *dst = &dev->data->dev_link;
3723 struct rte_eth_link *src = link;
3725 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3726 *(uint64_t *)src) == 0)
3733 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3735 #define CHECK_INTERVAL 100 /* 100ms */
3736 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3737 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3738 struct ice_link_status link_status;
3739 struct rte_eth_link link, old;
3741 unsigned int rep_cnt = MAX_REPEAT_TIME;
3742 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3744 memset(&link, 0, sizeof(link));
3745 memset(&old, 0, sizeof(old));
3746 memset(&link_status, 0, sizeof(link_status));
3747 ice_atomic_read_link_status(dev, &old);
3750 /* Get link status information from hardware */
3751 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3752 &link_status, NULL);
3753 if (status != ICE_SUCCESS) {
3754 link.link_speed = ETH_SPEED_NUM_100M;
3755 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3756 PMD_DRV_LOG(ERR, "Failed to get link info");
3760 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3761 if (!wait_to_complete || link.link_status)
3764 rte_delay_ms(CHECK_INTERVAL);
3765 } while (--rep_cnt);
3767 if (!link.link_status)
3770 /* Full-duplex operation at all supported speeds */
3771 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3773 /* Parse the link status */
3774 switch (link_status.link_speed) {
3775 case ICE_AQ_LINK_SPEED_10MB:
3776 link.link_speed = ETH_SPEED_NUM_10M;
3778 case ICE_AQ_LINK_SPEED_100MB:
3779 link.link_speed = ETH_SPEED_NUM_100M;
3781 case ICE_AQ_LINK_SPEED_1000MB:
3782 link.link_speed = ETH_SPEED_NUM_1G;
3784 case ICE_AQ_LINK_SPEED_2500MB:
3785 link.link_speed = ETH_SPEED_NUM_2_5G;
3787 case ICE_AQ_LINK_SPEED_5GB:
3788 link.link_speed = ETH_SPEED_NUM_5G;
3790 case ICE_AQ_LINK_SPEED_10GB:
3791 link.link_speed = ETH_SPEED_NUM_10G;
3793 case ICE_AQ_LINK_SPEED_20GB:
3794 link.link_speed = ETH_SPEED_NUM_20G;
3796 case ICE_AQ_LINK_SPEED_25GB:
3797 link.link_speed = ETH_SPEED_NUM_25G;
3799 case ICE_AQ_LINK_SPEED_40GB:
3800 link.link_speed = ETH_SPEED_NUM_40G;
3802 case ICE_AQ_LINK_SPEED_50GB:
3803 link.link_speed = ETH_SPEED_NUM_50G;
3805 case ICE_AQ_LINK_SPEED_100GB:
3806 link.link_speed = ETH_SPEED_NUM_100G;
3808 case ICE_AQ_LINK_SPEED_UNKNOWN:
3809 PMD_DRV_LOG(ERR, "Unknown link speed");
3810 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3813 PMD_DRV_LOG(ERR, "None link speed");
3814 link.link_speed = ETH_SPEED_NUM_NONE;
3818 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3819 ETH_LINK_SPEED_FIXED);
3822 ice_atomic_write_link_status(dev, &link);
3823 if (link.link_status == old.link_status)
3829 /* Force the physical link state by getting the current PHY capabilities from
3830 * hardware and setting the PHY config based on the determined capabilities. If
3831 * link changes, link event will be triggered because both the Enable Automatic
3832 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3834 static enum ice_status
3835 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3837 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3838 struct ice_aqc_get_phy_caps_data *pcaps;
3839 struct ice_port_info *pi;
3840 enum ice_status status;
3842 if (!hw || !hw->port_info)
3843 return ICE_ERR_PARAM;
3847 pcaps = (struct ice_aqc_get_phy_caps_data *)
3848 ice_malloc(hw, sizeof(*pcaps));
3850 return ICE_ERR_NO_MEMORY;
3852 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3857 /* No change in link */
3858 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3859 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3862 cfg.phy_type_low = pcaps->phy_type_low;
3863 cfg.phy_type_high = pcaps->phy_type_high;
3864 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3865 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3866 cfg.eee_cap = pcaps->eee_cap;
3867 cfg.eeer_value = pcaps->eeer_value;
3868 cfg.link_fec_opt = pcaps->link_fec_options;
3870 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3872 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3874 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3877 ice_free(hw, pcaps);
3882 ice_dev_set_link_up(struct rte_eth_dev *dev)
3884 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3886 return ice_force_phys_link_state(hw, true);
3890 ice_dev_set_link_down(struct rte_eth_dev *dev)
3892 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3894 return ice_force_phys_link_state(hw, false);
3898 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3900 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3901 struct rte_eth_dev_data *dev_data = pf->dev_data;
3902 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3904 /* check if mtu is within the allowed range */
3905 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3908 /* mtu setting is forbidden if port is start */
3909 if (dev_data->dev_started) {
3911 "port %d must be stopped before configuration",
3916 if (frame_size > ICE_ETH_MAX_LEN)
3917 dev_data->dev_conf.rxmode.offloads |=
3918 DEV_RX_OFFLOAD_JUMBO_FRAME;
3920 dev_data->dev_conf.rxmode.offloads &=
3921 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3923 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3928 static int ice_macaddr_set(struct rte_eth_dev *dev,
3929 struct rte_ether_addr *mac_addr)
3931 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3932 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3933 struct ice_vsi *vsi = pf->main_vsi;
3934 struct ice_mac_filter *f;
3938 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3939 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3943 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3944 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3949 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3953 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3954 if (ret != ICE_SUCCESS) {
3955 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3958 ret = ice_add_mac_filter(vsi, mac_addr);
3959 if (ret != ICE_SUCCESS) {
3960 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3963 rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3965 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3966 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3967 if (ret != ICE_SUCCESS)
3968 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3973 /* Add a MAC address, and update filters */
3975 ice_macaddr_add(struct rte_eth_dev *dev,
3976 struct rte_ether_addr *mac_addr,
3977 __rte_unused uint32_t index,
3978 __rte_unused uint32_t pool)
3980 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3981 struct ice_vsi *vsi = pf->main_vsi;
3984 ret = ice_add_mac_filter(vsi, mac_addr);
3985 if (ret != ICE_SUCCESS) {
3986 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3993 /* Remove a MAC address, and update filters */
3995 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3997 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3998 struct ice_vsi *vsi = pf->main_vsi;
3999 struct rte_eth_dev_data *data = dev->data;
4000 struct rte_ether_addr *macaddr;
4003 macaddr = &data->mac_addrs[index];
4004 ret = ice_remove_mac_filter(vsi, macaddr);
4006 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
4012 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4014 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4015 struct ice_vsi *vsi = pf->main_vsi;
4018 PMD_INIT_FUNC_TRACE();
4021 ret = ice_add_vlan_filter(vsi, vlan_id);
4023 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
4027 ret = ice_remove_vlan_filter(vsi, vlan_id);
4029 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
4037 /* Configure vlan filter on or off */
4039 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4041 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4042 struct ice_vsi_ctx ctxt;
4043 uint8_t sec_flags, sw_flags2;
4046 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
4047 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
4048 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4051 vsi->info.sec_flags |= sec_flags;
4052 vsi->info.sw_flags2 |= sw_flags2;
4054 vsi->info.sec_flags &= ~sec_flags;
4055 vsi->info.sw_flags2 &= ~sw_flags2;
4057 vsi->info.sw_id = hw->port_info->sw_id;
4058 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4059 ctxt.info.valid_sections =
4060 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4061 ICE_AQ_VSI_PROP_SECURITY_VALID);
4062 ctxt.vsi_num = vsi->vsi_id;
4064 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4066 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4067 on ? "enable" : "disable");
4070 vsi->info.valid_sections |=
4071 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4072 ICE_AQ_VSI_PROP_SECURITY_VALID);
4075 /* consist with other drivers, allow untagged packet when vlan filter on */
4077 ret = ice_add_vlan_filter(vsi, 0);
4079 ret = ice_remove_vlan_filter(vsi, 0);
4085 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
4087 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4088 struct ice_vsi_ctx ctxt;
4092 /* Check if it has been already on or off */
4093 if (vsi->info.valid_sections &
4094 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
4096 if ((vsi->info.inner_vlan_flags &
4097 ICE_AQ_VSI_INNER_VLAN_EMODE_M) ==
4098 ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH)
4099 return 0; /* already on */
4101 if ((vsi->info.inner_vlan_flags &
4102 ICE_AQ_VSI_INNER_VLAN_EMODE_M) ==
4103 ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING)
4104 return 0; /* already off */
4109 vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4111 vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4112 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4113 vsi->info.inner_vlan_flags |= vlan_flags;
4114 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4115 ctxt.info.valid_sections =
4116 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4117 ctxt.vsi_num = vsi->vsi_id;
4118 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4120 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4121 on ? "enable" : "disable");
4125 vsi->info.valid_sections |=
4126 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4132 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4134 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4135 struct ice_vsi *vsi = pf->main_vsi;
4136 struct rte_eth_rxmode *rxmode;
4138 rxmode = &dev->data->dev_conf.rxmode;
4139 if (mask & ETH_VLAN_FILTER_MASK) {
4140 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4141 ice_vsi_config_vlan_filter(vsi, true);
4143 ice_vsi_config_vlan_filter(vsi, false);
4146 if (mask & ETH_VLAN_STRIP_MASK) {
4147 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4148 ice_vsi_config_vlan_stripping(vsi, true);
4150 ice_vsi_config_vlan_stripping(vsi, false);
4153 if (mask & ETH_VLAN_EXTEND_MASK) {
4154 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
4155 ice_vsi_config_double_vlan(vsi, true);
4157 ice_vsi_config_double_vlan(vsi, false);
4164 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4166 struct ice_aq_get_set_rss_lut_params lut_params;
4167 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4168 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4174 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4175 lut_params.vsi_handle = vsi->idx;
4176 lut_params.lut_size = lut_size;
4177 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4178 lut_params.lut = lut;
4179 lut_params.global_lut_id = 0;
4180 ret = ice_aq_get_rss_lut(hw, &lut_params);
4182 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4186 uint64_t *lut_dw = (uint64_t *)lut;
4187 uint16_t i, lut_size_dw = lut_size / 4;
4189 for (i = 0; i < lut_size_dw; i++)
4190 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4197 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4199 struct ice_aq_get_set_rss_lut_params lut_params;
4207 pf = ICE_VSI_TO_PF(vsi);
4208 hw = ICE_VSI_TO_HW(vsi);
4210 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4211 lut_params.vsi_handle = vsi->idx;
4212 lut_params.lut_size = lut_size;
4213 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4214 lut_params.lut = lut;
4215 lut_params.global_lut_id = 0;
4216 ret = ice_aq_set_rss_lut(hw, &lut_params);
4218 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4222 uint64_t *lut_dw = (uint64_t *)lut;
4223 uint16_t i, lut_size_dw = lut_size / 4;
4225 for (i = 0; i < lut_size_dw; i++)
4226 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4235 ice_rss_reta_update(struct rte_eth_dev *dev,
4236 struct rte_eth_rss_reta_entry64 *reta_conf,
4239 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4240 uint16_t i, lut_size = pf->hash_lut_size;
4241 uint16_t idx, shift;
4245 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4246 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4247 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4249 "The size of hash lookup table configured (%d)"
4250 "doesn't match the number hardware can "
4251 "supported (128, 512, 2048)",
4256 /* It MUST use the current LUT size to get the RSS lookup table,
4257 * otherwise if will fail with -100 error code.
4259 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
4261 PMD_DRV_LOG(ERR, "No memory can be allocated");
4264 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4268 for (i = 0; i < reta_size; i++) {
4269 idx = i / RTE_RETA_GROUP_SIZE;
4270 shift = i % RTE_RETA_GROUP_SIZE;
4271 if (reta_conf[idx].mask & (1ULL << shift))
4272 lut[i] = reta_conf[idx].reta[shift];
4274 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4275 if (ret == 0 && lut_size != reta_size) {
4277 "The size of hash lookup table is changed from (%d) to (%d)",
4278 lut_size, reta_size);
4279 pf->hash_lut_size = reta_size;
4289 ice_rss_reta_query(struct rte_eth_dev *dev,
4290 struct rte_eth_rss_reta_entry64 *reta_conf,
4293 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4294 uint16_t i, lut_size = pf->hash_lut_size;
4295 uint16_t idx, shift;
4299 if (reta_size != lut_size) {
4301 "The size of hash lookup table configured (%d)"
4302 "doesn't match the number hardware can "
4304 reta_size, lut_size);
4308 lut = rte_zmalloc(NULL, reta_size, 0);
4310 PMD_DRV_LOG(ERR, "No memory can be allocated");
4314 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4318 for (i = 0; i < reta_size; i++) {
4319 idx = i / RTE_RETA_GROUP_SIZE;
4320 shift = i % RTE_RETA_GROUP_SIZE;
4321 if (reta_conf[idx].mask & (1ULL << shift))
4322 reta_conf[idx].reta[shift] = lut[i];
4332 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4334 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4337 if (!key || key_len == 0) {
4338 PMD_DRV_LOG(DEBUG, "No key to be configured");
4340 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4342 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4346 struct ice_aqc_get_set_rss_keys *key_dw =
4347 (struct ice_aqc_get_set_rss_keys *)key;
4349 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4351 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4359 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4361 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4364 if (!key || !key_len)
4367 ret = ice_aq_get_rss_key
4369 (struct ice_aqc_get_set_rss_keys *)key);
4371 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4374 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4380 ice_rss_hash_update(struct rte_eth_dev *dev,
4381 struct rte_eth_rss_conf *rss_conf)
4383 enum ice_status status = ICE_SUCCESS;
4384 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4385 struct ice_vsi *vsi = pf->main_vsi;
4388 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4392 if (rss_conf->rss_hf == 0)
4395 /* RSS hash configuration */
4396 ice_rss_hash_set(pf, rss_conf->rss_hf);
4402 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4403 struct rte_eth_rss_conf *rss_conf)
4405 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4406 struct ice_vsi *vsi = pf->main_vsi;
4408 ice_get_rss_key(vsi, rss_conf->rss_key,
4409 &rss_conf->rss_key_len);
4411 rss_conf->rss_hf = pf->rss_hf;
4416 ice_promisc_enable(struct rte_eth_dev *dev)
4418 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4419 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4420 struct ice_vsi *vsi = pf->main_vsi;
4421 enum ice_status status;
4425 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4426 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4428 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4430 case ICE_ERR_ALREADY_EXISTS:
4431 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4435 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4443 ice_promisc_disable(struct rte_eth_dev *dev)
4445 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4446 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447 struct ice_vsi *vsi = pf->main_vsi;
4448 enum ice_status status;
4452 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4453 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4455 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4456 if (status != ICE_SUCCESS) {
4457 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4465 ice_allmulti_enable(struct rte_eth_dev *dev)
4467 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4468 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4469 struct ice_vsi *vsi = pf->main_vsi;
4470 enum ice_status status;
4474 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4476 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4479 case ICE_ERR_ALREADY_EXISTS:
4480 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4484 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4492 ice_allmulti_disable(struct rte_eth_dev *dev)
4494 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4495 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4496 struct ice_vsi *vsi = pf->main_vsi;
4497 enum ice_status status;
4501 if (dev->data->promiscuous == 1)
4502 return 0; /* must remain in all_multicast mode */
4504 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4506 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4507 if (status != ICE_SUCCESS) {
4508 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4515 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4518 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4519 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4520 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524 msix_intr = intr_handle->intr_vec[queue_id];
4526 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4527 GLINT_DYN_CTL_ITR_INDX_M;
4528 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4530 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4531 rte_intr_ack(&pci_dev->intr_handle);
4536 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4539 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4540 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4541 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4544 msix_intr = intr_handle->intr_vec[queue_id];
4546 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4552 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4554 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4559 ver = hw->flash.orom.major;
4560 patch = hw->flash.orom.patch;
4561 build = hw->flash.orom.build;
4563 ret = snprintf(fw_version, fw_size,
4564 "%x.%02x 0x%08x %d.%d.%d",
4565 hw->flash.nvm.major,
4566 hw->flash.nvm.minor,
4567 hw->flash.nvm.eetrack,
4570 /* add the size of '\0' */
4572 if (fw_size < (u32)ret)
4579 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4582 struct ice_vsi_ctx ctxt;
4583 uint8_t vlan_flags = 0;
4586 if (!vsi || !info) {
4587 PMD_DRV_LOG(ERR, "invalid parameters");
4592 vsi->info.port_based_inner_vlan = info->config.pvid;
4594 * If insert pvid is enabled, only tagged pkts are
4595 * allowed to be sent out.
4597 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4598 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4600 vsi->info.port_based_inner_vlan = 0;
4601 if (info->config.reject.tagged == 0)
4602 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4604 if (info->config.reject.untagged == 0)
4605 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4607 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4608 ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4609 vsi->info.inner_vlan_flags |= vlan_flags;
4610 memset(&ctxt, 0, sizeof(ctxt));
4611 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4612 ctxt.info.valid_sections =
4613 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4614 ctxt.vsi_num = vsi->vsi_id;
4616 hw = ICE_VSI_TO_HW(vsi);
4617 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4618 if (ret != ICE_SUCCESS) {
4620 "update VSI for VLAN insert failed, err %d",
4625 vsi->info.valid_sections |=
4626 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4632 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4634 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4635 struct ice_vsi *vsi = pf->main_vsi;
4636 struct rte_eth_dev_data *data = pf->dev_data;
4637 struct ice_vsi_vlan_pvid_info info;
4640 memset(&info, 0, sizeof(info));
4643 info.config.pvid = pvid;
4645 info.config.reject.tagged =
4646 data->dev_conf.txmode.hw_vlan_reject_tagged;
4647 info.config.reject.untagged =
4648 data->dev_conf.txmode.hw_vlan_reject_untagged;
4651 ret = ice_vsi_vlan_pvid_set(vsi, &info);
4653 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4661 ice_get_eeprom_length(struct rte_eth_dev *dev)
4663 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4665 return hw->flash.flash_size;
4669 ice_get_eeprom(struct rte_eth_dev *dev,
4670 struct rte_dev_eeprom_info *eeprom)
4672 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4673 enum ice_status status = ICE_SUCCESS;
4674 uint8_t *data = eeprom->data;
4676 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4678 status = ice_acquire_nvm(hw, ICE_RES_READ);
4680 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4684 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4687 ice_release_nvm(hw);
4690 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4698 ice_stat_update_32(struct ice_hw *hw,
4706 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4710 if (new_data >= *offset)
4711 *stat = (uint64_t)(new_data - *offset);
4713 *stat = (uint64_t)((new_data +
4714 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4719 ice_stat_update_40(struct ice_hw *hw,
4728 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4729 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4735 if (new_data >= *offset)
4736 *stat = new_data - *offset;
4738 *stat = (uint64_t)((new_data +
4739 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4742 *stat &= ICE_40_BIT_MASK;
4745 /* Get all the statistics of a VSI */
4747 ice_update_vsi_stats(struct ice_vsi *vsi)
4749 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4750 struct ice_eth_stats *nes = &vsi->eth_stats;
4751 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4752 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4754 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4755 vsi->offset_loaded, &oes->rx_bytes,
4757 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4758 vsi->offset_loaded, &oes->rx_unicast,
4760 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4761 vsi->offset_loaded, &oes->rx_multicast,
4762 &nes->rx_multicast);
4763 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4764 vsi->offset_loaded, &oes->rx_broadcast,
4765 &nes->rx_broadcast);
4766 /* enlarge the limitation when rx_bytes overflowed */
4767 if (vsi->offset_loaded) {
4768 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4769 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4770 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4772 vsi->old_rx_bytes = nes->rx_bytes;
4773 /* exclude CRC bytes */
4774 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4775 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4777 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4778 &oes->rx_discards, &nes->rx_discards);
4779 /* GLV_REPC not supported */
4780 /* GLV_RMPC not supported */
4781 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4782 &oes->rx_unknown_protocol,
4783 &nes->rx_unknown_protocol);
4784 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4785 vsi->offset_loaded, &oes->tx_bytes,
4787 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4788 vsi->offset_loaded, &oes->tx_unicast,
4790 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4791 vsi->offset_loaded, &oes->tx_multicast,
4792 &nes->tx_multicast);
4793 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4794 vsi->offset_loaded, &oes->tx_broadcast,
4795 &nes->tx_broadcast);
4796 /* GLV_TDPC not supported */
4797 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4798 &oes->tx_errors, &nes->tx_errors);
4799 /* enlarge the limitation when tx_bytes overflowed */
4800 if (vsi->offset_loaded) {
4801 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4802 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4803 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4805 vsi->old_tx_bytes = nes->tx_bytes;
4806 vsi->offset_loaded = true;
4808 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4810 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4811 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4812 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4813 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4814 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4815 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4816 nes->rx_unknown_protocol);
4817 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4818 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4819 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4820 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4821 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4822 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4823 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4828 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4830 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4831 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4833 /* Get statistics of struct ice_eth_stats */
4834 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4835 GLPRT_GORCL(hw->port_info->lport),
4836 pf->offset_loaded, &os->eth.rx_bytes,
4838 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4839 GLPRT_UPRCL(hw->port_info->lport),
4840 pf->offset_loaded, &os->eth.rx_unicast,
4841 &ns->eth.rx_unicast);
4842 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4843 GLPRT_MPRCL(hw->port_info->lport),
4844 pf->offset_loaded, &os->eth.rx_multicast,
4845 &ns->eth.rx_multicast);
4846 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4847 GLPRT_BPRCL(hw->port_info->lport),
4848 pf->offset_loaded, &os->eth.rx_broadcast,
4849 &ns->eth.rx_broadcast);
4850 ice_stat_update_32(hw, PRTRPB_RDPC,
4851 pf->offset_loaded, &os->eth.rx_discards,
4852 &ns->eth.rx_discards);
4853 /* enlarge the limitation when rx_bytes overflowed */
4854 if (pf->offset_loaded) {
4855 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4856 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4857 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4859 pf->old_rx_bytes = ns->eth.rx_bytes;
4861 /* Workaround: CRC size should not be included in byte statistics,
4862 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4865 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4866 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4868 /* GLPRT_REPC not supported */
4869 /* GLPRT_RMPC not supported */
4870 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4872 &os->eth.rx_unknown_protocol,
4873 &ns->eth.rx_unknown_protocol);
4874 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4875 GLPRT_GOTCL(hw->port_info->lport),
4876 pf->offset_loaded, &os->eth.tx_bytes,
4878 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4879 GLPRT_UPTCL(hw->port_info->lport),
4880 pf->offset_loaded, &os->eth.tx_unicast,
4881 &ns->eth.tx_unicast);
4882 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4883 GLPRT_MPTCL(hw->port_info->lport),
4884 pf->offset_loaded, &os->eth.tx_multicast,
4885 &ns->eth.tx_multicast);
4886 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4887 GLPRT_BPTCL(hw->port_info->lport),
4888 pf->offset_loaded, &os->eth.tx_broadcast,
4889 &ns->eth.tx_broadcast);
4890 /* enlarge the limitation when tx_bytes overflowed */
4891 if (pf->offset_loaded) {
4892 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4893 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4894 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4896 pf->old_tx_bytes = ns->eth.tx_bytes;
4897 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4898 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4900 /* GLPRT_TEPC not supported */
4902 /* additional port specific stats */
4903 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4904 pf->offset_loaded, &os->tx_dropped_link_down,
4905 &ns->tx_dropped_link_down);
4906 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4907 pf->offset_loaded, &os->crc_errors,
4909 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4910 pf->offset_loaded, &os->illegal_bytes,
4911 &ns->illegal_bytes);
4912 /* GLPRT_ERRBC not supported */
4913 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4914 pf->offset_loaded, &os->mac_local_faults,
4915 &ns->mac_local_faults);
4916 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4917 pf->offset_loaded, &os->mac_remote_faults,
4918 &ns->mac_remote_faults);
4920 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4921 pf->offset_loaded, &os->rx_len_errors,
4922 &ns->rx_len_errors);
4924 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4925 pf->offset_loaded, &os->link_xon_rx,
4927 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4928 pf->offset_loaded, &os->link_xoff_rx,
4930 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4931 pf->offset_loaded, &os->link_xon_tx,
4933 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4934 pf->offset_loaded, &os->link_xoff_tx,
4936 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4937 GLPRT_PRC64L(hw->port_info->lport),
4938 pf->offset_loaded, &os->rx_size_64,
4940 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4941 GLPRT_PRC127L(hw->port_info->lport),
4942 pf->offset_loaded, &os->rx_size_127,
4944 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4945 GLPRT_PRC255L(hw->port_info->lport),
4946 pf->offset_loaded, &os->rx_size_255,
4948 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4949 GLPRT_PRC511L(hw->port_info->lport),
4950 pf->offset_loaded, &os->rx_size_511,
4952 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4953 GLPRT_PRC1023L(hw->port_info->lport),
4954 pf->offset_loaded, &os->rx_size_1023,
4956 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4957 GLPRT_PRC1522L(hw->port_info->lport),
4958 pf->offset_loaded, &os->rx_size_1522,
4960 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4961 GLPRT_PRC9522L(hw->port_info->lport),
4962 pf->offset_loaded, &os->rx_size_big,
4964 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4965 pf->offset_loaded, &os->rx_undersize,
4967 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4968 pf->offset_loaded, &os->rx_fragments,
4970 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4971 pf->offset_loaded, &os->rx_oversize,
4973 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4974 pf->offset_loaded, &os->rx_jabber,
4976 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4977 GLPRT_PTC64L(hw->port_info->lport),
4978 pf->offset_loaded, &os->tx_size_64,
4980 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4981 GLPRT_PTC127L(hw->port_info->lport),
4982 pf->offset_loaded, &os->tx_size_127,
4984 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4985 GLPRT_PTC255L(hw->port_info->lport),
4986 pf->offset_loaded, &os->tx_size_255,
4988 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4989 GLPRT_PTC511L(hw->port_info->lport),
4990 pf->offset_loaded, &os->tx_size_511,
4992 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4993 GLPRT_PTC1023L(hw->port_info->lport),
4994 pf->offset_loaded, &os->tx_size_1023,
4996 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4997 GLPRT_PTC1522L(hw->port_info->lport),
4998 pf->offset_loaded, &os->tx_size_1522,
5000 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5001 GLPRT_PTC9522L(hw->port_info->lport),
5002 pf->offset_loaded, &os->tx_size_big,
5005 /* GLPRT_MSPDC not supported */
5006 /* GLPRT_XEC not supported */
5008 pf->offset_loaded = true;
5011 ice_update_vsi_stats(pf->main_vsi);
5014 /* Get all statistics of a port */
5016 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5018 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5019 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5020 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5022 /* call read registers - updates values, now write them to struct */
5023 ice_read_stats_registers(pf, hw);
5025 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5026 pf->main_vsi->eth_stats.rx_multicast +
5027 pf->main_vsi->eth_stats.rx_broadcast -
5028 pf->main_vsi->eth_stats.rx_discards;
5029 stats->opackets = ns->eth.tx_unicast +
5030 ns->eth.tx_multicast +
5031 ns->eth.tx_broadcast;
5032 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
5033 stats->obytes = ns->eth.tx_bytes;
5034 stats->oerrors = ns->eth.tx_errors +
5035 pf->main_vsi->eth_stats.tx_errors;
5038 stats->imissed = ns->eth.rx_discards +
5039 pf->main_vsi->eth_stats.rx_discards;
5040 stats->ierrors = ns->crc_errors +
5042 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5044 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5045 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
5046 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5047 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5048 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5049 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5050 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5051 pf->main_vsi->eth_stats.rx_discards);
5052 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5053 ns->eth.rx_unknown_protocol);
5054 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
5055 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5056 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5057 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5058 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5059 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5060 pf->main_vsi->eth_stats.tx_discards);
5061 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
5063 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
5064 ns->tx_dropped_link_down);
5065 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5066 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
5068 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
5069 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
5070 ns->mac_local_faults);
5071 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
5072 ns->mac_remote_faults);
5073 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
5074 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
5075 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
5076 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
5077 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
5078 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
5079 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
5080 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
5081 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
5082 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
5083 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
5084 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
5085 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
5086 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
5087 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
5088 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
5089 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
5090 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
5091 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
5092 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
5093 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
5094 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
5095 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
5096 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5100 /* Reset the statistics */
5102 ice_stats_reset(struct rte_eth_dev *dev)
5104 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5105 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5107 /* Mark PF and VSI stats to update the offset, aka "reset" */
5108 pf->offset_loaded = false;
5110 pf->main_vsi->offset_loaded = false;
5112 /* read the stats, reading current register values into offset */
5113 ice_read_stats_registers(pf, hw);
5119 ice_xstats_calc_num(void)
5123 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5129 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5132 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5133 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5136 struct ice_hw_port_stats *hw_stats = &pf->stats;
5138 count = ice_xstats_calc_num();
5142 ice_read_stats_registers(pf, hw);
5149 /* Get stats from ice_eth_stats struct */
5150 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5151 xstats[count].value =
5152 *(uint64_t *)((char *)&hw_stats->eth +
5153 ice_stats_strings[i].offset);
5154 xstats[count].id = count;
5158 /* Get individiual stats from ice_hw_port struct */
5159 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5160 xstats[count].value =
5161 *(uint64_t *)((char *)hw_stats +
5162 ice_hw_port_strings[i].offset);
5163 xstats[count].id = count;
5170 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5171 struct rte_eth_xstat_name *xstats_names,
5172 __rte_unused unsigned int limit)
5174 unsigned int count = 0;
5178 return ice_xstats_calc_num();
5180 /* Note: limit checked in rte_eth_xstats_names() */
5182 /* Get stats from ice_eth_stats struct */
5183 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5184 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5185 sizeof(xstats_names[count].name));
5189 /* Get individiual stats from ice_hw_port struct */
5190 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5191 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5192 sizeof(xstats_names[count].name));
5200 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
5201 enum rte_filter_type filter_type,
5202 enum rte_filter_op filter_op,
5210 switch (filter_type) {
5211 case RTE_ETH_FILTER_GENERIC:
5212 if (filter_op != RTE_ETH_FILTER_GET)
5214 *(const void **)arg = &ice_flow_ops;
5217 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5226 /* Add UDP tunneling port */
5228 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5229 struct rte_eth_udp_tunnel *udp_tunnel)
5232 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5234 if (udp_tunnel == NULL)
5237 switch (udp_tunnel->prot_type) {
5238 case RTE_TUNNEL_TYPE_VXLAN:
5239 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5242 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5250 /* Delete UDP tunneling port */
5252 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5253 struct rte_eth_udp_tunnel *udp_tunnel)
5256 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5258 if (udp_tunnel == NULL)
5261 switch (udp_tunnel->prot_type) {
5262 case RTE_TUNNEL_TYPE_VXLAN:
5263 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5266 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5275 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5276 struct rte_pci_device *pci_dev)
5278 return rte_eth_dev_pci_generic_probe(pci_dev,
5279 sizeof(struct ice_adapter),
5284 ice_pci_remove(struct rte_pci_device *pci_dev)
5286 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5289 static struct rte_pci_driver rte_ice_pmd = {
5290 .id_table = pci_id_ice_map,
5291 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5292 .probe = ice_pci_probe,
5293 .remove = ice_pci_remove,
5297 * Driver initialization routine.
5298 * Invoked once at EAL init time.
5299 * Register itself as the [Poll Mode] Driver of PCI devices.
5301 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5302 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5303 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5304 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5305 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5306 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5307 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5309 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5310 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5311 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5312 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5314 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5315 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5317 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5318 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);