1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
18 #include "rte_pmd_ice.h"
19 #include "ice_ethdev.h"
21 #include "ice_generic_flow.h"
24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
26 #define ICE_PROTO_XTR_ARG "proto_xtr"
28 static const char * const ice_valid_args[] = {
29 ICE_SAFE_MODE_SUPPORT_ARG,
30 ICE_PIPELINE_MODE_SUPPORT_ARG,
35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
36 .name = "intel_pmd_dynfield_proto_xtr_metadata",
37 .size = sizeof(uint32_t),
38 .align = __alignof__(uint32_t),
42 struct proto_xtr_ol_flag {
43 const struct rte_mbuf_dynflag param;
48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
52 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
55 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
58 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
60 [PROTO_XTR_IPV6_FLOW] = {
61 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
64 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
66 [PROTO_XTR_IP_OFFSET] = {
67 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
68 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
71 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
72 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
73 #define ICE_MAX_RES_DESC_NUM 1024
75 static int ice_dev_configure(struct rte_eth_dev *dev);
76 static int ice_dev_start(struct rte_eth_dev *dev);
77 static int ice_dev_stop(struct rte_eth_dev *dev);
78 static int ice_dev_close(struct rte_eth_dev *dev);
79 static int ice_dev_reset(struct rte_eth_dev *dev);
80 static int ice_dev_info_get(struct rte_eth_dev *dev,
81 struct rte_eth_dev_info *dev_info);
82 static int ice_link_update(struct rte_eth_dev *dev,
83 int wait_to_complete);
84 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
85 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
87 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
88 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
89 static int ice_rss_reta_update(struct rte_eth_dev *dev,
90 struct rte_eth_rss_reta_entry64 *reta_conf,
92 static int ice_rss_reta_query(struct rte_eth_dev *dev,
93 struct rte_eth_rss_reta_entry64 *reta_conf,
95 static int ice_rss_hash_update(struct rte_eth_dev *dev,
96 struct rte_eth_rss_conf *rss_conf);
97 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
98 struct rte_eth_rss_conf *rss_conf);
99 static int ice_promisc_enable(struct rte_eth_dev *dev);
100 static int ice_promisc_disable(struct rte_eth_dev *dev);
101 static int ice_allmulti_enable(struct rte_eth_dev *dev);
102 static int ice_allmulti_disable(struct rte_eth_dev *dev);
103 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
106 static int ice_macaddr_set(struct rte_eth_dev *dev,
107 struct rte_ether_addr *mac_addr);
108 static int ice_macaddr_add(struct rte_eth_dev *dev,
109 struct rte_ether_addr *mac_addr,
110 __rte_unused uint32_t index,
112 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
113 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
115 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
117 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
119 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
120 uint16_t pvid, int on);
121 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
122 static int ice_get_eeprom(struct rte_eth_dev *dev,
123 struct rte_dev_eeprom_info *eeprom);
124 static int ice_stats_get(struct rte_eth_dev *dev,
125 struct rte_eth_stats *stats);
126 static int ice_stats_reset(struct rte_eth_dev *dev);
127 static int ice_xstats_get(struct rte_eth_dev *dev,
128 struct rte_eth_xstat *xstats, unsigned int n);
129 static int ice_xstats_get_names(struct rte_eth_dev *dev,
130 struct rte_eth_xstat_name *xstats_names,
132 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
133 enum rte_filter_type filter_type,
134 enum rte_filter_op filter_op,
136 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
137 struct rte_eth_udp_tunnel *udp_tunnel);
138 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
139 struct rte_eth_udp_tunnel *udp_tunnel);
141 static const struct rte_pci_id pci_id_ice_map[] = {
142 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
143 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
144 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
145 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
146 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
147 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
148 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
149 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
150 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
157 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
159 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
164 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
165 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
166 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
167 { .vendor_id = 0, /* sentinel */ },
170 static const struct eth_dev_ops ice_eth_dev_ops = {
171 .dev_configure = ice_dev_configure,
172 .dev_start = ice_dev_start,
173 .dev_stop = ice_dev_stop,
174 .dev_close = ice_dev_close,
175 .dev_reset = ice_dev_reset,
176 .dev_set_link_up = ice_dev_set_link_up,
177 .dev_set_link_down = ice_dev_set_link_down,
178 .rx_queue_start = ice_rx_queue_start,
179 .rx_queue_stop = ice_rx_queue_stop,
180 .tx_queue_start = ice_tx_queue_start,
181 .tx_queue_stop = ice_tx_queue_stop,
182 .rx_queue_setup = ice_rx_queue_setup,
183 .rx_queue_release = ice_rx_queue_release,
184 .tx_queue_setup = ice_tx_queue_setup,
185 .tx_queue_release = ice_tx_queue_release,
186 .dev_infos_get = ice_dev_info_get,
187 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
188 .link_update = ice_link_update,
189 .mtu_set = ice_mtu_set,
190 .mac_addr_set = ice_macaddr_set,
191 .mac_addr_add = ice_macaddr_add,
192 .mac_addr_remove = ice_macaddr_remove,
193 .vlan_filter_set = ice_vlan_filter_set,
194 .vlan_offload_set = ice_vlan_offload_set,
195 .reta_update = ice_rss_reta_update,
196 .reta_query = ice_rss_reta_query,
197 .rss_hash_update = ice_rss_hash_update,
198 .rss_hash_conf_get = ice_rss_hash_conf_get,
199 .promiscuous_enable = ice_promisc_enable,
200 .promiscuous_disable = ice_promisc_disable,
201 .allmulticast_enable = ice_allmulti_enable,
202 .allmulticast_disable = ice_allmulti_disable,
203 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
204 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
205 .fw_version_get = ice_fw_version_get,
206 .vlan_pvid_set = ice_vlan_pvid_set,
207 .rxq_info_get = ice_rxq_info_get,
208 .txq_info_get = ice_txq_info_get,
209 .rx_burst_mode_get = ice_rx_burst_mode_get,
210 .tx_burst_mode_get = ice_tx_burst_mode_get,
211 .get_eeprom_length = ice_get_eeprom_length,
212 .get_eeprom = ice_get_eeprom,
213 .stats_get = ice_stats_get,
214 .stats_reset = ice_stats_reset,
215 .xstats_get = ice_xstats_get,
216 .xstats_get_names = ice_xstats_get_names,
217 .xstats_reset = ice_stats_reset,
218 .filter_ctrl = ice_dev_filter_ctrl,
219 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
220 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
221 .tx_done_cleanup = ice_tx_done_cleanup,
222 .get_monitor_addr = ice_get_monitor_addr,
225 /* store statistics names and its offset in stats structure */
226 struct ice_xstats_name_off {
227 char name[RTE_ETH_XSTATS_NAME_SIZE];
231 static const struct ice_xstats_name_off ice_stats_strings[] = {
232 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
233 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
234 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
235 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
236 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
237 rx_unknown_protocol)},
238 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
239 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
240 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
241 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
244 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
245 sizeof(ice_stats_strings[0]))
247 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
248 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
249 tx_dropped_link_down)},
250 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
251 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
253 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
254 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
256 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
258 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
260 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
261 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
262 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
263 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
264 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
265 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
267 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
269 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
271 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
273 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
275 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
277 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
279 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
281 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
282 mac_short_pkt_dropped)},
283 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
285 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
286 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
287 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
289 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
291 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
293 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
295 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
297 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
301 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
302 sizeof(ice_hw_port_strings[0]))
305 ice_init_controlq_parameter(struct ice_hw *hw)
307 /* fields for adminq */
308 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
309 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
310 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
311 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
313 /* fields for mailboxq, DPDK used as PF host */
314 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
315 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
316 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
317 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
321 lookup_proto_xtr_type(const char *xtr_name)
325 enum proto_xtr_type type;
327 { "vlan", PROTO_XTR_VLAN },
328 { "ipv4", PROTO_XTR_IPV4 },
329 { "ipv6", PROTO_XTR_IPV6 },
330 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
331 { "tcp", PROTO_XTR_TCP },
332 { "ip_offset", PROTO_XTR_IP_OFFSET },
336 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
337 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
338 return xtr_type_map[i].type;
345 * Parse elem, the elem could be single number/range or '(' ')' group
346 * 1) A single number elem, it's just a simple digit. e.g. 9
347 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
348 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
349 * Within group elem, '-' used for a range separator;
350 * ',' used for a single number.
353 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
355 const char *str = input;
360 while (isblank(*str))
363 if (!isdigit(*str) && *str != '(')
366 /* process single number or single range of number */
369 idx = strtoul(str, &end, 10);
370 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
373 while (isblank(*end))
379 /* process single <number>-<number> */
382 while (isblank(*end))
388 idx = strtoul(end, &end, 10);
389 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
393 while (isblank(*end))
400 for (idx = RTE_MIN(min, max);
401 idx <= RTE_MAX(min, max); idx++)
402 devargs->proto_xtr[idx] = xtr_type;
407 /* process set within bracket */
409 while (isblank(*str))
414 min = ICE_MAX_QUEUE_NUM;
416 /* go ahead to the first digit */
417 while (isblank(*str))
422 /* get the digit value */
424 idx = strtoul(str, &end, 10);
425 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
428 /* go ahead to separator '-',',' and ')' */
429 while (isblank(*end))
432 if (min == ICE_MAX_QUEUE_NUM)
434 else /* avoid continuous '-' */
436 } else if (*end == ',' || *end == ')') {
438 if (min == ICE_MAX_QUEUE_NUM)
441 for (idx = RTE_MIN(min, max);
442 idx <= RTE_MAX(min, max); idx++)
443 devargs->proto_xtr[idx] = xtr_type;
445 min = ICE_MAX_QUEUE_NUM;
451 } while (*end != ')' && *end != '\0');
457 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
459 const char *queue_start;
464 while (isblank(*queues))
467 if (*queues != '[') {
468 xtr_type = lookup_proto_xtr_type(queues);
472 devargs->proto_xtr_dflt = xtr_type;
479 while (isblank(*queues))
484 queue_start = queues;
486 /* go across a complete bracket */
487 if (*queue_start == '(') {
488 queues += strcspn(queues, ")");
493 /* scan the separator ':' */
494 queues += strcspn(queues, ":");
495 if (*queues++ != ':')
497 while (isblank(*queues))
500 for (idx = 0; ; idx++) {
501 if (isblank(queues[idx]) ||
502 queues[idx] == ',' ||
503 queues[idx] == ']' ||
507 if (idx > sizeof(xtr_name) - 2)
510 xtr_name[idx] = queues[idx];
512 xtr_name[idx] = '\0';
513 xtr_type = lookup_proto_xtr_type(xtr_name);
519 while (isblank(*queues) || *queues == ',' || *queues == ']')
522 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
524 } while (*queues != '\0');
530 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
533 struct ice_devargs *devargs = extra_args;
535 if (value == NULL || extra_args == NULL)
538 if (parse_queue_proto_xtr(value, devargs) < 0) {
540 "The protocol extraction parameter is wrong : '%s'",
549 ice_check_proto_xtr_support(struct ice_hw *hw)
551 #define FLX_REG(val, fld, idx) \
552 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
553 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
560 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
562 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
563 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
565 ICE_PROT_IPV4_OF_OR_S,
566 ICE_PROT_IPV4_OF_OR_S },
567 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
569 ICE_PROT_IPV6_OF_OR_S,
570 ICE_PROT_IPV6_OF_OR_S },
571 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
573 ICE_PROT_IPV6_OF_OR_S,
574 ICE_PROT_IPV6_OF_OR_S },
575 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
577 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
578 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
580 ICE_PROT_IPV4_OF_OR_S,
581 ICE_PROT_IPV6_OF_OR_S },
585 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
586 uint32_t rxdid = xtr_sets[i].rxdid;
589 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
590 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
592 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
593 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
594 ice_proto_xtr_hw_support[i] = true;
597 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
598 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
600 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
601 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
602 ice_proto_xtr_hw_support[i] = true;
608 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
611 struct pool_entry *entry;
616 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
619 "Failed to allocate memory for resource pool");
623 /* queue heap initialize */
624 pool->num_free = num;
627 LIST_INIT(&pool->alloc_list);
628 LIST_INIT(&pool->free_list);
630 /* Initialize element */
634 LIST_INSERT_HEAD(&pool->free_list, entry, next);
639 ice_res_pool_alloc(struct ice_res_pool_info *pool,
642 struct pool_entry *entry, *valid_entry;
645 PMD_INIT_LOG(ERR, "Invalid parameter");
649 if (pool->num_free < num) {
650 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
651 num, pool->num_free);
656 /* Lookup in free list and find most fit one */
657 LIST_FOREACH(entry, &pool->free_list, next) {
658 if (entry->len >= num) {
660 if (entry->len == num) {
665 valid_entry->len > entry->len)
670 /* Not find one to satisfy the request, return */
672 PMD_INIT_LOG(ERR, "No valid entry found");
676 * The entry have equal queue number as requested,
677 * remove it from alloc_list.
679 if (valid_entry->len == num) {
680 LIST_REMOVE(valid_entry, next);
683 * The entry have more numbers than requested,
684 * create a new entry for alloc_list and minus its
685 * queue base and number in free_list.
687 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
690 "Failed to allocate memory for "
694 entry->base = valid_entry->base;
696 valid_entry->base += num;
697 valid_entry->len -= num;
701 /* Insert it into alloc list, not sorted */
702 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
704 pool->num_free -= valid_entry->len;
705 pool->num_alloc += valid_entry->len;
707 return valid_entry->base + pool->base;
711 ice_res_pool_destroy(struct ice_res_pool_info *pool)
713 struct pool_entry *entry, *next_entry;
718 for (entry = LIST_FIRST(&pool->alloc_list);
719 entry && (next_entry = LIST_NEXT(entry, next), 1);
720 entry = next_entry) {
721 LIST_REMOVE(entry, next);
725 for (entry = LIST_FIRST(&pool->free_list);
726 entry && (next_entry = LIST_NEXT(entry, next), 1);
727 entry = next_entry) {
728 LIST_REMOVE(entry, next);
735 LIST_INIT(&pool->alloc_list);
736 LIST_INIT(&pool->free_list);
740 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
742 /* Set VSI LUT selection */
743 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
744 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
745 /* Set Hash scheme */
746 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
747 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
749 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
752 static enum ice_status
753 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
754 struct ice_aqc_vsi_props *info,
755 uint8_t enabled_tcmap)
757 uint16_t bsf, qp_idx;
759 /* default tc 0 now. Multi-TC supporting need to be done later.
760 * Configure TC and queue mapping parameters, for enabled TC,
761 * allocate qpnum_per_tc queues to this traffic.
763 if (enabled_tcmap != 0x01) {
764 PMD_INIT_LOG(ERR, "only TC0 is supported");
768 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
769 bsf = rte_bsf32(vsi->nb_qps);
770 /* Adjust the queue number to actual queues that can be applied */
771 vsi->nb_qps = 0x1 << bsf;
774 /* Set tc and queue mapping with VSI */
775 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
776 ICE_AQ_VSI_TC_Q_OFFSET_S) |
777 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
779 /* Associate queue number with VSI */
780 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
781 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
782 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
783 info->valid_sections |=
784 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
785 /* Set the info.ingress_table and info.egress_table
786 * for UP translate table. Now just set it to 1:1 map by default
787 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
789 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
790 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
791 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
792 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
797 ice_init_mac_address(struct rte_eth_dev *dev)
799 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
801 if (!rte_is_unicast_ether_addr
802 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
803 PMD_INIT_LOG(ERR, "Invalid MAC address");
808 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
809 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
811 dev->data->mac_addrs =
812 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
813 if (!dev->data->mac_addrs) {
815 "Failed to allocate memory to store mac address");
818 /* store it to dev data */
820 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
821 &dev->data->mac_addrs[0]);
825 /* Find out specific MAC filter */
826 static struct ice_mac_filter *
827 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
829 struct ice_mac_filter *f;
831 TAILQ_FOREACH(f, &vsi->mac_list, next) {
832 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
840 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
842 struct ice_fltr_list_entry *m_list_itr = NULL;
843 struct ice_mac_filter *f;
844 struct LIST_HEAD_TYPE list_head;
845 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
848 /* If it's added and configured, return */
849 f = ice_find_mac_filter(vsi, mac_addr);
851 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
855 INIT_LIST_HEAD(&list_head);
857 m_list_itr = (struct ice_fltr_list_entry *)
858 ice_malloc(hw, sizeof(*m_list_itr));
863 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
864 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
865 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
866 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
867 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
868 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
869 m_list_itr->fltr_info.vsi_handle = vsi->idx;
871 LIST_ADD(&m_list_itr->list_entry, &list_head);
874 ret = ice_add_mac(hw, &list_head);
875 if (ret != ICE_SUCCESS) {
876 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
880 /* Add the mac addr into mac list */
881 f = rte_zmalloc(NULL, sizeof(*f), 0);
883 PMD_DRV_LOG(ERR, "failed to allocate memory");
887 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
888 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
894 rte_free(m_list_itr);
899 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
901 struct ice_fltr_list_entry *m_list_itr = NULL;
902 struct ice_mac_filter *f;
903 struct LIST_HEAD_TYPE list_head;
904 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
907 /* Can't find it, return an error */
908 f = ice_find_mac_filter(vsi, mac_addr);
912 INIT_LIST_HEAD(&list_head);
914 m_list_itr = (struct ice_fltr_list_entry *)
915 ice_malloc(hw, sizeof(*m_list_itr));
920 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
921 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
922 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
923 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
924 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
925 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
926 m_list_itr->fltr_info.vsi_handle = vsi->idx;
928 LIST_ADD(&m_list_itr->list_entry, &list_head);
930 /* remove the mac filter */
931 ret = ice_remove_mac(hw, &list_head);
932 if (ret != ICE_SUCCESS) {
933 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
938 /* Remove the mac addr from mac list */
939 TAILQ_REMOVE(&vsi->mac_list, f, next);
945 rte_free(m_list_itr);
949 /* Find out specific VLAN filter */
950 static struct ice_vlan_filter *
951 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
953 struct ice_vlan_filter *f;
955 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
956 if (vlan->tpid == f->vlan_info.vlan.tpid &&
957 vlan->vid == f->vlan_info.vlan.vid)
965 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
967 struct ice_fltr_list_entry *v_list_itr = NULL;
968 struct ice_vlan_filter *f;
969 struct LIST_HEAD_TYPE list_head;
973 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
976 hw = ICE_VSI_TO_HW(vsi);
978 /* If it's added and configured, return. */
979 f = ice_find_vlan_filter(vsi, vlan);
981 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
985 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
988 INIT_LIST_HEAD(&list_head);
990 v_list_itr = (struct ice_fltr_list_entry *)
991 ice_malloc(hw, sizeof(*v_list_itr));
996 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
997 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
998 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
999 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1000 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1001 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1002 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1003 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1005 LIST_ADD(&v_list_itr->list_entry, &list_head);
1008 ret = ice_add_vlan(hw, &list_head);
1009 if (ret != ICE_SUCCESS) {
1010 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1015 /* Add vlan into vlan list */
1016 f = rte_zmalloc(NULL, sizeof(*f), 0);
1018 PMD_DRV_LOG(ERR, "failed to allocate memory");
1022 f->vlan_info.vlan.tpid = vlan->tpid;
1023 f->vlan_info.vlan.vid = vlan->vid;
1024 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1030 rte_free(v_list_itr);
1035 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1037 struct ice_fltr_list_entry *v_list_itr = NULL;
1038 struct ice_vlan_filter *f;
1039 struct LIST_HEAD_TYPE list_head;
1043 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1046 hw = ICE_VSI_TO_HW(vsi);
1048 /* Can't find it, return an error */
1049 f = ice_find_vlan_filter(vsi, vlan);
1053 INIT_LIST_HEAD(&list_head);
1055 v_list_itr = (struct ice_fltr_list_entry *)
1056 ice_malloc(hw, sizeof(*v_list_itr));
1062 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1063 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1064 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1065 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1066 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1067 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1068 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1069 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1071 LIST_ADD(&v_list_itr->list_entry, &list_head);
1073 /* remove the vlan filter */
1074 ret = ice_remove_vlan(hw, &list_head);
1075 if (ret != ICE_SUCCESS) {
1076 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1081 /* Remove the vlan id from vlan list */
1082 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1088 rte_free(v_list_itr);
1093 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1095 struct ice_mac_filter *m_f;
1096 struct ice_vlan_filter *v_f;
1099 if (!vsi || !vsi->mac_num)
1102 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1103 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1104 if (ret != ICE_SUCCESS) {
1110 if (vsi->vlan_num == 0)
1113 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1114 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1115 if (ret != ICE_SUCCESS) {
1127 ice_pf_enable_irq0(struct ice_hw *hw)
1129 /* reset the registers */
1130 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1131 ICE_READ_REG(hw, PFINT_OICR);
1134 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1135 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1136 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1138 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1139 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1140 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1141 PFINT_OICR_CTL_ITR_INDX_M) |
1142 PFINT_OICR_CTL_CAUSE_ENA_M);
1144 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1145 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1146 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1147 PFINT_FW_CTL_ITR_INDX_M) |
1148 PFINT_FW_CTL_CAUSE_ENA_M);
1150 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1153 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1154 GLINT_DYN_CTL_INTENA_M |
1155 GLINT_DYN_CTL_CLEARPBA_M |
1156 GLINT_DYN_CTL_ITR_INDX_M);
1163 ice_pf_disable_irq0(struct ice_hw *hw)
1165 /* Disable all interrupt types */
1166 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1172 ice_handle_aq_msg(struct rte_eth_dev *dev)
1174 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1175 struct ice_ctl_q_info *cq = &hw->adminq;
1176 struct ice_rq_event_info event;
1177 uint16_t pending, opcode;
1180 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1181 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1182 if (!event.msg_buf) {
1183 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1189 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1191 if (ret != ICE_SUCCESS) {
1193 "Failed to read msg from AdminQ, "
1195 hw->adminq.sq_last_status);
1198 opcode = rte_le_to_cpu_16(event.desc.opcode);
1201 case ice_aqc_opc_get_link_status:
1202 ret = ice_link_update(dev, 0);
1204 rte_eth_dev_callback_process
1205 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1208 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1213 rte_free(event.msg_buf);
1218 * Interrupt handler triggered by NIC for handling
1219 * specific interrupt.
1222 * Pointer to interrupt handle.
1224 * The address of parameter (struct rte_eth_dev *) regsitered before.
1230 ice_interrupt_handler(void *param)
1232 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1233 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1241 uint32_t int_fw_ctl;
1244 /* Disable interrupt */
1245 ice_pf_disable_irq0(hw);
1247 /* read out interrupt causes */
1248 oicr = ICE_READ_REG(hw, PFINT_OICR);
1250 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1253 /* No interrupt event indicated */
1254 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1255 PMD_DRV_LOG(INFO, "No interrupt event");
1260 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1261 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1262 ice_handle_aq_msg(dev);
1265 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1266 PMD_DRV_LOG(INFO, "OICR: link state change event");
1267 ret = ice_link_update(dev, 0);
1269 rte_eth_dev_callback_process
1270 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1274 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1275 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1276 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1277 if (reg & GL_MDET_TX_PQM_VALID_M) {
1278 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1279 GL_MDET_TX_PQM_PF_NUM_S;
1280 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1281 GL_MDET_TX_PQM_MAL_TYPE_S;
1282 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1283 GL_MDET_TX_PQM_QNUM_S;
1285 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1286 "%d by PQM on TX queue %d PF# %d",
1287 event, queue, pf_num);
1290 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1291 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1292 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1293 GL_MDET_TX_TCLAN_PF_NUM_S;
1294 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1295 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1296 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1297 GL_MDET_TX_TCLAN_QNUM_S;
1299 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1300 "%d by TCLAN on TX queue %d PF# %d",
1301 event, queue, pf_num);
1305 /* Enable interrupt */
1306 ice_pf_enable_irq0(hw);
1307 rte_intr_ack(dev->intr_handle);
1311 ice_init_proto_xtr(struct rte_eth_dev *dev)
1313 struct ice_adapter *ad =
1314 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1315 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1316 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1317 const struct proto_xtr_ol_flag *ol_flag;
1318 bool proto_xtr_enable = false;
1322 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1323 if (unlikely(pf->proto_xtr == NULL)) {
1324 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1328 for (i = 0; i < pf->lan_nb_qps; i++) {
1329 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1330 ad->devargs.proto_xtr[i] :
1331 ad->devargs.proto_xtr_dflt;
1333 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1334 uint8_t type = pf->proto_xtr[i];
1336 ice_proto_xtr_ol_flag_params[type].required = true;
1337 proto_xtr_enable = true;
1341 if (likely(!proto_xtr_enable))
1344 ice_check_proto_xtr_support(hw);
1346 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1347 if (unlikely(offset == -1)) {
1349 "Protocol extraction metadata is disabled in mbuf with error %d",
1355 "Protocol extraction metadata offset in mbuf is : %d",
1357 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1359 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1360 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1362 if (!ol_flag->required)
1365 if (!ice_proto_xtr_hw_support[i]) {
1367 "Protocol extraction type %u is not supported in hardware",
1369 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1373 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1374 if (unlikely(offset == -1)) {
1376 "Protocol extraction offload '%s' failed to register with error %d",
1377 ol_flag->param.name, -rte_errno);
1379 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1384 "Protocol extraction offload '%s' offset in mbuf is : %d",
1385 ol_flag->param.name, offset);
1386 *ol_flag->ol_flag = 1ULL << offset;
1390 /* Initialize SW parameters of PF */
1392 ice_pf_sw_init(struct rte_eth_dev *dev)
1394 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1395 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1398 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1399 hw->func_caps.common_cap.num_rxq);
1401 pf->lan_nb_qps = pf->lan_nb_qp_max;
1403 ice_init_proto_xtr(dev);
1405 if (hw->func_caps.fd_fltr_guar > 0 ||
1406 hw->func_caps.fd_fltr_best_effort > 0) {
1407 pf->flags |= ICE_FLAG_FDIR;
1408 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1409 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1411 pf->fdir_nb_qps = 0;
1413 pf->fdir_qp_offset = 0;
1419 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1421 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1422 struct ice_vsi *vsi = NULL;
1423 struct ice_vsi_ctx vsi_ctx;
1425 struct rte_ether_addr broadcast = {
1426 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1427 struct rte_ether_addr mac_addr;
1428 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1429 uint8_t tc_bitmap = 0x1;
1432 /* hw->num_lports = 1 in NIC mode */
1433 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1437 vsi->idx = pf->next_vsi_idx;
1440 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1441 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1442 vsi->vlan_anti_spoof_on = 0;
1443 vsi->vlan_filter_on = 1;
1444 TAILQ_INIT(&vsi->mac_list);
1445 TAILQ_INIT(&vsi->vlan_list);
1447 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1448 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1449 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1450 hw->func_caps.common_cap.rss_table_size;
1451 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1453 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1456 vsi->nb_qps = pf->lan_nb_qps;
1457 vsi->base_queue = 1;
1458 ice_vsi_config_default_rss(&vsi_ctx.info);
1459 vsi_ctx.alloc_from_pool = true;
1460 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1461 /* switch_id is queried by get_switch_config aq, which is done
1464 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1465 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1466 /* Allow all untagged or tagged packets */
1467 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1468 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1469 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1470 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1471 if (ice_is_dvm_ena(hw)) {
1472 vsi_ctx.info.outer_vlan_flags =
1473 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1474 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1475 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1476 vsi_ctx.info.outer_vlan_flags |=
1477 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1478 ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1479 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1483 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1484 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1485 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1486 cfg = ICE_AQ_VSI_FD_ENABLE;
1487 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1488 vsi_ctx.info.max_fd_fltr_dedicated =
1489 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1490 vsi_ctx.info.max_fd_fltr_shared =
1491 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1493 /* Enable VLAN/UP trip */
1494 ret = ice_vsi_config_tc_queue_mapping(vsi,
1499 "tc queue mapping with vsi failed, "
1507 vsi->nb_qps = pf->fdir_nb_qps;
1508 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1509 vsi_ctx.alloc_from_pool = true;
1510 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1512 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1513 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1514 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1515 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1516 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1517 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1518 ret = ice_vsi_config_tc_queue_mapping(vsi,
1523 "tc queue mapping with vsi failed, "
1530 /* for other types of VSI */
1531 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1535 /* VF has MSIX interrupt in VF range, don't allocate here */
1536 if (type == ICE_VSI_PF) {
1537 ret = ice_res_pool_alloc(&pf->msix_pool,
1538 RTE_MIN(vsi->nb_qps,
1539 RTE_MAX_RXTX_INTR_VEC_ID));
1541 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1544 vsi->msix_intr = ret;
1545 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1546 } else if (type == ICE_VSI_CTRL) {
1547 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1549 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1552 vsi->msix_intr = ret;
1558 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1559 if (ret != ICE_SUCCESS) {
1560 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1563 /* store vsi information is SW structure */
1564 vsi->vsi_id = vsi_ctx.vsi_num;
1565 vsi->info = vsi_ctx.info;
1566 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1567 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1569 if (type == ICE_VSI_PF) {
1570 /* MAC configuration */
1571 rte_ether_addr_copy((struct rte_ether_addr *)
1572 hw->port_info->mac.perm_addr,
1575 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1576 ret = ice_add_mac_filter(vsi, &mac_addr);
1577 if (ret != ICE_SUCCESS)
1578 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1580 rte_ether_addr_copy(&broadcast, &mac_addr);
1581 ret = ice_add_mac_filter(vsi, &mac_addr);
1582 if (ret != ICE_SUCCESS)
1583 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1586 /* At the beginning, only TC0. */
1587 /* What we need here is the maximam number of the TX queues.
1588 * Currently vsi->nb_qps means it.
1589 * Correct it if any change.
1591 max_txqs[0] = vsi->nb_qps;
1592 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1593 tc_bitmap, max_txqs);
1594 if (ret != ICE_SUCCESS)
1595 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1605 ice_send_driver_ver(struct ice_hw *hw)
1607 struct ice_driver_ver dv;
1609 /* we don't have driver version use 0 for dummy */
1613 dv.subbuild_ver = 0;
1614 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1616 return ice_aq_send_driver_ver(hw, &dv, NULL);
1620 ice_pf_setup(struct ice_pf *pf)
1622 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1623 struct ice_vsi *vsi;
1626 /* Clear all stats counters */
1627 pf->offset_loaded = false;
1628 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1629 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1630 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1631 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1633 /* force guaranteed filter pool for PF */
1634 ice_alloc_fd_guar_item(hw, &unused,
1635 hw->func_caps.fd_fltr_guar);
1636 /* force shared filter pool for PF */
1637 ice_alloc_fd_shrd_item(hw, &unused,
1638 hw->func_caps.fd_fltr_best_effort);
1640 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1642 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1652 * Extract device serial number from PCIe Configuration Space and
1653 * determine the pkg file path according to the DSN.
1656 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1659 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1660 uint32_t dsn_low, dsn_high;
1661 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1663 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1666 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1667 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1668 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1669 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1671 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1675 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1676 ICE_MAX_PKG_FILENAME_SIZE);
1677 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1680 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1681 ICE_MAX_PKG_FILENAME_SIZE);
1682 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1686 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1687 if (!access(pkg_file, 0))
1689 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1694 ice_load_pkg_type(struct ice_hw *hw)
1696 enum ice_pkg_type package_type;
1698 /* store the activated package type (OS default or Comms) */
1699 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1701 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1702 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1704 package_type = ICE_PKG_TYPE_COMMS;
1706 package_type = ICE_PKG_TYPE_UNKNOWN;
1708 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1709 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1710 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1711 hw->active_pkg_name,
1712 ice_is_dvm_ena(hw) ? "double" : "single");
1714 return package_type;
1717 static int ice_load_pkg(struct rte_eth_dev *dev)
1719 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1720 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1726 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1727 struct ice_adapter *ad =
1728 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1730 ice_pkg_file_search_path(pci_dev, pkg_file);
1732 file = fopen(pkg_file, "rb");
1734 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1738 err = stat(pkg_file, &fstat);
1740 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1745 buf_len = fstat.st_size;
1746 buf = rte_malloc(NULL, buf_len, 0);
1749 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1755 err = fread(buf, buf_len, 1, file);
1757 PMD_INIT_LOG(ERR, "failed to read package data\n");
1765 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1767 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1771 /* store the loaded pkg type info */
1772 ad->active_pkg_type = ice_load_pkg_type(hw);
1774 err = ice_init_hw_tbls(hw);
1776 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1777 goto fail_init_tbls;
1783 rte_free(hw->pkg_copy);
1790 ice_base_queue_get(struct ice_pf *pf)
1793 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1795 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1796 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1797 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1799 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1805 parse_bool(const char *key, const char *value, void *args)
1807 int *i = (int *)args;
1811 num = strtoul(value, &end, 10);
1813 if (num != 0 && num != 1) {
1814 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1815 "value must be 0 or 1",
1824 static int ice_parse_devargs(struct rte_eth_dev *dev)
1826 struct ice_adapter *ad =
1827 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1828 struct rte_devargs *devargs = dev->device->devargs;
1829 struct rte_kvargs *kvlist;
1832 if (devargs == NULL)
1835 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1836 if (kvlist == NULL) {
1837 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1841 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1842 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1843 sizeof(ad->devargs.proto_xtr));
1845 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1846 &handle_proto_xtr_arg, &ad->devargs);
1850 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1851 &parse_bool, &ad->devargs.safe_mode_support);
1855 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1856 &parse_bool, &ad->devargs.pipe_mode_support);
1861 rte_kvargs_free(kvlist);
1865 /* Forward LLDP packets to default VSI by set switch rules */
1867 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1869 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1870 struct ice_fltr_list_entry *s_list_itr = NULL;
1871 struct LIST_HEAD_TYPE list_head;
1874 INIT_LIST_HEAD(&list_head);
1876 s_list_itr = (struct ice_fltr_list_entry *)
1877 ice_malloc(hw, sizeof(*s_list_itr));
1880 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1881 s_list_itr->fltr_info.vsi_handle = vsi->idx;
1882 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1883 RTE_ETHER_TYPE_LLDP;
1884 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1885 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1886 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1887 LIST_ADD(&s_list_itr->list_entry, &list_head);
1889 ret = ice_add_eth_mac(hw, &list_head);
1891 ret = ice_remove_eth_mac(hw, &list_head);
1893 rte_free(s_list_itr);
1897 static enum ice_status
1898 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1899 uint16_t num, uint16_t desc_id,
1900 uint16_t *prof_buf, uint16_t *num_prof)
1902 struct ice_aqc_res_elem *resp_buf;
1905 bool res_shared = 1;
1906 struct ice_aq_desc aq_desc;
1907 struct ice_sq_cd *cd = NULL;
1908 struct ice_aqc_get_allocd_res_desc *cmd =
1909 &aq_desc.params.get_res_desc;
1911 buf_len = sizeof(*resp_buf) * num;
1912 resp_buf = ice_malloc(hw, buf_len);
1916 ice_fill_dflt_direct_cmd_desc(&aq_desc,
1917 ice_aqc_opc_get_allocd_res_desc);
1919 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1920 ICE_AQC_RES_TYPE_M) | (res_shared ?
1921 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1922 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1924 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1926 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1930 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
1931 (*num_prof), ICE_NONDMA_TO_NONDMA);
1938 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1942 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1943 uint16_t first_desc = 1;
1944 uint16_t num_prof = 0;
1946 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1947 first_desc, prof_buf, &num_prof);
1949 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
1953 for (prof_id = 0; prof_id < num_prof; prof_id++) {
1954 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
1956 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
1964 ice_reset_fxp_resource(struct ice_hw *hw)
1968 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
1970 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
1974 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
1976 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
1984 ice_rss_ctx_init(struct ice_pf *pf)
1986 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
1990 ice_get_supported_rxdid(struct ice_hw *hw)
1992 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
1996 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
1998 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
1999 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2000 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2001 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2002 supported_rxdid |= BIT(i);
2004 return supported_rxdid;
2008 ice_dev_init(struct rte_eth_dev *dev)
2010 struct rte_pci_device *pci_dev;
2011 struct rte_intr_handle *intr_handle;
2012 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2014 struct ice_adapter *ad =
2015 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2016 struct ice_vsi *vsi;
2019 dev->dev_ops = &ice_eth_dev_ops;
2020 dev->rx_queue_count = ice_rx_queue_count;
2021 dev->rx_descriptor_status = ice_rx_descriptor_status;
2022 dev->tx_descriptor_status = ice_tx_descriptor_status;
2023 dev->rx_pkt_burst = ice_recv_pkts;
2024 dev->tx_pkt_burst = ice_xmit_pkts;
2025 dev->tx_pkt_prepare = ice_prep_pkts;
2027 /* for secondary processes, we don't initialise any further as primary
2028 * has already done this work.
2030 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2031 ice_set_rx_function(dev);
2032 ice_set_tx_function(dev);
2036 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2038 ice_set_default_ptype_table(dev);
2039 pci_dev = RTE_DEV_TO_PCI(dev->device);
2040 intr_handle = &pci_dev->intr_handle;
2042 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2043 pf->adapter->eth_dev = dev;
2044 pf->dev_data = dev->data;
2045 hw->back = pf->adapter;
2046 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2047 hw->vendor_id = pci_dev->id.vendor_id;
2048 hw->device_id = pci_dev->id.device_id;
2049 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2050 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2051 hw->bus.device = pci_dev->addr.devid;
2052 hw->bus.func = pci_dev->addr.function;
2054 ret = ice_parse_devargs(dev);
2056 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2060 ice_init_controlq_parameter(hw);
2062 ret = ice_init_hw(hw);
2064 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2068 ret = ice_load_pkg(dev);
2070 if (ad->devargs.safe_mode_support == 0) {
2071 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2072 "Use safe-mode-support=1 to enter Safe Mode");
2076 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2077 "Entering Safe Mode");
2078 ad->is_safe_mode = 1;
2081 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2082 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2083 hw->api_maj_ver, hw->api_min_ver);
2085 ice_pf_sw_init(dev);
2086 ret = ice_init_mac_address(dev);
2088 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2092 ret = ice_res_pool_init(&pf->msix_pool, 1,
2093 hw->func_caps.common_cap.num_msix_vectors - 1);
2095 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2096 goto err_msix_pool_init;
2099 ret = ice_pf_setup(pf);
2101 PMD_INIT_LOG(ERR, "Failed to setup PF");
2105 ret = ice_send_driver_ver(hw);
2107 PMD_INIT_LOG(ERR, "Failed to send driver version");
2113 ret = ice_aq_stop_lldp(hw, true, false, NULL);
2114 if (ret != ICE_SUCCESS)
2115 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2116 ret = ice_init_dcb(hw, true);
2117 if (ret != ICE_SUCCESS)
2118 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2119 /* Forward LLDP packets to default VSI */
2120 ret = ice_vsi_config_sw_lldp(vsi, true);
2121 if (ret != ICE_SUCCESS)
2122 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2123 /* register callback func to eal lib */
2124 rte_intr_callback_register(intr_handle,
2125 ice_interrupt_handler, dev);
2127 ice_pf_enable_irq0(hw);
2129 /* enable uio intr after callback register */
2130 rte_intr_enable(intr_handle);
2132 /* get base queue pairs index in the device */
2133 ice_base_queue_get(pf);
2135 /* Initialize RSS context for gtpu_eh */
2136 ice_rss_ctx_init(pf);
2138 if (!ad->is_safe_mode) {
2139 ret = ice_flow_init(ad);
2141 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2146 ret = ice_reset_fxp_resource(hw);
2148 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2152 pf->supported_rxdid = ice_get_supported_rxdid(hw);
2157 ice_res_pool_destroy(&pf->msix_pool);
2159 rte_free(dev->data->mac_addrs);
2160 dev->data->mac_addrs = NULL;
2162 ice_sched_cleanup_all(hw);
2163 rte_free(hw->port_info);
2164 ice_shutdown_all_ctrlq(hw);
2165 rte_free(pf->proto_xtr);
2171 ice_release_vsi(struct ice_vsi *vsi)
2174 struct ice_vsi_ctx vsi_ctx;
2175 enum ice_status ret;
2181 hw = ICE_VSI_TO_HW(vsi);
2183 ice_remove_all_mac_vlan_filters(vsi);
2185 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2187 vsi_ctx.vsi_num = vsi->vsi_id;
2188 vsi_ctx.info = vsi->info;
2189 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2190 if (ret != ICE_SUCCESS) {
2191 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2195 rte_free(vsi->rss_lut);
2196 rte_free(vsi->rss_key);
2202 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2204 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2205 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2207 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2208 uint16_t msix_intr, i;
2210 /* disable interrupt and also clear all the exist config */
2211 for (i = 0; i < vsi->nb_qps; i++) {
2212 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2213 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2217 if (rte_intr_allow_others(intr_handle))
2219 for (i = 0; i < vsi->nb_msix; i++) {
2220 msix_intr = vsi->msix_intr + i;
2221 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2222 GLINT_DYN_CTL_WB_ON_ITR_M);
2226 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2230 ice_dev_stop(struct rte_eth_dev *dev)
2232 struct rte_eth_dev_data *data = dev->data;
2233 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2234 struct ice_vsi *main_vsi = pf->main_vsi;
2235 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2236 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2239 /* avoid stopping again */
2240 if (pf->adapter_stopped)
2243 /* stop and clear all Rx queues */
2244 for (i = 0; i < data->nb_rx_queues; i++)
2245 ice_rx_queue_stop(dev, i);
2247 /* stop and clear all Tx queues */
2248 for (i = 0; i < data->nb_tx_queues; i++)
2249 ice_tx_queue_stop(dev, i);
2251 /* disable all queue interrupts */
2252 ice_vsi_disable_queues_intr(main_vsi);
2254 if (pf->init_link_up)
2255 ice_dev_set_link_up(dev);
2257 ice_dev_set_link_down(dev);
2259 /* Clean datapath event and queue/vec mapping */
2260 rte_intr_efd_disable(intr_handle);
2261 if (intr_handle->intr_vec) {
2262 rte_free(intr_handle->intr_vec);
2263 intr_handle->intr_vec = NULL;
2266 pf->adapter_stopped = true;
2267 dev->data->dev_started = 0;
2273 ice_dev_close(struct rte_eth_dev *dev)
2275 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2276 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2278 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2279 struct ice_adapter *ad =
2280 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2283 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2286 /* Since stop will make link down, then the link event will be
2287 * triggered, disable the irq firstly to avoid the port_infoe etc
2288 * resources deallocation causing the interrupt service thread
2291 ice_pf_disable_irq0(hw);
2293 ret = ice_dev_stop(dev);
2295 if (!ad->is_safe_mode)
2296 ice_flow_uninit(ad);
2298 /* release all queue resource */
2299 ice_free_queues(dev);
2301 ice_res_pool_destroy(&pf->msix_pool);
2302 ice_release_vsi(pf->main_vsi);
2303 ice_sched_cleanup_all(hw);
2304 ice_free_hw_tbls(hw);
2305 rte_free(hw->port_info);
2306 hw->port_info = NULL;
2307 ice_shutdown_all_ctrlq(hw);
2308 rte_free(pf->proto_xtr);
2309 pf->proto_xtr = NULL;
2311 /* disable uio intr before callback unregister */
2312 rte_intr_disable(intr_handle);
2314 /* unregister callback func from eal lib */
2315 rte_intr_callback_unregister(intr_handle,
2316 ice_interrupt_handler, dev);
2322 ice_dev_uninit(struct rte_eth_dev *dev)
2330 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2332 return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2336 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2341 cfg->hdr_type = ICE_RSS_ANY_HEADERS;
2345 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2347 enum ice_status status = ICE_SUCCESS;
2348 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2349 struct ice_vsi *vsi = pf->main_vsi;
2351 if (!is_hash_cfg_valid(cfg))
2354 status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2355 if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2357 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2366 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2368 enum ice_status status = ICE_SUCCESS;
2369 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2370 struct ice_vsi *vsi = pf->main_vsi;
2372 if (!is_hash_cfg_valid(cfg))
2375 status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2378 "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2387 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2391 ret = ice_hash_moveout(pf, cfg);
2392 if (ret && (ret != -ENOENT))
2395 hash_cfg_reset(cfg);
2401 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2407 case ICE_HASH_GTPU_CTX_EH_IP:
2408 ret = ice_hash_remove(pf,
2409 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2410 if (ret && (ret != -ENOENT))
2413 ret = ice_hash_remove(pf,
2414 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2415 if (ret && (ret != -ENOENT))
2418 ret = ice_hash_remove(pf,
2419 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2420 if (ret && (ret != -ENOENT))
2423 ret = ice_hash_remove(pf,
2424 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2425 if (ret && (ret != -ENOENT))
2428 ret = ice_hash_remove(pf,
2429 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2430 if (ret && (ret != -ENOENT))
2433 ret = ice_hash_remove(pf,
2434 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2435 if (ret && (ret != -ENOENT))
2438 ret = ice_hash_remove(pf,
2439 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2440 if (ret && (ret != -ENOENT))
2443 ret = ice_hash_remove(pf,
2444 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2445 if (ret && (ret != -ENOENT))
2449 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2450 ret = ice_hash_remove(pf,
2451 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2452 if (ret && (ret != -ENOENT))
2455 ret = ice_hash_remove(pf,
2456 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2457 if (ret && (ret != -ENOENT))
2460 ret = ice_hash_moveout(pf,
2461 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2462 if (ret && (ret != -ENOENT))
2465 ret = ice_hash_moveout(pf,
2466 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2467 if (ret && (ret != -ENOENT))
2470 ret = ice_hash_moveout(pf,
2471 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2472 if (ret && (ret != -ENOENT))
2475 ret = ice_hash_moveout(pf,
2476 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2477 if (ret && (ret != -ENOENT))
2481 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2482 ret = ice_hash_remove(pf,
2483 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2484 if (ret && (ret != -ENOENT))
2487 ret = ice_hash_remove(pf,
2488 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2489 if (ret && (ret != -ENOENT))
2492 ret = ice_hash_moveout(pf,
2493 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2494 if (ret && (ret != -ENOENT))
2497 ret = ice_hash_moveout(pf,
2498 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2499 if (ret && (ret != -ENOENT))
2502 ret = ice_hash_moveout(pf,
2503 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2504 if (ret && (ret != -ENOENT))
2507 ret = ice_hash_moveout(pf,
2508 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2509 if (ret && (ret != -ENOENT))
2513 case ICE_HASH_GTPU_CTX_UP_IP:
2514 ret = ice_hash_remove(pf,
2515 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2516 if (ret && (ret != -ENOENT))
2519 ret = ice_hash_remove(pf,
2520 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2521 if (ret && (ret != -ENOENT))
2524 ret = ice_hash_moveout(pf,
2525 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2526 if (ret && (ret != -ENOENT))
2529 ret = ice_hash_moveout(pf,
2530 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2531 if (ret && (ret != -ENOENT))
2534 ret = ice_hash_moveout(pf,
2535 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2536 if (ret && (ret != -ENOENT))
2540 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2541 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2542 ret = ice_hash_moveout(pf,
2543 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2544 if (ret && (ret != -ENOENT))
2547 ret = ice_hash_moveout(pf,
2548 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2549 if (ret && (ret != -ENOENT))
2552 ret = ice_hash_moveout(pf,
2553 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2554 if (ret && (ret != -ENOENT))
2558 case ICE_HASH_GTPU_CTX_DW_IP:
2559 ret = ice_hash_remove(pf,
2560 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2561 if (ret && (ret != -ENOENT))
2564 ret = ice_hash_remove(pf,
2565 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2566 if (ret && (ret != -ENOENT))
2569 ret = ice_hash_moveout(pf,
2570 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2571 if (ret && (ret != -ENOENT))
2574 ret = ice_hash_moveout(pf,
2575 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2576 if (ret && (ret != -ENOENT))
2579 ret = ice_hash_moveout(pf,
2580 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2581 if (ret && (ret != -ENOENT))
2585 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2586 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2587 ret = ice_hash_moveout(pf,
2588 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2589 if (ret && (ret != -ENOENT))
2592 ret = ice_hash_moveout(pf,
2593 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2594 if (ret && (ret != -ENOENT))
2597 ret = ice_hash_moveout(pf,
2598 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2599 if (ret && (ret != -ENOENT))
2610 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2614 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2616 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2618 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2621 return ICE_HASH_GTPU_CTX_MAX;
2624 if (hdr & ICE_FLOW_SEG_HDR_UDP)
2626 else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2629 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2630 return eh_idx * 3 + ip_idx;
2632 return ICE_HASH_GTPU_CTX_MAX;
2636 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2638 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2640 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2641 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2643 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2644 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2651 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2652 u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2656 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2657 ctx->ctx[ctx_idx] = *cfg;
2660 case ICE_HASH_GTPU_CTX_EH_IP:
2662 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2663 ret = ice_hash_moveback(pf,
2664 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2665 if (ret && (ret != -ENOENT))
2668 ret = ice_hash_moveback(pf,
2669 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2670 if (ret && (ret != -ENOENT))
2673 ret = ice_hash_moveback(pf,
2674 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2675 if (ret && (ret != -ENOENT))
2678 ret = ice_hash_moveback(pf,
2679 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2680 if (ret && (ret != -ENOENT))
2684 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2685 ret = ice_hash_moveback(pf,
2686 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2687 if (ret && (ret != -ENOENT))
2690 ret = ice_hash_moveback(pf,
2691 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2692 if (ret && (ret != -ENOENT))
2695 ret = ice_hash_moveback(pf,
2696 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2697 if (ret && (ret != -ENOENT))
2700 ret = ice_hash_moveback(pf,
2701 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2702 if (ret && (ret != -ENOENT))
2706 case ICE_HASH_GTPU_CTX_UP_IP:
2707 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2708 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2709 case ICE_HASH_GTPU_CTX_DW_IP:
2710 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2711 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2712 ret = ice_hash_moveback(pf,
2713 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2714 if (ret && (ret != -ENOENT))
2717 ret = ice_hash_moveback(pf,
2718 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2719 if (ret && (ret != -ENOENT))
2722 ret = ice_hash_moveback(pf,
2723 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2724 if (ret && (ret != -ENOENT))
2736 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2738 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2740 if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2741 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2743 else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2744 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2751 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2753 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2755 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2758 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2759 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2760 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2761 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2765 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2766 struct ice_rss_hash_cfg *cfg)
2768 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2771 ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2772 if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2773 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2775 ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2781 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2782 struct ice_rss_hash_cfg *cfg)
2784 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2787 ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2789 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2791 ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2793 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2795 ret = ice_add_rss_cfg_post(pf, cfg);
2797 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2803 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2805 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2806 struct ice_vsi *vsi = pf->main_vsi;
2807 struct ice_rss_hash_cfg cfg;
2810 #define ICE_RSS_HF_ALL ( \
2813 ETH_RSS_NONFRAG_IPV4_UDP | \
2814 ETH_RSS_NONFRAG_IPV6_UDP | \
2815 ETH_RSS_NONFRAG_IPV4_TCP | \
2816 ETH_RSS_NONFRAG_IPV6_TCP | \
2817 ETH_RSS_NONFRAG_IPV4_SCTP | \
2818 ETH_RSS_NONFRAG_IPV6_SCTP)
2820 ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2822 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2826 cfg.hdr_type = ICE_RSS_ANY_HEADERS;
2827 /* Configure RSS for IPv4 with src/dst addr as input set */
2828 if (rss_hf & ETH_RSS_IPV4) {
2829 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2830 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2831 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2833 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2837 /* Configure RSS for IPv6 with src/dst addr as input set */
2838 if (rss_hf & ETH_RSS_IPV6) {
2839 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2840 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2841 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2843 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2847 /* Configure RSS for udp4 with src/dst addr and port as input set */
2848 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2849 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2850 ICE_FLOW_SEG_HDR_IPV_OTHER;
2851 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2852 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2854 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2858 /* Configure RSS for udp6 with src/dst addr and port as input set */
2859 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2860 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
2861 ICE_FLOW_SEG_HDR_IPV_OTHER;
2862 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2863 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2865 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2869 /* Configure RSS for tcp4 with src/dst addr and port as input set */
2870 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2871 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
2872 ICE_FLOW_SEG_HDR_IPV_OTHER;
2873 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2874 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2876 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2880 /* Configure RSS for tcp6 with src/dst addr and port as input set */
2881 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2882 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
2883 ICE_FLOW_SEG_HDR_IPV_OTHER;
2884 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2885 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2887 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2891 /* Configure RSS for sctp4 with src/dst addr and port as input set */
2892 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2893 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
2894 ICE_FLOW_SEG_HDR_IPV_OTHER;
2895 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
2896 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2898 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2902 /* Configure RSS for sctp6 with src/dst addr and port as input set */
2903 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2904 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
2905 ICE_FLOW_SEG_HDR_IPV_OTHER;
2906 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
2907 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2909 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2913 if (rss_hf & ETH_RSS_IPV4) {
2914 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV4 |
2915 ICE_FLOW_SEG_HDR_IPV_OTHER;
2916 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2917 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2919 PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
2922 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV4 |
2923 ICE_FLOW_SEG_HDR_IPV_OTHER;
2924 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2926 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
2929 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
2930 ICE_FLOW_SEG_HDR_IPV_OTHER;
2931 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2933 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2937 if (rss_hf & ETH_RSS_IPV6) {
2938 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV6 |
2939 ICE_FLOW_SEG_HDR_IPV_OTHER;
2940 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2941 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2943 PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
2946 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV6 |
2947 ICE_FLOW_SEG_HDR_IPV_OTHER;
2948 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2950 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
2953 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
2954 ICE_FLOW_SEG_HDR_IPV_OTHER;
2955 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2957 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2961 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2962 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2963 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2964 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2965 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2967 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
2970 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
2971 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2972 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2974 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
2977 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2978 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2979 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2981 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2985 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2986 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2987 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2988 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2989 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2991 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
2994 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
2995 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2996 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2998 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
3001 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3002 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3003 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3005 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3009 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3010 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3011 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3012 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3013 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3015 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
3018 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3019 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3020 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3022 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
3025 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3026 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3027 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3029 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3033 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3034 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3035 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3036 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3037 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3039 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
3042 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3043 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3044 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3046 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
3049 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3050 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3051 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3053 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3057 pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3060 static int ice_init_rss(struct ice_pf *pf)
3062 struct ice_hw *hw = ICE_PF_TO_HW(pf);
3063 struct ice_vsi *vsi = pf->main_vsi;
3064 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3065 struct ice_aq_get_set_rss_lut_params lut_params;
3066 struct rte_eth_rss_conf *rss_conf;
3067 struct ice_aqc_get_set_rss_keys key;
3070 bool is_safe_mode = pf->adapter->is_safe_mode;
3073 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3074 nb_q = dev->data->nb_rx_queues;
3075 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3076 vsi->rss_lut_size = pf->hash_lut_size;
3079 PMD_DRV_LOG(WARNING,
3080 "RSS is not supported as rx queues number is zero\n");
3085 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3089 if (!vsi->rss_key) {
3090 vsi->rss_key = rte_zmalloc(NULL,
3091 vsi->rss_key_size, 0);
3092 if (vsi->rss_key == NULL) {
3093 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3097 if (!vsi->rss_lut) {
3098 vsi->rss_lut = rte_zmalloc(NULL,
3099 vsi->rss_lut_size, 0);
3100 if (vsi->rss_lut == NULL) {
3101 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3102 rte_free(vsi->rss_key);
3103 vsi->rss_key = NULL;
3107 /* configure RSS key */
3108 if (!rss_conf->rss_key) {
3109 /* Calculate the default hash key */
3110 for (i = 0; i <= vsi->rss_key_size; i++)
3111 vsi->rss_key[i] = (uint8_t)rte_rand();
3113 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3114 RTE_MIN(rss_conf->rss_key_len,
3115 vsi->rss_key_size));
3117 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3118 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3122 /* init RSS LUT table */
3123 for (i = 0; i < vsi->rss_lut_size; i++)
3124 vsi->rss_lut[i] = i % nb_q;
3126 lut_params.vsi_handle = vsi->idx;
3127 lut_params.lut_size = vsi->rss_lut_size;
3128 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3129 lut_params.lut = vsi->rss_lut;
3130 lut_params.global_lut_id = 0;
3131 ret = ice_aq_set_rss_lut(hw, &lut_params);
3135 /* Enable registers for symmetric_toeplitz function. */
3136 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3137 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3138 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3139 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3141 /* RSS hash configuration */
3142 ice_rss_hash_set(pf, rss_conf->rss_hf);
3146 rte_free(vsi->rss_key);
3147 vsi->rss_key = NULL;
3148 rte_free(vsi->rss_lut);
3149 vsi->rss_lut = NULL;
3154 ice_dev_configure(struct rte_eth_dev *dev)
3156 struct ice_adapter *ad =
3157 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3158 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3161 /* Initialize to TRUE. If any of Rx queues doesn't meet the
3162 * bulk allocation or vector Rx preconditions we will reset it.
3164 ad->rx_bulk_alloc_allowed = true;
3165 ad->tx_simple_allowed = true;
3167 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3168 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3170 if (dev->data->nb_rx_queues) {
3171 ret = ice_init_rss(pf);
3173 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3182 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3183 int base_queue, int nb_queue)
3185 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3186 uint32_t val, val_tx;
3189 for (i = 0; i < nb_queue; i++) {
3191 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3192 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3193 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3194 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3196 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3197 base_queue + i, msix_vect);
3198 /* set ITR0 value */
3199 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3200 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3201 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3206 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3208 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3209 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3210 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3211 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3212 uint16_t msix_vect = vsi->msix_intr;
3213 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3214 uint16_t queue_idx = 0;
3218 /* clear Rx/Tx queue interrupt */
3219 for (i = 0; i < vsi->nb_used_qps; i++) {
3220 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3221 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3224 /* PF bind interrupt */
3225 if (rte_intr_dp_is_en(intr_handle)) {
3230 for (i = 0; i < vsi->nb_used_qps; i++) {
3232 if (!rte_intr_allow_others(intr_handle))
3233 msix_vect = ICE_MISC_VEC_ID;
3235 /* uio mapping all queue to one msix_vect */
3236 __vsi_queues_bind_intr(vsi, msix_vect,
3237 vsi->base_queue + i,
3238 vsi->nb_used_qps - i);
3240 for (; !!record && i < vsi->nb_used_qps; i++)
3241 intr_handle->intr_vec[queue_idx + i] =
3246 /* vfio 1:1 queue/msix_vect mapping */
3247 __vsi_queues_bind_intr(vsi, msix_vect,
3248 vsi->base_queue + i, 1);
3251 intr_handle->intr_vec[queue_idx + i] = msix_vect;
3259 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3261 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3262 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3263 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3264 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3265 uint16_t msix_intr, i;
3267 if (rte_intr_allow_others(intr_handle))
3268 for (i = 0; i < vsi->nb_used_qps; i++) {
3269 msix_intr = vsi->msix_intr + i;
3270 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3271 GLINT_DYN_CTL_INTENA_M |
3272 GLINT_DYN_CTL_CLEARPBA_M |
3273 GLINT_DYN_CTL_ITR_INDX_M |
3274 GLINT_DYN_CTL_WB_ON_ITR_M);
3277 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3278 GLINT_DYN_CTL_INTENA_M |
3279 GLINT_DYN_CTL_CLEARPBA_M |
3280 GLINT_DYN_CTL_ITR_INDX_M |
3281 GLINT_DYN_CTL_WB_ON_ITR_M);
3285 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3287 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3288 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3289 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3290 struct ice_vsi *vsi = pf->main_vsi;
3291 uint32_t intr_vector = 0;
3293 rte_intr_disable(intr_handle);
3295 /* check and configure queue intr-vector mapping */
3296 if ((rte_intr_cap_multiple(intr_handle) ||
3297 !RTE_ETH_DEV_SRIOV(dev).active) &&
3298 dev->data->dev_conf.intr_conf.rxq != 0) {
3299 intr_vector = dev->data->nb_rx_queues;
3300 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3301 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3302 ICE_MAX_INTR_QUEUE_NUM);
3305 if (rte_intr_efd_enable(intr_handle, intr_vector))
3309 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3310 intr_handle->intr_vec =
3311 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3313 if (!intr_handle->intr_vec) {
3315 "Failed to allocate %d rx_queues intr_vec",
3316 dev->data->nb_rx_queues);
3321 /* Map queues with MSIX interrupt */
3322 vsi->nb_used_qps = dev->data->nb_rx_queues;
3323 ice_vsi_queues_bind_intr(vsi);
3325 /* Enable interrupts for all the queues */
3326 ice_vsi_enable_queues_intr(vsi);
3328 rte_intr_enable(intr_handle);
3334 ice_get_init_link_status(struct rte_eth_dev *dev)
3336 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3338 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3339 struct ice_link_status link_status;
3342 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3343 &link_status, NULL);
3344 if (ret != ICE_SUCCESS) {
3345 PMD_DRV_LOG(ERR, "Failed to get link info");
3346 pf->init_link_up = false;
3350 if (link_status.link_info & ICE_AQ_LINK_UP)
3351 pf->init_link_up = true;
3355 ice_dev_start(struct rte_eth_dev *dev)
3357 struct rte_eth_dev_data *data = dev->data;
3358 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3359 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3360 struct ice_vsi *vsi = pf->main_vsi;
3361 uint16_t nb_rxq = 0;
3363 uint16_t max_frame_size;
3366 /* program Tx queues' context in hardware */
3367 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3368 ret = ice_tx_queue_start(dev, nb_txq);
3370 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3375 /* program Rx queues' context in hardware*/
3376 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3377 ret = ice_rx_queue_start(dev, nb_rxq);
3379 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3384 ice_set_rx_function(dev);
3385 ice_set_tx_function(dev);
3387 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3388 ETH_VLAN_EXTEND_MASK;
3389 ret = ice_vlan_offload_set(dev, mask);
3391 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3395 /* enable Rx interrput and mapping Rx queue to interrupt vector */
3396 if (ice_rxq_intr_setup(dev))
3399 /* Enable receiving broadcast packets and transmitting packets */
3400 ret = ice_set_vsi_promisc(hw, vsi->idx,
3401 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3402 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3404 if (ret != ICE_SUCCESS)
3405 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3407 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3408 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3409 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3410 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3411 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3412 ICE_AQ_LINK_EVENT_AN_COMPLETED |
3413 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3415 if (ret != ICE_SUCCESS)
3416 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3418 ice_get_init_link_status(dev);
3420 ice_dev_set_link_up(dev);
3422 /* Call get_link_info aq commond to enable/disable LSE */
3423 ice_link_update(dev, 0);
3425 pf->adapter_stopped = false;
3427 /* Set the max frame size to default value*/
3428 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3429 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3432 /* Set the max frame size to HW*/
3433 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3437 /* stop the started queues if failed to start all queues */
3439 for (i = 0; i < nb_rxq; i++)
3440 ice_rx_queue_stop(dev, i);
3442 for (i = 0; i < nb_txq; i++)
3443 ice_tx_queue_stop(dev, i);
3449 ice_dev_reset(struct rte_eth_dev *dev)
3453 if (dev->data->sriov.active)
3456 ret = ice_dev_uninit(dev);
3458 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3462 ret = ice_dev_init(dev);
3464 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3472 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3474 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3475 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3476 struct ice_vsi *vsi = pf->main_vsi;
3477 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3478 bool is_safe_mode = pf->adapter->is_safe_mode;
3482 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3483 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3484 dev_info->max_rx_queues = vsi->nb_qps;
3485 dev_info->max_tx_queues = vsi->nb_qps;
3486 dev_info->max_mac_addrs = vsi->max_macaddrs;
3487 dev_info->max_vfs = pci_dev->max_vfs;
3488 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3489 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3491 dev_info->rx_offload_capa =
3492 DEV_RX_OFFLOAD_VLAN_STRIP |
3493 DEV_RX_OFFLOAD_JUMBO_FRAME |
3494 DEV_RX_OFFLOAD_KEEP_CRC |
3495 DEV_RX_OFFLOAD_SCATTER |
3496 DEV_RX_OFFLOAD_VLAN_FILTER;
3497 dev_info->tx_offload_capa =
3498 DEV_TX_OFFLOAD_VLAN_INSERT |
3499 DEV_TX_OFFLOAD_TCP_TSO |
3500 DEV_TX_OFFLOAD_MULTI_SEGS |
3501 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3502 dev_info->flow_type_rss_offloads = 0;
3504 if (!is_safe_mode) {
3505 dev_info->rx_offload_capa |=
3506 DEV_RX_OFFLOAD_IPV4_CKSUM |
3507 DEV_RX_OFFLOAD_UDP_CKSUM |
3508 DEV_RX_OFFLOAD_TCP_CKSUM |
3509 DEV_RX_OFFLOAD_QINQ_STRIP |
3510 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3511 DEV_RX_OFFLOAD_VLAN_EXTEND |
3512 DEV_RX_OFFLOAD_RSS_HASH;
3513 dev_info->tx_offload_capa |=
3514 DEV_TX_OFFLOAD_QINQ_INSERT |
3515 DEV_TX_OFFLOAD_IPV4_CKSUM |
3516 DEV_TX_OFFLOAD_UDP_CKSUM |
3517 DEV_TX_OFFLOAD_TCP_CKSUM |
3518 DEV_TX_OFFLOAD_SCTP_CKSUM |
3519 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3520 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3521 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3524 dev_info->rx_queue_offload_capa = 0;
3525 dev_info->tx_queue_offload_capa = 0;
3527 dev_info->reta_size = pf->hash_lut_size;
3528 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3530 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3532 .pthresh = ICE_DEFAULT_RX_PTHRESH,
3533 .hthresh = ICE_DEFAULT_RX_HTHRESH,
3534 .wthresh = ICE_DEFAULT_RX_WTHRESH,
3536 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3541 dev_info->default_txconf = (struct rte_eth_txconf) {
3543 .pthresh = ICE_DEFAULT_TX_PTHRESH,
3544 .hthresh = ICE_DEFAULT_TX_HTHRESH,
3545 .wthresh = ICE_DEFAULT_TX_WTHRESH,
3547 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3548 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3552 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3553 .nb_max = ICE_MAX_RING_DESC,
3554 .nb_min = ICE_MIN_RING_DESC,
3555 .nb_align = ICE_ALIGN_RING_DESC,
3558 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3559 .nb_max = ICE_MAX_RING_DESC,
3560 .nb_min = ICE_MIN_RING_DESC,
3561 .nb_align = ICE_ALIGN_RING_DESC,
3564 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3565 ETH_LINK_SPEED_100M |
3567 ETH_LINK_SPEED_2_5G |
3569 ETH_LINK_SPEED_10G |
3570 ETH_LINK_SPEED_20G |
3573 phy_type_low = hw->port_info->phy.phy_type_low;
3574 phy_type_high = hw->port_info->phy.phy_type_high;
3576 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3577 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3579 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3580 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3581 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3583 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3584 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3586 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3587 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3588 dev_info->default_rxportconf.nb_queues = 1;
3589 dev_info->default_txportconf.nb_queues = 1;
3590 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3591 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3597 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3598 struct rte_eth_link *link)
3600 struct rte_eth_link *dst = link;
3601 struct rte_eth_link *src = &dev->data->dev_link;
3603 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3604 *(uint64_t *)src) == 0)
3611 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3612 struct rte_eth_link *link)
3614 struct rte_eth_link *dst = &dev->data->dev_link;
3615 struct rte_eth_link *src = link;
3617 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3618 *(uint64_t *)src) == 0)
3625 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3627 #define CHECK_INTERVAL 100 /* 100ms */
3628 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3629 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3630 struct ice_link_status link_status;
3631 struct rte_eth_link link, old;
3633 unsigned int rep_cnt = MAX_REPEAT_TIME;
3634 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3636 memset(&link, 0, sizeof(link));
3637 memset(&old, 0, sizeof(old));
3638 memset(&link_status, 0, sizeof(link_status));
3639 ice_atomic_read_link_status(dev, &old);
3642 /* Get link status information from hardware */
3643 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3644 &link_status, NULL);
3645 if (status != ICE_SUCCESS) {
3646 link.link_speed = ETH_SPEED_NUM_100M;
3647 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3648 PMD_DRV_LOG(ERR, "Failed to get link info");
3652 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3653 if (!wait_to_complete || link.link_status)
3656 rte_delay_ms(CHECK_INTERVAL);
3657 } while (--rep_cnt);
3659 if (!link.link_status)
3662 /* Full-duplex operation at all supported speeds */
3663 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3665 /* Parse the link status */
3666 switch (link_status.link_speed) {
3667 case ICE_AQ_LINK_SPEED_10MB:
3668 link.link_speed = ETH_SPEED_NUM_10M;
3670 case ICE_AQ_LINK_SPEED_100MB:
3671 link.link_speed = ETH_SPEED_NUM_100M;
3673 case ICE_AQ_LINK_SPEED_1000MB:
3674 link.link_speed = ETH_SPEED_NUM_1G;
3676 case ICE_AQ_LINK_SPEED_2500MB:
3677 link.link_speed = ETH_SPEED_NUM_2_5G;
3679 case ICE_AQ_LINK_SPEED_5GB:
3680 link.link_speed = ETH_SPEED_NUM_5G;
3682 case ICE_AQ_LINK_SPEED_10GB:
3683 link.link_speed = ETH_SPEED_NUM_10G;
3685 case ICE_AQ_LINK_SPEED_20GB:
3686 link.link_speed = ETH_SPEED_NUM_20G;
3688 case ICE_AQ_LINK_SPEED_25GB:
3689 link.link_speed = ETH_SPEED_NUM_25G;
3691 case ICE_AQ_LINK_SPEED_40GB:
3692 link.link_speed = ETH_SPEED_NUM_40G;
3694 case ICE_AQ_LINK_SPEED_50GB:
3695 link.link_speed = ETH_SPEED_NUM_50G;
3697 case ICE_AQ_LINK_SPEED_100GB:
3698 link.link_speed = ETH_SPEED_NUM_100G;
3700 case ICE_AQ_LINK_SPEED_UNKNOWN:
3701 PMD_DRV_LOG(ERR, "Unknown link speed");
3702 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3705 PMD_DRV_LOG(ERR, "None link speed");
3706 link.link_speed = ETH_SPEED_NUM_NONE;
3710 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3711 ETH_LINK_SPEED_FIXED);
3714 ice_atomic_write_link_status(dev, &link);
3715 if (link.link_status == old.link_status)
3721 /* Force the physical link state by getting the current PHY capabilities from
3722 * hardware and setting the PHY config based on the determined capabilities. If
3723 * link changes, link event will be triggered because both the Enable Automatic
3724 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3726 static enum ice_status
3727 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3729 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3730 struct ice_aqc_get_phy_caps_data *pcaps;
3731 struct ice_port_info *pi;
3732 enum ice_status status;
3734 if (!hw || !hw->port_info)
3735 return ICE_ERR_PARAM;
3739 pcaps = (struct ice_aqc_get_phy_caps_data *)
3740 ice_malloc(hw, sizeof(*pcaps));
3742 return ICE_ERR_NO_MEMORY;
3744 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3749 /* No change in link */
3750 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3751 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3754 cfg.phy_type_low = pcaps->phy_type_low;
3755 cfg.phy_type_high = pcaps->phy_type_high;
3756 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3757 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3758 cfg.eee_cap = pcaps->eee_cap;
3759 cfg.eeer_value = pcaps->eeer_value;
3760 cfg.link_fec_opt = pcaps->link_fec_options;
3762 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3764 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3766 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3769 ice_free(hw, pcaps);
3774 ice_dev_set_link_up(struct rte_eth_dev *dev)
3776 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3778 return ice_force_phys_link_state(hw, true);
3782 ice_dev_set_link_down(struct rte_eth_dev *dev)
3784 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786 return ice_force_phys_link_state(hw, false);
3790 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3792 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3793 struct rte_eth_dev_data *dev_data = pf->dev_data;
3794 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3796 /* check if mtu is within the allowed range */
3797 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3800 /* mtu setting is forbidden if port is start */
3801 if (dev_data->dev_started) {
3803 "port %d must be stopped before configuration",
3808 if (frame_size > ICE_ETH_MAX_LEN)
3809 dev_data->dev_conf.rxmode.offloads |=
3810 DEV_RX_OFFLOAD_JUMBO_FRAME;
3812 dev_data->dev_conf.rxmode.offloads &=
3813 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3815 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3820 static int ice_macaddr_set(struct rte_eth_dev *dev,
3821 struct rte_ether_addr *mac_addr)
3823 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3824 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3825 struct ice_vsi *vsi = pf->main_vsi;
3826 struct ice_mac_filter *f;
3830 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3831 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3835 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3836 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3841 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3845 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3846 if (ret != ICE_SUCCESS) {
3847 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3850 ret = ice_add_mac_filter(vsi, mac_addr);
3851 if (ret != ICE_SUCCESS) {
3852 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3855 rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3857 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3858 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3859 if (ret != ICE_SUCCESS)
3860 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3865 /* Add a MAC address, and update filters */
3867 ice_macaddr_add(struct rte_eth_dev *dev,
3868 struct rte_ether_addr *mac_addr,
3869 __rte_unused uint32_t index,
3870 __rte_unused uint32_t pool)
3872 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3873 struct ice_vsi *vsi = pf->main_vsi;
3876 ret = ice_add_mac_filter(vsi, mac_addr);
3877 if (ret != ICE_SUCCESS) {
3878 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3885 /* Remove a MAC address, and update filters */
3887 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3889 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3890 struct ice_vsi *vsi = pf->main_vsi;
3891 struct rte_eth_dev_data *data = dev->data;
3892 struct rte_ether_addr *macaddr;
3895 macaddr = &data->mac_addrs[index];
3896 ret = ice_remove_mac_filter(vsi, macaddr);
3898 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3904 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3906 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3907 struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
3908 struct ice_vsi *vsi = pf->main_vsi;
3911 PMD_INIT_FUNC_TRACE();
3914 * Vlan 0 is the generic filter for untagged packets
3915 * and can't be removed or added by user.
3921 ret = ice_add_vlan_filter(vsi, &vlan);
3923 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3927 ret = ice_remove_vlan_filter(vsi, &vlan);
3929 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3937 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
3938 * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
3939 * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
3940 * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
3942 * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
3943 * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
3944 * traffic in SVM, since the VLAN TPID isn't part of filtering.
3946 * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
3947 * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
3948 * part of filtering.
3951 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
3953 struct ice_vlan vlan;
3956 vlan = ICE_VLAN(0, 0);
3957 err = ice_add_vlan_filter(vsi, &vlan);
3959 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
3963 /* in SVM both VLAN 0 filters are identical */
3964 if (!ice_is_dvm_ena(&vsi->adapter->hw))
3967 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3968 err = ice_add_vlan_filter(vsi, &vlan);
3970 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
3978 * Delete the VLAN 0 filters in the same manner that they were added in
3979 * ice_vsi_add_vlan_zero.
3982 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
3984 struct ice_vlan vlan;
3987 vlan = ICE_VLAN(0, 0);
3988 err = ice_remove_vlan_filter(vsi, &vlan);
3990 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
3994 /* in SVM both VLAN 0 filters are identical */
3995 if (!ice_is_dvm_ena(&vsi->adapter->hw))
3998 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3999 err = ice_remove_vlan_filter(vsi, &vlan);
4001 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
4008 /* Configure vlan filter on or off */
4010 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4012 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4013 struct ice_vsi_ctx ctxt;
4014 uint8_t sec_flags, sw_flags2;
4017 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
4018 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
4019 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4022 vsi->info.sec_flags |= sec_flags;
4023 vsi->info.sw_flags2 |= sw_flags2;
4025 vsi->info.sec_flags &= ~sec_flags;
4026 vsi->info.sw_flags2 &= ~sw_flags2;
4028 vsi->info.sw_id = hw->port_info->sw_id;
4029 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4030 ctxt.info.valid_sections =
4031 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4032 ICE_AQ_VSI_PROP_SECURITY_VALID);
4033 ctxt.vsi_num = vsi->vsi_id;
4035 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4037 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4038 on ? "enable" : "disable");
4041 vsi->info.valid_sections |=
4042 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4043 ICE_AQ_VSI_PROP_SECURITY_VALID);
4046 /* consist with other drivers, allow untagged packet when vlan filter on */
4048 ret = ice_vsi_add_vlan_zero(vsi);
4050 ret = ice_vsi_del_vlan_zero(vsi);
4055 /* Manage VLAN stripping for the VSI for Rx */
4057 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4059 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4060 struct ice_vsi_ctx ctxt;
4061 enum ice_status status;
4064 /* do not allow modifying VLAN stripping when a port VLAN is configured
4067 if (vsi->info.port_based_inner_vlan)
4070 memset(&ctxt, 0, sizeof(ctxt));
4073 /* Strip VLAN tag from Rx packet and put it in the desc */
4074 ctxt.info.inner_vlan_flags =
4075 ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4077 /* Disable stripping. Leave tag in packet */
4078 ctxt.info.inner_vlan_flags =
4079 ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4081 /* Allow all packets untagged/tagged */
4082 ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4084 ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4086 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4088 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4089 ena ? "enable" : "disable");
4092 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4099 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4101 return ice_vsi_manage_vlan_stripping(vsi, true);
4105 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4107 return ice_vsi_manage_vlan_stripping(vsi, false);
4110 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4112 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4113 struct ice_vsi_ctx ctxt;
4114 enum ice_status status;
4117 /* do not allow modifying VLAN stripping when a port VLAN is configured
4120 if (vsi->info.port_based_outer_vlan)
4123 memset(&ctxt, 0, sizeof(ctxt));
4125 ctxt.info.valid_sections =
4126 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4127 /* clear current outer VLAN strip settings */
4128 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4129 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4130 ctxt.info.outer_vlan_flags |=
4131 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4132 ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4133 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4134 ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4136 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4138 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4141 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4148 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4150 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4151 struct ice_vsi_ctx ctxt;
4152 enum ice_status status;
4155 if (vsi->info.port_based_outer_vlan)
4158 memset(&ctxt, 0, sizeof(ctxt));
4160 ctxt.info.valid_sections =
4161 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4162 /* clear current outer VLAN strip settings */
4163 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4164 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4165 ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4166 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4168 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4170 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4173 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4180 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4182 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4185 if (ice_is_dvm_ena(hw)) {
4187 ret = ice_vsi_ena_outer_stripping(vsi);
4189 ret = ice_vsi_dis_outer_stripping(vsi);
4192 ret = ice_vsi_ena_inner_stripping(vsi);
4194 ret = ice_vsi_dis_inner_stripping(vsi);
4201 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4203 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4204 struct ice_vsi *vsi = pf->main_vsi;
4205 struct rte_eth_rxmode *rxmode;
4207 rxmode = &dev->data->dev_conf.rxmode;
4208 if (mask & ETH_VLAN_FILTER_MASK) {
4209 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4210 ice_vsi_config_vlan_filter(vsi, true);
4212 ice_vsi_config_vlan_filter(vsi, false);
4215 if (mask & ETH_VLAN_STRIP_MASK) {
4216 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4217 ice_vsi_config_vlan_stripping(vsi, true);
4219 ice_vsi_config_vlan_stripping(vsi, false);
4226 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4228 struct ice_aq_get_set_rss_lut_params lut_params;
4229 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4230 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4236 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4237 lut_params.vsi_handle = vsi->idx;
4238 lut_params.lut_size = lut_size;
4239 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4240 lut_params.lut = lut;
4241 lut_params.global_lut_id = 0;
4242 ret = ice_aq_get_rss_lut(hw, &lut_params);
4244 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4248 uint64_t *lut_dw = (uint64_t *)lut;
4249 uint16_t i, lut_size_dw = lut_size / 4;
4251 for (i = 0; i < lut_size_dw; i++)
4252 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4259 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4261 struct ice_aq_get_set_rss_lut_params lut_params;
4269 pf = ICE_VSI_TO_PF(vsi);
4270 hw = ICE_VSI_TO_HW(vsi);
4272 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4273 lut_params.vsi_handle = vsi->idx;
4274 lut_params.lut_size = lut_size;
4275 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4276 lut_params.lut = lut;
4277 lut_params.global_lut_id = 0;
4278 ret = ice_aq_set_rss_lut(hw, &lut_params);
4280 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4284 uint64_t *lut_dw = (uint64_t *)lut;
4285 uint16_t i, lut_size_dw = lut_size / 4;
4287 for (i = 0; i < lut_size_dw; i++)
4288 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4297 ice_rss_reta_update(struct rte_eth_dev *dev,
4298 struct rte_eth_rss_reta_entry64 *reta_conf,
4301 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4302 uint16_t i, lut_size = pf->hash_lut_size;
4303 uint16_t idx, shift;
4307 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4308 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4309 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4311 "The size of hash lookup table configured (%d)"
4312 "doesn't match the number hardware can "
4313 "supported (128, 512, 2048)",
4318 /* It MUST use the current LUT size to get the RSS lookup table,
4319 * otherwise if will fail with -100 error code.
4321 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
4323 PMD_DRV_LOG(ERR, "No memory can be allocated");
4326 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4330 for (i = 0; i < reta_size; i++) {
4331 idx = i / RTE_RETA_GROUP_SIZE;
4332 shift = i % RTE_RETA_GROUP_SIZE;
4333 if (reta_conf[idx].mask & (1ULL << shift))
4334 lut[i] = reta_conf[idx].reta[shift];
4336 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4337 if (ret == 0 && lut_size != reta_size) {
4339 "The size of hash lookup table is changed from (%d) to (%d)",
4340 lut_size, reta_size);
4341 pf->hash_lut_size = reta_size;
4351 ice_rss_reta_query(struct rte_eth_dev *dev,
4352 struct rte_eth_rss_reta_entry64 *reta_conf,
4355 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4356 uint16_t i, lut_size = pf->hash_lut_size;
4357 uint16_t idx, shift;
4361 if (reta_size != lut_size) {
4363 "The size of hash lookup table configured (%d)"
4364 "doesn't match the number hardware can "
4366 reta_size, lut_size);
4370 lut = rte_zmalloc(NULL, reta_size, 0);
4372 PMD_DRV_LOG(ERR, "No memory can be allocated");
4376 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4380 for (i = 0; i < reta_size; i++) {
4381 idx = i / RTE_RETA_GROUP_SIZE;
4382 shift = i % RTE_RETA_GROUP_SIZE;
4383 if (reta_conf[idx].mask & (1ULL << shift))
4384 reta_conf[idx].reta[shift] = lut[i];
4394 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4396 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4399 if (!key || key_len == 0) {
4400 PMD_DRV_LOG(DEBUG, "No key to be configured");
4402 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4404 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4408 struct ice_aqc_get_set_rss_keys *key_dw =
4409 (struct ice_aqc_get_set_rss_keys *)key;
4411 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4413 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4421 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4423 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4426 if (!key || !key_len)
4429 ret = ice_aq_get_rss_key
4431 (struct ice_aqc_get_set_rss_keys *)key);
4433 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4436 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4442 ice_rss_hash_update(struct rte_eth_dev *dev,
4443 struct rte_eth_rss_conf *rss_conf)
4445 enum ice_status status = ICE_SUCCESS;
4446 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4447 struct ice_vsi *vsi = pf->main_vsi;
4450 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4454 if (rss_conf->rss_hf == 0)
4457 /* RSS hash configuration */
4458 ice_rss_hash_set(pf, rss_conf->rss_hf);
4464 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4465 struct rte_eth_rss_conf *rss_conf)
4467 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4468 struct ice_vsi *vsi = pf->main_vsi;
4470 ice_get_rss_key(vsi, rss_conf->rss_key,
4471 &rss_conf->rss_key_len);
4473 rss_conf->rss_hf = pf->rss_hf;
4478 ice_promisc_enable(struct rte_eth_dev *dev)
4480 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4481 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4482 struct ice_vsi *vsi = pf->main_vsi;
4483 enum ice_status status;
4487 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4488 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4490 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4492 case ICE_ERR_ALREADY_EXISTS:
4493 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4497 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4505 ice_promisc_disable(struct rte_eth_dev *dev)
4507 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4508 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4509 struct ice_vsi *vsi = pf->main_vsi;
4510 enum ice_status status;
4514 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4515 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4517 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4518 if (status != ICE_SUCCESS) {
4519 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4527 ice_allmulti_enable(struct rte_eth_dev *dev)
4529 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4530 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4531 struct ice_vsi *vsi = pf->main_vsi;
4532 enum ice_status status;
4536 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4538 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4541 case ICE_ERR_ALREADY_EXISTS:
4542 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4546 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4554 ice_allmulti_disable(struct rte_eth_dev *dev)
4556 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4557 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4558 struct ice_vsi *vsi = pf->main_vsi;
4559 enum ice_status status;
4563 if (dev->data->promiscuous == 1)
4564 return 0; /* must remain in all_multicast mode */
4566 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4568 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4569 if (status != ICE_SUCCESS) {
4570 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4577 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4580 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4581 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4582 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4586 msix_intr = intr_handle->intr_vec[queue_id];
4588 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4589 GLINT_DYN_CTL_ITR_INDX_M;
4590 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4592 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4593 rte_intr_ack(&pci_dev->intr_handle);
4598 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4601 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4602 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4603 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4606 msix_intr = intr_handle->intr_vec[queue_id];
4608 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4614 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4616 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4621 ver = hw->flash.orom.major;
4622 patch = hw->flash.orom.patch;
4623 build = hw->flash.orom.build;
4625 ret = snprintf(fw_version, fw_size,
4626 "%x.%02x 0x%08x %d.%d.%d",
4627 hw->flash.nvm.major,
4628 hw->flash.nvm.minor,
4629 hw->flash.nvm.eetrack,
4632 /* add the size of '\0' */
4634 if (fw_size < (u32)ret)
4641 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4644 struct ice_vsi_ctx ctxt;
4645 uint8_t vlan_flags = 0;
4648 if (!vsi || !info) {
4649 PMD_DRV_LOG(ERR, "invalid parameters");
4654 vsi->info.port_based_inner_vlan = info->config.pvid;
4656 * If insert pvid is enabled, only tagged pkts are
4657 * allowed to be sent out.
4659 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4660 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4662 vsi->info.port_based_inner_vlan = 0;
4663 if (info->config.reject.tagged == 0)
4664 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4666 if (info->config.reject.untagged == 0)
4667 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4669 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4670 ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4671 vsi->info.inner_vlan_flags |= vlan_flags;
4672 memset(&ctxt, 0, sizeof(ctxt));
4673 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4674 ctxt.info.valid_sections =
4675 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4676 ctxt.vsi_num = vsi->vsi_id;
4678 hw = ICE_VSI_TO_HW(vsi);
4679 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4680 if (ret != ICE_SUCCESS) {
4682 "update VSI for VLAN insert failed, err %d",
4687 vsi->info.valid_sections |=
4688 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4694 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4696 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4697 struct ice_vsi *vsi = pf->main_vsi;
4698 struct rte_eth_dev_data *data = pf->dev_data;
4699 struct ice_vsi_vlan_pvid_info info;
4702 memset(&info, 0, sizeof(info));
4705 info.config.pvid = pvid;
4707 info.config.reject.tagged =
4708 data->dev_conf.txmode.hw_vlan_reject_tagged;
4709 info.config.reject.untagged =
4710 data->dev_conf.txmode.hw_vlan_reject_untagged;
4713 ret = ice_vsi_vlan_pvid_set(vsi, &info);
4715 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4723 ice_get_eeprom_length(struct rte_eth_dev *dev)
4725 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4727 return hw->flash.flash_size;
4731 ice_get_eeprom(struct rte_eth_dev *dev,
4732 struct rte_dev_eeprom_info *eeprom)
4734 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4735 enum ice_status status = ICE_SUCCESS;
4736 uint8_t *data = eeprom->data;
4738 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4740 status = ice_acquire_nvm(hw, ICE_RES_READ);
4742 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4746 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4749 ice_release_nvm(hw);
4752 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4760 ice_stat_update_32(struct ice_hw *hw,
4768 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4772 if (new_data >= *offset)
4773 *stat = (uint64_t)(new_data - *offset);
4775 *stat = (uint64_t)((new_data +
4776 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4781 ice_stat_update_40(struct ice_hw *hw,
4790 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4791 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4797 if (new_data >= *offset)
4798 *stat = new_data - *offset;
4800 *stat = (uint64_t)((new_data +
4801 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4804 *stat &= ICE_40_BIT_MASK;
4807 /* Get all the statistics of a VSI */
4809 ice_update_vsi_stats(struct ice_vsi *vsi)
4811 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4812 struct ice_eth_stats *nes = &vsi->eth_stats;
4813 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4814 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4816 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4817 vsi->offset_loaded, &oes->rx_bytes,
4819 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4820 vsi->offset_loaded, &oes->rx_unicast,
4822 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4823 vsi->offset_loaded, &oes->rx_multicast,
4824 &nes->rx_multicast);
4825 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4826 vsi->offset_loaded, &oes->rx_broadcast,
4827 &nes->rx_broadcast);
4828 /* enlarge the limitation when rx_bytes overflowed */
4829 if (vsi->offset_loaded) {
4830 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4831 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4832 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4834 vsi->old_rx_bytes = nes->rx_bytes;
4835 /* exclude CRC bytes */
4836 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4837 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4839 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4840 &oes->rx_discards, &nes->rx_discards);
4841 /* GLV_REPC not supported */
4842 /* GLV_RMPC not supported */
4843 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4844 &oes->rx_unknown_protocol,
4845 &nes->rx_unknown_protocol);
4846 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4847 vsi->offset_loaded, &oes->tx_bytes,
4849 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4850 vsi->offset_loaded, &oes->tx_unicast,
4852 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4853 vsi->offset_loaded, &oes->tx_multicast,
4854 &nes->tx_multicast);
4855 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4856 vsi->offset_loaded, &oes->tx_broadcast,
4857 &nes->tx_broadcast);
4858 /* GLV_TDPC not supported */
4859 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4860 &oes->tx_errors, &nes->tx_errors);
4861 /* enlarge the limitation when tx_bytes overflowed */
4862 if (vsi->offset_loaded) {
4863 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4864 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4865 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4867 vsi->old_tx_bytes = nes->tx_bytes;
4868 vsi->offset_loaded = true;
4870 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4872 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4873 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4874 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4875 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4876 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4877 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4878 nes->rx_unknown_protocol);
4879 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4880 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4881 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4882 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4883 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4884 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4885 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4890 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4892 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4893 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4895 /* Get statistics of struct ice_eth_stats */
4896 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4897 GLPRT_GORCL(hw->port_info->lport),
4898 pf->offset_loaded, &os->eth.rx_bytes,
4900 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4901 GLPRT_UPRCL(hw->port_info->lport),
4902 pf->offset_loaded, &os->eth.rx_unicast,
4903 &ns->eth.rx_unicast);
4904 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4905 GLPRT_MPRCL(hw->port_info->lport),
4906 pf->offset_loaded, &os->eth.rx_multicast,
4907 &ns->eth.rx_multicast);
4908 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4909 GLPRT_BPRCL(hw->port_info->lport),
4910 pf->offset_loaded, &os->eth.rx_broadcast,
4911 &ns->eth.rx_broadcast);
4912 ice_stat_update_32(hw, PRTRPB_RDPC,
4913 pf->offset_loaded, &os->eth.rx_discards,
4914 &ns->eth.rx_discards);
4915 /* enlarge the limitation when rx_bytes overflowed */
4916 if (pf->offset_loaded) {
4917 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4918 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4919 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4921 pf->old_rx_bytes = ns->eth.rx_bytes;
4923 /* Workaround: CRC size should not be included in byte statistics,
4924 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4927 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4928 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4930 /* GLPRT_REPC not supported */
4931 /* GLPRT_RMPC not supported */
4932 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4934 &os->eth.rx_unknown_protocol,
4935 &ns->eth.rx_unknown_protocol);
4936 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4937 GLPRT_GOTCL(hw->port_info->lport),
4938 pf->offset_loaded, &os->eth.tx_bytes,
4940 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4941 GLPRT_UPTCL(hw->port_info->lport),
4942 pf->offset_loaded, &os->eth.tx_unicast,
4943 &ns->eth.tx_unicast);
4944 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4945 GLPRT_MPTCL(hw->port_info->lport),
4946 pf->offset_loaded, &os->eth.tx_multicast,
4947 &ns->eth.tx_multicast);
4948 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4949 GLPRT_BPTCL(hw->port_info->lport),
4950 pf->offset_loaded, &os->eth.tx_broadcast,
4951 &ns->eth.tx_broadcast);
4952 /* enlarge the limitation when tx_bytes overflowed */
4953 if (pf->offset_loaded) {
4954 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4955 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4956 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4958 pf->old_tx_bytes = ns->eth.tx_bytes;
4959 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4960 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4962 /* GLPRT_TEPC not supported */
4964 /* additional port specific stats */
4965 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4966 pf->offset_loaded, &os->tx_dropped_link_down,
4967 &ns->tx_dropped_link_down);
4968 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4969 pf->offset_loaded, &os->crc_errors,
4971 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4972 pf->offset_loaded, &os->illegal_bytes,
4973 &ns->illegal_bytes);
4974 /* GLPRT_ERRBC not supported */
4975 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4976 pf->offset_loaded, &os->mac_local_faults,
4977 &ns->mac_local_faults);
4978 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4979 pf->offset_loaded, &os->mac_remote_faults,
4980 &ns->mac_remote_faults);
4982 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4983 pf->offset_loaded, &os->rx_len_errors,
4984 &ns->rx_len_errors);
4986 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4987 pf->offset_loaded, &os->link_xon_rx,
4989 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4990 pf->offset_loaded, &os->link_xoff_rx,
4992 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4993 pf->offset_loaded, &os->link_xon_tx,
4995 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4996 pf->offset_loaded, &os->link_xoff_tx,
4998 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4999 GLPRT_PRC64L(hw->port_info->lport),
5000 pf->offset_loaded, &os->rx_size_64,
5002 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
5003 GLPRT_PRC127L(hw->port_info->lport),
5004 pf->offset_loaded, &os->rx_size_127,
5006 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
5007 GLPRT_PRC255L(hw->port_info->lport),
5008 pf->offset_loaded, &os->rx_size_255,
5010 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
5011 GLPRT_PRC511L(hw->port_info->lport),
5012 pf->offset_loaded, &os->rx_size_511,
5014 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
5015 GLPRT_PRC1023L(hw->port_info->lport),
5016 pf->offset_loaded, &os->rx_size_1023,
5018 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
5019 GLPRT_PRC1522L(hw->port_info->lport),
5020 pf->offset_loaded, &os->rx_size_1522,
5022 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
5023 GLPRT_PRC9522L(hw->port_info->lport),
5024 pf->offset_loaded, &os->rx_size_big,
5026 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
5027 pf->offset_loaded, &os->rx_undersize,
5029 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
5030 pf->offset_loaded, &os->rx_fragments,
5032 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5033 pf->offset_loaded, &os->rx_oversize,
5035 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5036 pf->offset_loaded, &os->rx_jabber,
5038 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5039 GLPRT_PTC64L(hw->port_info->lport),
5040 pf->offset_loaded, &os->tx_size_64,
5042 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5043 GLPRT_PTC127L(hw->port_info->lport),
5044 pf->offset_loaded, &os->tx_size_127,
5046 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5047 GLPRT_PTC255L(hw->port_info->lport),
5048 pf->offset_loaded, &os->tx_size_255,
5050 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5051 GLPRT_PTC511L(hw->port_info->lport),
5052 pf->offset_loaded, &os->tx_size_511,
5054 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5055 GLPRT_PTC1023L(hw->port_info->lport),
5056 pf->offset_loaded, &os->tx_size_1023,
5058 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5059 GLPRT_PTC1522L(hw->port_info->lport),
5060 pf->offset_loaded, &os->tx_size_1522,
5062 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5063 GLPRT_PTC9522L(hw->port_info->lport),
5064 pf->offset_loaded, &os->tx_size_big,
5067 /* GLPRT_MSPDC not supported */
5068 /* GLPRT_XEC not supported */
5070 pf->offset_loaded = true;
5073 ice_update_vsi_stats(pf->main_vsi);
5076 /* Get all statistics of a port */
5078 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5080 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5081 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5082 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5084 /* call read registers - updates values, now write them to struct */
5085 ice_read_stats_registers(pf, hw);
5087 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5088 pf->main_vsi->eth_stats.rx_multicast +
5089 pf->main_vsi->eth_stats.rx_broadcast -
5090 pf->main_vsi->eth_stats.rx_discards;
5091 stats->opackets = ns->eth.tx_unicast +
5092 ns->eth.tx_multicast +
5093 ns->eth.tx_broadcast;
5094 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
5095 stats->obytes = ns->eth.tx_bytes;
5096 stats->oerrors = ns->eth.tx_errors +
5097 pf->main_vsi->eth_stats.tx_errors;
5100 stats->imissed = ns->eth.rx_discards +
5101 pf->main_vsi->eth_stats.rx_discards;
5102 stats->ierrors = ns->crc_errors +
5104 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5106 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5107 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
5108 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5109 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5110 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5111 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5112 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5113 pf->main_vsi->eth_stats.rx_discards);
5114 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5115 ns->eth.rx_unknown_protocol);
5116 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
5117 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5118 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5119 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5120 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5121 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5122 pf->main_vsi->eth_stats.tx_discards);
5123 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
5125 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
5126 ns->tx_dropped_link_down);
5127 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5128 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
5130 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
5131 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
5132 ns->mac_local_faults);
5133 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
5134 ns->mac_remote_faults);
5135 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
5136 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
5137 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
5138 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
5139 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
5140 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
5141 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
5142 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
5143 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
5144 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
5145 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
5146 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
5147 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
5148 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
5149 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
5150 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
5151 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
5152 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
5153 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
5154 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
5155 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
5156 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
5157 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
5158 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5162 /* Reset the statistics */
5164 ice_stats_reset(struct rte_eth_dev *dev)
5166 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5167 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5169 /* Mark PF and VSI stats to update the offset, aka "reset" */
5170 pf->offset_loaded = false;
5172 pf->main_vsi->offset_loaded = false;
5174 /* read the stats, reading current register values into offset */
5175 ice_read_stats_registers(pf, hw);
5181 ice_xstats_calc_num(void)
5185 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5191 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5194 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5195 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5198 struct ice_hw_port_stats *hw_stats = &pf->stats;
5200 count = ice_xstats_calc_num();
5204 ice_read_stats_registers(pf, hw);
5211 /* Get stats from ice_eth_stats struct */
5212 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5213 xstats[count].value =
5214 *(uint64_t *)((char *)&hw_stats->eth +
5215 ice_stats_strings[i].offset);
5216 xstats[count].id = count;
5220 /* Get individiual stats from ice_hw_port struct */
5221 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5222 xstats[count].value =
5223 *(uint64_t *)((char *)hw_stats +
5224 ice_hw_port_strings[i].offset);
5225 xstats[count].id = count;
5232 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5233 struct rte_eth_xstat_name *xstats_names,
5234 __rte_unused unsigned int limit)
5236 unsigned int count = 0;
5240 return ice_xstats_calc_num();
5242 /* Note: limit checked in rte_eth_xstats_names() */
5244 /* Get stats from ice_eth_stats struct */
5245 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5246 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5247 sizeof(xstats_names[count].name));
5251 /* Get individiual stats from ice_hw_port struct */
5252 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5253 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5254 sizeof(xstats_names[count].name));
5262 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
5263 enum rte_filter_type filter_type,
5264 enum rte_filter_op filter_op,
5272 switch (filter_type) {
5273 case RTE_ETH_FILTER_GENERIC:
5274 if (filter_op != RTE_ETH_FILTER_GET)
5276 *(const void **)arg = &ice_flow_ops;
5279 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5288 /* Add UDP tunneling port */
5290 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5291 struct rte_eth_udp_tunnel *udp_tunnel)
5294 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5296 if (udp_tunnel == NULL)
5299 switch (udp_tunnel->prot_type) {
5300 case RTE_TUNNEL_TYPE_VXLAN:
5301 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5304 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5312 /* Delete UDP tunneling port */
5314 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5315 struct rte_eth_udp_tunnel *udp_tunnel)
5318 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5320 if (udp_tunnel == NULL)
5323 switch (udp_tunnel->prot_type) {
5324 case RTE_TUNNEL_TYPE_VXLAN:
5325 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5328 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5337 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5338 struct rte_pci_device *pci_dev)
5340 return rte_eth_dev_pci_generic_probe(pci_dev,
5341 sizeof(struct ice_adapter),
5346 ice_pci_remove(struct rte_pci_device *pci_dev)
5348 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5351 static struct rte_pci_driver rte_ice_pmd = {
5352 .id_table = pci_id_ice_map,
5353 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5354 .probe = ice_pci_probe,
5355 .remove = ice_pci_remove,
5359 * Driver initialization routine.
5360 * Invoked once at EAL init time.
5361 * Register itself as the [Poll Mode] Driver of PCI devices.
5363 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5364 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5365 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5366 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5367 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5368 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5369 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5371 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5372 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5373 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5374 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5376 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5377 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5379 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5380 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);