1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <ethdev_pci.h>
13 #include <rte_tailq.h>
15 #include "eal_firmware.h"
17 #include "base/ice_sched.h"
18 #include "base/ice_flow.h"
19 #include "base/ice_dcb.h"
20 #include "base/ice_common.h"
22 #include "rte_pmd_ice.h"
23 #include "ice_ethdev.h"
25 #include "ice_generic_flow.h"
28 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
29 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
30 #define ICE_PROTO_XTR_ARG "proto_xtr"
31 #define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask"
32 #define ICE_ONE_PPS_OUT_ARG "pps_out"
34 static const char * const ice_valid_args[] = {
35 ICE_SAFE_MODE_SUPPORT_ARG,
36 ICE_PIPELINE_MODE_SUPPORT_ARG,
38 ICE_HW_DEBUG_MASK_ARG,
43 #define NSEC_PER_SEC 1000000000
44 #define PPS_OUT_DELAY_NS 1
46 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
47 .name = "intel_pmd_dynfield_proto_xtr_metadata",
48 .size = sizeof(uint32_t),
49 .align = __alignof__(uint32_t),
53 struct proto_xtr_ol_flag {
54 const struct rte_mbuf_dynflag param;
59 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
61 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
63 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
64 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
66 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
67 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
69 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
70 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
71 [PROTO_XTR_IPV6_FLOW] = {
72 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
73 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
75 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
76 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
77 [PROTO_XTR_IP_OFFSET] = {
78 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
79 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
82 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
83 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
84 #define ICE_MAX_RES_DESC_NUM 1024
86 static int ice_dev_configure(struct rte_eth_dev *dev);
87 static int ice_dev_start(struct rte_eth_dev *dev);
88 static int ice_dev_stop(struct rte_eth_dev *dev);
89 static int ice_dev_close(struct rte_eth_dev *dev);
90 static int ice_dev_reset(struct rte_eth_dev *dev);
91 static int ice_dev_info_get(struct rte_eth_dev *dev,
92 struct rte_eth_dev_info *dev_info);
93 static int ice_link_update(struct rte_eth_dev *dev,
94 int wait_to_complete);
95 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
96 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
98 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
99 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
100 static int ice_rss_reta_update(struct rte_eth_dev *dev,
101 struct rte_eth_rss_reta_entry64 *reta_conf,
103 static int ice_rss_reta_query(struct rte_eth_dev *dev,
104 struct rte_eth_rss_reta_entry64 *reta_conf,
106 static int ice_rss_hash_update(struct rte_eth_dev *dev,
107 struct rte_eth_rss_conf *rss_conf);
108 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
109 struct rte_eth_rss_conf *rss_conf);
110 static int ice_promisc_enable(struct rte_eth_dev *dev);
111 static int ice_promisc_disable(struct rte_eth_dev *dev);
112 static int ice_allmulti_enable(struct rte_eth_dev *dev);
113 static int ice_allmulti_disable(struct rte_eth_dev *dev);
114 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
117 static int ice_macaddr_set(struct rte_eth_dev *dev,
118 struct rte_ether_addr *mac_addr);
119 static int ice_macaddr_add(struct rte_eth_dev *dev,
120 struct rte_ether_addr *mac_addr,
121 __rte_unused uint32_t index,
123 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
124 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
126 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
128 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
130 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
131 uint16_t pvid, int on);
132 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
133 static int ice_get_eeprom(struct rte_eth_dev *dev,
134 struct rte_dev_eeprom_info *eeprom);
135 static int ice_stats_get(struct rte_eth_dev *dev,
136 struct rte_eth_stats *stats);
137 static int ice_stats_reset(struct rte_eth_dev *dev);
138 static int ice_xstats_get(struct rte_eth_dev *dev,
139 struct rte_eth_xstat *xstats, unsigned int n);
140 static int ice_xstats_get_names(struct rte_eth_dev *dev,
141 struct rte_eth_xstat_name *xstats_names,
143 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev,
144 const struct rte_flow_ops **ops);
145 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
146 struct rte_eth_udp_tunnel *udp_tunnel);
147 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
148 struct rte_eth_udp_tunnel *udp_tunnel);
150 static const struct rte_pci_id pci_id_ice_map[] = {
151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
157 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
159 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
164 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
165 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
166 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
167 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
168 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
169 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
170 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
171 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
172 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
173 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
174 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
175 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
176 { .vendor_id = 0, /* sentinel */ },
179 static const struct eth_dev_ops ice_eth_dev_ops = {
180 .dev_configure = ice_dev_configure,
181 .dev_start = ice_dev_start,
182 .dev_stop = ice_dev_stop,
183 .dev_close = ice_dev_close,
184 .dev_reset = ice_dev_reset,
185 .dev_set_link_up = ice_dev_set_link_up,
186 .dev_set_link_down = ice_dev_set_link_down,
187 .rx_queue_start = ice_rx_queue_start,
188 .rx_queue_stop = ice_rx_queue_stop,
189 .tx_queue_start = ice_tx_queue_start,
190 .tx_queue_stop = ice_tx_queue_stop,
191 .rx_queue_setup = ice_rx_queue_setup,
192 .rx_queue_release = ice_rx_queue_release,
193 .tx_queue_setup = ice_tx_queue_setup,
194 .tx_queue_release = ice_tx_queue_release,
195 .dev_infos_get = ice_dev_info_get,
196 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
197 .link_update = ice_link_update,
198 .mtu_set = ice_mtu_set,
199 .mac_addr_set = ice_macaddr_set,
200 .mac_addr_add = ice_macaddr_add,
201 .mac_addr_remove = ice_macaddr_remove,
202 .vlan_filter_set = ice_vlan_filter_set,
203 .vlan_offload_set = ice_vlan_offload_set,
204 .reta_update = ice_rss_reta_update,
205 .reta_query = ice_rss_reta_query,
206 .rss_hash_update = ice_rss_hash_update,
207 .rss_hash_conf_get = ice_rss_hash_conf_get,
208 .promiscuous_enable = ice_promisc_enable,
209 .promiscuous_disable = ice_promisc_disable,
210 .allmulticast_enable = ice_allmulti_enable,
211 .allmulticast_disable = ice_allmulti_disable,
212 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
213 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
214 .fw_version_get = ice_fw_version_get,
215 .vlan_pvid_set = ice_vlan_pvid_set,
216 .rxq_info_get = ice_rxq_info_get,
217 .txq_info_get = ice_txq_info_get,
218 .rx_burst_mode_get = ice_rx_burst_mode_get,
219 .tx_burst_mode_get = ice_tx_burst_mode_get,
220 .get_eeprom_length = ice_get_eeprom_length,
221 .get_eeprom = ice_get_eeprom,
222 .stats_get = ice_stats_get,
223 .stats_reset = ice_stats_reset,
224 .xstats_get = ice_xstats_get,
225 .xstats_get_names = ice_xstats_get_names,
226 .xstats_reset = ice_stats_reset,
227 .flow_ops_get = ice_dev_flow_ops_get,
228 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
229 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
230 .tx_done_cleanup = ice_tx_done_cleanup,
231 .get_monitor_addr = ice_get_monitor_addr,
234 /* store statistics names and its offset in stats structure */
235 struct ice_xstats_name_off {
236 char name[RTE_ETH_XSTATS_NAME_SIZE];
240 static const struct ice_xstats_name_off ice_stats_strings[] = {
241 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
242 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
243 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
244 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
245 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
246 rx_unknown_protocol)},
247 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
248 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
249 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
250 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
253 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
254 sizeof(ice_stats_strings[0]))
256 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
257 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
258 tx_dropped_link_down)},
259 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
260 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
262 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
263 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
265 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
267 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
269 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
270 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
271 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
272 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
273 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
274 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
276 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
278 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
280 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
282 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
284 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
286 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
288 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
290 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
291 mac_short_pkt_dropped)},
292 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
294 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
295 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
296 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
298 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
300 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
302 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
304 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
306 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
310 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
311 sizeof(ice_hw_port_strings[0]))
314 ice_init_controlq_parameter(struct ice_hw *hw)
316 /* fields for adminq */
317 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
318 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
319 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
320 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
322 /* fields for mailboxq, DPDK used as PF host */
323 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
324 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
325 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
326 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
330 lookup_proto_xtr_type(const char *xtr_name)
334 enum proto_xtr_type type;
336 { "vlan", PROTO_XTR_VLAN },
337 { "ipv4", PROTO_XTR_IPV4 },
338 { "ipv6", PROTO_XTR_IPV6 },
339 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
340 { "tcp", PROTO_XTR_TCP },
341 { "ip_offset", PROTO_XTR_IP_OFFSET },
345 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
346 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
347 return xtr_type_map[i].type;
354 * Parse elem, the elem could be single number/range or '(' ')' group
355 * 1) A single number elem, it's just a simple digit. e.g. 9
356 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
357 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
358 * Within group elem, '-' used for a range separator;
359 * ',' used for a single number.
362 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
364 const char *str = input;
369 while (isblank(*str))
372 if (!isdigit(*str) && *str != '(')
375 /* process single number or single range of number */
378 idx = strtoul(str, &end, 10);
379 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
382 while (isblank(*end))
388 /* process single <number>-<number> */
391 while (isblank(*end))
397 idx = strtoul(end, &end, 10);
398 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
402 while (isblank(*end))
409 for (idx = RTE_MIN(min, max);
410 idx <= RTE_MAX(min, max); idx++)
411 devargs->proto_xtr[idx] = xtr_type;
416 /* process set within bracket */
418 while (isblank(*str))
423 min = ICE_MAX_QUEUE_NUM;
425 /* go ahead to the first digit */
426 while (isblank(*str))
431 /* get the digit value */
433 idx = strtoul(str, &end, 10);
434 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
437 /* go ahead to separator '-',',' and ')' */
438 while (isblank(*end))
441 if (min == ICE_MAX_QUEUE_NUM)
443 else /* avoid continuous '-' */
445 } else if (*end == ',' || *end == ')') {
447 if (min == ICE_MAX_QUEUE_NUM)
450 for (idx = RTE_MIN(min, max);
451 idx <= RTE_MAX(min, max); idx++)
452 devargs->proto_xtr[idx] = xtr_type;
454 min = ICE_MAX_QUEUE_NUM;
460 } while (*end != ')' && *end != '\0');
466 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
468 const char *queue_start;
473 while (isblank(*queues))
476 if (*queues != '[') {
477 xtr_type = lookup_proto_xtr_type(queues);
481 devargs->proto_xtr_dflt = xtr_type;
488 while (isblank(*queues))
493 queue_start = queues;
495 /* go across a complete bracket */
496 if (*queue_start == '(') {
497 queues += strcspn(queues, ")");
502 /* scan the separator ':' */
503 queues += strcspn(queues, ":");
504 if (*queues++ != ':')
506 while (isblank(*queues))
509 for (idx = 0; ; idx++) {
510 if (isblank(queues[idx]) ||
511 queues[idx] == ',' ||
512 queues[idx] == ']' ||
516 if (idx > sizeof(xtr_name) - 2)
519 xtr_name[idx] = queues[idx];
521 xtr_name[idx] = '\0';
522 xtr_type = lookup_proto_xtr_type(xtr_name);
528 while (isblank(*queues) || *queues == ',' || *queues == ']')
531 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
533 } while (*queues != '\0');
539 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
542 struct ice_devargs *devargs = extra_args;
544 if (value == NULL || extra_args == NULL)
547 if (parse_queue_proto_xtr(value, devargs) < 0) {
549 "The protocol extraction parameter is wrong : '%s'",
558 ice_check_proto_xtr_support(struct ice_hw *hw)
560 #define FLX_REG(val, fld, idx) \
561 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
562 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
569 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
571 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
572 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
574 ICE_PROT_IPV4_OF_OR_S,
575 ICE_PROT_IPV4_OF_OR_S },
576 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
578 ICE_PROT_IPV6_OF_OR_S,
579 ICE_PROT_IPV6_OF_OR_S },
580 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
582 ICE_PROT_IPV6_OF_OR_S,
583 ICE_PROT_IPV6_OF_OR_S },
584 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
586 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
587 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
589 ICE_PROT_IPV4_OF_OR_S,
590 ICE_PROT_IPV6_OF_OR_S },
594 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
595 uint32_t rxdid = xtr_sets[i].rxdid;
598 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
599 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
601 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
602 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
603 ice_proto_xtr_hw_support[i] = true;
606 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
607 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
609 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
610 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
611 ice_proto_xtr_hw_support[i] = true;
617 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
620 struct pool_entry *entry;
625 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
628 "Failed to allocate memory for resource pool");
632 /* queue heap initialize */
633 pool->num_free = num;
636 LIST_INIT(&pool->alloc_list);
637 LIST_INIT(&pool->free_list);
639 /* Initialize element */
643 LIST_INSERT_HEAD(&pool->free_list, entry, next);
648 ice_res_pool_alloc(struct ice_res_pool_info *pool,
651 struct pool_entry *entry, *valid_entry;
654 PMD_INIT_LOG(ERR, "Invalid parameter");
658 if (pool->num_free < num) {
659 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
660 num, pool->num_free);
665 /* Lookup in free list and find most fit one */
666 LIST_FOREACH(entry, &pool->free_list, next) {
667 if (entry->len >= num) {
669 if (entry->len == num) {
674 valid_entry->len > entry->len)
679 /* Not find one to satisfy the request, return */
681 PMD_INIT_LOG(ERR, "No valid entry found");
685 * The entry have equal queue number as requested,
686 * remove it from alloc_list.
688 if (valid_entry->len == num) {
689 LIST_REMOVE(valid_entry, next);
692 * The entry have more numbers than requested,
693 * create a new entry for alloc_list and minus its
694 * queue base and number in free_list.
696 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
699 "Failed to allocate memory for "
703 entry->base = valid_entry->base;
705 valid_entry->base += num;
706 valid_entry->len -= num;
710 /* Insert it into alloc list, not sorted */
711 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
713 pool->num_free -= valid_entry->len;
714 pool->num_alloc += valid_entry->len;
716 return valid_entry->base + pool->base;
720 ice_res_pool_destroy(struct ice_res_pool_info *pool)
722 struct pool_entry *entry, *next_entry;
727 for (entry = LIST_FIRST(&pool->alloc_list);
728 entry && (next_entry = LIST_NEXT(entry, next), 1);
729 entry = next_entry) {
730 LIST_REMOVE(entry, next);
734 for (entry = LIST_FIRST(&pool->free_list);
735 entry && (next_entry = LIST_NEXT(entry, next), 1);
736 entry = next_entry) {
737 LIST_REMOVE(entry, next);
744 LIST_INIT(&pool->alloc_list);
745 LIST_INIT(&pool->free_list);
749 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
751 /* Set VSI LUT selection */
752 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
753 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
754 /* Set Hash scheme */
755 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
756 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
758 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
761 static enum ice_status
762 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
763 struct ice_aqc_vsi_props *info,
764 uint8_t enabled_tcmap)
766 uint16_t bsf, qp_idx;
768 /* default tc 0 now. Multi-TC supporting need to be done later.
769 * Configure TC and queue mapping parameters, for enabled TC,
770 * allocate qpnum_per_tc queues to this traffic.
772 if (enabled_tcmap != 0x01) {
773 PMD_INIT_LOG(ERR, "only TC0 is supported");
777 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
778 bsf = rte_bsf32(vsi->nb_qps);
779 /* Adjust the queue number to actual queues that can be applied */
780 vsi->nb_qps = 0x1 << bsf;
783 /* Set tc and queue mapping with VSI */
784 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
785 ICE_AQ_VSI_TC_Q_OFFSET_S) |
786 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
788 /* Associate queue number with VSI */
789 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
790 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
791 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
792 info->valid_sections |=
793 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
794 /* Set the info.ingress_table and info.egress_table
795 * for UP translate table. Now just set it to 1:1 map by default
796 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
798 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
799 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
800 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
801 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
806 ice_init_mac_address(struct rte_eth_dev *dev)
808 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
810 if (!rte_is_unicast_ether_addr
811 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
812 PMD_INIT_LOG(ERR, "Invalid MAC address");
817 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
818 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
820 dev->data->mac_addrs =
821 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0);
822 if (!dev->data->mac_addrs) {
824 "Failed to allocate memory to store mac address");
827 /* store it to dev data */
829 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
830 &dev->data->mac_addrs[0]);
834 /* Find out specific MAC filter */
835 static struct ice_mac_filter *
836 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
838 struct ice_mac_filter *f;
840 TAILQ_FOREACH(f, &vsi->mac_list, next) {
841 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
849 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
851 struct ice_fltr_list_entry *m_list_itr = NULL;
852 struct ice_mac_filter *f;
853 struct LIST_HEAD_TYPE list_head;
854 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
857 /* If it's added and configured, return */
858 f = ice_find_mac_filter(vsi, mac_addr);
860 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
864 INIT_LIST_HEAD(&list_head);
866 m_list_itr = (struct ice_fltr_list_entry *)
867 ice_malloc(hw, sizeof(*m_list_itr));
872 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
873 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
874 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
875 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
876 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
877 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
878 m_list_itr->fltr_info.vsi_handle = vsi->idx;
880 LIST_ADD(&m_list_itr->list_entry, &list_head);
883 ret = ice_add_mac(hw, &list_head);
884 if (ret != ICE_SUCCESS) {
885 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
889 /* Add the mac addr into mac list */
890 f = rte_zmalloc(NULL, sizeof(*f), 0);
892 PMD_DRV_LOG(ERR, "failed to allocate memory");
896 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
897 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
903 rte_free(m_list_itr);
908 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
910 struct ice_fltr_list_entry *m_list_itr = NULL;
911 struct ice_mac_filter *f;
912 struct LIST_HEAD_TYPE list_head;
913 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
916 /* Can't find it, return an error */
917 f = ice_find_mac_filter(vsi, mac_addr);
921 INIT_LIST_HEAD(&list_head);
923 m_list_itr = (struct ice_fltr_list_entry *)
924 ice_malloc(hw, sizeof(*m_list_itr));
929 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
930 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
931 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
932 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
933 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
934 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
935 m_list_itr->fltr_info.vsi_handle = vsi->idx;
937 LIST_ADD(&m_list_itr->list_entry, &list_head);
939 /* remove the mac filter */
940 ret = ice_remove_mac(hw, &list_head);
941 if (ret != ICE_SUCCESS) {
942 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
947 /* Remove the mac addr from mac list */
948 TAILQ_REMOVE(&vsi->mac_list, f, next);
954 rte_free(m_list_itr);
958 /* Find out specific VLAN filter */
959 static struct ice_vlan_filter *
960 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
962 struct ice_vlan_filter *f;
964 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
965 if (vlan->tpid == f->vlan_info.vlan.tpid &&
966 vlan->vid == f->vlan_info.vlan.vid)
974 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
976 struct ice_fltr_list_entry *v_list_itr = NULL;
977 struct ice_vlan_filter *f;
978 struct LIST_HEAD_TYPE list_head;
982 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
985 hw = ICE_VSI_TO_HW(vsi);
987 /* If it's added and configured, return. */
988 f = ice_find_vlan_filter(vsi, vlan);
990 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
994 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
997 INIT_LIST_HEAD(&list_head);
999 v_list_itr = (struct ice_fltr_list_entry *)
1000 ice_malloc(hw, sizeof(*v_list_itr));
1005 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1006 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1007 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1008 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1009 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1010 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1011 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1012 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1014 LIST_ADD(&v_list_itr->list_entry, &list_head);
1017 ret = ice_add_vlan(hw, &list_head);
1018 if (ret != ICE_SUCCESS) {
1019 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1024 /* Add vlan into vlan list */
1025 f = rte_zmalloc(NULL, sizeof(*f), 0);
1027 PMD_DRV_LOG(ERR, "failed to allocate memory");
1031 f->vlan_info.vlan.tpid = vlan->tpid;
1032 f->vlan_info.vlan.vid = vlan->vid;
1033 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1039 rte_free(v_list_itr);
1044 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1046 struct ice_fltr_list_entry *v_list_itr = NULL;
1047 struct ice_vlan_filter *f;
1048 struct LIST_HEAD_TYPE list_head;
1052 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1055 hw = ICE_VSI_TO_HW(vsi);
1057 /* Can't find it, return an error */
1058 f = ice_find_vlan_filter(vsi, vlan);
1062 INIT_LIST_HEAD(&list_head);
1064 v_list_itr = (struct ice_fltr_list_entry *)
1065 ice_malloc(hw, sizeof(*v_list_itr));
1071 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1072 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1073 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1074 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1075 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1076 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1077 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1078 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1080 LIST_ADD(&v_list_itr->list_entry, &list_head);
1082 /* remove the vlan filter */
1083 ret = ice_remove_vlan(hw, &list_head);
1084 if (ret != ICE_SUCCESS) {
1085 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1090 /* Remove the vlan id from vlan list */
1091 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1097 rte_free(v_list_itr);
1102 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1104 struct ice_mac_filter *m_f;
1105 struct ice_vlan_filter *v_f;
1109 if (!vsi || !vsi->mac_num)
1112 TAILQ_FOREACH_SAFE(m_f, &vsi->mac_list, next, temp) {
1113 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1114 if (ret != ICE_SUCCESS) {
1120 if (vsi->vlan_num == 0)
1123 TAILQ_FOREACH_SAFE(v_f, &vsi->vlan_list, next, temp) {
1124 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1125 if (ret != ICE_SUCCESS) {
1137 ice_pf_enable_irq0(struct ice_hw *hw)
1139 /* reset the registers */
1140 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1141 ICE_READ_REG(hw, PFINT_OICR);
1144 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1145 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1146 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1148 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1149 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1150 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1151 PFINT_OICR_CTL_ITR_INDX_M) |
1152 PFINT_OICR_CTL_CAUSE_ENA_M);
1154 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1155 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1156 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1157 PFINT_FW_CTL_ITR_INDX_M) |
1158 PFINT_FW_CTL_CAUSE_ENA_M);
1160 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1163 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1164 GLINT_DYN_CTL_INTENA_M |
1165 GLINT_DYN_CTL_CLEARPBA_M |
1166 GLINT_DYN_CTL_ITR_INDX_M);
1173 ice_pf_disable_irq0(struct ice_hw *hw)
1175 /* Disable all interrupt types */
1176 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1182 ice_handle_aq_msg(struct rte_eth_dev *dev)
1184 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1185 struct ice_ctl_q_info *cq = &hw->adminq;
1186 struct ice_rq_event_info event;
1187 uint16_t pending, opcode;
1190 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1191 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1192 if (!event.msg_buf) {
1193 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1199 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1201 if (ret != ICE_SUCCESS) {
1203 "Failed to read msg from AdminQ, "
1205 hw->adminq.sq_last_status);
1208 opcode = rte_le_to_cpu_16(event.desc.opcode);
1211 case ice_aqc_opc_get_link_status:
1212 ret = ice_link_update(dev, 0);
1214 rte_eth_dev_callback_process
1215 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1218 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1223 rte_free(event.msg_buf);
1228 * Interrupt handler triggered by NIC for handling
1229 * specific interrupt.
1232 * Pointer to interrupt handle.
1234 * The address of parameter (struct rte_eth_dev *) regsitered before.
1240 ice_interrupt_handler(void *param)
1242 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1243 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1251 uint32_t int_fw_ctl;
1254 /* Disable interrupt */
1255 ice_pf_disable_irq0(hw);
1257 /* read out interrupt causes */
1258 oicr = ICE_READ_REG(hw, PFINT_OICR);
1260 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1263 /* No interrupt event indicated */
1264 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1265 PMD_DRV_LOG(INFO, "No interrupt event");
1270 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1271 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1272 ice_handle_aq_msg(dev);
1275 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1276 PMD_DRV_LOG(INFO, "OICR: link state change event");
1277 ret = ice_link_update(dev, 0);
1279 rte_eth_dev_callback_process
1280 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1284 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1285 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1286 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1287 if (reg & GL_MDET_TX_PQM_VALID_M) {
1288 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1289 GL_MDET_TX_PQM_PF_NUM_S;
1290 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1291 GL_MDET_TX_PQM_MAL_TYPE_S;
1292 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1293 GL_MDET_TX_PQM_QNUM_S;
1295 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1296 "%d by PQM on TX queue %d PF# %d",
1297 event, queue, pf_num);
1300 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1301 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1302 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1303 GL_MDET_TX_TCLAN_PF_NUM_S;
1304 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1305 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1306 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1307 GL_MDET_TX_TCLAN_QNUM_S;
1309 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1310 "%d by TCLAN on TX queue %d PF# %d",
1311 event, queue, pf_num);
1315 /* Enable interrupt */
1316 ice_pf_enable_irq0(hw);
1317 rte_intr_ack(dev->intr_handle);
1321 ice_init_proto_xtr(struct rte_eth_dev *dev)
1323 struct ice_adapter *ad =
1324 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1325 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1326 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1327 const struct proto_xtr_ol_flag *ol_flag;
1328 bool proto_xtr_enable = false;
1332 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1333 if (unlikely(pf->proto_xtr == NULL)) {
1334 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1338 for (i = 0; i < pf->lan_nb_qps; i++) {
1339 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1340 ad->devargs.proto_xtr[i] :
1341 ad->devargs.proto_xtr_dflt;
1343 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1344 uint8_t type = pf->proto_xtr[i];
1346 ice_proto_xtr_ol_flag_params[type].required = true;
1347 proto_xtr_enable = true;
1351 if (likely(!proto_xtr_enable))
1354 ice_check_proto_xtr_support(hw);
1356 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1357 if (unlikely(offset == -1)) {
1359 "Protocol extraction metadata is disabled in mbuf with error %d",
1365 "Protocol extraction metadata offset in mbuf is : %d",
1367 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1369 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1370 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1372 if (!ol_flag->required)
1375 if (!ice_proto_xtr_hw_support[i]) {
1377 "Protocol extraction type %u is not supported in hardware",
1379 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1383 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1384 if (unlikely(offset == -1)) {
1386 "Protocol extraction offload '%s' failed to register with error %d",
1387 ol_flag->param.name, -rte_errno);
1389 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1394 "Protocol extraction offload '%s' offset in mbuf is : %d",
1395 ol_flag->param.name, offset);
1396 *ol_flag->ol_flag = 1ULL << offset;
1400 /* Initialize SW parameters of PF */
1402 ice_pf_sw_init(struct rte_eth_dev *dev)
1404 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1405 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1408 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1409 hw->func_caps.common_cap.num_rxq);
1411 pf->lan_nb_qps = pf->lan_nb_qp_max;
1413 ice_init_proto_xtr(dev);
1415 if (hw->func_caps.fd_fltr_guar > 0 ||
1416 hw->func_caps.fd_fltr_best_effort > 0) {
1417 pf->flags |= ICE_FLAG_FDIR;
1418 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1419 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1421 pf->fdir_nb_qps = 0;
1423 pf->fdir_qp_offset = 0;
1429 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1431 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1432 struct ice_vsi *vsi = NULL;
1433 struct ice_vsi_ctx vsi_ctx;
1435 struct rte_ether_addr broadcast = {
1436 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1437 struct rte_ether_addr mac_addr;
1438 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1439 uint8_t tc_bitmap = 0x1;
1442 /* hw->num_lports = 1 in NIC mode */
1443 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1447 vsi->idx = pf->next_vsi_idx;
1450 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1451 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1452 vsi->vlan_anti_spoof_on = 0;
1453 vsi->vlan_filter_on = 1;
1454 TAILQ_INIT(&vsi->mac_list);
1455 TAILQ_INIT(&vsi->vlan_list);
1457 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1458 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1459 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1460 hw->func_caps.common_cap.rss_table_size;
1461 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1463 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1466 vsi->nb_qps = pf->lan_nb_qps;
1467 vsi->base_queue = 1;
1468 ice_vsi_config_default_rss(&vsi_ctx.info);
1469 vsi_ctx.alloc_from_pool = true;
1470 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1471 /* switch_id is queried by get_switch_config aq, which is done
1474 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1475 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1476 /* Allow all untagged or tagged packets */
1477 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1478 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1479 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1480 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1481 if (ice_is_dvm_ena(hw)) {
1482 vsi_ctx.info.outer_vlan_flags =
1483 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1484 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1485 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1486 vsi_ctx.info.outer_vlan_flags |=
1487 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1488 ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1489 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1493 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1494 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1495 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1496 cfg = ICE_AQ_VSI_FD_ENABLE;
1497 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1498 vsi_ctx.info.max_fd_fltr_dedicated =
1499 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1500 vsi_ctx.info.max_fd_fltr_shared =
1501 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1503 /* Enable VLAN/UP trip */
1504 ret = ice_vsi_config_tc_queue_mapping(vsi,
1509 "tc queue mapping with vsi failed, "
1517 vsi->nb_qps = pf->fdir_nb_qps;
1518 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1519 vsi_ctx.alloc_from_pool = true;
1520 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1522 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1523 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1524 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1525 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1526 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1527 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1528 ret = ice_vsi_config_tc_queue_mapping(vsi,
1533 "tc queue mapping with vsi failed, "
1540 /* for other types of VSI */
1541 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1545 /* VF has MSIX interrupt in VF range, don't allocate here */
1546 if (type == ICE_VSI_PF) {
1547 ret = ice_res_pool_alloc(&pf->msix_pool,
1548 RTE_MIN(vsi->nb_qps,
1549 RTE_MAX_RXTX_INTR_VEC_ID));
1551 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1554 vsi->msix_intr = ret;
1555 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1556 } else if (type == ICE_VSI_CTRL) {
1557 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1559 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1562 vsi->msix_intr = ret;
1568 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1569 if (ret != ICE_SUCCESS) {
1570 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1573 /* store vsi information is SW structure */
1574 vsi->vsi_id = vsi_ctx.vsi_num;
1575 vsi->info = vsi_ctx.info;
1576 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1577 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1579 if (type == ICE_VSI_PF) {
1580 /* MAC configuration */
1581 rte_ether_addr_copy((struct rte_ether_addr *)
1582 hw->port_info->mac.perm_addr,
1585 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1586 ret = ice_add_mac_filter(vsi, &mac_addr);
1587 if (ret != ICE_SUCCESS)
1588 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1590 rte_ether_addr_copy(&broadcast, &mac_addr);
1591 ret = ice_add_mac_filter(vsi, &mac_addr);
1592 if (ret != ICE_SUCCESS)
1593 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1596 /* At the beginning, only TC0. */
1597 /* What we need here is the maximam number of the TX queues.
1598 * Currently vsi->nb_qps means it.
1599 * Correct it if any change.
1601 max_txqs[0] = vsi->nb_qps;
1602 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1603 tc_bitmap, max_txqs);
1604 if (ret != ICE_SUCCESS)
1605 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1615 ice_send_driver_ver(struct ice_hw *hw)
1617 struct ice_driver_ver dv;
1619 /* we don't have driver version use 0 for dummy */
1623 dv.subbuild_ver = 0;
1624 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1626 return ice_aq_send_driver_ver(hw, &dv, NULL);
1630 ice_pf_setup(struct ice_pf *pf)
1632 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1633 struct ice_vsi *vsi;
1636 /* Clear all stats counters */
1637 pf->offset_loaded = false;
1638 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1639 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1640 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1641 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1643 /* force guaranteed filter pool for PF */
1644 ice_alloc_fd_guar_item(hw, &unused,
1645 hw->func_caps.fd_fltr_guar);
1646 /* force shared filter pool for PF */
1647 ice_alloc_fd_shrd_item(hw, &unused,
1648 hw->func_caps.fd_fltr_best_effort);
1650 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1652 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1661 static enum ice_pkg_type
1662 ice_load_pkg_type(struct ice_hw *hw)
1664 enum ice_pkg_type package_type;
1666 /* store the activated package type (OS default or Comms) */
1667 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1669 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1670 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1672 package_type = ICE_PKG_TYPE_COMMS;
1674 package_type = ICE_PKG_TYPE_UNKNOWN;
1676 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1677 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1678 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1679 hw->active_pkg_name,
1680 ice_is_dvm_ena(hw) ? "double" : "single");
1682 return package_type;
1685 int ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn)
1687 struct ice_hw *hw = &adapter->hw;
1688 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1689 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1697 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1698 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1699 "ice-%016" PRIx64 ".pkg", dsn);
1700 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1701 ICE_MAX_PKG_FILENAME_SIZE);
1702 strcat(pkg_file, opt_ddp_filename);
1703 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1706 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1707 ICE_MAX_PKG_FILENAME_SIZE);
1708 strcat(pkg_file, opt_ddp_filename);
1709 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1713 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1714 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1717 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1718 if (rte_firmware_read(pkg_file, &buf, &bufsz) < 0) {
1719 PMD_INIT_LOG(ERR, "failed to search file path\n");
1724 PMD_INIT_LOG(DEBUG, "DDP package name: %s", pkg_file);
1726 err = ice_copy_and_init_pkg(hw, buf, bufsz);
1728 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1732 /* store the loaded pkg type info */
1733 adapter->active_pkg_type = ice_load_pkg_type(hw);
1741 ice_base_queue_get(struct ice_pf *pf)
1744 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1746 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1747 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1748 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1750 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1756 parse_bool(const char *key, const char *value, void *args)
1758 int *i = (int *)args;
1762 num = strtoul(value, &end, 10);
1764 if (num != 0 && num != 1) {
1765 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1766 "value must be 0 or 1",
1776 parse_u64(const char *key, const char *value, void *args)
1778 u64 *num = (u64 *)args;
1782 tmp = strtoull(value, NULL, 16);
1784 PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u64",
1795 lookup_pps_type(const char *pps_name)
1800 } pps_type_map[] = {
1806 for (i = 0; i < RTE_DIM(pps_type_map); i++) {
1807 if (strcmp(pps_name, pps_type_map[i].name) == 0)
1808 return pps_type_map[i].type;
1815 parse_pin_set(const char *input, int pps_type, struct ice_devargs *devargs)
1817 const char *str = input;
1821 while (isblank(*str))
1827 if (pps_type == PPS_PIN) {
1828 idx = strtoul(str, &end, 10);
1829 if (end == NULL || idx >= ICE_MAX_PIN_NUM)
1832 devargs->pin_idx = idx;
1833 devargs->pps_out_ena = 1;
1836 while (isblank(*end))
1846 parse_pps_out_parameter(const char *pins, struct ice_devargs *devargs)
1848 const char *pin_start;
1853 while (isblank(*pins))
1857 while (isblank(*pins))
1862 for (idx = 0; ; idx++) {
1863 if (isblank(pins[idx]) ||
1868 pps_name[idx] = pins[idx];
1870 pps_name[idx] = '\0';
1871 pps_type = lookup_pps_type(pps_name);
1877 pins += strcspn(pins, ":");
1880 while (isblank(*pins))
1885 while (isblank(*pins))
1888 if (parse_pin_set(pin_start, pps_type, devargs) < 0)
1895 handle_pps_out_arg(__rte_unused const char *key, const char *value,
1898 struct ice_devargs *devargs = extra_args;
1900 if (value == NULL || extra_args == NULL)
1903 if (parse_pps_out_parameter(value, devargs) < 0) {
1905 "The GPIO pin parameter is wrong : '%s'",
1913 static int ice_parse_devargs(struct rte_eth_dev *dev)
1915 struct ice_adapter *ad =
1916 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1917 struct rte_devargs *devargs = dev->device->devargs;
1918 struct rte_kvargs *kvlist;
1921 if (devargs == NULL)
1924 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1925 if (kvlist == NULL) {
1926 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1930 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1931 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1932 sizeof(ad->devargs.proto_xtr));
1934 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1935 &handle_proto_xtr_arg, &ad->devargs);
1939 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1940 &parse_bool, &ad->devargs.safe_mode_support);
1944 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1945 &parse_bool, &ad->devargs.pipe_mode_support);
1949 ret = rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG,
1950 &parse_u64, &ad->hw.debug_mask);
1954 ret = rte_kvargs_process(kvlist, ICE_ONE_PPS_OUT_ARG,
1955 &handle_pps_out_arg, &ad->devargs);
1960 rte_kvargs_free(kvlist);
1964 /* Forward LLDP packets to default VSI by set switch rules */
1966 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1968 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1969 struct ice_fltr_list_entry *s_list_itr = NULL;
1970 struct LIST_HEAD_TYPE list_head;
1973 INIT_LIST_HEAD(&list_head);
1975 s_list_itr = (struct ice_fltr_list_entry *)
1976 ice_malloc(hw, sizeof(*s_list_itr));
1979 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1980 s_list_itr->fltr_info.vsi_handle = vsi->idx;
1981 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1982 RTE_ETHER_TYPE_LLDP;
1983 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1984 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1985 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1986 LIST_ADD(&s_list_itr->list_entry, &list_head);
1988 ret = ice_add_eth_mac(hw, &list_head);
1990 ret = ice_remove_eth_mac(hw, &list_head);
1992 rte_free(s_list_itr);
1996 static enum ice_status
1997 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1998 uint16_t num, uint16_t desc_id,
1999 uint16_t *prof_buf, uint16_t *num_prof)
2001 struct ice_aqc_res_elem *resp_buf;
2004 bool res_shared = 1;
2005 struct ice_aq_desc aq_desc;
2006 struct ice_sq_cd *cd = NULL;
2007 struct ice_aqc_get_allocd_res_desc *cmd =
2008 &aq_desc.params.get_res_desc;
2010 buf_len = sizeof(*resp_buf) * num;
2011 resp_buf = ice_malloc(hw, buf_len);
2015 ice_fill_dflt_direct_cmd_desc(&aq_desc,
2016 ice_aqc_opc_get_allocd_res_desc);
2018 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2019 ICE_AQC_RES_TYPE_M) | (res_shared ?
2020 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2021 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2023 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2025 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2029 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
2030 (*num_prof), ICE_NONDMA_TO_NONDMA);
2037 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2041 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2042 uint16_t first_desc = 1;
2043 uint16_t num_prof = 0;
2045 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2046 first_desc, prof_buf, &num_prof);
2048 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2052 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2053 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2055 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2063 ice_reset_fxp_resource(struct ice_hw *hw)
2067 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2069 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2073 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2075 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2083 ice_rss_ctx_init(struct ice_pf *pf)
2085 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
2089 ice_get_supported_rxdid(struct ice_hw *hw)
2091 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2095 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2097 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2098 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2099 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2100 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2101 supported_rxdid |= BIT(i);
2103 return supported_rxdid;
2107 ice_dev_init(struct rte_eth_dev *dev)
2109 struct rte_pci_device *pci_dev;
2110 struct rte_intr_handle *intr_handle;
2111 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2113 struct ice_adapter *ad =
2114 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2115 struct ice_vsi *vsi;
2117 #ifndef RTE_EXEC_ENV_WINDOWS
2119 uint32_t dsn_low, dsn_high;
2124 dev->dev_ops = &ice_eth_dev_ops;
2125 dev->rx_queue_count = ice_rx_queue_count;
2126 dev->rx_descriptor_status = ice_rx_descriptor_status;
2127 dev->tx_descriptor_status = ice_tx_descriptor_status;
2128 dev->rx_pkt_burst = ice_recv_pkts;
2129 dev->tx_pkt_burst = ice_xmit_pkts;
2130 dev->tx_pkt_prepare = ice_prep_pkts;
2132 /* for secondary processes, we don't initialise any further as primary
2133 * has already done this work.
2135 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2136 ice_set_rx_function(dev);
2137 ice_set_tx_function(dev);
2141 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2143 ice_set_default_ptype_table(dev);
2144 pci_dev = RTE_DEV_TO_PCI(dev->device);
2145 intr_handle = &pci_dev->intr_handle;
2147 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2148 pf->dev_data = dev->data;
2149 hw->back = pf->adapter;
2150 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2151 hw->vendor_id = pci_dev->id.vendor_id;
2152 hw->device_id = pci_dev->id.device_id;
2153 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2154 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2155 hw->bus.device = pci_dev->addr.devid;
2156 hw->bus.func = pci_dev->addr.function;
2158 ret = ice_parse_devargs(dev);
2160 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2164 ice_init_controlq_parameter(hw);
2166 ret = ice_init_hw(hw);
2168 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2172 #ifndef RTE_EXEC_ENV_WINDOWS
2175 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
2177 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0 ||
2178 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) {
2179 PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
2182 dsn = (uint64_t)dsn_high << 32 | dsn_low;
2185 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
2188 ret = ice_load_pkg(pf->adapter, use_dsn, dsn);
2190 ret = ice_init_hw_tbls(hw);
2192 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", ret);
2193 rte_free(hw->pkg_copy);
2198 if (ad->devargs.safe_mode_support == 0) {
2199 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2200 "Use safe-mode-support=1 to enter Safe Mode");
2204 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2205 "Entering Safe Mode");
2206 ad->is_safe_mode = 1;
2210 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2211 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2212 hw->api_maj_ver, hw->api_min_ver);
2214 ice_pf_sw_init(dev);
2215 ret = ice_init_mac_address(dev);
2217 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2221 ret = ice_res_pool_init(&pf->msix_pool, 1,
2222 hw->func_caps.common_cap.num_msix_vectors - 1);
2224 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2225 goto err_msix_pool_init;
2228 ret = ice_pf_setup(pf);
2230 PMD_INIT_LOG(ERR, "Failed to setup PF");
2234 ret = ice_send_driver_ver(hw);
2236 PMD_INIT_LOG(ERR, "Failed to send driver version");
2242 ret = ice_aq_stop_lldp(hw, true, false, NULL);
2243 if (ret != ICE_SUCCESS)
2244 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2245 ret = ice_init_dcb(hw, true);
2246 if (ret != ICE_SUCCESS)
2247 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2248 /* Forward LLDP packets to default VSI */
2249 ret = ice_vsi_config_sw_lldp(vsi, true);
2250 if (ret != ICE_SUCCESS)
2251 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2252 /* register callback func to eal lib */
2253 rte_intr_callback_register(intr_handle,
2254 ice_interrupt_handler, dev);
2256 ice_pf_enable_irq0(hw);
2258 /* enable uio intr after callback register */
2259 rte_intr_enable(intr_handle);
2261 /* get base queue pairs index in the device */
2262 ice_base_queue_get(pf);
2264 /* Initialize RSS context for gtpu_eh */
2265 ice_rss_ctx_init(pf);
2267 if (!ad->is_safe_mode) {
2268 ret = ice_flow_init(ad);
2270 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2275 ret = ice_reset_fxp_resource(hw);
2277 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2281 pf->supported_rxdid = ice_get_supported_rxdid(hw);
2286 ice_flow_uninit(ad);
2287 rte_intr_disable(intr_handle);
2288 ice_pf_disable_irq0(hw);
2289 rte_intr_callback_unregister(intr_handle,
2290 ice_interrupt_handler, dev);
2292 ice_res_pool_destroy(&pf->msix_pool);
2294 rte_free(dev->data->mac_addrs);
2295 dev->data->mac_addrs = NULL;
2297 rte_free(pf->proto_xtr);
2298 #ifndef RTE_EXEC_ENV_WINDOWS
2307 ice_release_vsi(struct ice_vsi *vsi)
2310 struct ice_vsi_ctx vsi_ctx;
2311 enum ice_status ret;
2317 hw = ICE_VSI_TO_HW(vsi);
2319 ice_remove_all_mac_vlan_filters(vsi);
2321 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2323 vsi_ctx.vsi_num = vsi->vsi_id;
2324 vsi_ctx.info = vsi->info;
2325 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2326 if (ret != ICE_SUCCESS) {
2327 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2331 rte_free(vsi->rss_lut);
2332 rte_free(vsi->rss_key);
2338 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2340 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
2341 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2342 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2343 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2344 uint16_t msix_intr, i;
2346 /* disable interrupt and also clear all the exist config */
2347 for (i = 0; i < vsi->nb_qps; i++) {
2348 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2349 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2353 if (rte_intr_allow_others(intr_handle))
2355 for (i = 0; i < vsi->nb_msix; i++) {
2356 msix_intr = vsi->msix_intr + i;
2357 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2358 GLINT_DYN_CTL_WB_ON_ITR_M);
2362 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2366 ice_dev_stop(struct rte_eth_dev *dev)
2368 struct rte_eth_dev_data *data = dev->data;
2369 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2370 struct ice_vsi *main_vsi = pf->main_vsi;
2371 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2372 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2375 /* avoid stopping again */
2376 if (pf->adapter_stopped)
2379 /* stop and clear all Rx queues */
2380 for (i = 0; i < data->nb_rx_queues; i++)
2381 ice_rx_queue_stop(dev, i);
2383 /* stop and clear all Tx queues */
2384 for (i = 0; i < data->nb_tx_queues; i++)
2385 ice_tx_queue_stop(dev, i);
2387 /* disable all queue interrupts */
2388 ice_vsi_disable_queues_intr(main_vsi);
2390 if (pf->init_link_up)
2391 ice_dev_set_link_up(dev);
2393 ice_dev_set_link_down(dev);
2395 /* Clean datapath event and queue/vec mapping */
2396 rte_intr_efd_disable(intr_handle);
2397 if (intr_handle->intr_vec) {
2398 rte_free(intr_handle->intr_vec);
2399 intr_handle->intr_vec = NULL;
2402 pf->adapter_stopped = true;
2403 dev->data->dev_started = 0;
2409 ice_dev_close(struct rte_eth_dev *dev)
2411 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2412 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2414 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2415 struct ice_adapter *ad =
2416 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2419 uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned;
2420 uint32_t pin_idx = ad->devargs.pin_idx;
2422 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2425 /* Since stop will make link down, then the link event will be
2426 * triggered, disable the irq firstly to avoid the port_infoe etc
2427 * resources deallocation causing the interrupt service thread
2430 ice_pf_disable_irq0(hw);
2432 ret = ice_dev_stop(dev);
2434 if (!ad->is_safe_mode)
2435 ice_flow_uninit(ad);
2437 /* release all queue resource */
2438 ice_free_queues(dev);
2440 ice_res_pool_destroy(&pf->msix_pool);
2441 ice_release_vsi(pf->main_vsi);
2442 ice_sched_cleanup_all(hw);
2443 ice_free_hw_tbls(hw);
2444 rte_free(hw->port_info);
2445 hw->port_info = NULL;
2446 ice_shutdown_all_ctrlq(hw);
2447 rte_free(pf->proto_xtr);
2448 pf->proto_xtr = NULL;
2450 if (ad->devargs.pps_out_ena) {
2451 ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(pin_idx, timer), 0);
2452 ICE_WRITE_REG(hw, GLTSYN_CLKO(pin_idx, timer), 0);
2453 ICE_WRITE_REG(hw, GLTSYN_TGT_L(pin_idx, timer), 0);
2454 ICE_WRITE_REG(hw, GLTSYN_TGT_H(pin_idx, timer), 0);
2456 val = GLGEN_GPIO_CTL_PIN_DIR_M;
2457 ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(pin_idx), val);
2460 /* disable uio intr before callback unregister */
2461 rte_intr_disable(intr_handle);
2463 /* unregister callback func from eal lib */
2464 rte_intr_callback_unregister(intr_handle,
2465 ice_interrupt_handler, dev);
2471 ice_dev_uninit(struct rte_eth_dev *dev)
2479 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2481 return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2485 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2490 cfg->hdr_type = ICE_RSS_OUTER_HEADERS;
2494 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2496 enum ice_status status = ICE_SUCCESS;
2497 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2498 struct ice_vsi *vsi = pf->main_vsi;
2500 if (!is_hash_cfg_valid(cfg))
2503 status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2504 if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2506 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2515 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2517 enum ice_status status = ICE_SUCCESS;
2518 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2519 struct ice_vsi *vsi = pf->main_vsi;
2521 if (!is_hash_cfg_valid(cfg))
2524 status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2527 "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2536 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2540 ret = ice_hash_moveout(pf, cfg);
2541 if (ret && (ret != -ENOENT))
2544 hash_cfg_reset(cfg);
2550 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2556 case ICE_HASH_GTPU_CTX_EH_IP:
2557 ret = ice_hash_remove(pf,
2558 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2559 if (ret && (ret != -ENOENT))
2562 ret = ice_hash_remove(pf,
2563 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2564 if (ret && (ret != -ENOENT))
2567 ret = ice_hash_remove(pf,
2568 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2569 if (ret && (ret != -ENOENT))
2572 ret = ice_hash_remove(pf,
2573 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2574 if (ret && (ret != -ENOENT))
2577 ret = ice_hash_remove(pf,
2578 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2579 if (ret && (ret != -ENOENT))
2582 ret = ice_hash_remove(pf,
2583 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2584 if (ret && (ret != -ENOENT))
2587 ret = ice_hash_remove(pf,
2588 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2589 if (ret && (ret != -ENOENT))
2592 ret = ice_hash_remove(pf,
2593 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2594 if (ret && (ret != -ENOENT))
2598 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2599 ret = ice_hash_remove(pf,
2600 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2601 if (ret && (ret != -ENOENT))
2604 ret = ice_hash_remove(pf,
2605 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2606 if (ret && (ret != -ENOENT))
2609 ret = ice_hash_moveout(pf,
2610 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2611 if (ret && (ret != -ENOENT))
2614 ret = ice_hash_moveout(pf,
2615 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2616 if (ret && (ret != -ENOENT))
2619 ret = ice_hash_moveout(pf,
2620 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2621 if (ret && (ret != -ENOENT))
2624 ret = ice_hash_moveout(pf,
2625 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2626 if (ret && (ret != -ENOENT))
2630 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2631 ret = ice_hash_remove(pf,
2632 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2633 if (ret && (ret != -ENOENT))
2636 ret = ice_hash_remove(pf,
2637 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2638 if (ret && (ret != -ENOENT))
2641 ret = ice_hash_moveout(pf,
2642 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2643 if (ret && (ret != -ENOENT))
2646 ret = ice_hash_moveout(pf,
2647 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2648 if (ret && (ret != -ENOENT))
2651 ret = ice_hash_moveout(pf,
2652 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2653 if (ret && (ret != -ENOENT))
2656 ret = ice_hash_moveout(pf,
2657 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2658 if (ret && (ret != -ENOENT))
2662 case ICE_HASH_GTPU_CTX_UP_IP:
2663 ret = ice_hash_remove(pf,
2664 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2665 if (ret && (ret != -ENOENT))
2668 ret = ice_hash_remove(pf,
2669 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2670 if (ret && (ret != -ENOENT))
2673 ret = ice_hash_moveout(pf,
2674 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2675 if (ret && (ret != -ENOENT))
2678 ret = ice_hash_moveout(pf,
2679 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2680 if (ret && (ret != -ENOENT))
2683 ret = ice_hash_moveout(pf,
2684 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2685 if (ret && (ret != -ENOENT))
2689 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2690 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2691 ret = ice_hash_moveout(pf,
2692 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2693 if (ret && (ret != -ENOENT))
2696 ret = ice_hash_moveout(pf,
2697 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2698 if (ret && (ret != -ENOENT))
2701 ret = ice_hash_moveout(pf,
2702 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2703 if (ret && (ret != -ENOENT))
2707 case ICE_HASH_GTPU_CTX_DW_IP:
2708 ret = ice_hash_remove(pf,
2709 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2710 if (ret && (ret != -ENOENT))
2713 ret = ice_hash_remove(pf,
2714 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2715 if (ret && (ret != -ENOENT))
2718 ret = ice_hash_moveout(pf,
2719 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2720 if (ret && (ret != -ENOENT))
2723 ret = ice_hash_moveout(pf,
2724 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2725 if (ret && (ret != -ENOENT))
2728 ret = ice_hash_moveout(pf,
2729 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2730 if (ret && (ret != -ENOENT))
2734 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2735 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2736 ret = ice_hash_moveout(pf,
2737 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2738 if (ret && (ret != -ENOENT))
2741 ret = ice_hash_moveout(pf,
2742 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2743 if (ret && (ret != -ENOENT))
2746 ret = ice_hash_moveout(pf,
2747 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2748 if (ret && (ret != -ENOENT))
2759 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2763 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2765 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2767 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2770 return ICE_HASH_GTPU_CTX_MAX;
2773 if (hdr & ICE_FLOW_SEG_HDR_UDP)
2775 else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2778 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2779 return eh_idx * 3 + ip_idx;
2781 return ICE_HASH_GTPU_CTX_MAX;
2785 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2787 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2789 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2790 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2792 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2793 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2800 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2801 u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2805 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2806 ctx->ctx[ctx_idx] = *cfg;
2809 case ICE_HASH_GTPU_CTX_EH_IP:
2811 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2812 ret = ice_hash_moveback(pf,
2813 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2814 if (ret && (ret != -ENOENT))
2817 ret = ice_hash_moveback(pf,
2818 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2819 if (ret && (ret != -ENOENT))
2822 ret = ice_hash_moveback(pf,
2823 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2824 if (ret && (ret != -ENOENT))
2827 ret = ice_hash_moveback(pf,
2828 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2829 if (ret && (ret != -ENOENT))
2833 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2834 ret = ice_hash_moveback(pf,
2835 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2836 if (ret && (ret != -ENOENT))
2839 ret = ice_hash_moveback(pf,
2840 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2841 if (ret && (ret != -ENOENT))
2844 ret = ice_hash_moveback(pf,
2845 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2846 if (ret && (ret != -ENOENT))
2849 ret = ice_hash_moveback(pf,
2850 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2851 if (ret && (ret != -ENOENT))
2855 case ICE_HASH_GTPU_CTX_UP_IP:
2856 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2857 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2858 case ICE_HASH_GTPU_CTX_DW_IP:
2859 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2860 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2861 ret = ice_hash_moveback(pf,
2862 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2863 if (ret && (ret != -ENOENT))
2866 ret = ice_hash_moveback(pf,
2867 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2868 if (ret && (ret != -ENOENT))
2871 ret = ice_hash_moveback(pf,
2872 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2873 if (ret && (ret != -ENOENT))
2885 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2887 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2889 if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2890 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2892 else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2893 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2900 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2902 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2904 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2907 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2908 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2909 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2910 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2914 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2915 struct ice_rss_hash_cfg *cfg)
2917 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2920 ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2921 if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2922 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2924 ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2930 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2931 struct ice_rss_hash_cfg *cfg)
2933 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2936 ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2938 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2940 ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2942 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2944 ret = ice_add_rss_cfg_post(pf, cfg);
2946 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2952 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2954 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2955 struct ice_vsi *vsi = pf->main_vsi;
2956 struct ice_rss_hash_cfg cfg;
2959 #define ICE_RSS_HF_ALL ( \
2962 ETH_RSS_NONFRAG_IPV4_UDP | \
2963 ETH_RSS_NONFRAG_IPV6_UDP | \
2964 ETH_RSS_NONFRAG_IPV4_TCP | \
2965 ETH_RSS_NONFRAG_IPV6_TCP | \
2966 ETH_RSS_NONFRAG_IPV4_SCTP | \
2967 ETH_RSS_NONFRAG_IPV6_SCTP)
2969 ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2971 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2975 cfg.hdr_type = ICE_RSS_OUTER_HEADERS;
2976 /* Configure RSS for IPv4 with src/dst addr as input set */
2977 if (rss_hf & ETH_RSS_IPV4) {
2978 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2979 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2980 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2982 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2986 /* Configure RSS for IPv6 with src/dst addr as input set */
2987 if (rss_hf & ETH_RSS_IPV6) {
2988 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2989 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2990 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2992 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2996 /* Configure RSS for udp4 with src/dst addr and port as input set */
2997 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2998 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2999 ICE_FLOW_SEG_HDR_IPV_OTHER;
3000 cfg.hash_flds = ICE_HASH_UDP_IPV4;
3001 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3003 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
3007 /* Configure RSS for udp6 with src/dst addr and port as input set */
3008 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
3009 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
3010 ICE_FLOW_SEG_HDR_IPV_OTHER;
3011 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3012 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3014 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
3018 /* Configure RSS for tcp4 with src/dst addr and port as input set */
3019 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3020 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
3021 ICE_FLOW_SEG_HDR_IPV_OTHER;
3022 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3023 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3025 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
3029 /* Configure RSS for tcp6 with src/dst addr and port as input set */
3030 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3031 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
3032 ICE_FLOW_SEG_HDR_IPV_OTHER;
3033 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3034 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3036 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
3040 /* Configure RSS for sctp4 with src/dst addr and port as input set */
3041 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
3042 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
3043 ICE_FLOW_SEG_HDR_IPV_OTHER;
3044 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
3045 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3047 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
3051 /* Configure RSS for sctp6 with src/dst addr and port as input set */
3052 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
3053 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
3054 ICE_FLOW_SEG_HDR_IPV_OTHER;
3055 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
3056 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3058 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
3062 if (rss_hf & ETH_RSS_IPV4) {
3063 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
3064 ICE_FLOW_SEG_HDR_IPV_OTHER;
3065 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
3066 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3068 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
3072 if (rss_hf & ETH_RSS_IPV6) {
3073 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
3074 ICE_FLOW_SEG_HDR_IPV_OTHER;
3075 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
3076 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3078 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
3082 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
3083 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3084 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3085 cfg.hash_flds = ICE_HASH_UDP_IPV4;
3086 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3088 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
3092 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
3093 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3094 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3095 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3096 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3098 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3102 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3103 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3104 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3105 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3106 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3108 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3112 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3113 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3114 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3115 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3116 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3118 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3122 pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3126 ice_get_default_rss_key(uint8_t *rss_key, uint32_t rss_key_size)
3128 static struct ice_aqc_get_set_rss_keys default_key;
3129 static bool default_key_done;
3130 uint8_t *key = (uint8_t *)&default_key;
3133 if (rss_key_size > sizeof(default_key)) {
3134 PMD_DRV_LOG(WARNING,
3135 "requested size %u is larger than default %zu, "
3136 "only %zu bytes are gotten for key\n",
3137 rss_key_size, sizeof(default_key),
3138 sizeof(default_key));
3141 if (!default_key_done) {
3142 /* Calculate the default hash key */
3143 for (i = 0; i < sizeof(default_key); i++)
3144 key[i] = (uint8_t)rte_rand();
3145 default_key_done = true;
3147 rte_memcpy(rss_key, key, RTE_MIN(rss_key_size, sizeof(default_key)));
3150 static int ice_init_rss(struct ice_pf *pf)
3152 struct ice_hw *hw = ICE_PF_TO_HW(pf);
3153 struct ice_vsi *vsi = pf->main_vsi;
3154 struct rte_eth_dev_data *dev_data = pf->dev_data;
3155 struct ice_aq_get_set_rss_lut_params lut_params;
3156 struct rte_eth_rss_conf *rss_conf;
3157 struct ice_aqc_get_set_rss_keys key;
3160 bool is_safe_mode = pf->adapter->is_safe_mode;
3163 rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf;
3164 nb_q = dev_data->nb_rx_queues;
3165 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3166 vsi->rss_lut_size = pf->hash_lut_size;
3169 PMD_DRV_LOG(WARNING,
3170 "RSS is not supported as rx queues number is zero\n");
3175 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3179 if (!vsi->rss_key) {
3180 vsi->rss_key = rte_zmalloc(NULL,
3181 vsi->rss_key_size, 0);
3182 if (vsi->rss_key == NULL) {
3183 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3187 if (!vsi->rss_lut) {
3188 vsi->rss_lut = rte_zmalloc(NULL,
3189 vsi->rss_lut_size, 0);
3190 if (vsi->rss_lut == NULL) {
3191 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3192 rte_free(vsi->rss_key);
3193 vsi->rss_key = NULL;
3197 /* configure RSS key */
3198 if (!rss_conf->rss_key)
3199 ice_get_default_rss_key(vsi->rss_key, vsi->rss_key_size);
3201 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3202 RTE_MIN(rss_conf->rss_key_len,
3203 vsi->rss_key_size));
3205 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3206 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3210 /* init RSS LUT table */
3211 for (i = 0; i < vsi->rss_lut_size; i++)
3212 vsi->rss_lut[i] = i % nb_q;
3214 lut_params.vsi_handle = vsi->idx;
3215 lut_params.lut_size = vsi->rss_lut_size;
3216 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3217 lut_params.lut = vsi->rss_lut;
3218 lut_params.global_lut_id = 0;
3219 ret = ice_aq_set_rss_lut(hw, &lut_params);
3223 /* Enable registers for symmetric_toeplitz function. */
3224 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3225 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3226 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3227 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3229 /* RSS hash configuration */
3230 ice_rss_hash_set(pf, rss_conf->rss_hf);
3234 rte_free(vsi->rss_key);
3235 vsi->rss_key = NULL;
3236 rte_free(vsi->rss_lut);
3237 vsi->rss_lut = NULL;
3242 ice_dev_configure(struct rte_eth_dev *dev)
3244 struct ice_adapter *ad =
3245 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3246 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3249 /* Initialize to TRUE. If any of Rx queues doesn't meet the
3250 * bulk allocation or vector Rx preconditions we will reset it.
3252 ad->rx_bulk_alloc_allowed = true;
3253 ad->tx_simple_allowed = true;
3255 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3256 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3258 if (dev->data->nb_rx_queues) {
3259 ret = ice_init_rss(pf);
3261 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3270 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3271 int base_queue, int nb_queue)
3273 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3274 uint32_t val, val_tx;
3277 for (i = 0; i < nb_queue; i++) {
3279 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3280 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3281 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3282 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3284 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3285 base_queue + i, msix_vect);
3286 /* set ITR0 value */
3287 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3288 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3289 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3294 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3296 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3297 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3298 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3299 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3300 uint16_t msix_vect = vsi->msix_intr;
3301 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3302 uint16_t queue_idx = 0;
3306 /* clear Rx/Tx queue interrupt */
3307 for (i = 0; i < vsi->nb_used_qps; i++) {
3308 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3309 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3312 /* PF bind interrupt */
3313 if (rte_intr_dp_is_en(intr_handle)) {
3318 for (i = 0; i < vsi->nb_used_qps; i++) {
3320 if (!rte_intr_allow_others(intr_handle))
3321 msix_vect = ICE_MISC_VEC_ID;
3323 /* uio mapping all queue to one msix_vect */
3324 __vsi_queues_bind_intr(vsi, msix_vect,
3325 vsi->base_queue + i,
3326 vsi->nb_used_qps - i);
3328 for (; !!record && i < vsi->nb_used_qps; i++)
3329 intr_handle->intr_vec[queue_idx + i] =
3334 /* vfio 1:1 queue/msix_vect mapping */
3335 __vsi_queues_bind_intr(vsi, msix_vect,
3336 vsi->base_queue + i, 1);
3339 intr_handle->intr_vec[queue_idx + i] = msix_vect;
3347 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3349 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3350 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3351 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3352 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3353 uint16_t msix_intr, i;
3355 if (rte_intr_allow_others(intr_handle))
3356 for (i = 0; i < vsi->nb_used_qps; i++) {
3357 msix_intr = vsi->msix_intr + i;
3358 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3359 GLINT_DYN_CTL_INTENA_M |
3360 GLINT_DYN_CTL_CLEARPBA_M |
3361 GLINT_DYN_CTL_ITR_INDX_M |
3362 GLINT_DYN_CTL_WB_ON_ITR_M);
3365 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3366 GLINT_DYN_CTL_INTENA_M |
3367 GLINT_DYN_CTL_CLEARPBA_M |
3368 GLINT_DYN_CTL_ITR_INDX_M |
3369 GLINT_DYN_CTL_WB_ON_ITR_M);
3373 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3375 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3376 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3377 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3378 struct ice_vsi *vsi = pf->main_vsi;
3379 uint32_t intr_vector = 0;
3381 rte_intr_disable(intr_handle);
3383 /* check and configure queue intr-vector mapping */
3384 if ((rte_intr_cap_multiple(intr_handle) ||
3385 !RTE_ETH_DEV_SRIOV(dev).active) &&
3386 dev->data->dev_conf.intr_conf.rxq != 0) {
3387 intr_vector = dev->data->nb_rx_queues;
3388 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3389 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3390 ICE_MAX_INTR_QUEUE_NUM);
3393 if (rte_intr_efd_enable(intr_handle, intr_vector))
3397 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3398 intr_handle->intr_vec =
3399 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3401 if (!intr_handle->intr_vec) {
3403 "Failed to allocate %d rx_queues intr_vec",
3404 dev->data->nb_rx_queues);
3409 /* Map queues with MSIX interrupt */
3410 vsi->nb_used_qps = dev->data->nb_rx_queues;
3411 ice_vsi_queues_bind_intr(vsi);
3413 /* Enable interrupts for all the queues */
3414 ice_vsi_enable_queues_intr(vsi);
3416 rte_intr_enable(intr_handle);
3422 ice_get_init_link_status(struct rte_eth_dev *dev)
3424 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3426 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3427 struct ice_link_status link_status;
3430 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3431 &link_status, NULL);
3432 if (ret != ICE_SUCCESS) {
3433 PMD_DRV_LOG(ERR, "Failed to get link info");
3434 pf->init_link_up = false;
3438 if (link_status.link_info & ICE_AQ_LINK_UP)
3439 pf->init_link_up = true;
3443 ice_pps_out_cfg(struct ice_hw *hw, int idx, int timer)
3445 uint64_t current_time, start_time;
3446 uint32_t hi, lo, lo2, func, val;
3448 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3449 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer));
3450 lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3453 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3454 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer));
3457 current_time = ((uint64_t)hi << 32) | lo;
3459 start_time = (current_time + NSEC_PER_SEC) /
3460 NSEC_PER_SEC * NSEC_PER_SEC;
3461 start_time = start_time - PPS_OUT_DELAY_NS;
3463 func = 8 + idx + timer * 4;
3464 val = GLGEN_GPIO_CTL_PIN_DIR_M |
3465 ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) &
3466 GLGEN_GPIO_CTL_PIN_FUNC_M);
3468 /* Write clkout with half of period value */
3469 ICE_WRITE_REG(hw, GLTSYN_CLKO(idx, timer), NSEC_PER_SEC / 2);
3471 /* Write TARGET time register */
3472 ICE_WRITE_REG(hw, GLTSYN_TGT_L(idx, timer), start_time & 0xffffffff);
3473 ICE_WRITE_REG(hw, GLTSYN_TGT_H(idx, timer), start_time >> 32);
3475 /* Write AUX_OUT register */
3476 ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(idx, timer),
3477 GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M);
3479 /* Write GPIO CTL register */
3480 ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(idx), val);
3486 ice_dev_start(struct rte_eth_dev *dev)
3488 struct rte_eth_dev_data *data = dev->data;
3489 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3490 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3491 struct ice_vsi *vsi = pf->main_vsi;
3492 struct ice_adapter *ad =
3493 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3494 uint16_t nb_rxq = 0;
3496 uint16_t max_frame_size;
3498 uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned;
3499 uint32_t pin_idx = ad->devargs.pin_idx;
3501 /* program Tx queues' context in hardware */
3502 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3503 ret = ice_tx_queue_start(dev, nb_txq);
3505 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3510 /* program Rx queues' context in hardware*/
3511 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3512 ret = ice_rx_queue_start(dev, nb_rxq);
3514 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3519 ice_set_rx_function(dev);
3520 ice_set_tx_function(dev);
3522 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3523 ETH_VLAN_EXTEND_MASK;
3524 ret = ice_vlan_offload_set(dev, mask);
3526 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3530 /* enable Rx interrput and mapping Rx queue to interrupt vector */
3531 if (ice_rxq_intr_setup(dev))
3534 /* Enable receiving broadcast packets and transmitting packets */
3535 ret = ice_set_vsi_promisc(hw, vsi->idx,
3536 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3537 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3539 if (ret != ICE_SUCCESS)
3540 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3542 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3543 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3544 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3545 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3546 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3547 ICE_AQ_LINK_EVENT_AN_COMPLETED |
3548 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3550 if (ret != ICE_SUCCESS)
3551 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3553 ice_get_init_link_status(dev);
3555 ice_dev_set_link_up(dev);
3557 /* Call get_link_info aq commond to enable/disable LSE */
3558 ice_link_update(dev, 0);
3560 pf->adapter_stopped = false;
3562 /* Set the max frame size to default value*/
3563 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3564 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3567 /* Set the max frame size to HW*/
3568 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3570 if (ad->devargs.pps_out_ena) {
3571 ret = ice_pps_out_cfg(hw, pin_idx, timer);
3573 PMD_DRV_LOG(ERR, "Fail to configure 1pps out");
3580 /* stop the started queues if failed to start all queues */
3582 for (i = 0; i < nb_rxq; i++)
3583 ice_rx_queue_stop(dev, i);
3585 for (i = 0; i < nb_txq; i++)
3586 ice_tx_queue_stop(dev, i);
3592 ice_dev_reset(struct rte_eth_dev *dev)
3596 if (dev->data->sriov.active)
3599 ret = ice_dev_uninit(dev);
3601 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3605 ret = ice_dev_init(dev);
3607 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3615 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3617 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3618 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619 struct ice_vsi *vsi = pf->main_vsi;
3620 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3621 bool is_safe_mode = pf->adapter->is_safe_mode;
3625 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3626 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3627 dev_info->max_rx_queues = vsi->nb_qps;
3628 dev_info->max_tx_queues = vsi->nb_qps;
3629 dev_info->max_mac_addrs = vsi->max_macaddrs;
3630 dev_info->max_vfs = pci_dev->max_vfs;
3631 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3632 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3634 dev_info->rx_offload_capa =
3635 DEV_RX_OFFLOAD_VLAN_STRIP |
3636 DEV_RX_OFFLOAD_JUMBO_FRAME |
3637 DEV_RX_OFFLOAD_KEEP_CRC |
3638 DEV_RX_OFFLOAD_SCATTER |
3639 DEV_RX_OFFLOAD_VLAN_FILTER;
3640 dev_info->tx_offload_capa =
3641 DEV_TX_OFFLOAD_VLAN_INSERT |
3642 DEV_TX_OFFLOAD_TCP_TSO |
3643 DEV_TX_OFFLOAD_MULTI_SEGS |
3644 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3645 dev_info->flow_type_rss_offloads = 0;
3647 if (!is_safe_mode) {
3648 dev_info->rx_offload_capa |=
3649 DEV_RX_OFFLOAD_IPV4_CKSUM |
3650 DEV_RX_OFFLOAD_UDP_CKSUM |
3651 DEV_RX_OFFLOAD_TCP_CKSUM |
3652 DEV_RX_OFFLOAD_QINQ_STRIP |
3653 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3654 DEV_RX_OFFLOAD_VLAN_EXTEND |
3655 DEV_RX_OFFLOAD_RSS_HASH;
3656 dev_info->tx_offload_capa |=
3657 DEV_TX_OFFLOAD_QINQ_INSERT |
3658 DEV_TX_OFFLOAD_IPV4_CKSUM |
3659 DEV_TX_OFFLOAD_UDP_CKSUM |
3660 DEV_TX_OFFLOAD_TCP_CKSUM |
3661 DEV_TX_OFFLOAD_SCTP_CKSUM |
3662 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3663 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3664 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3667 dev_info->rx_queue_offload_capa = 0;
3668 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3670 dev_info->reta_size = pf->hash_lut_size;
3671 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3673 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3675 .pthresh = ICE_DEFAULT_RX_PTHRESH,
3676 .hthresh = ICE_DEFAULT_RX_HTHRESH,
3677 .wthresh = ICE_DEFAULT_RX_WTHRESH,
3679 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3684 dev_info->default_txconf = (struct rte_eth_txconf) {
3686 .pthresh = ICE_DEFAULT_TX_PTHRESH,
3687 .hthresh = ICE_DEFAULT_TX_HTHRESH,
3688 .wthresh = ICE_DEFAULT_TX_WTHRESH,
3690 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3691 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3695 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3696 .nb_max = ICE_MAX_RING_DESC,
3697 .nb_min = ICE_MIN_RING_DESC,
3698 .nb_align = ICE_ALIGN_RING_DESC,
3701 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3702 .nb_max = ICE_MAX_RING_DESC,
3703 .nb_min = ICE_MIN_RING_DESC,
3704 .nb_align = ICE_ALIGN_RING_DESC,
3707 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3708 ETH_LINK_SPEED_100M |
3710 ETH_LINK_SPEED_2_5G |
3712 ETH_LINK_SPEED_10G |
3713 ETH_LINK_SPEED_20G |
3716 phy_type_low = hw->port_info->phy.phy_type_low;
3717 phy_type_high = hw->port_info->phy.phy_type_high;
3719 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3720 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3722 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3723 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3724 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3726 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3727 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3729 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3730 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3731 dev_info->default_rxportconf.nb_queues = 1;
3732 dev_info->default_txportconf.nb_queues = 1;
3733 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3734 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3740 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3741 struct rte_eth_link *link)
3743 struct rte_eth_link *dst = link;
3744 struct rte_eth_link *src = &dev->data->dev_link;
3746 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3747 *(uint64_t *)src) == 0)
3754 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3755 struct rte_eth_link *link)
3757 struct rte_eth_link *dst = &dev->data->dev_link;
3758 struct rte_eth_link *src = link;
3760 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3761 *(uint64_t *)src) == 0)
3768 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3770 #define CHECK_INTERVAL 100 /* 100ms */
3771 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3772 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3773 struct ice_link_status link_status;
3774 struct rte_eth_link link, old;
3776 unsigned int rep_cnt = MAX_REPEAT_TIME;
3777 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3779 memset(&link, 0, sizeof(link));
3780 memset(&old, 0, sizeof(old));
3781 memset(&link_status, 0, sizeof(link_status));
3782 ice_atomic_read_link_status(dev, &old);
3785 /* Get link status information from hardware */
3786 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3787 &link_status, NULL);
3788 if (status != ICE_SUCCESS) {
3789 link.link_speed = ETH_SPEED_NUM_100M;
3790 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3791 PMD_DRV_LOG(ERR, "Failed to get link info");
3795 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3796 if (!wait_to_complete || link.link_status)
3799 rte_delay_ms(CHECK_INTERVAL);
3800 } while (--rep_cnt);
3802 if (!link.link_status)
3805 /* Full-duplex operation at all supported speeds */
3806 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3808 /* Parse the link status */
3809 switch (link_status.link_speed) {
3810 case ICE_AQ_LINK_SPEED_10MB:
3811 link.link_speed = ETH_SPEED_NUM_10M;
3813 case ICE_AQ_LINK_SPEED_100MB:
3814 link.link_speed = ETH_SPEED_NUM_100M;
3816 case ICE_AQ_LINK_SPEED_1000MB:
3817 link.link_speed = ETH_SPEED_NUM_1G;
3819 case ICE_AQ_LINK_SPEED_2500MB:
3820 link.link_speed = ETH_SPEED_NUM_2_5G;
3822 case ICE_AQ_LINK_SPEED_5GB:
3823 link.link_speed = ETH_SPEED_NUM_5G;
3825 case ICE_AQ_LINK_SPEED_10GB:
3826 link.link_speed = ETH_SPEED_NUM_10G;
3828 case ICE_AQ_LINK_SPEED_20GB:
3829 link.link_speed = ETH_SPEED_NUM_20G;
3831 case ICE_AQ_LINK_SPEED_25GB:
3832 link.link_speed = ETH_SPEED_NUM_25G;
3834 case ICE_AQ_LINK_SPEED_40GB:
3835 link.link_speed = ETH_SPEED_NUM_40G;
3837 case ICE_AQ_LINK_SPEED_50GB:
3838 link.link_speed = ETH_SPEED_NUM_50G;
3840 case ICE_AQ_LINK_SPEED_100GB:
3841 link.link_speed = ETH_SPEED_NUM_100G;
3843 case ICE_AQ_LINK_SPEED_UNKNOWN:
3844 PMD_DRV_LOG(ERR, "Unknown link speed");
3845 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3848 PMD_DRV_LOG(ERR, "None link speed");
3849 link.link_speed = ETH_SPEED_NUM_NONE;
3853 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3854 ETH_LINK_SPEED_FIXED);
3857 ice_atomic_write_link_status(dev, &link);
3858 if (link.link_status == old.link_status)
3864 /* Force the physical link state by getting the current PHY capabilities from
3865 * hardware and setting the PHY config based on the determined capabilities. If
3866 * link changes, link event will be triggered because both the Enable Automatic
3867 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3869 static enum ice_status
3870 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3872 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3873 struct ice_aqc_get_phy_caps_data *pcaps;
3874 struct ice_port_info *pi;
3875 enum ice_status status;
3877 if (!hw || !hw->port_info)
3878 return ICE_ERR_PARAM;
3882 pcaps = (struct ice_aqc_get_phy_caps_data *)
3883 ice_malloc(hw, sizeof(*pcaps));
3885 return ICE_ERR_NO_MEMORY;
3887 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3892 /* No change in link */
3893 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3894 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3897 cfg.phy_type_low = pcaps->phy_type_low;
3898 cfg.phy_type_high = pcaps->phy_type_high;
3899 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3900 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3901 cfg.eee_cap = pcaps->eee_cap;
3902 cfg.eeer_value = pcaps->eeer_value;
3903 cfg.link_fec_opt = pcaps->link_fec_options;
3905 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3907 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3909 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3912 ice_free(hw, pcaps);
3917 ice_dev_set_link_up(struct rte_eth_dev *dev)
3919 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921 return ice_force_phys_link_state(hw, true);
3925 ice_dev_set_link_down(struct rte_eth_dev *dev)
3927 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3929 return ice_force_phys_link_state(hw, false);
3933 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3935 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3936 struct rte_eth_dev_data *dev_data = pf->dev_data;
3937 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3939 /* check if mtu is within the allowed range */
3940 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3943 /* mtu setting is forbidden if port is start */
3944 if (dev_data->dev_started) {
3946 "port %d must be stopped before configuration",
3951 if (frame_size > ICE_ETH_MAX_LEN)
3952 dev_data->dev_conf.rxmode.offloads |=
3953 DEV_RX_OFFLOAD_JUMBO_FRAME;
3955 dev_data->dev_conf.rxmode.offloads &=
3956 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3958 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3963 static int ice_macaddr_set(struct rte_eth_dev *dev,
3964 struct rte_ether_addr *mac_addr)
3966 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3967 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3968 struct ice_vsi *vsi = pf->main_vsi;
3969 struct ice_mac_filter *f;
3973 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3974 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3978 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3979 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3984 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3988 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3989 if (ret != ICE_SUCCESS) {
3990 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3993 ret = ice_add_mac_filter(vsi, mac_addr);
3994 if (ret != ICE_SUCCESS) {
3995 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3998 rte_ether_addr_copy(mac_addr, &pf->dev_addr);
4000 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
4001 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
4002 if (ret != ICE_SUCCESS)
4003 PMD_DRV_LOG(ERR, "Failed to set manage mac");
4008 /* Add a MAC address, and update filters */
4010 ice_macaddr_add(struct rte_eth_dev *dev,
4011 struct rte_ether_addr *mac_addr,
4012 __rte_unused uint32_t index,
4013 __rte_unused uint32_t pool)
4015 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4016 struct ice_vsi *vsi = pf->main_vsi;
4019 ret = ice_add_mac_filter(vsi, mac_addr);
4020 if (ret != ICE_SUCCESS) {
4021 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
4028 /* Remove a MAC address, and update filters */
4030 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4032 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4033 struct ice_vsi *vsi = pf->main_vsi;
4034 struct rte_eth_dev_data *data = dev->data;
4035 struct rte_ether_addr *macaddr;
4038 macaddr = &data->mac_addrs[index];
4039 ret = ice_remove_mac_filter(vsi, macaddr);
4041 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
4047 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4049 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4050 struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
4051 struct ice_vsi *vsi = pf->main_vsi;
4054 PMD_INIT_FUNC_TRACE();
4057 * Vlan 0 is the generic filter for untagged packets
4058 * and can't be removed or added by user.
4064 ret = ice_add_vlan_filter(vsi, &vlan);
4066 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
4070 ret = ice_remove_vlan_filter(vsi, &vlan);
4072 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
4080 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
4081 * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
4082 * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
4083 * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
4085 * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
4086 * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
4087 * traffic in SVM, since the VLAN TPID isn't part of filtering.
4089 * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
4090 * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
4091 * part of filtering.
4094 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
4096 struct ice_vlan vlan;
4099 vlan = ICE_VLAN(0, 0);
4100 err = ice_add_vlan_filter(vsi, &vlan);
4102 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
4106 /* in SVM both VLAN 0 filters are identical */
4107 if (!ice_is_dvm_ena(&vsi->adapter->hw))
4110 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4111 err = ice_add_vlan_filter(vsi, &vlan);
4113 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
4121 * Delete the VLAN 0 filters in the same manner that they were added in
4122 * ice_vsi_add_vlan_zero.
4125 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
4127 struct ice_vlan vlan;
4130 vlan = ICE_VLAN(0, 0);
4131 err = ice_remove_vlan_filter(vsi, &vlan);
4133 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
4137 /* in SVM both VLAN 0 filters are identical */
4138 if (!ice_is_dvm_ena(&vsi->adapter->hw))
4141 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4142 err = ice_remove_vlan_filter(vsi, &vlan);
4144 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
4151 /* Configure vlan filter on or off */
4153 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4155 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4156 struct ice_vsi_ctx ctxt;
4160 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4163 vsi->info.sw_flags2 |= sw_flags2;
4165 vsi->info.sw_flags2 &= ~sw_flags2;
4167 vsi->info.sw_id = hw->port_info->sw_id;
4168 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4169 ctxt.info.valid_sections =
4170 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4171 ICE_AQ_VSI_PROP_SECURITY_VALID);
4172 ctxt.vsi_num = vsi->vsi_id;
4174 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4176 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4177 on ? "enable" : "disable");
4180 vsi->info.valid_sections |=
4181 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4182 ICE_AQ_VSI_PROP_SECURITY_VALID);
4185 /* consist with other drivers, allow untagged packet when vlan filter on */
4187 ret = ice_vsi_add_vlan_zero(vsi);
4189 ret = ice_vsi_del_vlan_zero(vsi);
4194 /* Manage VLAN stripping for the VSI for Rx */
4196 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4198 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4199 struct ice_vsi_ctx ctxt;
4200 enum ice_status status;
4203 /* do not allow modifying VLAN stripping when a port VLAN is configured
4206 if (vsi->info.port_based_inner_vlan)
4209 memset(&ctxt, 0, sizeof(ctxt));
4212 /* Strip VLAN tag from Rx packet and put it in the desc */
4213 ctxt.info.inner_vlan_flags =
4214 ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4216 /* Disable stripping. Leave tag in packet */
4217 ctxt.info.inner_vlan_flags =
4218 ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4220 /* Allow all packets untagged/tagged */
4221 ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4223 ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4225 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4227 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4228 ena ? "enable" : "disable");
4231 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4238 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4240 return ice_vsi_manage_vlan_stripping(vsi, true);
4244 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4246 return ice_vsi_manage_vlan_stripping(vsi, false);
4249 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4251 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4252 struct ice_vsi_ctx ctxt;
4253 enum ice_status status;
4256 /* do not allow modifying VLAN stripping when a port VLAN is configured
4259 if (vsi->info.port_based_outer_vlan)
4262 memset(&ctxt, 0, sizeof(ctxt));
4264 ctxt.info.valid_sections =
4265 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4266 /* clear current outer VLAN strip settings */
4267 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4268 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4269 ctxt.info.outer_vlan_flags |=
4270 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4271 ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4272 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4273 ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4275 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4277 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4280 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4287 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4289 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4290 struct ice_vsi_ctx ctxt;
4291 enum ice_status status;
4294 if (vsi->info.port_based_outer_vlan)
4297 memset(&ctxt, 0, sizeof(ctxt));
4299 ctxt.info.valid_sections =
4300 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4301 /* clear current outer VLAN strip settings */
4302 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4303 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4304 ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4305 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4307 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4309 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4312 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4319 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4321 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4324 if (ice_is_dvm_ena(hw)) {
4326 ret = ice_vsi_ena_outer_stripping(vsi);
4328 ret = ice_vsi_dis_outer_stripping(vsi);
4331 ret = ice_vsi_ena_inner_stripping(vsi);
4333 ret = ice_vsi_dis_inner_stripping(vsi);
4340 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4342 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4343 struct ice_vsi *vsi = pf->main_vsi;
4344 struct rte_eth_rxmode *rxmode;
4346 rxmode = &dev->data->dev_conf.rxmode;
4347 if (mask & ETH_VLAN_FILTER_MASK) {
4348 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4349 ice_vsi_config_vlan_filter(vsi, true);
4351 ice_vsi_config_vlan_filter(vsi, false);
4354 if (mask & ETH_VLAN_STRIP_MASK) {
4355 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4356 ice_vsi_config_vlan_stripping(vsi, true);
4358 ice_vsi_config_vlan_stripping(vsi, false);
4365 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4367 struct ice_aq_get_set_rss_lut_params lut_params;
4368 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4369 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4375 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4376 lut_params.vsi_handle = vsi->idx;
4377 lut_params.lut_size = lut_size;
4378 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4379 lut_params.lut = lut;
4380 lut_params.global_lut_id = 0;
4381 ret = ice_aq_get_rss_lut(hw, &lut_params);
4383 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4387 uint64_t *lut_dw = (uint64_t *)lut;
4388 uint16_t i, lut_size_dw = lut_size / 4;
4390 for (i = 0; i < lut_size_dw; i++)
4391 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4398 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4400 struct ice_aq_get_set_rss_lut_params lut_params;
4408 pf = ICE_VSI_TO_PF(vsi);
4409 hw = ICE_VSI_TO_HW(vsi);
4411 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4412 lut_params.vsi_handle = vsi->idx;
4413 lut_params.lut_size = lut_size;
4414 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4415 lut_params.lut = lut;
4416 lut_params.global_lut_id = 0;
4417 ret = ice_aq_set_rss_lut(hw, &lut_params);
4419 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4423 uint64_t *lut_dw = (uint64_t *)lut;
4424 uint16_t i, lut_size_dw = lut_size / 4;
4426 for (i = 0; i < lut_size_dw; i++)
4427 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4436 ice_rss_reta_update(struct rte_eth_dev *dev,
4437 struct rte_eth_rss_reta_entry64 *reta_conf,
4440 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4441 uint16_t i, lut_size = pf->hash_lut_size;
4442 uint16_t idx, shift;
4446 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4447 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4448 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4450 "The size of hash lookup table configured (%d)"
4451 "doesn't match the number hardware can "
4452 "supported (128, 512, 2048)",
4457 /* It MUST use the current LUT size to get the RSS lookup table,
4458 * otherwise if will fail with -100 error code.
4460 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
4462 PMD_DRV_LOG(ERR, "No memory can be allocated");
4465 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4469 for (i = 0; i < reta_size; i++) {
4470 idx = i / RTE_RETA_GROUP_SIZE;
4471 shift = i % RTE_RETA_GROUP_SIZE;
4472 if (reta_conf[idx].mask & (1ULL << shift))
4473 lut[i] = reta_conf[idx].reta[shift];
4475 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4476 if (ret == 0 && lut_size != reta_size) {
4478 "The size of hash lookup table is changed from (%d) to (%d)",
4479 lut_size, reta_size);
4480 pf->hash_lut_size = reta_size;
4490 ice_rss_reta_query(struct rte_eth_dev *dev,
4491 struct rte_eth_rss_reta_entry64 *reta_conf,
4494 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4495 uint16_t i, lut_size = pf->hash_lut_size;
4496 uint16_t idx, shift;
4500 if (reta_size != lut_size) {
4502 "The size of hash lookup table configured (%d)"
4503 "doesn't match the number hardware can "
4505 reta_size, lut_size);
4509 lut = rte_zmalloc(NULL, reta_size, 0);
4511 PMD_DRV_LOG(ERR, "No memory can be allocated");
4515 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4519 for (i = 0; i < reta_size; i++) {
4520 idx = i / RTE_RETA_GROUP_SIZE;
4521 shift = i % RTE_RETA_GROUP_SIZE;
4522 if (reta_conf[idx].mask & (1ULL << shift))
4523 reta_conf[idx].reta[shift] = lut[i];
4533 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4535 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4538 if (!key || key_len == 0) {
4539 PMD_DRV_LOG(DEBUG, "No key to be configured");
4541 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4543 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4547 struct ice_aqc_get_set_rss_keys *key_dw =
4548 (struct ice_aqc_get_set_rss_keys *)key;
4550 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4552 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4560 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4562 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4565 if (!key || !key_len)
4568 ret = ice_aq_get_rss_key
4570 (struct ice_aqc_get_set_rss_keys *)key);
4572 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4575 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4581 ice_rss_hash_update(struct rte_eth_dev *dev,
4582 struct rte_eth_rss_conf *rss_conf)
4584 enum ice_status status = ICE_SUCCESS;
4585 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4586 struct ice_vsi *vsi = pf->main_vsi;
4589 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4593 if (rss_conf->rss_hf == 0) {
4598 /* RSS hash configuration */
4599 ice_rss_hash_set(pf, rss_conf->rss_hf);
4605 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4606 struct rte_eth_rss_conf *rss_conf)
4608 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4609 struct ice_vsi *vsi = pf->main_vsi;
4611 ice_get_rss_key(vsi, rss_conf->rss_key,
4612 &rss_conf->rss_key_len);
4614 rss_conf->rss_hf = pf->rss_hf;
4619 ice_promisc_enable(struct rte_eth_dev *dev)
4621 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4622 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4623 struct ice_vsi *vsi = pf->main_vsi;
4624 enum ice_status status;
4628 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4629 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4631 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4633 case ICE_ERR_ALREADY_EXISTS:
4634 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4638 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4646 ice_promisc_disable(struct rte_eth_dev *dev)
4648 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4649 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4650 struct ice_vsi *vsi = pf->main_vsi;
4651 enum ice_status status;
4655 if (dev->data->all_multicast == 1)
4656 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX;
4658 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4659 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4661 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4662 if (status != ICE_SUCCESS) {
4663 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4671 ice_allmulti_enable(struct rte_eth_dev *dev)
4673 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4674 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4675 struct ice_vsi *vsi = pf->main_vsi;
4676 enum ice_status status;
4680 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4682 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4685 case ICE_ERR_ALREADY_EXISTS:
4686 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4690 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4698 ice_allmulti_disable(struct rte_eth_dev *dev)
4700 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4701 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702 struct ice_vsi *vsi = pf->main_vsi;
4703 enum ice_status status;
4707 if (dev->data->promiscuous == 1)
4708 return 0; /* must remain in all_multicast mode */
4710 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4712 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4713 if (status != ICE_SUCCESS) {
4714 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4721 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4724 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4725 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4726 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4730 msix_intr = intr_handle->intr_vec[queue_id];
4732 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4733 GLINT_DYN_CTL_ITR_INDX_M;
4734 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4736 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4737 rte_intr_ack(&pci_dev->intr_handle);
4742 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4745 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4746 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4747 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4750 msix_intr = intr_handle->intr_vec[queue_id];
4752 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4758 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4760 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4765 ver = hw->flash.orom.major;
4766 patch = hw->flash.orom.patch;
4767 build = hw->flash.orom.build;
4769 ret = snprintf(fw_version, fw_size,
4770 "%x.%02x 0x%08x %d.%d.%d",
4771 hw->flash.nvm.major,
4772 hw->flash.nvm.minor,
4773 hw->flash.nvm.eetrack,
4778 /* add the size of '\0' */
4780 if (fw_size < (size_t)ret)
4787 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4790 struct ice_vsi_ctx ctxt;
4791 uint8_t vlan_flags = 0;
4794 if (!vsi || !info) {
4795 PMD_DRV_LOG(ERR, "invalid parameters");
4800 vsi->info.port_based_inner_vlan = info->config.pvid;
4802 * If insert pvid is enabled, only tagged pkts are
4803 * allowed to be sent out.
4805 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4806 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4808 vsi->info.port_based_inner_vlan = 0;
4809 if (info->config.reject.tagged == 0)
4810 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4812 if (info->config.reject.untagged == 0)
4813 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4815 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4816 ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4817 vsi->info.inner_vlan_flags |= vlan_flags;
4818 memset(&ctxt, 0, sizeof(ctxt));
4819 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4820 ctxt.info.valid_sections =
4821 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4822 ctxt.vsi_num = vsi->vsi_id;
4824 hw = ICE_VSI_TO_HW(vsi);
4825 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4826 if (ret != ICE_SUCCESS) {
4828 "update VSI for VLAN insert failed, err %d",
4833 vsi->info.valid_sections |=
4834 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4840 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4842 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4843 struct ice_vsi *vsi = pf->main_vsi;
4844 struct rte_eth_dev_data *data = pf->dev_data;
4845 struct ice_vsi_vlan_pvid_info info;
4848 memset(&info, 0, sizeof(info));
4851 info.config.pvid = pvid;
4853 info.config.reject.tagged =
4854 data->dev_conf.txmode.hw_vlan_reject_tagged;
4855 info.config.reject.untagged =
4856 data->dev_conf.txmode.hw_vlan_reject_untagged;
4859 ret = ice_vsi_vlan_pvid_set(vsi, &info);
4861 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4869 ice_get_eeprom_length(struct rte_eth_dev *dev)
4871 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4873 return hw->flash.flash_size;
4877 ice_get_eeprom(struct rte_eth_dev *dev,
4878 struct rte_dev_eeprom_info *eeprom)
4880 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4881 enum ice_status status = ICE_SUCCESS;
4882 uint8_t *data = eeprom->data;
4884 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4886 status = ice_acquire_nvm(hw, ICE_RES_READ);
4888 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4892 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4895 ice_release_nvm(hw);
4898 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4906 ice_stat_update_32(struct ice_hw *hw,
4914 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4918 if (new_data >= *offset)
4919 *stat = (uint64_t)(new_data - *offset);
4921 *stat = (uint64_t)((new_data +
4922 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4927 ice_stat_update_40(struct ice_hw *hw,
4936 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4937 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4943 if (new_data >= *offset)
4944 *stat = new_data - *offset;
4946 *stat = (uint64_t)((new_data +
4947 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4950 *stat &= ICE_40_BIT_MASK;
4953 /* Get all the statistics of a VSI */
4955 ice_update_vsi_stats(struct ice_vsi *vsi)
4957 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4958 struct ice_eth_stats *nes = &vsi->eth_stats;
4959 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4960 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4962 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4963 vsi->offset_loaded, &oes->rx_bytes,
4965 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4966 vsi->offset_loaded, &oes->rx_unicast,
4968 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4969 vsi->offset_loaded, &oes->rx_multicast,
4970 &nes->rx_multicast);
4971 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4972 vsi->offset_loaded, &oes->rx_broadcast,
4973 &nes->rx_broadcast);
4974 /* enlarge the limitation when rx_bytes overflowed */
4975 if (vsi->offset_loaded) {
4976 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4977 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4978 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4980 vsi->old_rx_bytes = nes->rx_bytes;
4981 /* exclude CRC bytes */
4982 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4983 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4985 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4986 &oes->rx_discards, &nes->rx_discards);
4987 /* GLV_REPC not supported */
4988 /* GLV_RMPC not supported */
4989 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4990 &oes->rx_unknown_protocol,
4991 &nes->rx_unknown_protocol);
4992 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4993 vsi->offset_loaded, &oes->tx_bytes,
4995 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4996 vsi->offset_loaded, &oes->tx_unicast,
4998 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4999 vsi->offset_loaded, &oes->tx_multicast,
5000 &nes->tx_multicast);
5001 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
5002 vsi->offset_loaded, &oes->tx_broadcast,
5003 &nes->tx_broadcast);
5004 /* GLV_TDPC not supported */
5005 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
5006 &oes->tx_errors, &nes->tx_errors);
5007 /* enlarge the limitation when tx_bytes overflowed */
5008 if (vsi->offset_loaded) {
5009 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
5010 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5011 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
5013 vsi->old_tx_bytes = nes->tx_bytes;
5014 vsi->offset_loaded = true;
5016 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
5018 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
5019 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
5020 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
5021 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
5022 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
5023 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5024 nes->rx_unknown_protocol);
5025 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
5026 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
5027 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
5028 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
5029 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
5030 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
5031 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
5036 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
5038 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5039 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
5041 /* Get statistics of struct ice_eth_stats */
5042 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
5043 GLPRT_GORCL(hw->port_info->lport),
5044 pf->offset_loaded, &os->eth.rx_bytes,
5046 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
5047 GLPRT_UPRCL(hw->port_info->lport),
5048 pf->offset_loaded, &os->eth.rx_unicast,
5049 &ns->eth.rx_unicast);
5050 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
5051 GLPRT_MPRCL(hw->port_info->lport),
5052 pf->offset_loaded, &os->eth.rx_multicast,
5053 &ns->eth.rx_multicast);
5054 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
5055 GLPRT_BPRCL(hw->port_info->lport),
5056 pf->offset_loaded, &os->eth.rx_broadcast,
5057 &ns->eth.rx_broadcast);
5058 ice_stat_update_32(hw, PRTRPB_RDPC,
5059 pf->offset_loaded, &os->eth.rx_discards,
5060 &ns->eth.rx_discards);
5061 /* enlarge the limitation when rx_bytes overflowed */
5062 if (pf->offset_loaded) {
5063 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
5064 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5065 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
5067 pf->old_rx_bytes = ns->eth.rx_bytes;
5069 /* Workaround: CRC size should not be included in byte statistics,
5070 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
5073 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
5074 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
5076 /* GLPRT_REPC not supported */
5077 /* GLPRT_RMPC not supported */
5078 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
5080 &os->eth.rx_unknown_protocol,
5081 &ns->eth.rx_unknown_protocol);
5082 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
5083 GLPRT_GOTCL(hw->port_info->lport),
5084 pf->offset_loaded, &os->eth.tx_bytes,
5086 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
5087 GLPRT_UPTCL(hw->port_info->lport),
5088 pf->offset_loaded, &os->eth.tx_unicast,
5089 &ns->eth.tx_unicast);
5090 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
5091 GLPRT_MPTCL(hw->port_info->lport),
5092 pf->offset_loaded, &os->eth.tx_multicast,
5093 &ns->eth.tx_multicast);
5094 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
5095 GLPRT_BPTCL(hw->port_info->lport),
5096 pf->offset_loaded, &os->eth.tx_broadcast,
5097 &ns->eth.tx_broadcast);
5098 /* enlarge the limitation when tx_bytes overflowed */
5099 if (pf->offset_loaded) {
5100 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
5101 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5102 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
5104 pf->old_tx_bytes = ns->eth.tx_bytes;
5105 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
5106 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
5108 /* GLPRT_TEPC not supported */
5110 /* additional port specific stats */
5111 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
5112 pf->offset_loaded, &os->tx_dropped_link_down,
5113 &ns->tx_dropped_link_down);
5114 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
5115 pf->offset_loaded, &os->crc_errors,
5117 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
5118 pf->offset_loaded, &os->illegal_bytes,
5119 &ns->illegal_bytes);
5120 /* GLPRT_ERRBC not supported */
5121 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
5122 pf->offset_loaded, &os->mac_local_faults,
5123 &ns->mac_local_faults);
5124 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
5125 pf->offset_loaded, &os->mac_remote_faults,
5126 &ns->mac_remote_faults);
5128 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
5129 pf->offset_loaded, &os->rx_len_errors,
5130 &ns->rx_len_errors);
5132 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
5133 pf->offset_loaded, &os->link_xon_rx,
5135 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
5136 pf->offset_loaded, &os->link_xoff_rx,
5138 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
5139 pf->offset_loaded, &os->link_xon_tx,
5141 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
5142 pf->offset_loaded, &os->link_xoff_tx,
5144 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
5145 GLPRT_PRC64L(hw->port_info->lport),
5146 pf->offset_loaded, &os->rx_size_64,
5148 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
5149 GLPRT_PRC127L(hw->port_info->lport),
5150 pf->offset_loaded, &os->rx_size_127,
5152 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
5153 GLPRT_PRC255L(hw->port_info->lport),
5154 pf->offset_loaded, &os->rx_size_255,
5156 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
5157 GLPRT_PRC511L(hw->port_info->lport),
5158 pf->offset_loaded, &os->rx_size_511,
5160 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
5161 GLPRT_PRC1023L(hw->port_info->lport),
5162 pf->offset_loaded, &os->rx_size_1023,
5164 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
5165 GLPRT_PRC1522L(hw->port_info->lport),
5166 pf->offset_loaded, &os->rx_size_1522,
5168 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
5169 GLPRT_PRC9522L(hw->port_info->lport),
5170 pf->offset_loaded, &os->rx_size_big,
5172 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
5173 pf->offset_loaded, &os->rx_undersize,
5175 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
5176 pf->offset_loaded, &os->rx_fragments,
5178 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5179 pf->offset_loaded, &os->rx_oversize,
5181 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5182 pf->offset_loaded, &os->rx_jabber,
5184 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5185 GLPRT_PTC64L(hw->port_info->lport),
5186 pf->offset_loaded, &os->tx_size_64,
5188 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5189 GLPRT_PTC127L(hw->port_info->lport),
5190 pf->offset_loaded, &os->tx_size_127,
5192 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5193 GLPRT_PTC255L(hw->port_info->lport),
5194 pf->offset_loaded, &os->tx_size_255,
5196 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5197 GLPRT_PTC511L(hw->port_info->lport),
5198 pf->offset_loaded, &os->tx_size_511,
5200 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5201 GLPRT_PTC1023L(hw->port_info->lport),
5202 pf->offset_loaded, &os->tx_size_1023,
5204 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5205 GLPRT_PTC1522L(hw->port_info->lport),
5206 pf->offset_loaded, &os->tx_size_1522,
5208 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5209 GLPRT_PTC9522L(hw->port_info->lport),
5210 pf->offset_loaded, &os->tx_size_big,
5213 /* GLPRT_MSPDC not supported */
5214 /* GLPRT_XEC not supported */
5216 pf->offset_loaded = true;
5219 ice_update_vsi_stats(pf->main_vsi);
5222 /* Get all statistics of a port */
5224 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5226 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5227 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5228 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5230 /* call read registers - updates values, now write them to struct */
5231 ice_read_stats_registers(pf, hw);
5233 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5234 pf->main_vsi->eth_stats.rx_multicast +
5235 pf->main_vsi->eth_stats.rx_broadcast -
5236 pf->main_vsi->eth_stats.rx_discards;
5237 stats->opackets = ns->eth.tx_unicast +
5238 ns->eth.tx_multicast +
5239 ns->eth.tx_broadcast;
5240 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
5241 stats->obytes = ns->eth.tx_bytes;
5242 stats->oerrors = ns->eth.tx_errors +
5243 pf->main_vsi->eth_stats.tx_errors;
5246 stats->imissed = ns->eth.rx_discards +
5247 pf->main_vsi->eth_stats.rx_discards;
5248 stats->ierrors = ns->crc_errors +
5250 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5252 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5253 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
5254 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5255 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5256 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5257 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5258 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5259 pf->main_vsi->eth_stats.rx_discards);
5260 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5261 ns->eth.rx_unknown_protocol);
5262 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
5263 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5264 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5265 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5266 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5267 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5268 pf->main_vsi->eth_stats.tx_discards);
5269 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
5271 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
5272 ns->tx_dropped_link_down);
5273 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5274 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
5276 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
5277 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
5278 ns->mac_local_faults);
5279 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
5280 ns->mac_remote_faults);
5281 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
5282 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
5283 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
5284 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
5285 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
5286 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
5287 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
5288 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
5289 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
5290 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
5291 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
5292 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
5293 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
5294 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
5295 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
5296 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
5297 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
5298 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
5299 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
5300 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
5301 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
5302 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
5303 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
5304 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5308 /* Reset the statistics */
5310 ice_stats_reset(struct rte_eth_dev *dev)
5312 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5313 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5315 /* Mark PF and VSI stats to update the offset, aka "reset" */
5316 pf->offset_loaded = false;
5318 pf->main_vsi->offset_loaded = false;
5320 /* read the stats, reading current register values into offset */
5321 ice_read_stats_registers(pf, hw);
5327 ice_xstats_calc_num(void)
5331 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5337 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5340 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5341 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5344 struct ice_hw_port_stats *hw_stats = &pf->stats;
5346 count = ice_xstats_calc_num();
5350 ice_read_stats_registers(pf, hw);
5357 /* Get stats from ice_eth_stats struct */
5358 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5359 xstats[count].value =
5360 *(uint64_t *)((char *)&hw_stats->eth +
5361 ice_stats_strings[i].offset);
5362 xstats[count].id = count;
5366 /* Get individiual stats from ice_hw_port struct */
5367 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5368 xstats[count].value =
5369 *(uint64_t *)((char *)hw_stats +
5370 ice_hw_port_strings[i].offset);
5371 xstats[count].id = count;
5378 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5379 struct rte_eth_xstat_name *xstats_names,
5380 __rte_unused unsigned int limit)
5382 unsigned int count = 0;
5386 return ice_xstats_calc_num();
5388 /* Note: limit checked in rte_eth_xstats_names() */
5390 /* Get stats from ice_eth_stats struct */
5391 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5392 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5393 sizeof(xstats_names[count].name));
5397 /* Get individiual stats from ice_hw_port struct */
5398 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5399 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5400 sizeof(xstats_names[count].name));
5408 ice_dev_flow_ops_get(struct rte_eth_dev *dev,
5409 const struct rte_flow_ops **ops)
5414 *ops = &ice_flow_ops;
5418 /* Add UDP tunneling port */
5420 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5421 struct rte_eth_udp_tunnel *udp_tunnel)
5424 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5426 if (udp_tunnel == NULL)
5429 switch (udp_tunnel->prot_type) {
5430 case RTE_TUNNEL_TYPE_VXLAN:
5431 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5434 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5442 /* Delete UDP tunneling port */
5444 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5445 struct rte_eth_udp_tunnel *udp_tunnel)
5448 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5450 if (udp_tunnel == NULL)
5453 switch (udp_tunnel->prot_type) {
5454 case RTE_TUNNEL_TYPE_VXLAN:
5455 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5458 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5467 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5468 struct rte_pci_device *pci_dev)
5470 return rte_eth_dev_pci_generic_probe(pci_dev,
5471 sizeof(struct ice_adapter),
5476 ice_pci_remove(struct rte_pci_device *pci_dev)
5478 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5481 static struct rte_pci_driver rte_ice_pmd = {
5482 .id_table = pci_id_ice_map,
5483 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5484 .probe = ice_pci_probe,
5485 .remove = ice_pci_remove,
5489 * Driver initialization routine.
5490 * Invoked once at EAL init time.
5491 * Register itself as the [Poll Mode] Driver of PCI devices.
5493 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5494 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5495 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5496 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5497 ICE_HW_DEBUG_MASK_ARG "=0xXXX"
5498 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5499 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5500 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5502 RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE);
5503 RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE);
5504 #ifdef RTE_ETHDEV_DEBUG_RX
5505 RTE_LOG_REGISTER_SUFFIX(ice_logtype_rx, rx, DEBUG);
5507 #ifdef RTE_ETHDEV_DEBUG_TX
5508 RTE_LOG_REGISTER_SUFFIX(ice_logtype_tx, tx, DEBUG);