1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
18 #include "rte_pmd_ice.h"
19 #include "ice_ethdev.h"
21 #include "ice_generic_flow.h"
24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
26 #define ICE_PROTO_XTR_ARG "proto_xtr"
28 static const char * const ice_valid_args[] = {
29 ICE_SAFE_MODE_SUPPORT_ARG,
30 ICE_PIPELINE_MODE_SUPPORT_ARG,
35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
36 .name = "intel_pmd_dynfield_proto_xtr_metadata",
37 .size = sizeof(uint32_t),
38 .align = __alignof__(uint32_t),
42 struct proto_xtr_ol_flag {
43 const struct rte_mbuf_dynflag param;
48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
52 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
55 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
58 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
60 [PROTO_XTR_IPV6_FLOW] = {
61 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
64 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
66 [PROTO_XTR_IP_OFFSET] = {
67 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
68 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
71 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
72 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
73 #define ICE_MAX_RES_DESC_NUM 1024
75 static int ice_dev_configure(struct rte_eth_dev *dev);
76 static int ice_dev_start(struct rte_eth_dev *dev);
77 static int ice_dev_stop(struct rte_eth_dev *dev);
78 static int ice_dev_close(struct rte_eth_dev *dev);
79 static int ice_dev_reset(struct rte_eth_dev *dev);
80 static int ice_dev_info_get(struct rte_eth_dev *dev,
81 struct rte_eth_dev_info *dev_info);
82 static int ice_link_update(struct rte_eth_dev *dev,
83 int wait_to_complete);
84 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
85 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
87 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
88 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
89 static int ice_rss_reta_update(struct rte_eth_dev *dev,
90 struct rte_eth_rss_reta_entry64 *reta_conf,
92 static int ice_rss_reta_query(struct rte_eth_dev *dev,
93 struct rte_eth_rss_reta_entry64 *reta_conf,
95 static int ice_rss_hash_update(struct rte_eth_dev *dev,
96 struct rte_eth_rss_conf *rss_conf);
97 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
98 struct rte_eth_rss_conf *rss_conf);
99 static int ice_promisc_enable(struct rte_eth_dev *dev);
100 static int ice_promisc_disable(struct rte_eth_dev *dev);
101 static int ice_allmulti_enable(struct rte_eth_dev *dev);
102 static int ice_allmulti_disable(struct rte_eth_dev *dev);
103 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
106 static int ice_macaddr_set(struct rte_eth_dev *dev,
107 struct rte_ether_addr *mac_addr);
108 static int ice_macaddr_add(struct rte_eth_dev *dev,
109 struct rte_ether_addr *mac_addr,
110 __rte_unused uint32_t index,
112 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
113 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
115 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
117 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
119 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
120 uint16_t pvid, int on);
121 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
122 static int ice_get_eeprom(struct rte_eth_dev *dev,
123 struct rte_dev_eeprom_info *eeprom);
124 static int ice_stats_get(struct rte_eth_dev *dev,
125 struct rte_eth_stats *stats);
126 static int ice_stats_reset(struct rte_eth_dev *dev);
127 static int ice_xstats_get(struct rte_eth_dev *dev,
128 struct rte_eth_xstat *xstats, unsigned int n);
129 static int ice_xstats_get_names(struct rte_eth_dev *dev,
130 struct rte_eth_xstat_name *xstats_names,
132 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev,
133 const struct rte_flow_ops **ops);
134 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
135 struct rte_eth_udp_tunnel *udp_tunnel);
136 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
137 struct rte_eth_udp_tunnel *udp_tunnel);
139 static const struct rte_pci_id pci_id_ice_map[] = {
140 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
141 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
142 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
143 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
144 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
145 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
146 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
147 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
148 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
149 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
150 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
157 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
159 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
164 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
165 { .vendor_id = 0, /* sentinel */ },
168 static const struct eth_dev_ops ice_eth_dev_ops = {
169 .dev_configure = ice_dev_configure,
170 .dev_start = ice_dev_start,
171 .dev_stop = ice_dev_stop,
172 .dev_close = ice_dev_close,
173 .dev_reset = ice_dev_reset,
174 .dev_set_link_up = ice_dev_set_link_up,
175 .dev_set_link_down = ice_dev_set_link_down,
176 .rx_queue_start = ice_rx_queue_start,
177 .rx_queue_stop = ice_rx_queue_stop,
178 .tx_queue_start = ice_tx_queue_start,
179 .tx_queue_stop = ice_tx_queue_stop,
180 .rx_queue_setup = ice_rx_queue_setup,
181 .rx_queue_release = ice_rx_queue_release,
182 .tx_queue_setup = ice_tx_queue_setup,
183 .tx_queue_release = ice_tx_queue_release,
184 .dev_infos_get = ice_dev_info_get,
185 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
186 .link_update = ice_link_update,
187 .mtu_set = ice_mtu_set,
188 .mac_addr_set = ice_macaddr_set,
189 .mac_addr_add = ice_macaddr_add,
190 .mac_addr_remove = ice_macaddr_remove,
191 .vlan_filter_set = ice_vlan_filter_set,
192 .vlan_offload_set = ice_vlan_offload_set,
193 .reta_update = ice_rss_reta_update,
194 .reta_query = ice_rss_reta_query,
195 .rss_hash_update = ice_rss_hash_update,
196 .rss_hash_conf_get = ice_rss_hash_conf_get,
197 .promiscuous_enable = ice_promisc_enable,
198 .promiscuous_disable = ice_promisc_disable,
199 .allmulticast_enable = ice_allmulti_enable,
200 .allmulticast_disable = ice_allmulti_disable,
201 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
202 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
203 .fw_version_get = ice_fw_version_get,
204 .vlan_pvid_set = ice_vlan_pvid_set,
205 .rxq_info_get = ice_rxq_info_get,
206 .txq_info_get = ice_txq_info_get,
207 .rx_burst_mode_get = ice_rx_burst_mode_get,
208 .tx_burst_mode_get = ice_tx_burst_mode_get,
209 .get_eeprom_length = ice_get_eeprom_length,
210 .get_eeprom = ice_get_eeprom,
211 .stats_get = ice_stats_get,
212 .stats_reset = ice_stats_reset,
213 .xstats_get = ice_xstats_get,
214 .xstats_get_names = ice_xstats_get_names,
215 .xstats_reset = ice_stats_reset,
216 .flow_ops_get = ice_dev_flow_ops_get,
217 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
218 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
219 .tx_done_cleanup = ice_tx_done_cleanup,
220 .get_monitor_addr = ice_get_monitor_addr,
223 /* store statistics names and its offset in stats structure */
224 struct ice_xstats_name_off {
225 char name[RTE_ETH_XSTATS_NAME_SIZE];
229 static const struct ice_xstats_name_off ice_stats_strings[] = {
230 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
231 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
232 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
233 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
234 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
235 rx_unknown_protocol)},
236 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
237 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
238 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
239 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
242 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
243 sizeof(ice_stats_strings[0]))
245 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
246 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
247 tx_dropped_link_down)},
248 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
249 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
251 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
252 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
254 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
256 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
258 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
259 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
260 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
261 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
262 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
263 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
265 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
267 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
269 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
271 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
273 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
275 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
277 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
279 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
280 mac_short_pkt_dropped)},
281 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
283 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
284 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
285 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
287 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
289 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
291 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
293 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
295 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
299 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
300 sizeof(ice_hw_port_strings[0]))
303 ice_init_controlq_parameter(struct ice_hw *hw)
305 /* fields for adminq */
306 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
307 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
308 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
309 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
311 /* fields for mailboxq, DPDK used as PF host */
312 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
313 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
314 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
315 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
319 lookup_proto_xtr_type(const char *xtr_name)
323 enum proto_xtr_type type;
325 { "vlan", PROTO_XTR_VLAN },
326 { "ipv4", PROTO_XTR_IPV4 },
327 { "ipv6", PROTO_XTR_IPV6 },
328 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
329 { "tcp", PROTO_XTR_TCP },
330 { "ip_offset", PROTO_XTR_IP_OFFSET },
334 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
335 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
336 return xtr_type_map[i].type;
343 * Parse elem, the elem could be single number/range or '(' ')' group
344 * 1) A single number elem, it's just a simple digit. e.g. 9
345 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
346 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
347 * Within group elem, '-' used for a range separator;
348 * ',' used for a single number.
351 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
353 const char *str = input;
358 while (isblank(*str))
361 if (!isdigit(*str) && *str != '(')
364 /* process single number or single range of number */
367 idx = strtoul(str, &end, 10);
368 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
371 while (isblank(*end))
377 /* process single <number>-<number> */
380 while (isblank(*end))
386 idx = strtoul(end, &end, 10);
387 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
391 while (isblank(*end))
398 for (idx = RTE_MIN(min, max);
399 idx <= RTE_MAX(min, max); idx++)
400 devargs->proto_xtr[idx] = xtr_type;
405 /* process set within bracket */
407 while (isblank(*str))
412 min = ICE_MAX_QUEUE_NUM;
414 /* go ahead to the first digit */
415 while (isblank(*str))
420 /* get the digit value */
422 idx = strtoul(str, &end, 10);
423 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
426 /* go ahead to separator '-',',' and ')' */
427 while (isblank(*end))
430 if (min == ICE_MAX_QUEUE_NUM)
432 else /* avoid continuous '-' */
434 } else if (*end == ',' || *end == ')') {
436 if (min == ICE_MAX_QUEUE_NUM)
439 for (idx = RTE_MIN(min, max);
440 idx <= RTE_MAX(min, max); idx++)
441 devargs->proto_xtr[idx] = xtr_type;
443 min = ICE_MAX_QUEUE_NUM;
449 } while (*end != ')' && *end != '\0');
455 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
457 const char *queue_start;
462 while (isblank(*queues))
465 if (*queues != '[') {
466 xtr_type = lookup_proto_xtr_type(queues);
470 devargs->proto_xtr_dflt = xtr_type;
477 while (isblank(*queues))
482 queue_start = queues;
484 /* go across a complete bracket */
485 if (*queue_start == '(') {
486 queues += strcspn(queues, ")");
491 /* scan the separator ':' */
492 queues += strcspn(queues, ":");
493 if (*queues++ != ':')
495 while (isblank(*queues))
498 for (idx = 0; ; idx++) {
499 if (isblank(queues[idx]) ||
500 queues[idx] == ',' ||
501 queues[idx] == ']' ||
505 if (idx > sizeof(xtr_name) - 2)
508 xtr_name[idx] = queues[idx];
510 xtr_name[idx] = '\0';
511 xtr_type = lookup_proto_xtr_type(xtr_name);
517 while (isblank(*queues) || *queues == ',' || *queues == ']')
520 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
522 } while (*queues != '\0');
528 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
531 struct ice_devargs *devargs = extra_args;
533 if (value == NULL || extra_args == NULL)
536 if (parse_queue_proto_xtr(value, devargs) < 0) {
538 "The protocol extraction parameter is wrong : '%s'",
547 ice_check_proto_xtr_support(struct ice_hw *hw)
549 #define FLX_REG(val, fld, idx) \
550 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
551 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
558 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
560 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
561 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
563 ICE_PROT_IPV4_OF_OR_S,
564 ICE_PROT_IPV4_OF_OR_S },
565 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
567 ICE_PROT_IPV6_OF_OR_S,
568 ICE_PROT_IPV6_OF_OR_S },
569 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
571 ICE_PROT_IPV6_OF_OR_S,
572 ICE_PROT_IPV6_OF_OR_S },
573 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
575 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
576 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
578 ICE_PROT_IPV4_OF_OR_S,
579 ICE_PROT_IPV6_OF_OR_S },
583 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
584 uint32_t rxdid = xtr_sets[i].rxdid;
587 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
588 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
590 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
591 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
592 ice_proto_xtr_hw_support[i] = true;
595 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
596 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
598 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
599 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
600 ice_proto_xtr_hw_support[i] = true;
606 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
609 struct pool_entry *entry;
614 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
617 "Failed to allocate memory for resource pool");
621 /* queue heap initialize */
622 pool->num_free = num;
625 LIST_INIT(&pool->alloc_list);
626 LIST_INIT(&pool->free_list);
628 /* Initialize element */
632 LIST_INSERT_HEAD(&pool->free_list, entry, next);
637 ice_res_pool_alloc(struct ice_res_pool_info *pool,
640 struct pool_entry *entry, *valid_entry;
643 PMD_INIT_LOG(ERR, "Invalid parameter");
647 if (pool->num_free < num) {
648 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
649 num, pool->num_free);
654 /* Lookup in free list and find most fit one */
655 LIST_FOREACH(entry, &pool->free_list, next) {
656 if (entry->len >= num) {
658 if (entry->len == num) {
663 valid_entry->len > entry->len)
668 /* Not find one to satisfy the request, return */
670 PMD_INIT_LOG(ERR, "No valid entry found");
674 * The entry have equal queue number as requested,
675 * remove it from alloc_list.
677 if (valid_entry->len == num) {
678 LIST_REMOVE(valid_entry, next);
681 * The entry have more numbers than requested,
682 * create a new entry for alloc_list and minus its
683 * queue base and number in free_list.
685 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
688 "Failed to allocate memory for "
692 entry->base = valid_entry->base;
694 valid_entry->base += num;
695 valid_entry->len -= num;
699 /* Insert it into alloc list, not sorted */
700 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
702 pool->num_free -= valid_entry->len;
703 pool->num_alloc += valid_entry->len;
705 return valid_entry->base + pool->base;
709 ice_res_pool_destroy(struct ice_res_pool_info *pool)
711 struct pool_entry *entry, *next_entry;
716 for (entry = LIST_FIRST(&pool->alloc_list);
717 entry && (next_entry = LIST_NEXT(entry, next), 1);
718 entry = next_entry) {
719 LIST_REMOVE(entry, next);
723 for (entry = LIST_FIRST(&pool->free_list);
724 entry && (next_entry = LIST_NEXT(entry, next), 1);
725 entry = next_entry) {
726 LIST_REMOVE(entry, next);
733 LIST_INIT(&pool->alloc_list);
734 LIST_INIT(&pool->free_list);
738 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
740 /* Set VSI LUT selection */
741 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
742 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
743 /* Set Hash scheme */
744 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
745 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
747 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
750 static enum ice_status
751 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
752 struct ice_aqc_vsi_props *info,
753 uint8_t enabled_tcmap)
755 uint16_t bsf, qp_idx;
757 /* default tc 0 now. Multi-TC supporting need to be done later.
758 * Configure TC and queue mapping parameters, for enabled TC,
759 * allocate qpnum_per_tc queues to this traffic.
761 if (enabled_tcmap != 0x01) {
762 PMD_INIT_LOG(ERR, "only TC0 is supported");
766 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
767 bsf = rte_bsf32(vsi->nb_qps);
768 /* Adjust the queue number to actual queues that can be applied */
769 vsi->nb_qps = 0x1 << bsf;
772 /* Set tc and queue mapping with VSI */
773 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
774 ICE_AQ_VSI_TC_Q_OFFSET_S) |
775 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
777 /* Associate queue number with VSI */
778 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
779 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
780 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
781 info->valid_sections |=
782 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
783 /* Set the info.ingress_table and info.egress_table
784 * for UP translate table. Now just set it to 1:1 map by default
785 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
787 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
788 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
789 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
790 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
795 ice_init_mac_address(struct rte_eth_dev *dev)
797 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
799 if (!rte_is_unicast_ether_addr
800 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
801 PMD_INIT_LOG(ERR, "Invalid MAC address");
806 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
807 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
809 dev->data->mac_addrs =
810 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0);
811 if (!dev->data->mac_addrs) {
813 "Failed to allocate memory to store mac address");
816 /* store it to dev data */
818 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
819 &dev->data->mac_addrs[0]);
823 /* Find out specific MAC filter */
824 static struct ice_mac_filter *
825 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
827 struct ice_mac_filter *f;
829 TAILQ_FOREACH(f, &vsi->mac_list, next) {
830 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
838 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
840 struct ice_fltr_list_entry *m_list_itr = NULL;
841 struct ice_mac_filter *f;
842 struct LIST_HEAD_TYPE list_head;
843 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
846 /* If it's added and configured, return */
847 f = ice_find_mac_filter(vsi, mac_addr);
849 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
853 INIT_LIST_HEAD(&list_head);
855 m_list_itr = (struct ice_fltr_list_entry *)
856 ice_malloc(hw, sizeof(*m_list_itr));
861 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
862 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
863 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
864 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
865 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
866 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
867 m_list_itr->fltr_info.vsi_handle = vsi->idx;
869 LIST_ADD(&m_list_itr->list_entry, &list_head);
872 ret = ice_add_mac(hw, &list_head);
873 if (ret != ICE_SUCCESS) {
874 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
878 /* Add the mac addr into mac list */
879 f = rte_zmalloc(NULL, sizeof(*f), 0);
881 PMD_DRV_LOG(ERR, "failed to allocate memory");
885 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
886 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
892 rte_free(m_list_itr);
897 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
899 struct ice_fltr_list_entry *m_list_itr = NULL;
900 struct ice_mac_filter *f;
901 struct LIST_HEAD_TYPE list_head;
902 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
905 /* Can't find it, return an error */
906 f = ice_find_mac_filter(vsi, mac_addr);
910 INIT_LIST_HEAD(&list_head);
912 m_list_itr = (struct ice_fltr_list_entry *)
913 ice_malloc(hw, sizeof(*m_list_itr));
918 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
919 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
920 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
921 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
922 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
923 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
924 m_list_itr->fltr_info.vsi_handle = vsi->idx;
926 LIST_ADD(&m_list_itr->list_entry, &list_head);
928 /* remove the mac filter */
929 ret = ice_remove_mac(hw, &list_head);
930 if (ret != ICE_SUCCESS) {
931 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
936 /* Remove the mac addr from mac list */
937 TAILQ_REMOVE(&vsi->mac_list, f, next);
943 rte_free(m_list_itr);
947 /* Find out specific VLAN filter */
948 static struct ice_vlan_filter *
949 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
951 struct ice_vlan_filter *f;
953 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
954 if (vlan->tpid == f->vlan_info.vlan.tpid &&
955 vlan->vid == f->vlan_info.vlan.vid)
963 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
965 struct ice_fltr_list_entry *v_list_itr = NULL;
966 struct ice_vlan_filter *f;
967 struct LIST_HEAD_TYPE list_head;
971 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
974 hw = ICE_VSI_TO_HW(vsi);
976 /* If it's added and configured, return. */
977 f = ice_find_vlan_filter(vsi, vlan);
979 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
983 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
986 INIT_LIST_HEAD(&list_head);
988 v_list_itr = (struct ice_fltr_list_entry *)
989 ice_malloc(hw, sizeof(*v_list_itr));
994 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
995 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
996 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
997 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
998 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
999 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1000 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1001 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1003 LIST_ADD(&v_list_itr->list_entry, &list_head);
1006 ret = ice_add_vlan(hw, &list_head);
1007 if (ret != ICE_SUCCESS) {
1008 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1013 /* Add vlan into vlan list */
1014 f = rte_zmalloc(NULL, sizeof(*f), 0);
1016 PMD_DRV_LOG(ERR, "failed to allocate memory");
1020 f->vlan_info.vlan.tpid = vlan->tpid;
1021 f->vlan_info.vlan.vid = vlan->vid;
1022 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1028 rte_free(v_list_itr);
1033 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1035 struct ice_fltr_list_entry *v_list_itr = NULL;
1036 struct ice_vlan_filter *f;
1037 struct LIST_HEAD_TYPE list_head;
1041 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1044 hw = ICE_VSI_TO_HW(vsi);
1046 /* Can't find it, return an error */
1047 f = ice_find_vlan_filter(vsi, vlan);
1051 INIT_LIST_HEAD(&list_head);
1053 v_list_itr = (struct ice_fltr_list_entry *)
1054 ice_malloc(hw, sizeof(*v_list_itr));
1060 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1061 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1062 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1063 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1064 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1065 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1066 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1067 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1069 LIST_ADD(&v_list_itr->list_entry, &list_head);
1071 /* remove the vlan filter */
1072 ret = ice_remove_vlan(hw, &list_head);
1073 if (ret != ICE_SUCCESS) {
1074 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1079 /* Remove the vlan id from vlan list */
1080 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1086 rte_free(v_list_itr);
1091 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1093 struct ice_mac_filter *m_f;
1094 struct ice_vlan_filter *v_f;
1097 if (!vsi || !vsi->mac_num)
1100 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1101 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1102 if (ret != ICE_SUCCESS) {
1108 if (vsi->vlan_num == 0)
1111 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1112 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1113 if (ret != ICE_SUCCESS) {
1125 ice_pf_enable_irq0(struct ice_hw *hw)
1127 /* reset the registers */
1128 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1129 ICE_READ_REG(hw, PFINT_OICR);
1132 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1133 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1134 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1136 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1137 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1138 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1139 PFINT_OICR_CTL_ITR_INDX_M) |
1140 PFINT_OICR_CTL_CAUSE_ENA_M);
1142 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1143 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1144 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1145 PFINT_FW_CTL_ITR_INDX_M) |
1146 PFINT_FW_CTL_CAUSE_ENA_M);
1148 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1151 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1152 GLINT_DYN_CTL_INTENA_M |
1153 GLINT_DYN_CTL_CLEARPBA_M |
1154 GLINT_DYN_CTL_ITR_INDX_M);
1161 ice_pf_disable_irq0(struct ice_hw *hw)
1163 /* Disable all interrupt types */
1164 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1170 ice_handle_aq_msg(struct rte_eth_dev *dev)
1172 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1173 struct ice_ctl_q_info *cq = &hw->adminq;
1174 struct ice_rq_event_info event;
1175 uint16_t pending, opcode;
1178 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1179 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1180 if (!event.msg_buf) {
1181 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1187 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1189 if (ret != ICE_SUCCESS) {
1191 "Failed to read msg from AdminQ, "
1193 hw->adminq.sq_last_status);
1196 opcode = rte_le_to_cpu_16(event.desc.opcode);
1199 case ice_aqc_opc_get_link_status:
1200 ret = ice_link_update(dev, 0);
1202 rte_eth_dev_callback_process
1203 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1206 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1211 rte_free(event.msg_buf);
1216 * Interrupt handler triggered by NIC for handling
1217 * specific interrupt.
1220 * Pointer to interrupt handle.
1222 * The address of parameter (struct rte_eth_dev *) regsitered before.
1228 ice_interrupt_handler(void *param)
1230 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1231 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1239 uint32_t int_fw_ctl;
1242 /* Disable interrupt */
1243 ice_pf_disable_irq0(hw);
1245 /* read out interrupt causes */
1246 oicr = ICE_READ_REG(hw, PFINT_OICR);
1248 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1251 /* No interrupt event indicated */
1252 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1253 PMD_DRV_LOG(INFO, "No interrupt event");
1258 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1259 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1260 ice_handle_aq_msg(dev);
1263 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1264 PMD_DRV_LOG(INFO, "OICR: link state change event");
1265 ret = ice_link_update(dev, 0);
1267 rte_eth_dev_callback_process
1268 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1272 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1273 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1274 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1275 if (reg & GL_MDET_TX_PQM_VALID_M) {
1276 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1277 GL_MDET_TX_PQM_PF_NUM_S;
1278 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1279 GL_MDET_TX_PQM_MAL_TYPE_S;
1280 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1281 GL_MDET_TX_PQM_QNUM_S;
1283 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1284 "%d by PQM on TX queue %d PF# %d",
1285 event, queue, pf_num);
1288 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1289 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1290 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1291 GL_MDET_TX_TCLAN_PF_NUM_S;
1292 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1293 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1294 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1295 GL_MDET_TX_TCLAN_QNUM_S;
1297 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1298 "%d by TCLAN on TX queue %d PF# %d",
1299 event, queue, pf_num);
1303 /* Enable interrupt */
1304 ice_pf_enable_irq0(hw);
1305 rte_intr_ack(dev->intr_handle);
1309 ice_init_proto_xtr(struct rte_eth_dev *dev)
1311 struct ice_adapter *ad =
1312 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1313 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1314 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1315 const struct proto_xtr_ol_flag *ol_flag;
1316 bool proto_xtr_enable = false;
1320 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1321 if (unlikely(pf->proto_xtr == NULL)) {
1322 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1326 for (i = 0; i < pf->lan_nb_qps; i++) {
1327 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1328 ad->devargs.proto_xtr[i] :
1329 ad->devargs.proto_xtr_dflt;
1331 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1332 uint8_t type = pf->proto_xtr[i];
1334 ice_proto_xtr_ol_flag_params[type].required = true;
1335 proto_xtr_enable = true;
1339 if (likely(!proto_xtr_enable))
1342 ice_check_proto_xtr_support(hw);
1344 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1345 if (unlikely(offset == -1)) {
1347 "Protocol extraction metadata is disabled in mbuf with error %d",
1353 "Protocol extraction metadata offset in mbuf is : %d",
1355 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1357 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1358 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1360 if (!ol_flag->required)
1363 if (!ice_proto_xtr_hw_support[i]) {
1365 "Protocol extraction type %u is not supported in hardware",
1367 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1371 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1372 if (unlikely(offset == -1)) {
1374 "Protocol extraction offload '%s' failed to register with error %d",
1375 ol_flag->param.name, -rte_errno);
1377 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1382 "Protocol extraction offload '%s' offset in mbuf is : %d",
1383 ol_flag->param.name, offset);
1384 *ol_flag->ol_flag = 1ULL << offset;
1388 /* Initialize SW parameters of PF */
1390 ice_pf_sw_init(struct rte_eth_dev *dev)
1392 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1393 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1396 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1397 hw->func_caps.common_cap.num_rxq);
1399 pf->lan_nb_qps = pf->lan_nb_qp_max;
1401 ice_init_proto_xtr(dev);
1403 if (hw->func_caps.fd_fltr_guar > 0 ||
1404 hw->func_caps.fd_fltr_best_effort > 0) {
1405 pf->flags |= ICE_FLAG_FDIR;
1406 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1407 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1409 pf->fdir_nb_qps = 0;
1411 pf->fdir_qp_offset = 0;
1417 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1419 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1420 struct ice_vsi *vsi = NULL;
1421 struct ice_vsi_ctx vsi_ctx;
1423 struct rte_ether_addr broadcast = {
1424 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1425 struct rte_ether_addr mac_addr;
1426 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1427 uint8_t tc_bitmap = 0x1;
1430 /* hw->num_lports = 1 in NIC mode */
1431 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1435 vsi->idx = pf->next_vsi_idx;
1438 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1439 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1440 vsi->vlan_anti_spoof_on = 0;
1441 vsi->vlan_filter_on = 1;
1442 TAILQ_INIT(&vsi->mac_list);
1443 TAILQ_INIT(&vsi->vlan_list);
1445 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1446 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1447 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1448 hw->func_caps.common_cap.rss_table_size;
1449 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1451 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1454 vsi->nb_qps = pf->lan_nb_qps;
1455 vsi->base_queue = 1;
1456 ice_vsi_config_default_rss(&vsi_ctx.info);
1457 vsi_ctx.alloc_from_pool = true;
1458 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1459 /* switch_id is queried by get_switch_config aq, which is done
1462 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1463 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1464 /* Allow all untagged or tagged packets */
1465 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1466 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1467 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1468 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1469 if (ice_is_dvm_ena(hw)) {
1470 vsi_ctx.info.outer_vlan_flags =
1471 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1472 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1473 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1474 vsi_ctx.info.outer_vlan_flags |=
1475 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1476 ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1477 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1481 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1482 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1483 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1484 cfg = ICE_AQ_VSI_FD_ENABLE;
1485 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1486 vsi_ctx.info.max_fd_fltr_dedicated =
1487 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1488 vsi_ctx.info.max_fd_fltr_shared =
1489 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1491 /* Enable VLAN/UP trip */
1492 ret = ice_vsi_config_tc_queue_mapping(vsi,
1497 "tc queue mapping with vsi failed, "
1505 vsi->nb_qps = pf->fdir_nb_qps;
1506 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1507 vsi_ctx.alloc_from_pool = true;
1508 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1510 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1511 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1512 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1513 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1514 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1515 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1516 ret = ice_vsi_config_tc_queue_mapping(vsi,
1521 "tc queue mapping with vsi failed, "
1528 /* for other types of VSI */
1529 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1533 /* VF has MSIX interrupt in VF range, don't allocate here */
1534 if (type == ICE_VSI_PF) {
1535 ret = ice_res_pool_alloc(&pf->msix_pool,
1536 RTE_MIN(vsi->nb_qps,
1537 RTE_MAX_RXTX_INTR_VEC_ID));
1539 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1542 vsi->msix_intr = ret;
1543 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1544 } else if (type == ICE_VSI_CTRL) {
1545 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1547 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1550 vsi->msix_intr = ret;
1556 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1557 if (ret != ICE_SUCCESS) {
1558 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1561 /* store vsi information is SW structure */
1562 vsi->vsi_id = vsi_ctx.vsi_num;
1563 vsi->info = vsi_ctx.info;
1564 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1565 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1567 if (type == ICE_VSI_PF) {
1568 /* MAC configuration */
1569 rte_ether_addr_copy((struct rte_ether_addr *)
1570 hw->port_info->mac.perm_addr,
1573 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1574 ret = ice_add_mac_filter(vsi, &mac_addr);
1575 if (ret != ICE_SUCCESS)
1576 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1578 rte_ether_addr_copy(&broadcast, &mac_addr);
1579 ret = ice_add_mac_filter(vsi, &mac_addr);
1580 if (ret != ICE_SUCCESS)
1581 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1584 /* At the beginning, only TC0. */
1585 /* What we need here is the maximam number of the TX queues.
1586 * Currently vsi->nb_qps means it.
1587 * Correct it if any change.
1589 max_txqs[0] = vsi->nb_qps;
1590 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1591 tc_bitmap, max_txqs);
1592 if (ret != ICE_SUCCESS)
1593 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1603 ice_send_driver_ver(struct ice_hw *hw)
1605 struct ice_driver_ver dv;
1607 /* we don't have driver version use 0 for dummy */
1611 dv.subbuild_ver = 0;
1612 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1614 return ice_aq_send_driver_ver(hw, &dv, NULL);
1618 ice_pf_setup(struct ice_pf *pf)
1620 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1621 struct ice_vsi *vsi;
1624 /* Clear all stats counters */
1625 pf->offset_loaded = false;
1626 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1627 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1628 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1629 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1631 /* force guaranteed filter pool for PF */
1632 ice_alloc_fd_guar_item(hw, &unused,
1633 hw->func_caps.fd_fltr_guar);
1634 /* force shared filter pool for PF */
1635 ice_alloc_fd_shrd_item(hw, &unused,
1636 hw->func_caps.fd_fltr_best_effort);
1638 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1640 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1650 * Extract device serial number from PCIe Configuration Space and
1651 * determine the pkg file path according to the DSN.
1654 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1657 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1658 uint32_t dsn_low, dsn_high;
1659 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1661 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1664 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0) {
1665 PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
1668 if (rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) {
1669 PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
1672 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1673 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1675 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1679 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1680 ICE_MAX_PKG_FILENAME_SIZE);
1681 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1684 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1685 ICE_MAX_PKG_FILENAME_SIZE);
1686 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1690 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1691 if (!access(pkg_file, 0))
1693 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1698 ice_load_pkg_type(struct ice_hw *hw)
1700 enum ice_pkg_type package_type;
1702 /* store the activated package type (OS default or Comms) */
1703 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1705 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1706 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1708 package_type = ICE_PKG_TYPE_COMMS;
1710 package_type = ICE_PKG_TYPE_UNKNOWN;
1712 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1713 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1714 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1715 hw->active_pkg_name,
1716 ice_is_dvm_ena(hw) ? "double" : "single");
1718 return package_type;
1721 static int ice_load_pkg(struct rte_eth_dev *dev)
1723 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1724 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1730 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1731 struct ice_adapter *ad =
1732 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1734 err = ice_pkg_file_search_path(pci_dev, pkg_file);
1736 PMD_INIT_LOG(ERR, "failed to search file path\n");
1740 file = fopen(pkg_file, "rb");
1742 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1746 err = stat(pkg_file, &fstat);
1748 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1753 buf_len = fstat.st_size;
1754 buf = rte_malloc(NULL, buf_len, 0);
1757 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1763 err = fread(buf, buf_len, 1, file);
1765 PMD_INIT_LOG(ERR, "failed to read package data\n");
1773 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1775 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1779 /* store the loaded pkg type info */
1780 ad->active_pkg_type = ice_load_pkg_type(hw);
1782 err = ice_init_hw_tbls(hw);
1784 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1785 goto fail_init_tbls;
1791 rte_free(hw->pkg_copy);
1798 ice_base_queue_get(struct ice_pf *pf)
1801 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1803 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1804 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1805 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1807 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1813 parse_bool(const char *key, const char *value, void *args)
1815 int *i = (int *)args;
1819 num = strtoul(value, &end, 10);
1821 if (num != 0 && num != 1) {
1822 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1823 "value must be 0 or 1",
1832 static int ice_parse_devargs(struct rte_eth_dev *dev)
1834 struct ice_adapter *ad =
1835 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1836 struct rte_devargs *devargs = dev->device->devargs;
1837 struct rte_kvargs *kvlist;
1840 if (devargs == NULL)
1843 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1844 if (kvlist == NULL) {
1845 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1849 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1850 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1851 sizeof(ad->devargs.proto_xtr));
1853 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1854 &handle_proto_xtr_arg, &ad->devargs);
1858 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1859 &parse_bool, &ad->devargs.safe_mode_support);
1863 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1864 &parse_bool, &ad->devargs.pipe_mode_support);
1869 rte_kvargs_free(kvlist);
1873 /* Forward LLDP packets to default VSI by set switch rules */
1875 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1877 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1878 struct ice_fltr_list_entry *s_list_itr = NULL;
1879 struct LIST_HEAD_TYPE list_head;
1882 INIT_LIST_HEAD(&list_head);
1884 s_list_itr = (struct ice_fltr_list_entry *)
1885 ice_malloc(hw, sizeof(*s_list_itr));
1888 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1889 s_list_itr->fltr_info.vsi_handle = vsi->idx;
1890 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1891 RTE_ETHER_TYPE_LLDP;
1892 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1893 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1894 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1895 LIST_ADD(&s_list_itr->list_entry, &list_head);
1897 ret = ice_add_eth_mac(hw, &list_head);
1899 ret = ice_remove_eth_mac(hw, &list_head);
1901 rte_free(s_list_itr);
1905 static enum ice_status
1906 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1907 uint16_t num, uint16_t desc_id,
1908 uint16_t *prof_buf, uint16_t *num_prof)
1910 struct ice_aqc_res_elem *resp_buf;
1913 bool res_shared = 1;
1914 struct ice_aq_desc aq_desc;
1915 struct ice_sq_cd *cd = NULL;
1916 struct ice_aqc_get_allocd_res_desc *cmd =
1917 &aq_desc.params.get_res_desc;
1919 buf_len = sizeof(*resp_buf) * num;
1920 resp_buf = ice_malloc(hw, buf_len);
1924 ice_fill_dflt_direct_cmd_desc(&aq_desc,
1925 ice_aqc_opc_get_allocd_res_desc);
1927 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1928 ICE_AQC_RES_TYPE_M) | (res_shared ?
1929 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1930 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1932 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1934 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1938 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
1939 (*num_prof), ICE_NONDMA_TO_NONDMA);
1946 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1950 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1951 uint16_t first_desc = 1;
1952 uint16_t num_prof = 0;
1954 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1955 first_desc, prof_buf, &num_prof);
1957 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
1961 for (prof_id = 0; prof_id < num_prof; prof_id++) {
1962 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
1964 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
1972 ice_reset_fxp_resource(struct ice_hw *hw)
1976 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
1978 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
1982 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
1984 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
1992 ice_rss_ctx_init(struct ice_pf *pf)
1994 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
1998 ice_get_supported_rxdid(struct ice_hw *hw)
2000 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2004 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2006 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2007 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2008 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2009 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2010 supported_rxdid |= BIT(i);
2012 return supported_rxdid;
2016 ice_dev_init(struct rte_eth_dev *dev)
2018 struct rte_pci_device *pci_dev;
2019 struct rte_intr_handle *intr_handle;
2020 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2021 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2022 struct ice_adapter *ad =
2023 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2024 struct ice_vsi *vsi;
2027 dev->dev_ops = &ice_eth_dev_ops;
2028 dev->rx_queue_count = ice_rx_queue_count;
2029 dev->rx_descriptor_status = ice_rx_descriptor_status;
2030 dev->tx_descriptor_status = ice_tx_descriptor_status;
2031 dev->rx_pkt_burst = ice_recv_pkts;
2032 dev->tx_pkt_burst = ice_xmit_pkts;
2033 dev->tx_pkt_prepare = ice_prep_pkts;
2035 /* for secondary processes, we don't initialise any further as primary
2036 * has already done this work.
2038 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2039 ice_set_rx_function(dev);
2040 ice_set_tx_function(dev);
2044 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2046 ice_set_default_ptype_table(dev);
2047 pci_dev = RTE_DEV_TO_PCI(dev->device);
2048 intr_handle = &pci_dev->intr_handle;
2050 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2051 pf->adapter->eth_dev = dev;
2052 pf->dev_data = dev->data;
2053 hw->back = pf->adapter;
2054 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2055 hw->vendor_id = pci_dev->id.vendor_id;
2056 hw->device_id = pci_dev->id.device_id;
2057 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2058 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2059 hw->bus.device = pci_dev->addr.devid;
2060 hw->bus.func = pci_dev->addr.function;
2062 ret = ice_parse_devargs(dev);
2064 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2068 ice_init_controlq_parameter(hw);
2070 ret = ice_init_hw(hw);
2072 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2076 ret = ice_load_pkg(dev);
2078 if (ad->devargs.safe_mode_support == 0) {
2079 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2080 "Use safe-mode-support=1 to enter Safe Mode");
2084 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2085 "Entering Safe Mode");
2086 ad->is_safe_mode = 1;
2089 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2090 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2091 hw->api_maj_ver, hw->api_min_ver);
2093 ice_pf_sw_init(dev);
2094 ret = ice_init_mac_address(dev);
2096 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2100 ret = ice_res_pool_init(&pf->msix_pool, 1,
2101 hw->func_caps.common_cap.num_msix_vectors - 1);
2103 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2104 goto err_msix_pool_init;
2107 ret = ice_pf_setup(pf);
2109 PMD_INIT_LOG(ERR, "Failed to setup PF");
2113 ret = ice_send_driver_ver(hw);
2115 PMD_INIT_LOG(ERR, "Failed to send driver version");
2121 ret = ice_aq_stop_lldp(hw, true, false, NULL);
2122 if (ret != ICE_SUCCESS)
2123 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2124 ret = ice_init_dcb(hw, true);
2125 if (ret != ICE_SUCCESS)
2126 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2127 /* Forward LLDP packets to default VSI */
2128 ret = ice_vsi_config_sw_lldp(vsi, true);
2129 if (ret != ICE_SUCCESS)
2130 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2131 /* register callback func to eal lib */
2132 rte_intr_callback_register(intr_handle,
2133 ice_interrupt_handler, dev);
2135 ice_pf_enable_irq0(hw);
2137 /* enable uio intr after callback register */
2138 rte_intr_enable(intr_handle);
2140 /* get base queue pairs index in the device */
2141 ice_base_queue_get(pf);
2143 /* Initialize RSS context for gtpu_eh */
2144 ice_rss_ctx_init(pf);
2146 if (!ad->is_safe_mode) {
2147 ret = ice_flow_init(ad);
2149 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2154 ret = ice_reset_fxp_resource(hw);
2156 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2160 pf->supported_rxdid = ice_get_supported_rxdid(hw);
2165 ice_res_pool_destroy(&pf->msix_pool);
2167 rte_free(dev->data->mac_addrs);
2168 dev->data->mac_addrs = NULL;
2170 ice_sched_cleanup_all(hw);
2171 rte_free(hw->port_info);
2172 ice_shutdown_all_ctrlq(hw);
2173 rte_free(pf->proto_xtr);
2179 ice_release_vsi(struct ice_vsi *vsi)
2182 struct ice_vsi_ctx vsi_ctx;
2183 enum ice_status ret;
2189 hw = ICE_VSI_TO_HW(vsi);
2191 ice_remove_all_mac_vlan_filters(vsi);
2193 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2195 vsi_ctx.vsi_num = vsi->vsi_id;
2196 vsi_ctx.info = vsi->info;
2197 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2198 if (ret != ICE_SUCCESS) {
2199 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2203 rte_free(vsi->rss_lut);
2204 rte_free(vsi->rss_key);
2210 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2212 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2213 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2214 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2215 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2216 uint16_t msix_intr, i;
2218 /* disable interrupt and also clear all the exist config */
2219 for (i = 0; i < vsi->nb_qps; i++) {
2220 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2221 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2225 if (rte_intr_allow_others(intr_handle))
2227 for (i = 0; i < vsi->nb_msix; i++) {
2228 msix_intr = vsi->msix_intr + i;
2229 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2230 GLINT_DYN_CTL_WB_ON_ITR_M);
2234 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2238 ice_dev_stop(struct rte_eth_dev *dev)
2240 struct rte_eth_dev_data *data = dev->data;
2241 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2242 struct ice_vsi *main_vsi = pf->main_vsi;
2243 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2244 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2247 /* avoid stopping again */
2248 if (pf->adapter_stopped)
2251 /* stop and clear all Rx queues */
2252 for (i = 0; i < data->nb_rx_queues; i++)
2253 ice_rx_queue_stop(dev, i);
2255 /* stop and clear all Tx queues */
2256 for (i = 0; i < data->nb_tx_queues; i++)
2257 ice_tx_queue_stop(dev, i);
2259 /* disable all queue interrupts */
2260 ice_vsi_disable_queues_intr(main_vsi);
2262 if (pf->init_link_up)
2263 ice_dev_set_link_up(dev);
2265 ice_dev_set_link_down(dev);
2267 /* Clean datapath event and queue/vec mapping */
2268 rte_intr_efd_disable(intr_handle);
2269 if (intr_handle->intr_vec) {
2270 rte_free(intr_handle->intr_vec);
2271 intr_handle->intr_vec = NULL;
2274 pf->adapter_stopped = true;
2275 dev->data->dev_started = 0;
2281 ice_dev_close(struct rte_eth_dev *dev)
2283 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2284 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2285 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2286 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2287 struct ice_adapter *ad =
2288 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2291 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2294 /* Since stop will make link down, then the link event will be
2295 * triggered, disable the irq firstly to avoid the port_infoe etc
2296 * resources deallocation causing the interrupt service thread
2299 ice_pf_disable_irq0(hw);
2301 ret = ice_dev_stop(dev);
2303 if (!ad->is_safe_mode)
2304 ice_flow_uninit(ad);
2306 /* release all queue resource */
2307 ice_free_queues(dev);
2309 ice_res_pool_destroy(&pf->msix_pool);
2310 ice_release_vsi(pf->main_vsi);
2311 ice_sched_cleanup_all(hw);
2312 ice_free_hw_tbls(hw);
2313 rte_free(hw->port_info);
2314 hw->port_info = NULL;
2315 ice_shutdown_all_ctrlq(hw);
2316 rte_free(pf->proto_xtr);
2317 pf->proto_xtr = NULL;
2319 /* disable uio intr before callback unregister */
2320 rte_intr_disable(intr_handle);
2322 /* unregister callback func from eal lib */
2323 rte_intr_callback_unregister(intr_handle,
2324 ice_interrupt_handler, dev);
2330 ice_dev_uninit(struct rte_eth_dev *dev)
2338 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2340 return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2344 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2349 cfg->hdr_type = ICE_RSS_OUTER_HEADERS;
2353 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2355 enum ice_status status = ICE_SUCCESS;
2356 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2357 struct ice_vsi *vsi = pf->main_vsi;
2359 if (!is_hash_cfg_valid(cfg))
2362 status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2363 if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2365 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2374 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2376 enum ice_status status = ICE_SUCCESS;
2377 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2378 struct ice_vsi *vsi = pf->main_vsi;
2380 if (!is_hash_cfg_valid(cfg))
2383 status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2386 "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2395 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2399 ret = ice_hash_moveout(pf, cfg);
2400 if (ret && (ret != -ENOENT))
2403 hash_cfg_reset(cfg);
2409 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2415 case ICE_HASH_GTPU_CTX_EH_IP:
2416 ret = ice_hash_remove(pf,
2417 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2418 if (ret && (ret != -ENOENT))
2421 ret = ice_hash_remove(pf,
2422 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2423 if (ret && (ret != -ENOENT))
2426 ret = ice_hash_remove(pf,
2427 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2428 if (ret && (ret != -ENOENT))
2431 ret = ice_hash_remove(pf,
2432 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2433 if (ret && (ret != -ENOENT))
2436 ret = ice_hash_remove(pf,
2437 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2438 if (ret && (ret != -ENOENT))
2441 ret = ice_hash_remove(pf,
2442 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2443 if (ret && (ret != -ENOENT))
2446 ret = ice_hash_remove(pf,
2447 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2448 if (ret && (ret != -ENOENT))
2451 ret = ice_hash_remove(pf,
2452 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2453 if (ret && (ret != -ENOENT))
2457 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2458 ret = ice_hash_remove(pf,
2459 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2460 if (ret && (ret != -ENOENT))
2463 ret = ice_hash_remove(pf,
2464 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2465 if (ret && (ret != -ENOENT))
2468 ret = ice_hash_moveout(pf,
2469 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2470 if (ret && (ret != -ENOENT))
2473 ret = ice_hash_moveout(pf,
2474 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2475 if (ret && (ret != -ENOENT))
2478 ret = ice_hash_moveout(pf,
2479 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2480 if (ret && (ret != -ENOENT))
2483 ret = ice_hash_moveout(pf,
2484 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2485 if (ret && (ret != -ENOENT))
2489 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2490 ret = ice_hash_remove(pf,
2491 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2492 if (ret && (ret != -ENOENT))
2495 ret = ice_hash_remove(pf,
2496 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2497 if (ret && (ret != -ENOENT))
2500 ret = ice_hash_moveout(pf,
2501 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2502 if (ret && (ret != -ENOENT))
2505 ret = ice_hash_moveout(pf,
2506 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2507 if (ret && (ret != -ENOENT))
2510 ret = ice_hash_moveout(pf,
2511 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2512 if (ret && (ret != -ENOENT))
2515 ret = ice_hash_moveout(pf,
2516 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2517 if (ret && (ret != -ENOENT))
2521 case ICE_HASH_GTPU_CTX_UP_IP:
2522 ret = ice_hash_remove(pf,
2523 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2524 if (ret && (ret != -ENOENT))
2527 ret = ice_hash_remove(pf,
2528 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2529 if (ret && (ret != -ENOENT))
2532 ret = ice_hash_moveout(pf,
2533 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2534 if (ret && (ret != -ENOENT))
2537 ret = ice_hash_moveout(pf,
2538 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2539 if (ret && (ret != -ENOENT))
2542 ret = ice_hash_moveout(pf,
2543 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2544 if (ret && (ret != -ENOENT))
2548 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2549 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2550 ret = ice_hash_moveout(pf,
2551 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2552 if (ret && (ret != -ENOENT))
2555 ret = ice_hash_moveout(pf,
2556 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2557 if (ret && (ret != -ENOENT))
2560 ret = ice_hash_moveout(pf,
2561 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2562 if (ret && (ret != -ENOENT))
2566 case ICE_HASH_GTPU_CTX_DW_IP:
2567 ret = ice_hash_remove(pf,
2568 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2569 if (ret && (ret != -ENOENT))
2572 ret = ice_hash_remove(pf,
2573 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2574 if (ret && (ret != -ENOENT))
2577 ret = ice_hash_moveout(pf,
2578 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2579 if (ret && (ret != -ENOENT))
2582 ret = ice_hash_moveout(pf,
2583 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2584 if (ret && (ret != -ENOENT))
2587 ret = ice_hash_moveout(pf,
2588 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2589 if (ret && (ret != -ENOENT))
2593 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2594 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2595 ret = ice_hash_moveout(pf,
2596 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2597 if (ret && (ret != -ENOENT))
2600 ret = ice_hash_moveout(pf,
2601 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2602 if (ret && (ret != -ENOENT))
2605 ret = ice_hash_moveout(pf,
2606 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2607 if (ret && (ret != -ENOENT))
2618 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2622 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2624 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2626 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2629 return ICE_HASH_GTPU_CTX_MAX;
2632 if (hdr & ICE_FLOW_SEG_HDR_UDP)
2634 else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2637 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2638 return eh_idx * 3 + ip_idx;
2640 return ICE_HASH_GTPU_CTX_MAX;
2644 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2646 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2648 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2649 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2651 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2652 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2659 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2660 u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2664 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2665 ctx->ctx[ctx_idx] = *cfg;
2668 case ICE_HASH_GTPU_CTX_EH_IP:
2670 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2671 ret = ice_hash_moveback(pf,
2672 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2673 if (ret && (ret != -ENOENT))
2676 ret = ice_hash_moveback(pf,
2677 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2678 if (ret && (ret != -ENOENT))
2681 ret = ice_hash_moveback(pf,
2682 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2683 if (ret && (ret != -ENOENT))
2686 ret = ice_hash_moveback(pf,
2687 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2688 if (ret && (ret != -ENOENT))
2692 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2693 ret = ice_hash_moveback(pf,
2694 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2695 if (ret && (ret != -ENOENT))
2698 ret = ice_hash_moveback(pf,
2699 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2700 if (ret && (ret != -ENOENT))
2703 ret = ice_hash_moveback(pf,
2704 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2705 if (ret && (ret != -ENOENT))
2708 ret = ice_hash_moveback(pf,
2709 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2710 if (ret && (ret != -ENOENT))
2714 case ICE_HASH_GTPU_CTX_UP_IP:
2715 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2716 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2717 case ICE_HASH_GTPU_CTX_DW_IP:
2718 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2719 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2720 ret = ice_hash_moveback(pf,
2721 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2722 if (ret && (ret != -ENOENT))
2725 ret = ice_hash_moveback(pf,
2726 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2727 if (ret && (ret != -ENOENT))
2730 ret = ice_hash_moveback(pf,
2731 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2732 if (ret && (ret != -ENOENT))
2744 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2746 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2748 if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2749 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2751 else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2752 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2759 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2761 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2763 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2766 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2767 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2768 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2769 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2773 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2774 struct ice_rss_hash_cfg *cfg)
2776 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2779 ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2780 if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2781 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2783 ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2789 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2790 struct ice_rss_hash_cfg *cfg)
2792 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2795 ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2797 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2799 ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2801 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2803 ret = ice_add_rss_cfg_post(pf, cfg);
2805 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2811 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2813 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2814 struct ice_vsi *vsi = pf->main_vsi;
2815 struct ice_rss_hash_cfg cfg;
2818 #define ICE_RSS_HF_ALL ( \
2821 ETH_RSS_NONFRAG_IPV4_UDP | \
2822 ETH_RSS_NONFRAG_IPV6_UDP | \
2823 ETH_RSS_NONFRAG_IPV4_TCP | \
2824 ETH_RSS_NONFRAG_IPV6_TCP | \
2825 ETH_RSS_NONFRAG_IPV4_SCTP | \
2826 ETH_RSS_NONFRAG_IPV6_SCTP)
2828 ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2830 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2834 cfg.hdr_type = ICE_RSS_OUTER_HEADERS;
2835 /* Configure RSS for IPv4 with src/dst addr as input set */
2836 if (rss_hf & ETH_RSS_IPV4) {
2837 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2838 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2839 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2841 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2845 /* Configure RSS for IPv6 with src/dst addr as input set */
2846 if (rss_hf & ETH_RSS_IPV6) {
2847 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2848 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2849 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2851 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2855 /* Configure RSS for udp4 with src/dst addr and port as input set */
2856 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2857 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2858 ICE_FLOW_SEG_HDR_IPV_OTHER;
2859 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2860 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2862 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2866 /* Configure RSS for udp6 with src/dst addr and port as input set */
2867 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2868 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
2869 ICE_FLOW_SEG_HDR_IPV_OTHER;
2870 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2871 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2873 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2877 /* Configure RSS for tcp4 with src/dst addr and port as input set */
2878 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2879 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
2880 ICE_FLOW_SEG_HDR_IPV_OTHER;
2881 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2882 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2884 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2888 /* Configure RSS for tcp6 with src/dst addr and port as input set */
2889 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2890 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
2891 ICE_FLOW_SEG_HDR_IPV_OTHER;
2892 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2893 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2895 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2899 /* Configure RSS for sctp4 with src/dst addr and port as input set */
2900 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2901 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
2902 ICE_FLOW_SEG_HDR_IPV_OTHER;
2903 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
2904 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2906 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2910 /* Configure RSS for sctp6 with src/dst addr and port as input set */
2911 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2912 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
2913 ICE_FLOW_SEG_HDR_IPV_OTHER;
2914 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
2915 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2917 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2921 if (rss_hf & ETH_RSS_IPV4) {
2922 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV4 |
2923 ICE_FLOW_SEG_HDR_IPV_OTHER;
2924 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2925 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2927 PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
2930 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV4 |
2931 ICE_FLOW_SEG_HDR_IPV_OTHER;
2932 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2934 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
2937 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
2938 ICE_FLOW_SEG_HDR_IPV_OTHER;
2939 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2941 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2945 if (rss_hf & ETH_RSS_IPV6) {
2946 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV6 |
2947 ICE_FLOW_SEG_HDR_IPV_OTHER;
2948 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2949 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2951 PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
2954 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV6 |
2955 ICE_FLOW_SEG_HDR_IPV_OTHER;
2956 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2958 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
2961 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
2962 ICE_FLOW_SEG_HDR_IPV_OTHER;
2963 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2965 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2969 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2970 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2971 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2972 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2973 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2975 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
2978 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
2979 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2980 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2982 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
2985 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2986 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2987 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2989 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2993 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2994 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2995 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2996 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2997 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2999 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
3002 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
3003 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3004 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3006 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
3009 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3010 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3011 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3013 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3017 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3018 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3019 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3020 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3021 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3023 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
3026 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3027 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3028 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3030 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
3033 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3034 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3035 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3037 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3041 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3042 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3043 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3044 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3045 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3047 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
3050 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3051 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3052 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3054 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
3057 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3058 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3059 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3061 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3065 pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3068 static int ice_init_rss(struct ice_pf *pf)
3070 struct ice_hw *hw = ICE_PF_TO_HW(pf);
3071 struct ice_vsi *vsi = pf->main_vsi;
3072 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3073 struct ice_aq_get_set_rss_lut_params lut_params;
3074 struct rte_eth_rss_conf *rss_conf;
3075 struct ice_aqc_get_set_rss_keys key;
3078 bool is_safe_mode = pf->adapter->is_safe_mode;
3081 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3082 nb_q = dev->data->nb_rx_queues;
3083 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3084 vsi->rss_lut_size = pf->hash_lut_size;
3087 PMD_DRV_LOG(WARNING,
3088 "RSS is not supported as rx queues number is zero\n");
3093 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3097 if (!vsi->rss_key) {
3098 vsi->rss_key = rte_zmalloc(NULL,
3099 vsi->rss_key_size, 0);
3100 if (vsi->rss_key == NULL) {
3101 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3105 if (!vsi->rss_lut) {
3106 vsi->rss_lut = rte_zmalloc(NULL,
3107 vsi->rss_lut_size, 0);
3108 if (vsi->rss_lut == NULL) {
3109 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3110 rte_free(vsi->rss_key);
3111 vsi->rss_key = NULL;
3115 /* configure RSS key */
3116 if (!rss_conf->rss_key) {
3117 /* Calculate the default hash key */
3118 for (i = 0; i <= vsi->rss_key_size; i++)
3119 vsi->rss_key[i] = (uint8_t)rte_rand();
3121 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3122 RTE_MIN(rss_conf->rss_key_len,
3123 vsi->rss_key_size));
3125 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3126 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3130 /* init RSS LUT table */
3131 for (i = 0; i < vsi->rss_lut_size; i++)
3132 vsi->rss_lut[i] = i % nb_q;
3134 lut_params.vsi_handle = vsi->idx;
3135 lut_params.lut_size = vsi->rss_lut_size;
3136 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3137 lut_params.lut = vsi->rss_lut;
3138 lut_params.global_lut_id = 0;
3139 ret = ice_aq_set_rss_lut(hw, &lut_params);
3143 /* Enable registers for symmetric_toeplitz function. */
3144 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3145 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3146 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3147 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3149 /* RSS hash configuration */
3150 ice_rss_hash_set(pf, rss_conf->rss_hf);
3154 rte_free(vsi->rss_key);
3155 vsi->rss_key = NULL;
3156 rte_free(vsi->rss_lut);
3157 vsi->rss_lut = NULL;
3162 ice_dev_configure(struct rte_eth_dev *dev)
3164 struct ice_adapter *ad =
3165 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3166 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3169 /* Initialize to TRUE. If any of Rx queues doesn't meet the
3170 * bulk allocation or vector Rx preconditions we will reset it.
3172 ad->rx_bulk_alloc_allowed = true;
3173 ad->tx_simple_allowed = true;
3175 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3176 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3178 if (dev->data->nb_rx_queues) {
3179 ret = ice_init_rss(pf);
3181 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3190 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3191 int base_queue, int nb_queue)
3193 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3194 uint32_t val, val_tx;
3197 for (i = 0; i < nb_queue; i++) {
3199 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3200 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3201 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3202 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3204 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3205 base_queue + i, msix_vect);
3206 /* set ITR0 value */
3207 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3208 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3209 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3214 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3216 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3217 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3218 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3219 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3220 uint16_t msix_vect = vsi->msix_intr;
3221 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3222 uint16_t queue_idx = 0;
3226 /* clear Rx/Tx queue interrupt */
3227 for (i = 0; i < vsi->nb_used_qps; i++) {
3228 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3229 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3232 /* PF bind interrupt */
3233 if (rte_intr_dp_is_en(intr_handle)) {
3238 for (i = 0; i < vsi->nb_used_qps; i++) {
3240 if (!rte_intr_allow_others(intr_handle))
3241 msix_vect = ICE_MISC_VEC_ID;
3243 /* uio mapping all queue to one msix_vect */
3244 __vsi_queues_bind_intr(vsi, msix_vect,
3245 vsi->base_queue + i,
3246 vsi->nb_used_qps - i);
3248 for (; !!record && i < vsi->nb_used_qps; i++)
3249 intr_handle->intr_vec[queue_idx + i] =
3254 /* vfio 1:1 queue/msix_vect mapping */
3255 __vsi_queues_bind_intr(vsi, msix_vect,
3256 vsi->base_queue + i, 1);
3259 intr_handle->intr_vec[queue_idx + i] = msix_vect;
3267 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3269 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3270 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3271 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3272 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3273 uint16_t msix_intr, i;
3275 if (rte_intr_allow_others(intr_handle))
3276 for (i = 0; i < vsi->nb_used_qps; i++) {
3277 msix_intr = vsi->msix_intr + i;
3278 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3279 GLINT_DYN_CTL_INTENA_M |
3280 GLINT_DYN_CTL_CLEARPBA_M |
3281 GLINT_DYN_CTL_ITR_INDX_M |
3282 GLINT_DYN_CTL_WB_ON_ITR_M);
3285 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3286 GLINT_DYN_CTL_INTENA_M |
3287 GLINT_DYN_CTL_CLEARPBA_M |
3288 GLINT_DYN_CTL_ITR_INDX_M |
3289 GLINT_DYN_CTL_WB_ON_ITR_M);
3293 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3295 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3296 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3297 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3298 struct ice_vsi *vsi = pf->main_vsi;
3299 uint32_t intr_vector = 0;
3301 rte_intr_disable(intr_handle);
3303 /* check and configure queue intr-vector mapping */
3304 if ((rte_intr_cap_multiple(intr_handle) ||
3305 !RTE_ETH_DEV_SRIOV(dev).active) &&
3306 dev->data->dev_conf.intr_conf.rxq != 0) {
3307 intr_vector = dev->data->nb_rx_queues;
3308 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3309 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3310 ICE_MAX_INTR_QUEUE_NUM);
3313 if (rte_intr_efd_enable(intr_handle, intr_vector))
3317 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3318 intr_handle->intr_vec =
3319 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3321 if (!intr_handle->intr_vec) {
3323 "Failed to allocate %d rx_queues intr_vec",
3324 dev->data->nb_rx_queues);
3329 /* Map queues with MSIX interrupt */
3330 vsi->nb_used_qps = dev->data->nb_rx_queues;
3331 ice_vsi_queues_bind_intr(vsi);
3333 /* Enable interrupts for all the queues */
3334 ice_vsi_enable_queues_intr(vsi);
3336 rte_intr_enable(intr_handle);
3342 ice_get_init_link_status(struct rte_eth_dev *dev)
3344 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3345 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3346 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3347 struct ice_link_status link_status;
3350 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3351 &link_status, NULL);
3352 if (ret != ICE_SUCCESS) {
3353 PMD_DRV_LOG(ERR, "Failed to get link info");
3354 pf->init_link_up = false;
3358 if (link_status.link_info & ICE_AQ_LINK_UP)
3359 pf->init_link_up = true;
3363 ice_dev_start(struct rte_eth_dev *dev)
3365 struct rte_eth_dev_data *data = dev->data;
3366 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3367 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3368 struct ice_vsi *vsi = pf->main_vsi;
3369 uint16_t nb_rxq = 0;
3371 uint16_t max_frame_size;
3374 /* program Tx queues' context in hardware */
3375 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3376 ret = ice_tx_queue_start(dev, nb_txq);
3378 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3383 /* program Rx queues' context in hardware*/
3384 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3385 ret = ice_rx_queue_start(dev, nb_rxq);
3387 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3392 ice_set_rx_function(dev);
3393 ice_set_tx_function(dev);
3395 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3396 ETH_VLAN_EXTEND_MASK;
3397 ret = ice_vlan_offload_set(dev, mask);
3399 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3403 /* enable Rx interrput and mapping Rx queue to interrupt vector */
3404 if (ice_rxq_intr_setup(dev))
3407 /* Enable receiving broadcast packets and transmitting packets */
3408 ret = ice_set_vsi_promisc(hw, vsi->idx,
3409 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3410 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3412 if (ret != ICE_SUCCESS)
3413 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3415 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3416 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3417 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3418 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3419 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3420 ICE_AQ_LINK_EVENT_AN_COMPLETED |
3421 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3423 if (ret != ICE_SUCCESS)
3424 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3426 ice_get_init_link_status(dev);
3428 ice_dev_set_link_up(dev);
3430 /* Call get_link_info aq commond to enable/disable LSE */
3431 ice_link_update(dev, 0);
3433 pf->adapter_stopped = false;
3435 /* Set the max frame size to default value*/
3436 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3437 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3440 /* Set the max frame size to HW*/
3441 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3445 /* stop the started queues if failed to start all queues */
3447 for (i = 0; i < nb_rxq; i++)
3448 ice_rx_queue_stop(dev, i);
3450 for (i = 0; i < nb_txq; i++)
3451 ice_tx_queue_stop(dev, i);
3457 ice_dev_reset(struct rte_eth_dev *dev)
3461 if (dev->data->sriov.active)
3464 ret = ice_dev_uninit(dev);
3466 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3470 ret = ice_dev_init(dev);
3472 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3480 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3482 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3483 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3484 struct ice_vsi *vsi = pf->main_vsi;
3485 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3486 bool is_safe_mode = pf->adapter->is_safe_mode;
3490 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3491 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3492 dev_info->max_rx_queues = vsi->nb_qps;
3493 dev_info->max_tx_queues = vsi->nb_qps;
3494 dev_info->max_mac_addrs = vsi->max_macaddrs;
3495 dev_info->max_vfs = pci_dev->max_vfs;
3496 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3497 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3499 dev_info->rx_offload_capa =
3500 DEV_RX_OFFLOAD_VLAN_STRIP |
3501 DEV_RX_OFFLOAD_JUMBO_FRAME |
3502 DEV_RX_OFFLOAD_KEEP_CRC |
3503 DEV_RX_OFFLOAD_SCATTER |
3504 DEV_RX_OFFLOAD_VLAN_FILTER;
3505 dev_info->tx_offload_capa =
3506 DEV_TX_OFFLOAD_VLAN_INSERT |
3507 DEV_TX_OFFLOAD_TCP_TSO |
3508 DEV_TX_OFFLOAD_MULTI_SEGS |
3509 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3510 dev_info->flow_type_rss_offloads = 0;
3512 if (!is_safe_mode) {
3513 dev_info->rx_offload_capa |=
3514 DEV_RX_OFFLOAD_IPV4_CKSUM |
3515 DEV_RX_OFFLOAD_UDP_CKSUM |
3516 DEV_RX_OFFLOAD_TCP_CKSUM |
3517 DEV_RX_OFFLOAD_QINQ_STRIP |
3518 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3519 DEV_RX_OFFLOAD_VLAN_EXTEND |
3520 DEV_RX_OFFLOAD_RSS_HASH;
3521 dev_info->tx_offload_capa |=
3522 DEV_TX_OFFLOAD_QINQ_INSERT |
3523 DEV_TX_OFFLOAD_IPV4_CKSUM |
3524 DEV_TX_OFFLOAD_UDP_CKSUM |
3525 DEV_TX_OFFLOAD_TCP_CKSUM |
3526 DEV_TX_OFFLOAD_SCTP_CKSUM |
3527 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3528 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3529 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3532 dev_info->rx_queue_offload_capa = 0;
3533 dev_info->tx_queue_offload_capa = 0;
3535 dev_info->reta_size = pf->hash_lut_size;
3536 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3538 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3540 .pthresh = ICE_DEFAULT_RX_PTHRESH,
3541 .hthresh = ICE_DEFAULT_RX_HTHRESH,
3542 .wthresh = ICE_DEFAULT_RX_WTHRESH,
3544 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3549 dev_info->default_txconf = (struct rte_eth_txconf) {
3551 .pthresh = ICE_DEFAULT_TX_PTHRESH,
3552 .hthresh = ICE_DEFAULT_TX_HTHRESH,
3553 .wthresh = ICE_DEFAULT_TX_WTHRESH,
3555 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3556 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3560 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3561 .nb_max = ICE_MAX_RING_DESC,
3562 .nb_min = ICE_MIN_RING_DESC,
3563 .nb_align = ICE_ALIGN_RING_DESC,
3566 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3567 .nb_max = ICE_MAX_RING_DESC,
3568 .nb_min = ICE_MIN_RING_DESC,
3569 .nb_align = ICE_ALIGN_RING_DESC,
3572 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3573 ETH_LINK_SPEED_100M |
3575 ETH_LINK_SPEED_2_5G |
3577 ETH_LINK_SPEED_10G |
3578 ETH_LINK_SPEED_20G |
3581 phy_type_low = hw->port_info->phy.phy_type_low;
3582 phy_type_high = hw->port_info->phy.phy_type_high;
3584 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3585 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3587 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3588 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3589 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3591 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3592 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3594 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3595 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3596 dev_info->default_rxportconf.nb_queues = 1;
3597 dev_info->default_txportconf.nb_queues = 1;
3598 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3599 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3605 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3606 struct rte_eth_link *link)
3608 struct rte_eth_link *dst = link;
3609 struct rte_eth_link *src = &dev->data->dev_link;
3611 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3612 *(uint64_t *)src) == 0)
3619 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3620 struct rte_eth_link *link)
3622 struct rte_eth_link *dst = &dev->data->dev_link;
3623 struct rte_eth_link *src = link;
3625 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3626 *(uint64_t *)src) == 0)
3633 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3635 #define CHECK_INTERVAL 100 /* 100ms */
3636 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3637 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3638 struct ice_link_status link_status;
3639 struct rte_eth_link link, old;
3641 unsigned int rep_cnt = MAX_REPEAT_TIME;
3642 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3644 memset(&link, 0, sizeof(link));
3645 memset(&old, 0, sizeof(old));
3646 memset(&link_status, 0, sizeof(link_status));
3647 ice_atomic_read_link_status(dev, &old);
3650 /* Get link status information from hardware */
3651 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3652 &link_status, NULL);
3653 if (status != ICE_SUCCESS) {
3654 link.link_speed = ETH_SPEED_NUM_100M;
3655 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3656 PMD_DRV_LOG(ERR, "Failed to get link info");
3660 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3661 if (!wait_to_complete || link.link_status)
3664 rte_delay_ms(CHECK_INTERVAL);
3665 } while (--rep_cnt);
3667 if (!link.link_status)
3670 /* Full-duplex operation at all supported speeds */
3671 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3673 /* Parse the link status */
3674 switch (link_status.link_speed) {
3675 case ICE_AQ_LINK_SPEED_10MB:
3676 link.link_speed = ETH_SPEED_NUM_10M;
3678 case ICE_AQ_LINK_SPEED_100MB:
3679 link.link_speed = ETH_SPEED_NUM_100M;
3681 case ICE_AQ_LINK_SPEED_1000MB:
3682 link.link_speed = ETH_SPEED_NUM_1G;
3684 case ICE_AQ_LINK_SPEED_2500MB:
3685 link.link_speed = ETH_SPEED_NUM_2_5G;
3687 case ICE_AQ_LINK_SPEED_5GB:
3688 link.link_speed = ETH_SPEED_NUM_5G;
3690 case ICE_AQ_LINK_SPEED_10GB:
3691 link.link_speed = ETH_SPEED_NUM_10G;
3693 case ICE_AQ_LINK_SPEED_20GB:
3694 link.link_speed = ETH_SPEED_NUM_20G;
3696 case ICE_AQ_LINK_SPEED_25GB:
3697 link.link_speed = ETH_SPEED_NUM_25G;
3699 case ICE_AQ_LINK_SPEED_40GB:
3700 link.link_speed = ETH_SPEED_NUM_40G;
3702 case ICE_AQ_LINK_SPEED_50GB:
3703 link.link_speed = ETH_SPEED_NUM_50G;
3705 case ICE_AQ_LINK_SPEED_100GB:
3706 link.link_speed = ETH_SPEED_NUM_100G;
3708 case ICE_AQ_LINK_SPEED_UNKNOWN:
3709 PMD_DRV_LOG(ERR, "Unknown link speed");
3710 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3713 PMD_DRV_LOG(ERR, "None link speed");
3714 link.link_speed = ETH_SPEED_NUM_NONE;
3718 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3719 ETH_LINK_SPEED_FIXED);
3722 ice_atomic_write_link_status(dev, &link);
3723 if (link.link_status == old.link_status)
3729 /* Force the physical link state by getting the current PHY capabilities from
3730 * hardware and setting the PHY config based on the determined capabilities. If
3731 * link changes, link event will be triggered because both the Enable Automatic
3732 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3734 static enum ice_status
3735 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3737 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3738 struct ice_aqc_get_phy_caps_data *pcaps;
3739 struct ice_port_info *pi;
3740 enum ice_status status;
3742 if (!hw || !hw->port_info)
3743 return ICE_ERR_PARAM;
3747 pcaps = (struct ice_aqc_get_phy_caps_data *)
3748 ice_malloc(hw, sizeof(*pcaps));
3750 return ICE_ERR_NO_MEMORY;
3752 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3757 /* No change in link */
3758 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3759 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3762 cfg.phy_type_low = pcaps->phy_type_low;
3763 cfg.phy_type_high = pcaps->phy_type_high;
3764 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3765 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3766 cfg.eee_cap = pcaps->eee_cap;
3767 cfg.eeer_value = pcaps->eeer_value;
3768 cfg.link_fec_opt = pcaps->link_fec_options;
3770 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3772 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3774 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3777 ice_free(hw, pcaps);
3782 ice_dev_set_link_up(struct rte_eth_dev *dev)
3784 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786 return ice_force_phys_link_state(hw, true);
3790 ice_dev_set_link_down(struct rte_eth_dev *dev)
3792 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3794 return ice_force_phys_link_state(hw, false);
3798 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3800 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3801 struct rte_eth_dev_data *dev_data = pf->dev_data;
3802 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3804 /* check if mtu is within the allowed range */
3805 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3808 /* mtu setting is forbidden if port is start */
3809 if (dev_data->dev_started) {
3811 "port %d must be stopped before configuration",
3816 if (frame_size > ICE_ETH_MAX_LEN)
3817 dev_data->dev_conf.rxmode.offloads |=
3818 DEV_RX_OFFLOAD_JUMBO_FRAME;
3820 dev_data->dev_conf.rxmode.offloads &=
3821 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3823 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3828 static int ice_macaddr_set(struct rte_eth_dev *dev,
3829 struct rte_ether_addr *mac_addr)
3831 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3832 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3833 struct ice_vsi *vsi = pf->main_vsi;
3834 struct ice_mac_filter *f;
3838 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3839 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3843 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3844 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3849 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3853 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3854 if (ret != ICE_SUCCESS) {
3855 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3858 ret = ice_add_mac_filter(vsi, mac_addr);
3859 if (ret != ICE_SUCCESS) {
3860 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3863 rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3865 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3866 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3867 if (ret != ICE_SUCCESS)
3868 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3873 /* Add a MAC address, and update filters */
3875 ice_macaddr_add(struct rte_eth_dev *dev,
3876 struct rte_ether_addr *mac_addr,
3877 __rte_unused uint32_t index,
3878 __rte_unused uint32_t pool)
3880 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3881 struct ice_vsi *vsi = pf->main_vsi;
3884 ret = ice_add_mac_filter(vsi, mac_addr);
3885 if (ret != ICE_SUCCESS) {
3886 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3893 /* Remove a MAC address, and update filters */
3895 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3897 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3898 struct ice_vsi *vsi = pf->main_vsi;
3899 struct rte_eth_dev_data *data = dev->data;
3900 struct rte_ether_addr *macaddr;
3903 macaddr = &data->mac_addrs[index];
3904 ret = ice_remove_mac_filter(vsi, macaddr);
3906 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3912 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3914 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3915 struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
3916 struct ice_vsi *vsi = pf->main_vsi;
3919 PMD_INIT_FUNC_TRACE();
3922 * Vlan 0 is the generic filter for untagged packets
3923 * and can't be removed or added by user.
3929 ret = ice_add_vlan_filter(vsi, &vlan);
3931 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3935 ret = ice_remove_vlan_filter(vsi, &vlan);
3937 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3945 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
3946 * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
3947 * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
3948 * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
3950 * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
3951 * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
3952 * traffic in SVM, since the VLAN TPID isn't part of filtering.
3954 * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
3955 * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
3956 * part of filtering.
3959 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
3961 struct ice_vlan vlan;
3964 vlan = ICE_VLAN(0, 0);
3965 err = ice_add_vlan_filter(vsi, &vlan);
3967 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
3971 /* in SVM both VLAN 0 filters are identical */
3972 if (!ice_is_dvm_ena(&vsi->adapter->hw))
3975 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3976 err = ice_add_vlan_filter(vsi, &vlan);
3978 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
3986 * Delete the VLAN 0 filters in the same manner that they were added in
3987 * ice_vsi_add_vlan_zero.
3990 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
3992 struct ice_vlan vlan;
3995 vlan = ICE_VLAN(0, 0);
3996 err = ice_remove_vlan_filter(vsi, &vlan);
3998 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
4002 /* in SVM both VLAN 0 filters are identical */
4003 if (!ice_is_dvm_ena(&vsi->adapter->hw))
4006 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4007 err = ice_remove_vlan_filter(vsi, &vlan);
4009 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
4016 /* Configure vlan filter on or off */
4018 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4020 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4021 struct ice_vsi_ctx ctxt;
4025 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4028 vsi->info.sw_flags2 |= sw_flags2;
4030 vsi->info.sw_flags2 &= ~sw_flags2;
4032 vsi->info.sw_id = hw->port_info->sw_id;
4033 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4034 ctxt.info.valid_sections =
4035 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4036 ICE_AQ_VSI_PROP_SECURITY_VALID);
4037 ctxt.vsi_num = vsi->vsi_id;
4039 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4041 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4042 on ? "enable" : "disable");
4045 vsi->info.valid_sections |=
4046 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4047 ICE_AQ_VSI_PROP_SECURITY_VALID);
4050 /* consist with other drivers, allow untagged packet when vlan filter on */
4052 ret = ice_vsi_add_vlan_zero(vsi);
4054 ret = ice_vsi_del_vlan_zero(vsi);
4059 /* Manage VLAN stripping for the VSI for Rx */
4061 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4063 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4064 struct ice_vsi_ctx ctxt;
4065 enum ice_status status;
4068 /* do not allow modifying VLAN stripping when a port VLAN is configured
4071 if (vsi->info.port_based_inner_vlan)
4074 memset(&ctxt, 0, sizeof(ctxt));
4077 /* Strip VLAN tag from Rx packet and put it in the desc */
4078 ctxt.info.inner_vlan_flags =
4079 ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4081 /* Disable stripping. Leave tag in packet */
4082 ctxt.info.inner_vlan_flags =
4083 ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4085 /* Allow all packets untagged/tagged */
4086 ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4088 ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4090 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4092 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4093 ena ? "enable" : "disable");
4096 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4103 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4105 return ice_vsi_manage_vlan_stripping(vsi, true);
4109 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4111 return ice_vsi_manage_vlan_stripping(vsi, false);
4114 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4116 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4117 struct ice_vsi_ctx ctxt;
4118 enum ice_status status;
4121 /* do not allow modifying VLAN stripping when a port VLAN is configured
4124 if (vsi->info.port_based_outer_vlan)
4127 memset(&ctxt, 0, sizeof(ctxt));
4129 ctxt.info.valid_sections =
4130 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4131 /* clear current outer VLAN strip settings */
4132 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4133 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4134 ctxt.info.outer_vlan_flags |=
4135 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4136 ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4137 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4138 ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4140 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4142 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4145 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4152 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4154 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4155 struct ice_vsi_ctx ctxt;
4156 enum ice_status status;
4159 if (vsi->info.port_based_outer_vlan)
4162 memset(&ctxt, 0, sizeof(ctxt));
4164 ctxt.info.valid_sections =
4165 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4166 /* clear current outer VLAN strip settings */
4167 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4168 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4169 ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4170 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4172 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4174 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4177 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4184 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4186 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4189 if (ice_is_dvm_ena(hw)) {
4191 ret = ice_vsi_ena_outer_stripping(vsi);
4193 ret = ice_vsi_dis_outer_stripping(vsi);
4196 ret = ice_vsi_ena_inner_stripping(vsi);
4198 ret = ice_vsi_dis_inner_stripping(vsi);
4205 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4207 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4208 struct ice_vsi *vsi = pf->main_vsi;
4209 struct rte_eth_rxmode *rxmode;
4211 rxmode = &dev->data->dev_conf.rxmode;
4212 if (mask & ETH_VLAN_FILTER_MASK) {
4213 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4214 ice_vsi_config_vlan_filter(vsi, true);
4216 ice_vsi_config_vlan_filter(vsi, false);
4219 if (mask & ETH_VLAN_STRIP_MASK) {
4220 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4221 ice_vsi_config_vlan_stripping(vsi, true);
4223 ice_vsi_config_vlan_stripping(vsi, false);
4230 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4232 struct ice_aq_get_set_rss_lut_params lut_params;
4233 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4234 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4240 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4241 lut_params.vsi_handle = vsi->idx;
4242 lut_params.lut_size = lut_size;
4243 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4244 lut_params.lut = lut;
4245 lut_params.global_lut_id = 0;
4246 ret = ice_aq_get_rss_lut(hw, &lut_params);
4248 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4252 uint64_t *lut_dw = (uint64_t *)lut;
4253 uint16_t i, lut_size_dw = lut_size / 4;
4255 for (i = 0; i < lut_size_dw; i++)
4256 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4263 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4265 struct ice_aq_get_set_rss_lut_params lut_params;
4273 pf = ICE_VSI_TO_PF(vsi);
4274 hw = ICE_VSI_TO_HW(vsi);
4276 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4277 lut_params.vsi_handle = vsi->idx;
4278 lut_params.lut_size = lut_size;
4279 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4280 lut_params.lut = lut;
4281 lut_params.global_lut_id = 0;
4282 ret = ice_aq_set_rss_lut(hw, &lut_params);
4284 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4288 uint64_t *lut_dw = (uint64_t *)lut;
4289 uint16_t i, lut_size_dw = lut_size / 4;
4291 for (i = 0; i < lut_size_dw; i++)
4292 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4301 ice_rss_reta_update(struct rte_eth_dev *dev,
4302 struct rte_eth_rss_reta_entry64 *reta_conf,
4305 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4306 uint16_t i, lut_size = pf->hash_lut_size;
4307 uint16_t idx, shift;
4311 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4312 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4313 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4315 "The size of hash lookup table configured (%d)"
4316 "doesn't match the number hardware can "
4317 "supported (128, 512, 2048)",
4322 /* It MUST use the current LUT size to get the RSS lookup table,
4323 * otherwise if will fail with -100 error code.
4325 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
4327 PMD_DRV_LOG(ERR, "No memory can be allocated");
4330 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4334 for (i = 0; i < reta_size; i++) {
4335 idx = i / RTE_RETA_GROUP_SIZE;
4336 shift = i % RTE_RETA_GROUP_SIZE;
4337 if (reta_conf[idx].mask & (1ULL << shift))
4338 lut[i] = reta_conf[idx].reta[shift];
4340 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4341 if (ret == 0 && lut_size != reta_size) {
4343 "The size of hash lookup table is changed from (%d) to (%d)",
4344 lut_size, reta_size);
4345 pf->hash_lut_size = reta_size;
4355 ice_rss_reta_query(struct rte_eth_dev *dev,
4356 struct rte_eth_rss_reta_entry64 *reta_conf,
4359 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4360 uint16_t i, lut_size = pf->hash_lut_size;
4361 uint16_t idx, shift;
4365 if (reta_size != lut_size) {
4367 "The size of hash lookup table configured (%d)"
4368 "doesn't match the number hardware can "
4370 reta_size, lut_size);
4374 lut = rte_zmalloc(NULL, reta_size, 0);
4376 PMD_DRV_LOG(ERR, "No memory can be allocated");
4380 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4384 for (i = 0; i < reta_size; i++) {
4385 idx = i / RTE_RETA_GROUP_SIZE;
4386 shift = i % RTE_RETA_GROUP_SIZE;
4387 if (reta_conf[idx].mask & (1ULL << shift))
4388 reta_conf[idx].reta[shift] = lut[i];
4398 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4400 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4403 if (!key || key_len == 0) {
4404 PMD_DRV_LOG(DEBUG, "No key to be configured");
4406 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4408 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4412 struct ice_aqc_get_set_rss_keys *key_dw =
4413 (struct ice_aqc_get_set_rss_keys *)key;
4415 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4417 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4425 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4427 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4430 if (!key || !key_len)
4433 ret = ice_aq_get_rss_key
4435 (struct ice_aqc_get_set_rss_keys *)key);
4437 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4440 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4446 ice_rss_hash_update(struct rte_eth_dev *dev,
4447 struct rte_eth_rss_conf *rss_conf)
4449 enum ice_status status = ICE_SUCCESS;
4450 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4451 struct ice_vsi *vsi = pf->main_vsi;
4454 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4458 if (rss_conf->rss_hf == 0) {
4463 /* RSS hash configuration */
4464 ice_rss_hash_set(pf, rss_conf->rss_hf);
4470 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4471 struct rte_eth_rss_conf *rss_conf)
4473 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4474 struct ice_vsi *vsi = pf->main_vsi;
4476 ice_get_rss_key(vsi, rss_conf->rss_key,
4477 &rss_conf->rss_key_len);
4479 rss_conf->rss_hf = pf->rss_hf;
4484 ice_promisc_enable(struct rte_eth_dev *dev)
4486 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4487 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4488 struct ice_vsi *vsi = pf->main_vsi;
4489 enum ice_status status;
4493 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4494 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4496 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4498 case ICE_ERR_ALREADY_EXISTS:
4499 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4503 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4511 ice_promisc_disable(struct rte_eth_dev *dev)
4513 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4514 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4515 struct ice_vsi *vsi = pf->main_vsi;
4516 enum ice_status status;
4520 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4521 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4523 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4524 if (status != ICE_SUCCESS) {
4525 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4533 ice_allmulti_enable(struct rte_eth_dev *dev)
4535 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4536 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4537 struct ice_vsi *vsi = pf->main_vsi;
4538 enum ice_status status;
4542 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4544 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4547 case ICE_ERR_ALREADY_EXISTS:
4548 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4552 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4560 ice_allmulti_disable(struct rte_eth_dev *dev)
4562 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4563 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4564 struct ice_vsi *vsi = pf->main_vsi;
4565 enum ice_status status;
4569 if (dev->data->promiscuous == 1)
4570 return 0; /* must remain in all_multicast mode */
4572 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4574 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4575 if (status != ICE_SUCCESS) {
4576 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4583 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4586 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4587 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4588 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4592 msix_intr = intr_handle->intr_vec[queue_id];
4594 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4595 GLINT_DYN_CTL_ITR_INDX_M;
4596 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4598 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4599 rte_intr_ack(&pci_dev->intr_handle);
4604 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4607 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4608 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4609 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4612 msix_intr = intr_handle->intr_vec[queue_id];
4614 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4620 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4622 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4627 ver = hw->flash.orom.major;
4628 patch = hw->flash.orom.patch;
4629 build = hw->flash.orom.build;
4631 ret = snprintf(fw_version, fw_size,
4632 "%x.%02x 0x%08x %d.%d.%d",
4633 hw->flash.nvm.major,
4634 hw->flash.nvm.minor,
4635 hw->flash.nvm.eetrack,
4638 /* add the size of '\0' */
4640 if (fw_size < (u32)ret)
4647 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4650 struct ice_vsi_ctx ctxt;
4651 uint8_t vlan_flags = 0;
4654 if (!vsi || !info) {
4655 PMD_DRV_LOG(ERR, "invalid parameters");
4660 vsi->info.port_based_inner_vlan = info->config.pvid;
4662 * If insert pvid is enabled, only tagged pkts are
4663 * allowed to be sent out.
4665 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4666 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4668 vsi->info.port_based_inner_vlan = 0;
4669 if (info->config.reject.tagged == 0)
4670 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4672 if (info->config.reject.untagged == 0)
4673 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4675 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4676 ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4677 vsi->info.inner_vlan_flags |= vlan_flags;
4678 memset(&ctxt, 0, sizeof(ctxt));
4679 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4680 ctxt.info.valid_sections =
4681 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4682 ctxt.vsi_num = vsi->vsi_id;
4684 hw = ICE_VSI_TO_HW(vsi);
4685 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4686 if (ret != ICE_SUCCESS) {
4688 "update VSI for VLAN insert failed, err %d",
4693 vsi->info.valid_sections |=
4694 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4700 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4702 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4703 struct ice_vsi *vsi = pf->main_vsi;
4704 struct rte_eth_dev_data *data = pf->dev_data;
4705 struct ice_vsi_vlan_pvid_info info;
4708 memset(&info, 0, sizeof(info));
4711 info.config.pvid = pvid;
4713 info.config.reject.tagged =
4714 data->dev_conf.txmode.hw_vlan_reject_tagged;
4715 info.config.reject.untagged =
4716 data->dev_conf.txmode.hw_vlan_reject_untagged;
4719 ret = ice_vsi_vlan_pvid_set(vsi, &info);
4721 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4729 ice_get_eeprom_length(struct rte_eth_dev *dev)
4731 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4733 return hw->flash.flash_size;
4737 ice_get_eeprom(struct rte_eth_dev *dev,
4738 struct rte_dev_eeprom_info *eeprom)
4740 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4741 enum ice_status status = ICE_SUCCESS;
4742 uint8_t *data = eeprom->data;
4744 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4746 status = ice_acquire_nvm(hw, ICE_RES_READ);
4748 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4752 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4755 ice_release_nvm(hw);
4758 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4766 ice_stat_update_32(struct ice_hw *hw,
4774 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4778 if (new_data >= *offset)
4779 *stat = (uint64_t)(new_data - *offset);
4781 *stat = (uint64_t)((new_data +
4782 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4787 ice_stat_update_40(struct ice_hw *hw,
4796 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4797 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4803 if (new_data >= *offset)
4804 *stat = new_data - *offset;
4806 *stat = (uint64_t)((new_data +
4807 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4810 *stat &= ICE_40_BIT_MASK;
4813 /* Get all the statistics of a VSI */
4815 ice_update_vsi_stats(struct ice_vsi *vsi)
4817 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4818 struct ice_eth_stats *nes = &vsi->eth_stats;
4819 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4820 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4822 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4823 vsi->offset_loaded, &oes->rx_bytes,
4825 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4826 vsi->offset_loaded, &oes->rx_unicast,
4828 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4829 vsi->offset_loaded, &oes->rx_multicast,
4830 &nes->rx_multicast);
4831 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4832 vsi->offset_loaded, &oes->rx_broadcast,
4833 &nes->rx_broadcast);
4834 /* enlarge the limitation when rx_bytes overflowed */
4835 if (vsi->offset_loaded) {
4836 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4837 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4838 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4840 vsi->old_rx_bytes = nes->rx_bytes;
4841 /* exclude CRC bytes */
4842 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4843 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4845 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4846 &oes->rx_discards, &nes->rx_discards);
4847 /* GLV_REPC not supported */
4848 /* GLV_RMPC not supported */
4849 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4850 &oes->rx_unknown_protocol,
4851 &nes->rx_unknown_protocol);
4852 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4853 vsi->offset_loaded, &oes->tx_bytes,
4855 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4856 vsi->offset_loaded, &oes->tx_unicast,
4858 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4859 vsi->offset_loaded, &oes->tx_multicast,
4860 &nes->tx_multicast);
4861 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4862 vsi->offset_loaded, &oes->tx_broadcast,
4863 &nes->tx_broadcast);
4864 /* GLV_TDPC not supported */
4865 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4866 &oes->tx_errors, &nes->tx_errors);
4867 /* enlarge the limitation when tx_bytes overflowed */
4868 if (vsi->offset_loaded) {
4869 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4870 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4871 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4873 vsi->old_tx_bytes = nes->tx_bytes;
4874 vsi->offset_loaded = true;
4876 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4878 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4879 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4880 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4881 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4882 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4883 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4884 nes->rx_unknown_protocol);
4885 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4886 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4887 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4888 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4889 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4890 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4891 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4896 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4898 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4899 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4901 /* Get statistics of struct ice_eth_stats */
4902 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4903 GLPRT_GORCL(hw->port_info->lport),
4904 pf->offset_loaded, &os->eth.rx_bytes,
4906 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4907 GLPRT_UPRCL(hw->port_info->lport),
4908 pf->offset_loaded, &os->eth.rx_unicast,
4909 &ns->eth.rx_unicast);
4910 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4911 GLPRT_MPRCL(hw->port_info->lport),
4912 pf->offset_loaded, &os->eth.rx_multicast,
4913 &ns->eth.rx_multicast);
4914 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4915 GLPRT_BPRCL(hw->port_info->lport),
4916 pf->offset_loaded, &os->eth.rx_broadcast,
4917 &ns->eth.rx_broadcast);
4918 ice_stat_update_32(hw, PRTRPB_RDPC,
4919 pf->offset_loaded, &os->eth.rx_discards,
4920 &ns->eth.rx_discards);
4921 /* enlarge the limitation when rx_bytes overflowed */
4922 if (pf->offset_loaded) {
4923 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4924 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4925 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4927 pf->old_rx_bytes = ns->eth.rx_bytes;
4929 /* Workaround: CRC size should not be included in byte statistics,
4930 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4933 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4934 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4936 /* GLPRT_REPC not supported */
4937 /* GLPRT_RMPC not supported */
4938 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4940 &os->eth.rx_unknown_protocol,
4941 &ns->eth.rx_unknown_protocol);
4942 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4943 GLPRT_GOTCL(hw->port_info->lport),
4944 pf->offset_loaded, &os->eth.tx_bytes,
4946 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4947 GLPRT_UPTCL(hw->port_info->lport),
4948 pf->offset_loaded, &os->eth.tx_unicast,
4949 &ns->eth.tx_unicast);
4950 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4951 GLPRT_MPTCL(hw->port_info->lport),
4952 pf->offset_loaded, &os->eth.tx_multicast,
4953 &ns->eth.tx_multicast);
4954 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4955 GLPRT_BPTCL(hw->port_info->lport),
4956 pf->offset_loaded, &os->eth.tx_broadcast,
4957 &ns->eth.tx_broadcast);
4958 /* enlarge the limitation when tx_bytes overflowed */
4959 if (pf->offset_loaded) {
4960 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4961 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4962 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4964 pf->old_tx_bytes = ns->eth.tx_bytes;
4965 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4966 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4968 /* GLPRT_TEPC not supported */
4970 /* additional port specific stats */
4971 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4972 pf->offset_loaded, &os->tx_dropped_link_down,
4973 &ns->tx_dropped_link_down);
4974 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4975 pf->offset_loaded, &os->crc_errors,
4977 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4978 pf->offset_loaded, &os->illegal_bytes,
4979 &ns->illegal_bytes);
4980 /* GLPRT_ERRBC not supported */
4981 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4982 pf->offset_loaded, &os->mac_local_faults,
4983 &ns->mac_local_faults);
4984 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4985 pf->offset_loaded, &os->mac_remote_faults,
4986 &ns->mac_remote_faults);
4988 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4989 pf->offset_loaded, &os->rx_len_errors,
4990 &ns->rx_len_errors);
4992 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4993 pf->offset_loaded, &os->link_xon_rx,
4995 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4996 pf->offset_loaded, &os->link_xoff_rx,
4998 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4999 pf->offset_loaded, &os->link_xon_tx,
5001 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
5002 pf->offset_loaded, &os->link_xoff_tx,
5004 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
5005 GLPRT_PRC64L(hw->port_info->lport),
5006 pf->offset_loaded, &os->rx_size_64,
5008 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
5009 GLPRT_PRC127L(hw->port_info->lport),
5010 pf->offset_loaded, &os->rx_size_127,
5012 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
5013 GLPRT_PRC255L(hw->port_info->lport),
5014 pf->offset_loaded, &os->rx_size_255,
5016 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
5017 GLPRT_PRC511L(hw->port_info->lport),
5018 pf->offset_loaded, &os->rx_size_511,
5020 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
5021 GLPRT_PRC1023L(hw->port_info->lport),
5022 pf->offset_loaded, &os->rx_size_1023,
5024 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
5025 GLPRT_PRC1522L(hw->port_info->lport),
5026 pf->offset_loaded, &os->rx_size_1522,
5028 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
5029 GLPRT_PRC9522L(hw->port_info->lport),
5030 pf->offset_loaded, &os->rx_size_big,
5032 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
5033 pf->offset_loaded, &os->rx_undersize,
5035 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
5036 pf->offset_loaded, &os->rx_fragments,
5038 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5039 pf->offset_loaded, &os->rx_oversize,
5041 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5042 pf->offset_loaded, &os->rx_jabber,
5044 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5045 GLPRT_PTC64L(hw->port_info->lport),
5046 pf->offset_loaded, &os->tx_size_64,
5048 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5049 GLPRT_PTC127L(hw->port_info->lport),
5050 pf->offset_loaded, &os->tx_size_127,
5052 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5053 GLPRT_PTC255L(hw->port_info->lport),
5054 pf->offset_loaded, &os->tx_size_255,
5056 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5057 GLPRT_PTC511L(hw->port_info->lport),
5058 pf->offset_loaded, &os->tx_size_511,
5060 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5061 GLPRT_PTC1023L(hw->port_info->lport),
5062 pf->offset_loaded, &os->tx_size_1023,
5064 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5065 GLPRT_PTC1522L(hw->port_info->lport),
5066 pf->offset_loaded, &os->tx_size_1522,
5068 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5069 GLPRT_PTC9522L(hw->port_info->lport),
5070 pf->offset_loaded, &os->tx_size_big,
5073 /* GLPRT_MSPDC not supported */
5074 /* GLPRT_XEC not supported */
5076 pf->offset_loaded = true;
5079 ice_update_vsi_stats(pf->main_vsi);
5082 /* Get all statistics of a port */
5084 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5086 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5087 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5088 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5090 /* call read registers - updates values, now write them to struct */
5091 ice_read_stats_registers(pf, hw);
5093 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5094 pf->main_vsi->eth_stats.rx_multicast +
5095 pf->main_vsi->eth_stats.rx_broadcast -
5096 pf->main_vsi->eth_stats.rx_discards;
5097 stats->opackets = ns->eth.tx_unicast +
5098 ns->eth.tx_multicast +
5099 ns->eth.tx_broadcast;
5100 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
5101 stats->obytes = ns->eth.tx_bytes;
5102 stats->oerrors = ns->eth.tx_errors +
5103 pf->main_vsi->eth_stats.tx_errors;
5106 stats->imissed = ns->eth.rx_discards +
5107 pf->main_vsi->eth_stats.rx_discards;
5108 stats->ierrors = ns->crc_errors +
5110 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5112 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5113 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
5114 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5115 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5116 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5117 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5118 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5119 pf->main_vsi->eth_stats.rx_discards);
5120 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5121 ns->eth.rx_unknown_protocol);
5122 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
5123 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5124 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5125 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5126 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5127 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5128 pf->main_vsi->eth_stats.tx_discards);
5129 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
5131 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
5132 ns->tx_dropped_link_down);
5133 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5134 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
5136 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
5137 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
5138 ns->mac_local_faults);
5139 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
5140 ns->mac_remote_faults);
5141 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
5142 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
5143 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
5144 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
5145 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
5146 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
5147 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
5148 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
5149 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
5150 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
5151 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
5152 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
5153 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
5154 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
5155 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
5156 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
5157 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
5158 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
5159 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
5160 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
5161 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
5162 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
5163 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
5164 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5168 /* Reset the statistics */
5170 ice_stats_reset(struct rte_eth_dev *dev)
5172 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5173 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5175 /* Mark PF and VSI stats to update the offset, aka "reset" */
5176 pf->offset_loaded = false;
5178 pf->main_vsi->offset_loaded = false;
5180 /* read the stats, reading current register values into offset */
5181 ice_read_stats_registers(pf, hw);
5187 ice_xstats_calc_num(void)
5191 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5197 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5200 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5201 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5204 struct ice_hw_port_stats *hw_stats = &pf->stats;
5206 count = ice_xstats_calc_num();
5210 ice_read_stats_registers(pf, hw);
5217 /* Get stats from ice_eth_stats struct */
5218 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5219 xstats[count].value =
5220 *(uint64_t *)((char *)&hw_stats->eth +
5221 ice_stats_strings[i].offset);
5222 xstats[count].id = count;
5226 /* Get individiual stats from ice_hw_port struct */
5227 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5228 xstats[count].value =
5229 *(uint64_t *)((char *)hw_stats +
5230 ice_hw_port_strings[i].offset);
5231 xstats[count].id = count;
5238 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5239 struct rte_eth_xstat_name *xstats_names,
5240 __rte_unused unsigned int limit)
5242 unsigned int count = 0;
5246 return ice_xstats_calc_num();
5248 /* Note: limit checked in rte_eth_xstats_names() */
5250 /* Get stats from ice_eth_stats struct */
5251 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5252 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5253 sizeof(xstats_names[count].name));
5257 /* Get individiual stats from ice_hw_port struct */
5258 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5259 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5260 sizeof(xstats_names[count].name));
5268 ice_dev_flow_ops_get(struct rte_eth_dev *dev,
5269 const struct rte_flow_ops **ops)
5274 *ops = &ice_flow_ops;
5278 /* Add UDP tunneling port */
5280 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5281 struct rte_eth_udp_tunnel *udp_tunnel)
5284 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5286 if (udp_tunnel == NULL)
5289 switch (udp_tunnel->prot_type) {
5290 case RTE_TUNNEL_TYPE_VXLAN:
5291 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5294 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5302 /* Delete UDP tunneling port */
5304 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5305 struct rte_eth_udp_tunnel *udp_tunnel)
5308 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5310 if (udp_tunnel == NULL)
5313 switch (udp_tunnel->prot_type) {
5314 case RTE_TUNNEL_TYPE_VXLAN:
5315 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5318 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5327 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5328 struct rte_pci_device *pci_dev)
5330 return rte_eth_dev_pci_generic_probe(pci_dev,
5331 sizeof(struct ice_adapter),
5336 ice_pci_remove(struct rte_pci_device *pci_dev)
5338 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5341 static struct rte_pci_driver rte_ice_pmd = {
5342 .id_table = pci_id_ice_map,
5343 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5344 .probe = ice_pci_probe,
5345 .remove = ice_pci_remove,
5349 * Driver initialization routine.
5350 * Invoked once at EAL init time.
5351 * Register itself as the [Poll Mode] Driver of PCI devices.
5353 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5354 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5355 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5356 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5357 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5358 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5359 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5361 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5362 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5363 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5364 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5366 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5367 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5369 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5370 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);