drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include <rte_tailq.h>
  14
  15 #include "eal_firmware.h"
  16
  17 #include "base/ice_sched.h"
  18 #include "base/ice_flow.h"
  19 #include "base/ice_dcb.h"
  20 #include "base/ice_common.h"
  21
  22 #include "rte_pmd_ice.h"
  23 #include "ice_ethdev.h"
  24 #include "ice_rxtx.h"
  25 #include "ice_generic_flow.h"
  26
  27 /* devargs */
  28 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  29 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  30 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  31 #define ICE_HW_DEBUG_MASK_ARG     "hw_debug_mask"
  32 #define ICE_ONE_PPS_OUT_ARG       "pps_out"
  33
  34 static const char * const ice_valid_args[] = {
  35         ICE_SAFE_MODE_SUPPORT_ARG,
  36         ICE_PIPELINE_MODE_SUPPORT_ARG,
  37         ICE_PROTO_XTR_ARG,
  38         ICE_HW_DEBUG_MASK_ARG,
  39         ICE_ONE_PPS_OUT_ARG,
  40         NULL
  41 };
  42
  43 #define NSEC_PER_SEC      1000000000
  44 #define PPS_OUT_DELAY_NS  1
  45
  46 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  47         .name = "intel_pmd_dynfield_proto_xtr_metadata",
  48         .size = sizeof(uint32_t),
  49         .align = __alignof__(uint32_t),
  50         .flags = 0,
  51 };
  52
  53 struct proto_xtr_ol_flag {
  54         const struct rte_mbuf_dynflag param;
  55         uint64_t *ol_flag;
  56         bool required;
  57 };
  58
  59 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  60
  61 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  62         [PROTO_XTR_VLAN] = {
  63                 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
  64                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  65         [PROTO_XTR_IPV4] = {
  66                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
  67                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  68         [PROTO_XTR_IPV6] = {
  69                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
  70                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  71         [PROTO_XTR_IPV6_FLOW] = {
  72                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
  73                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  74         [PROTO_XTR_TCP] = {
  75                 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
  76                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  77         [PROTO_XTR_IP_OFFSET] = {
  78                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
  79                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  80 };
  81
  82 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  83 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  84 #define ICE_MAX_RES_DESC_NUM        1024
  85
  86 static int ice_dev_configure(struct rte_eth_dev *dev);
  87 static int ice_dev_start(struct rte_eth_dev *dev);
  88 static int ice_dev_stop(struct rte_eth_dev *dev);
  89 static int ice_dev_close(struct rte_eth_dev *dev);
  90 static int ice_dev_reset(struct rte_eth_dev *dev);
  91 static int ice_dev_info_get(struct rte_eth_dev *dev,
  92                             struct rte_eth_dev_info *dev_info);
  93 static int ice_link_update(struct rte_eth_dev *dev,
  94                            int wait_to_complete);
  95 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  96 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  97
  98 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  99 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 100 static int ice_rss_reta_update(struct rte_eth_dev *dev,
 101                                struct rte_eth_rss_reta_entry64 *reta_conf,
 102                                uint16_t reta_size);
 103 static int ice_rss_reta_query(struct rte_eth_dev *dev,
 104                               struct rte_eth_rss_reta_entry64 *reta_conf,
 105                               uint16_t reta_size);
 106 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 107                                struct rte_eth_rss_conf *rss_conf);
 108 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 109                                  struct rte_eth_rss_conf *rss_conf);
 110 static int ice_promisc_enable(struct rte_eth_dev *dev);
 111 static int ice_promisc_disable(struct rte_eth_dev *dev);
 112 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 113 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 114 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 115                                uint16_t vlan_id,
 116                                int on);
 117 static int ice_macaddr_set(struct rte_eth_dev *dev,
 118                            struct rte_ether_addr *mac_addr);
 119 static int ice_macaddr_add(struct rte_eth_dev *dev,
 120                            struct rte_ether_addr *mac_addr,
 121                            __rte_unused uint32_t index,
 122                            uint32_t pool);
 123 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 124 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 125                                     uint16_t queue_id);
 126 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 127                                      uint16_t queue_id);
 128 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 129                               size_t fw_size);
 130 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 131                              uint16_t pvid, int on);
 132 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 133 static int ice_get_eeprom(struct rte_eth_dev *dev,
 134                           struct rte_dev_eeprom_info *eeprom);
 135 static int ice_stats_get(struct rte_eth_dev *dev,
 136                          struct rte_eth_stats *stats);
 137 static int ice_stats_reset(struct rte_eth_dev *dev);
 138 static int ice_xstats_get(struct rte_eth_dev *dev,
 139                           struct rte_eth_xstat *xstats, unsigned int n);
 140 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 141                                 struct rte_eth_xstat_name *xstats_names,
 142                                 unsigned int limit);
 143 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev,
 144                                 const struct rte_flow_ops **ops);
 145 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 146                         struct rte_eth_udp_tunnel *udp_tunnel);
 147 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 148                         struct rte_eth_udp_tunnel *udp_tunnel);
 149
 150 static const struct rte_pci_id pci_id_ice_map[] = {
 151         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 152         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
 165         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
 166         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
 167         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 168         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 169         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 170         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 171         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 172         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
 173         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
 174         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
 175         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
 176         { .vendor_id = 0, /* sentinel */ },
 177 };
 178
 179 static const struct eth_dev_ops ice_eth_dev_ops = {
 180         .dev_configure                = ice_dev_configure,
 181         .dev_start                    = ice_dev_start,
 182         .dev_stop                     = ice_dev_stop,
 183         .dev_close                    = ice_dev_close,
 184         .dev_reset                    = ice_dev_reset,
 185         .dev_set_link_up              = ice_dev_set_link_up,
 186         .dev_set_link_down            = ice_dev_set_link_down,
 187         .rx_queue_start               = ice_rx_queue_start,
 188         .rx_queue_stop                = ice_rx_queue_stop,
 189         .tx_queue_start               = ice_tx_queue_start,
 190         .tx_queue_stop                = ice_tx_queue_stop,
 191         .rx_queue_setup               = ice_rx_queue_setup,
 192         .rx_queue_release             = ice_rx_queue_release,
 193         .tx_queue_setup               = ice_tx_queue_setup,
 194         .tx_queue_release             = ice_tx_queue_release,
 195         .dev_infos_get                = ice_dev_info_get,
 196         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 197         .link_update                  = ice_link_update,
 198         .mtu_set                      = ice_mtu_set,
 199         .mac_addr_set                 = ice_macaddr_set,
 200         .mac_addr_add                 = ice_macaddr_add,
 201         .mac_addr_remove              = ice_macaddr_remove,
 202         .vlan_filter_set              = ice_vlan_filter_set,
 203         .vlan_offload_set             = ice_vlan_offload_set,
 204         .reta_update                  = ice_rss_reta_update,
 205         .reta_query                   = ice_rss_reta_query,
 206         .rss_hash_update              = ice_rss_hash_update,
 207         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 208         .promiscuous_enable           = ice_promisc_enable,
 209         .promiscuous_disable          = ice_promisc_disable,
 210         .allmulticast_enable          = ice_allmulti_enable,
 211         .allmulticast_disable         = ice_allmulti_disable,
 212         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 213         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 214         .fw_version_get               = ice_fw_version_get,
 215         .vlan_pvid_set                = ice_vlan_pvid_set,
 216         .rxq_info_get                 = ice_rxq_info_get,
 217         .txq_info_get                 = ice_txq_info_get,
 218         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 219         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 220         .get_eeprom_length            = ice_get_eeprom_length,
 221         .get_eeprom                   = ice_get_eeprom,
 222         .stats_get                    = ice_stats_get,
 223         .stats_reset                  = ice_stats_reset,
 224         .xstats_get                   = ice_xstats_get,
 225         .xstats_get_names             = ice_xstats_get_names,
 226         .xstats_reset                 = ice_stats_reset,
 227         .flow_ops_get                 = ice_dev_flow_ops_get,
 228         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 229         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 230         .tx_done_cleanup              = ice_tx_done_cleanup,
 231         .get_monitor_addr             = ice_get_monitor_addr,
 232 };
 233
 234 /* store statistics names and its offset in stats structure */
 235 struct ice_xstats_name_off {
 236         char name[RTE_ETH_XSTATS_NAME_SIZE];
 237         unsigned int offset;
 238 };
 239
 240 static const struct ice_xstats_name_off ice_stats_strings[] = {
 241         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 242         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 243         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 244         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 245         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 246                 rx_unknown_protocol)},
 247         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 248         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 249         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 250         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 251 };
 252
 253 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 254                 sizeof(ice_stats_strings[0]))
 255
 256 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 257         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 258                 tx_dropped_link_down)},
 259         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 260         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 261                 illegal_bytes)},
 262         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 263         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 264                 mac_local_faults)},
 265         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 266                 mac_remote_faults)},
 267         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 268                 rx_len_errors)},
 269         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 270         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 271         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 272         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 273         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 274         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 275                 rx_size_127)},
 276         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 277                 rx_size_255)},
 278         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 279                 rx_size_511)},
 280         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 281                 rx_size_1023)},
 282         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 283                 rx_size_1522)},
 284         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 285                 rx_size_big)},
 286         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 287                 rx_undersize)},
 288         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 289                 rx_oversize)},
 290         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 291                 mac_short_pkt_dropped)},
 292         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 293                 rx_fragments)},
 294         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 295         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 296         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 297                 tx_size_127)},
 298         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 299                 tx_size_255)},
 300         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 301                 tx_size_511)},
 302         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 303                 tx_size_1023)},
 304         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 305                 tx_size_1522)},
 306         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 307                 tx_size_big)},
 308 };
 309
 310 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 311                 sizeof(ice_hw_port_strings[0]))
 312
 313 static void
 314 ice_init_controlq_parameter(struct ice_hw *hw)
 315 {
 316         /* fields for adminq */
 317         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 318         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 319         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 320         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 321
 322         /* fields for mailboxq, DPDK used as PF host */
 323         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 324         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 325         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 326         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 327 }
 328
 329 static int
 330 lookup_proto_xtr_type(const char *xtr_name)
 331 {
 332         static struct {
 333                 const char *name;
 334                 enum proto_xtr_type type;
 335         } xtr_type_map[] = {
 336                 { "vlan",      PROTO_XTR_VLAN      },
 337                 { "ipv4",      PROTO_XTR_IPV4      },
 338                 { "ipv6",      PROTO_XTR_IPV6      },
 339                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 340                 { "tcp",       PROTO_XTR_TCP       },
 341                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 342         };
 343         uint32_t i;
 344
 345         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 346                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 347                         return xtr_type_map[i].type;
 348         }
 349
 350         return -1;
 351 }
 352
 353 /*
 354  * Parse elem, the elem could be single number/range or '(' ')' group
 355  * 1) A single number elem, it's just a simple digit. e.g. 9
 356  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 357  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 358  *    Within group elem, '-' used for a range separator;
 359  *                       ',' used for a single number.
 360  */
 361 static int
 362 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 363 {
 364         const char *str = input;
 365         char *end = NULL;
 366         uint32_t min, max;
 367         uint32_t idx;
 368
 369         while (isblank(*str))
 370                 str++;
 371
 372         if (!isdigit(*str) && *str != '(')
 373                 return -1;
 374
 375         /* process single number or single range of number */
 376         if (*str != '(') {
 377                 errno = 0;
 378                 idx = strtoul(str, &end, 10);
 379                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 380                         return -1;
 381
 382                 while (isblank(*end))
 383                         end++;
 384
 385                 min = idx;
 386                 max = idx;
 387
 388                 /* process single <number>-<number> */
 389                 if (*end == '-') {
 390                         end++;
 391                         while (isblank(*end))
 392                                 end++;
 393                         if (!isdigit(*end))
 394                                 return -1;
 395
 396                         errno = 0;
 397                         idx = strtoul(end, &end, 10);
 398                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 399                                 return -1;
 400
 401                         max = idx;
 402                         while (isblank(*end))
 403                                 end++;
 404                 }
 405
 406                 if (*end != ':')
 407                         return -1;
 408
 409                 for (idx = RTE_MIN(min, max);
 410                      idx <= RTE_MAX(min, max); idx++)
 411                         devargs->proto_xtr[idx] = xtr_type;
 412
 413                 return 0;
 414         }
 415
 416         /* process set within bracket */
 417         str++;
 418         while (isblank(*str))
 419                 str++;
 420         if (*str == '\0')
 421                 return -1;
 422
 423         min = ICE_MAX_QUEUE_NUM;
 424         do {
 425                 /* go ahead to the first digit */
 426                 while (isblank(*str))
 427                         str++;
 428                 if (!isdigit(*str))
 429                         return -1;
 430
 431                 /* get the digit value */
 432                 errno = 0;
 433                 idx = strtoul(str, &end, 10);
 434                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 435                         return -1;
 436
 437                 /* go ahead to separator '-',',' and ')' */
 438                 while (isblank(*end))
 439                         end++;
 440                 if (*end == '-') {
 441                         if (min == ICE_MAX_QUEUE_NUM)
 442                                 min = idx;
 443                         else /* avoid continuous '-' */
 444                                 return -1;
 445                 } else if (*end == ',' || *end == ')') {
 446                         max = idx;
 447                         if (min == ICE_MAX_QUEUE_NUM)
 448                                 min = idx;
 449
 450                         for (idx = RTE_MIN(min, max);
 451                              idx <= RTE_MAX(min, max); idx++)
 452                                 devargs->proto_xtr[idx] = xtr_type;
 453
 454                         min = ICE_MAX_QUEUE_NUM;
 455                 } else {
 456                         return -1;
 457                 }
 458
 459                 str = end + 1;
 460         } while (*end != ')' && *end != '\0');
 461
 462         return 0;
 463 }
 464
 465 static int
 466 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 467 {
 468         const char *queue_start;
 469         uint32_t idx;
 470         int xtr_type;
 471         char xtr_name[32];
 472
 473         while (isblank(*queues))
 474                 queues++;
 475
 476         if (*queues != '[') {
 477                 xtr_type = lookup_proto_xtr_type(queues);
 478                 if (xtr_type < 0)
 479                         return -1;
 480
 481                 devargs->proto_xtr_dflt = xtr_type;
 482
 483                 return 0;
 484         }
 485
 486         queues++;
 487         do {
 488                 while (isblank(*queues))
 489                         queues++;
 490                 if (*queues == '\0')
 491                         return -1;
 492
 493                 queue_start = queues;
 494
 495                 /* go across a complete bracket */
 496                 if (*queue_start == '(') {
 497                         queues += strcspn(queues, ")");
 498                         if (*queues != ')')
 499                                 return -1;
 500                 }
 501
 502                 /* scan the separator ':' */
 503                 queues += strcspn(queues, ":");
 504                 if (*queues++ != ':')
 505                         return -1;
 506                 while (isblank(*queues))
 507                         queues++;
 508
 509                 for (idx = 0; ; idx++) {
 510                         if (isblank(queues[idx]) ||
 511                             queues[idx] == ',' ||
 512                             queues[idx] == ']' ||
 513                             queues[idx] == '\0')
 514                                 break;
 515
 516                         if (idx > sizeof(xtr_name) - 2)
 517                                 return -1;
 518
 519                         xtr_name[idx] = queues[idx];
 520                 }
 521                 xtr_name[idx] = '\0';
 522                 xtr_type = lookup_proto_xtr_type(xtr_name);
 523                 if (xtr_type < 0)
 524                         return -1;
 525
 526                 queues += idx;
 527
 528                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 529                         queues++;
 530
 531                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 532                         return -1;
 533         } while (*queues != '\0');
 534
 535         return 0;
 536 }
 537
 538 static int
 539 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 540                      void *extra_args)
 541 {
 542         struct ice_devargs *devargs = extra_args;
 543
 544         if (value == NULL || extra_args == NULL)
 545                 return -EINVAL;
 546
 547         if (parse_queue_proto_xtr(value, devargs) < 0) {
 548                 PMD_DRV_LOG(ERR,
 549                             "The protocol extraction parameter is wrong : '%s'",
 550                             value);
 551                 return -1;
 552         }
 553
 554         return 0;
 555 }
 556
 557 static void
 558 ice_check_proto_xtr_support(struct ice_hw *hw)
 559 {
 560 #define FLX_REG(val, fld, idx) \
 561         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 562          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 563         static struct {
 564                 uint32_t rxdid;
 565                 uint8_t opcode;
 566                 uint8_t protid_0;
 567                 uint8_t protid_1;
 568         } xtr_sets[] = {
 569                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 570                                      ICE_RX_OPC_EXTRACT,
 571                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 572                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 573                                      ICE_RX_OPC_EXTRACT,
 574                                      ICE_PROT_IPV4_OF_OR_S,
 575                                      ICE_PROT_IPV4_OF_OR_S },
 576                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 577                                      ICE_RX_OPC_EXTRACT,
 578                                      ICE_PROT_IPV6_OF_OR_S,
 579                                      ICE_PROT_IPV6_OF_OR_S },
 580                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 581                                           ICE_RX_OPC_EXTRACT,
 582                                           ICE_PROT_IPV6_OF_OR_S,
 583                                           ICE_PROT_IPV6_OF_OR_S },
 584                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 585                                     ICE_RX_OPC_EXTRACT,
 586                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 587                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 588                                           ICE_RX_OPC_PROTID,
 589                                           ICE_PROT_IPV4_OF_OR_S,
 590                                           ICE_PROT_IPV6_OF_OR_S },
 591         };
 592         uint32_t i;
 593
 594         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 595                 uint32_t rxdid = xtr_sets[i].rxdid;
 596                 uint32_t v;
 597
 598                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 599                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 600
 601                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 602                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 603                                 ice_proto_xtr_hw_support[i] = true;
 604                 }
 605
 606                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 607                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 608
 609                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 610                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 611                                 ice_proto_xtr_hw_support[i] = true;
 612                 }
 613         }
 614 }
 615
 616 static int
 617 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 618                   uint32_t num)
 619 {
 620         struct pool_entry *entry;
 621
 622         if (!pool || !num)
 623                 return -EINVAL;
 624
 625         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 626         if (!entry) {
 627                 PMD_INIT_LOG(ERR,
 628                              "Failed to allocate memory for resource pool");
 629                 return -ENOMEM;
 630         }
 631
 632         /* queue heap initialize */
 633         pool->num_free = num;
 634         pool->num_alloc = 0;
 635         pool->base = base;
 636         LIST_INIT(&pool->alloc_list);
 637         LIST_INIT(&pool->free_list);
 638
 639         /* Initialize element  */
 640         entry->base = 0;
 641         entry->len = num;
 642
 643         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 644         return 0;
 645 }
 646
 647 static int
 648 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 649                    uint16_t num)
 650 {
 651         struct pool_entry *entry, *valid_entry;
 652
 653         if (!pool || !num) {
 654                 PMD_INIT_LOG(ERR, "Invalid parameter");
 655                 return -EINVAL;
 656         }
 657
 658         if (pool->num_free < num) {
 659                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 660                              num, pool->num_free);
 661                 return -ENOMEM;
 662         }
 663
 664         valid_entry = NULL;
 665         /* Lookup  in free list and find most fit one */
 666         LIST_FOREACH(entry, &pool->free_list, next) {
 667                 if (entry->len >= num) {
 668                         /* Find best one */
 669                         if (entry->len == num) {
 670                                 valid_entry = entry;
 671                                 break;
 672                         }
 673                         if (!valid_entry ||
 674                             valid_entry->len > entry->len)
 675                                 valid_entry = entry;
 676                 }
 677         }
 678
 679         /* Not find one to satisfy the request, return */
 680         if (!valid_entry) {
 681                 PMD_INIT_LOG(ERR, "No valid entry found");
 682                 return -ENOMEM;
 683         }
 684         /**
 685          * The entry have equal queue number as requested,
 686          * remove it from alloc_list.
 687          */
 688         if (valid_entry->len == num) {
 689                 LIST_REMOVE(valid_entry, next);
 690         } else {
 691                 /**
 692                  * The entry have more numbers than requested,
 693                  * create a new entry for alloc_list and minus its
 694                  * queue base and number in free_list.
 695                  */
 696                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 697                 if (!entry) {
 698                         PMD_INIT_LOG(ERR,
 699                                      "Failed to allocate memory for "
 700                                      "resource pool");
 701                         return -ENOMEM;
 702                 }
 703                 entry->base = valid_entry->base;
 704                 entry->len = num;
 705                 valid_entry->base += num;
 706                 valid_entry->len -= num;
 707                 valid_entry = entry;
 708         }
 709
 710         /* Insert it into alloc list, not sorted */
 711         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 712
 713         pool->num_free -= valid_entry->len;
 714         pool->num_alloc += valid_entry->len;
 715
 716         return valid_entry->base + pool->base;
 717 }
 718
 719 static void
 720 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 721 {
 722         struct pool_entry *entry, *next_entry;
 723
 724         if (!pool)
 725                 return;
 726
 727         for (entry = LIST_FIRST(&pool->alloc_list);
 728              entry && (next_entry = LIST_NEXT(entry, next), 1);
 729              entry = next_entry) {
 730                 LIST_REMOVE(entry, next);
 731                 rte_free(entry);
 732         }
 733
 734         for (entry = LIST_FIRST(&pool->free_list);
 735              entry && (next_entry = LIST_NEXT(entry, next), 1);
 736              entry = next_entry) {
 737                 LIST_REMOVE(entry, next);
 738                 rte_free(entry);
 739         }
 740
 741         pool->num_free = 0;
 742         pool->num_alloc = 0;
 743         pool->base = 0;
 744         LIST_INIT(&pool->alloc_list);
 745         LIST_INIT(&pool->free_list);
 746 }
 747
 748 static void
 749 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 750 {
 751         /* Set VSI LUT selection */
 752         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 753                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 754         /* Set Hash scheme */
 755         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 756                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 757         /* enable TC */
 758         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 759 }
 760
 761 static enum ice_status
 762 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 763                                 struct ice_aqc_vsi_props *info,
 764                                 uint8_t enabled_tcmap)
 765 {
 766         uint16_t bsf, qp_idx;
 767
 768         /* default tc 0 now. Multi-TC supporting need to be done later.
 769          * Configure TC and queue mapping parameters, for enabled TC,
 770          * allocate qpnum_per_tc queues to this traffic.
 771          */
 772         if (enabled_tcmap != 0x01) {
 773                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 774                 return -ENOTSUP;
 775         }
 776
 777         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 778         bsf = rte_bsf32(vsi->nb_qps);
 779         /* Adjust the queue number to actual queues that can be applied */
 780         vsi->nb_qps = 0x1 << bsf;
 781
 782         qp_idx = 0;
 783         /* Set tc and queue mapping with VSI */
 784         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 785                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 786                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 787
 788         /* Associate queue number with VSI */
 789         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 790         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 791         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 792         info->valid_sections |=
 793                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 794         /* Set the info.ingress_table and info.egress_table
 795          * for UP translate table. Now just set it to 1:1 map by default
 796          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 797          */
 798 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 799         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 800         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 801         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 802         return 0;
 803 }
 804
 805 static int
 806 ice_init_mac_address(struct rte_eth_dev *dev)
 807 {
 808         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 809
 810         if (!rte_is_unicast_ether_addr
 811                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 812                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 813                 return -EINVAL;
 814         }
 815
 816         rte_ether_addr_copy(
 817                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 818                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 819
 820         dev->data->mac_addrs =
 821                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0);
 822         if (!dev->data->mac_addrs) {
 823                 PMD_INIT_LOG(ERR,
 824                              "Failed to allocate memory to store mac address");
 825                 return -ENOMEM;
 826         }
 827         /* store it to dev data */
 828         rte_ether_addr_copy(
 829                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 830                 &dev->data->mac_addrs[0]);
 831         return 0;
 832 }
 833
 834 /* Find out specific MAC filter */
 835 static struct ice_mac_filter *
 836 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 837 {
 838         struct ice_mac_filter *f;
 839
 840         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 841                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 842                         return f;
 843         }
 844
 845         return NULL;
 846 }
 847
 848 static int
 849 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 850 {
 851         struct ice_fltr_list_entry *m_list_itr = NULL;
 852         struct ice_mac_filter *f;
 853         struct LIST_HEAD_TYPE list_head;
 854         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 855         int ret = 0;
 856
 857         /* If it's added and configured, return */
 858         f = ice_find_mac_filter(vsi, mac_addr);
 859         if (f) {
 860                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 861                 return 0;
 862         }
 863
 864         INIT_LIST_HEAD(&list_head);
 865
 866         m_list_itr = (struct ice_fltr_list_entry *)
 867                 ice_malloc(hw, sizeof(*m_list_itr));
 868         if (!m_list_itr) {
 869                 ret = -ENOMEM;
 870                 goto DONE;
 871         }
 872         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 873                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 874         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 875         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 876         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 877         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 878         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 879
 880         LIST_ADD(&m_list_itr->list_entry, &list_head);
 881
 882         /* Add the mac */
 883         ret = ice_add_mac(hw, &list_head);
 884         if (ret != ICE_SUCCESS) {
 885                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 886                 ret = -EINVAL;
 887                 goto DONE;
 888         }
 889         /* Add the mac addr into mac list */
 890         f = rte_zmalloc(NULL, sizeof(*f), 0);
 891         if (!f) {
 892                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 893                 ret = -ENOMEM;
 894                 goto DONE;
 895         }
 896         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 897         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 898         vsi->mac_num++;
 899
 900         ret = 0;
 901
 902 DONE:
 903         rte_free(m_list_itr);
 904         return ret;
 905 }
 906
 907 static int
 908 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 909 {
 910         struct ice_fltr_list_entry *m_list_itr = NULL;
 911         struct ice_mac_filter *f;
 912         struct LIST_HEAD_TYPE list_head;
 913         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 914         int ret = 0;
 915
 916         /* Can't find it, return an error */
 917         f = ice_find_mac_filter(vsi, mac_addr);
 918         if (!f)
 919                 return -EINVAL;
 920
 921         INIT_LIST_HEAD(&list_head);
 922
 923         m_list_itr = (struct ice_fltr_list_entry *)
 924                 ice_malloc(hw, sizeof(*m_list_itr));
 925         if (!m_list_itr) {
 926                 ret = -ENOMEM;
 927                 goto DONE;
 928         }
 929         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 930                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 931         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 932         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 933         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 934         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 935         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 936
 937         LIST_ADD(&m_list_itr->list_entry, &list_head);
 938
 939         /* remove the mac filter */
 940         ret = ice_remove_mac(hw, &list_head);
 941         if (ret != ICE_SUCCESS) {
 942                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 943                 ret = -EINVAL;
 944                 goto DONE;
 945         }
 946
 947         /* Remove the mac addr from mac list */
 948         TAILQ_REMOVE(&vsi->mac_list, f, next);
 949         rte_free(f);
 950         vsi->mac_num--;
 951
 952         ret = 0;
 953 DONE:
 954         rte_free(m_list_itr);
 955         return ret;
 956 }
 957
 958 /* Find out specific VLAN filter */
 959 static struct ice_vlan_filter *
 960 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 961 {
 962         struct ice_vlan_filter *f;
 963
 964         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 965                 if (vlan->tpid == f->vlan_info.vlan.tpid &&
 966                     vlan->vid == f->vlan_info.vlan.vid)
 967                         return f;
 968         }
 969
 970         return NULL;
 971 }
 972
 973 static int
 974 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 975 {
 976         struct ice_fltr_list_entry *v_list_itr = NULL;
 977         struct ice_vlan_filter *f;
 978         struct LIST_HEAD_TYPE list_head;
 979         struct ice_hw *hw;
 980         int ret = 0;
 981
 982         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
 983                 return -EINVAL;
 984
 985         hw = ICE_VSI_TO_HW(vsi);
 986
 987         /* If it's added and configured, return. */
 988         f = ice_find_vlan_filter(vsi, vlan);
 989         if (f) {
 990                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 991                 return 0;
 992         }
 993
 994         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 995                 return 0;
 996
 997         INIT_LIST_HEAD(&list_head);
 998
 999         v_list_itr = (struct ice_fltr_list_entry *)
1000                       ice_malloc(hw, sizeof(*v_list_itr));
1001         if (!v_list_itr) {
1002                 ret = -ENOMEM;
1003                 goto DONE;
1004         }
1005         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1006         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1007         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1008         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1009         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1010         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1011         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1012         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1013
1014         LIST_ADD(&v_list_itr->list_entry, &list_head);
1015
1016         /* Add the vlan */
1017         ret = ice_add_vlan(hw, &list_head);
1018         if (ret != ICE_SUCCESS) {
1019                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1020                 ret = -EINVAL;
1021                 goto DONE;
1022         }
1023
1024         /* Add vlan into vlan list */
1025         f = rte_zmalloc(NULL, sizeof(*f), 0);
1026         if (!f) {
1027                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1028                 ret = -ENOMEM;
1029                 goto DONE;
1030         }
1031         f->vlan_info.vlan.tpid = vlan->tpid;
1032         f->vlan_info.vlan.vid = vlan->vid;
1033         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1034         vsi->vlan_num++;
1035
1036         ret = 0;
1037
1038 DONE:
1039         rte_free(v_list_itr);
1040         return ret;
1041 }
1042
1043 static int
1044 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1045 {
1046         struct ice_fltr_list_entry *v_list_itr = NULL;
1047         struct ice_vlan_filter *f;
1048         struct LIST_HEAD_TYPE list_head;
1049         struct ice_hw *hw;
1050         int ret = 0;
1051
1052         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1053                 return -EINVAL;
1054
1055         hw = ICE_VSI_TO_HW(vsi);
1056
1057         /* Can't find it, return an error */
1058         f = ice_find_vlan_filter(vsi, vlan);
1059         if (!f)
1060                 return -EINVAL;
1061
1062         INIT_LIST_HEAD(&list_head);
1063
1064         v_list_itr = (struct ice_fltr_list_entry *)
1065                       ice_malloc(hw, sizeof(*v_list_itr));
1066         if (!v_list_itr) {
1067                 ret = -ENOMEM;
1068                 goto DONE;
1069         }
1070
1071         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1072         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1073         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1074         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1075         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1076         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1077         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1078         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1079
1080         LIST_ADD(&v_list_itr->list_entry, &list_head);
1081
1082         /* remove the vlan filter */
1083         ret = ice_remove_vlan(hw, &list_head);
1084         if (ret != ICE_SUCCESS) {
1085                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1086                 ret = -EINVAL;
1087                 goto DONE;
1088         }
1089
1090         /* Remove the vlan id from vlan list */
1091         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1092         rte_free(f);
1093         vsi->vlan_num--;
1094
1095         ret = 0;
1096 DONE:
1097         rte_free(v_list_itr);
1098         return ret;
1099 }
1100
1101 static int
1102 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1103 {
1104         struct ice_mac_filter *m_f;
1105         struct ice_vlan_filter *v_f;
1106         void *temp;
1107         int ret = 0;
1108
1109         if (!vsi || !vsi->mac_num)
1110                 return -EINVAL;
1111
1112         TAILQ_FOREACH_SAFE(m_f, &vsi->mac_list, next, temp) {
1113                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1114                 if (ret != ICE_SUCCESS) {
1115                         ret = -EINVAL;
1116                         goto DONE;
1117                 }
1118         }
1119
1120         if (vsi->vlan_num == 0)
1121                 return 0;
1122
1123         TAILQ_FOREACH_SAFE(v_f, &vsi->vlan_list, next, temp) {
1124                 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1125                 if (ret != ICE_SUCCESS) {
1126                         ret = -EINVAL;
1127                         goto DONE;
1128                 }
1129         }
1130
1131 DONE:
1132         return ret;
1133 }
1134
1135 /* Enable IRQ0 */
1136 static void
1137 ice_pf_enable_irq0(struct ice_hw *hw)
1138 {
1139         /* reset the registers */
1140         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1141         ICE_READ_REG(hw, PFINT_OICR);
1142
1143 #ifdef ICE_LSE_SPT
1144         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1145                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1146                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1147
1148         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1149                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1150                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1151                        PFINT_OICR_CTL_ITR_INDX_M) |
1152                       PFINT_OICR_CTL_CAUSE_ENA_M);
1153
1154         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1155                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1156                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1157                        PFINT_FW_CTL_ITR_INDX_M) |
1158                       PFINT_FW_CTL_CAUSE_ENA_M);
1159 #else
1160         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1161 #endif
1162
1163         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1164                       GLINT_DYN_CTL_INTENA_M |
1165                       GLINT_DYN_CTL_CLEARPBA_M |
1166                       GLINT_DYN_CTL_ITR_INDX_M);
1167
1168         ice_flush(hw);
1169 }
1170
1171 /* Disable IRQ0 */
1172 static void
1173 ice_pf_disable_irq0(struct ice_hw *hw)
1174 {
1175         /* Disable all interrupt types */
1176         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1177         ice_flush(hw);
1178 }
1179
1180 #ifdef ICE_LSE_SPT
1181 static void
1182 ice_handle_aq_msg(struct rte_eth_dev *dev)
1183 {
1184         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1185         struct ice_ctl_q_info *cq = &hw->adminq;
1186         struct ice_rq_event_info event;
1187         uint16_t pending, opcode;
1188         int ret;
1189
1190         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1191         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1192         if (!event.msg_buf) {
1193                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1194                 return;
1195         }
1196
1197         pending = 1;
1198         while (pending) {
1199                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1200
1201                 if (ret != ICE_SUCCESS) {
1202                         PMD_DRV_LOG(INFO,
1203                                     "Failed to read msg from AdminQ, "
1204                                     "adminq_err: %u",
1205                                     hw->adminq.sq_last_status);
1206                         break;
1207                 }
1208                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1209
1210                 switch (opcode) {
1211                 case ice_aqc_opc_get_link_status:
1212                         ret = ice_link_update(dev, 0);
1213                         if (!ret)
1214                                 rte_eth_dev_callback_process
1215                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1216                         break;
1217                 default:
1218                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1219                                     opcode);
1220                         break;
1221                 }
1222         }
1223         rte_free(event.msg_buf);
1224 }
1225 #endif
1226
1227 /**
1228  * Interrupt handler triggered by NIC for handling
1229  * specific interrupt.
1230  *
1231  * @param handle
1232  *  Pointer to interrupt handle.
1233  * @param param
1234  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1235  *
1236  * @return
1237  *  void
1238  */
1239 static void
1240 ice_interrupt_handler(void *param)
1241 {
1242         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1243         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1244         uint32_t oicr;
1245         uint32_t reg;
1246         uint8_t pf_num;
1247         uint8_t event;
1248         uint16_t queue;
1249         int ret;
1250 #ifdef ICE_LSE_SPT
1251         uint32_t int_fw_ctl;
1252 #endif
1253
1254         /* Disable interrupt */
1255         ice_pf_disable_irq0(hw);
1256
1257         /* read out interrupt causes */
1258         oicr = ICE_READ_REG(hw, PFINT_OICR);
1259 #ifdef ICE_LSE_SPT
1260         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1261 #endif
1262
1263         /* No interrupt event indicated */
1264         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1265                 PMD_DRV_LOG(INFO, "No interrupt event");
1266                 goto done;
1267         }
1268
1269 #ifdef ICE_LSE_SPT
1270         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1271                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1272                 ice_handle_aq_msg(dev);
1273         }
1274 #else
1275         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1276                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1277                 ret = ice_link_update(dev, 0);
1278                 if (!ret)
1279                         rte_eth_dev_callback_process
1280                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1281         }
1282 #endif
1283
1284         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1285                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1286                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1287                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1288                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1289                                  GL_MDET_TX_PQM_PF_NUM_S;
1290                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1291                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1292                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1293                                 GL_MDET_TX_PQM_QNUM_S;
1294
1295                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1296                                     "%d by PQM on TX queue %d PF# %d",
1297                                     event, queue, pf_num);
1298                 }
1299
1300                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1301                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1302                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1303                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1304                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1305                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1306                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1307                                 GL_MDET_TX_TCLAN_QNUM_S;
1308
1309                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1310                                     "%d by TCLAN on TX queue %d PF# %d",
1311                                     event, queue, pf_num);
1312                 }
1313         }
1314 done:
1315         /* Enable interrupt */
1316         ice_pf_enable_irq0(hw);
1317         rte_intr_ack(dev->intr_handle);
1318 }
1319
1320 static void
1321 ice_init_proto_xtr(struct rte_eth_dev *dev)
1322 {
1323         struct ice_adapter *ad =
1324                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1325         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1326         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1327         const struct proto_xtr_ol_flag *ol_flag;
1328         bool proto_xtr_enable = false;
1329         int offset;
1330         uint16_t i;
1331
1332         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1333         if (unlikely(pf->proto_xtr == NULL)) {
1334                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1335                 return;
1336         }
1337
1338         for (i = 0; i < pf->lan_nb_qps; i++) {
1339                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1340                                    ad->devargs.proto_xtr[i] :
1341                                    ad->devargs.proto_xtr_dflt;
1342
1343                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1344                         uint8_t type = pf->proto_xtr[i];
1345
1346                         ice_proto_xtr_ol_flag_params[type].required = true;
1347                         proto_xtr_enable = true;
1348                 }
1349         }
1350
1351         if (likely(!proto_xtr_enable))
1352                 return;
1353
1354         ice_check_proto_xtr_support(hw);
1355
1356         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1357         if (unlikely(offset == -1)) {
1358                 PMD_DRV_LOG(ERR,
1359                             "Protocol extraction metadata is disabled in mbuf with error %d",
1360                             -rte_errno);
1361                 return;
1362         }
1363
1364         PMD_DRV_LOG(DEBUG,
1365                     "Protocol extraction metadata offset in mbuf is : %d",
1366                     offset);
1367         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1368
1369         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1370                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1371
1372                 if (!ol_flag->required)
1373                         continue;
1374
1375                 if (!ice_proto_xtr_hw_support[i]) {
1376                         PMD_DRV_LOG(ERR,
1377                                     "Protocol extraction type %u is not supported in hardware",
1378                                     i);
1379                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1380                         break;
1381                 }
1382
1383                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1384                 if (unlikely(offset == -1)) {
1385                         PMD_DRV_LOG(ERR,
1386                                     "Protocol extraction offload '%s' failed to register with error %d",
1387                                     ol_flag->param.name, -rte_errno);
1388
1389                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1390                         break;
1391                 }
1392
1393                 PMD_DRV_LOG(DEBUG,
1394                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1395                             ol_flag->param.name, offset);
1396                 *ol_flag->ol_flag = 1ULL << offset;
1397         }
1398 }
1399
1400 /*  Initialize SW parameters of PF */
1401 static int
1402 ice_pf_sw_init(struct rte_eth_dev *dev)
1403 {
1404         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1405         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1406
1407         pf->lan_nb_qp_max =
1408                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1409                                   hw->func_caps.common_cap.num_rxq);
1410
1411         pf->lan_nb_qps = pf->lan_nb_qp_max;
1412
1413         ice_init_proto_xtr(dev);
1414
1415         if (hw->func_caps.fd_fltr_guar > 0 ||
1416             hw->func_caps.fd_fltr_best_effort > 0) {
1417                 pf->flags |= ICE_FLAG_FDIR;
1418                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1419                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1420         } else {
1421                 pf->fdir_nb_qps = 0;
1422         }
1423         pf->fdir_qp_offset = 0;
1424
1425         return 0;
1426 }
1427
1428 struct ice_vsi *
1429 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1430 {
1431         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1432         struct ice_vsi *vsi = NULL;
1433         struct ice_vsi_ctx vsi_ctx;
1434         int ret;
1435         struct rte_ether_addr broadcast = {
1436                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1437         struct rte_ether_addr mac_addr;
1438         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1439         uint8_t tc_bitmap = 0x1;
1440         uint16_t cfg;
1441
1442         /* hw->num_lports = 1 in NIC mode */
1443         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1444         if (!vsi)
1445                 return NULL;
1446
1447         vsi->idx = pf->next_vsi_idx;
1448         pf->next_vsi_idx++;
1449         vsi->type = type;
1450         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1451         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1452         vsi->vlan_anti_spoof_on = 0;
1453         vsi->vlan_filter_on = 1;
1454         TAILQ_INIT(&vsi->mac_list);
1455         TAILQ_INIT(&vsi->vlan_list);
1456
1457         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1458         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1459                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1460                         hw->func_caps.common_cap.rss_table_size;
1461         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1462
1463         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1464         switch (type) {
1465         case ICE_VSI_PF:
1466                 vsi->nb_qps = pf->lan_nb_qps;
1467                 vsi->base_queue = 1;
1468                 ice_vsi_config_default_rss(&vsi_ctx.info);
1469                 vsi_ctx.alloc_from_pool = true;
1470                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1471                 /* switch_id is queried by get_switch_config aq, which is done
1472                  * by ice_init_hw
1473                  */
1474                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1475                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1476                 /* Allow all untagged or tagged packets */
1477                 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1478                 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1479                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1480                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1481                 if (ice_is_dvm_ena(hw)) {
1482                         vsi_ctx.info.outer_vlan_flags =
1483                                 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1484                                  ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1485                                 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1486                         vsi_ctx.info.outer_vlan_flags |=
1487                                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1488                                  ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1489                                 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1490                 }
1491
1492                 /* FDIR */
1493                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1494                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1495                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1496                 cfg = ICE_AQ_VSI_FD_ENABLE;
1497                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1498                 vsi_ctx.info.max_fd_fltr_dedicated =
1499                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1500                 vsi_ctx.info.max_fd_fltr_shared =
1501                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1502
1503                 /* Enable VLAN/UP trip */
1504                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1505                                                       &vsi_ctx.info,
1506                                                       ICE_DEFAULT_TCMAP);
1507                 if (ret) {
1508                         PMD_INIT_LOG(ERR,
1509                                      "tc queue mapping with vsi failed, "
1510                                      "err = %d",
1511                                      ret);
1512                         goto fail_mem;
1513                 }
1514
1515                 break;
1516         case ICE_VSI_CTRL:
1517                 vsi->nb_qps = pf->fdir_nb_qps;
1518                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1519                 vsi_ctx.alloc_from_pool = true;
1520                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1521
1522                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1523                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1524                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1525                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1526                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1527                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1528                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1529                                                       &vsi_ctx.info,
1530                                                       ICE_DEFAULT_TCMAP);
1531                 if (ret) {
1532                         PMD_INIT_LOG(ERR,
1533                                      "tc queue mapping with vsi failed, "
1534                                      "err = %d",
1535                                      ret);
1536                         goto fail_mem;
1537                 }
1538                 break;
1539         default:
1540                 /* for other types of VSI */
1541                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1542                 goto fail_mem;
1543         }
1544
1545         /* VF has MSIX interrupt in VF range, don't allocate here */
1546         if (type == ICE_VSI_PF) {
1547                 ret = ice_res_pool_alloc(&pf->msix_pool,
1548                                          RTE_MIN(vsi->nb_qps,
1549                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1550                 if (ret < 0) {
1551                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1552                                      vsi->vsi_id, ret);
1553                 }
1554                 vsi->msix_intr = ret;
1555                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1556         } else if (type == ICE_VSI_CTRL) {
1557                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1558                 if (ret < 0) {
1559                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1560                                     vsi->vsi_id, ret);
1561                 }
1562                 vsi->msix_intr = ret;
1563                 vsi->nb_msix = 1;
1564         } else {
1565                 vsi->msix_intr = 0;
1566                 vsi->nb_msix = 0;
1567         }
1568         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1569         if (ret != ICE_SUCCESS) {
1570                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1571                 goto fail_mem;
1572         }
1573         /* store vsi information is SW structure */
1574         vsi->vsi_id = vsi_ctx.vsi_num;
1575         vsi->info = vsi_ctx.info;
1576         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1577         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1578
1579         if (type == ICE_VSI_PF) {
1580                 /* MAC configuration */
1581                 rte_ether_addr_copy((struct rte_ether_addr *)
1582                                         hw->port_info->mac.perm_addr,
1583                                     &pf->dev_addr);
1584
1585                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1586                 ret = ice_add_mac_filter(vsi, &mac_addr);
1587                 if (ret != ICE_SUCCESS)
1588                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1589
1590                 rte_ether_addr_copy(&broadcast, &mac_addr);
1591                 ret = ice_add_mac_filter(vsi, &mac_addr);
1592                 if (ret != ICE_SUCCESS)
1593                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1594         }
1595
1596         /* At the beginning, only TC0. */
1597         /* What we need here is the maximam number of the TX queues.
1598          * Currently vsi->nb_qps means it.
1599          * Correct it if any change.
1600          */
1601         max_txqs[0] = vsi->nb_qps;
1602         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1603                               tc_bitmap, max_txqs);
1604         if (ret != ICE_SUCCESS)
1605                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1606
1607         return vsi;
1608 fail_mem:
1609         rte_free(vsi);
1610         pf->next_vsi_idx--;
1611         return NULL;
1612 }
1613
1614 static int
1615 ice_send_driver_ver(struct ice_hw *hw)
1616 {
1617         struct ice_driver_ver dv;
1618
1619         /* we don't have driver version use 0 for dummy */
1620         dv.major_ver = 0;
1621         dv.minor_ver = 0;
1622         dv.build_ver = 0;
1623         dv.subbuild_ver = 0;
1624         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1625
1626         return ice_aq_send_driver_ver(hw, &dv, NULL);
1627 }
1628
1629 static int
1630 ice_pf_setup(struct ice_pf *pf)
1631 {
1632         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1633         struct ice_vsi *vsi;
1634         uint16_t unused;
1635
1636         /* Clear all stats counters */
1637         pf->offset_loaded = false;
1638         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1639         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1640         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1641         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1642
1643         /* force guaranteed filter pool for PF */
1644         ice_alloc_fd_guar_item(hw, &unused,
1645                                hw->func_caps.fd_fltr_guar);
1646         /* force shared filter pool for PF */
1647         ice_alloc_fd_shrd_item(hw, &unused,
1648                                hw->func_caps.fd_fltr_best_effort);
1649
1650         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1651         if (!vsi) {
1652                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1653                 return -EINVAL;
1654         }
1655
1656         pf->main_vsi = vsi;
1657
1658         return 0;
1659 }
1660
1661 static enum ice_pkg_type
1662 ice_load_pkg_type(struct ice_hw *hw)
1663 {
1664         enum ice_pkg_type package_type;
1665
1666         /* store the activated package type (OS default or Comms) */
1667         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1668                 ICE_PKG_NAME_SIZE))
1669                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1670         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1671                 ICE_PKG_NAME_SIZE))
1672                 package_type = ICE_PKG_TYPE_COMMS;
1673         else
1674                 package_type = ICE_PKG_TYPE_UNKNOWN;
1675
1676         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1677                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1678                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1679                 hw->active_pkg_name,
1680                 ice_is_dvm_ena(hw) ? "double" : "single");
1681
1682         return package_type;
1683 }
1684
1685 int ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn)
1686 {
1687         struct ice_hw *hw = &adapter->hw;
1688         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1689         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1690         void *buf;
1691         size_t bufsz;
1692         int err;
1693
1694         if (!use_dsn)
1695                 goto no_dsn;
1696
1697         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1698         snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1699                 "ice-%016" PRIx64 ".pkg", dsn);
1700         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1701                 ICE_MAX_PKG_FILENAME_SIZE);
1702         strcat(pkg_file, opt_ddp_filename);
1703         if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1704                 goto load_fw;
1705
1706         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1707                 ICE_MAX_PKG_FILENAME_SIZE);
1708         strcat(pkg_file, opt_ddp_filename);
1709         if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1710                 goto load_fw;
1711
1712 no_dsn:
1713         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1714         if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1715                 goto load_fw;
1716
1717         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1718         if (rte_firmware_read(pkg_file, &buf, &bufsz) < 0) {
1719                 PMD_INIT_LOG(ERR, "failed to search file path\n");
1720                 return -1;
1721         }
1722
1723 load_fw:
1724         PMD_INIT_LOG(DEBUG, "DDP package name: %s", pkg_file);
1725
1726         err = ice_copy_and_init_pkg(hw, buf, bufsz);
1727         if (err) {
1728                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1729                 goto out;
1730         }
1731
1732         /* store the loaded pkg type info */
1733         adapter->active_pkg_type = ice_load_pkg_type(hw);
1734
1735 out:
1736         free(buf);
1737         return err;
1738 }
1739
1740 static void
1741 ice_base_queue_get(struct ice_pf *pf)
1742 {
1743         uint32_t reg;
1744         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1745
1746         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1747         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1748                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1749         } else {
1750                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1751                                         " index");
1752         }
1753 }
1754
1755 static int
1756 parse_bool(const char *key, const char *value, void *args)
1757 {
1758         int *i = (int *)args;
1759         char *end;
1760         int num;
1761
1762         num = strtoul(value, &end, 10);
1763
1764         if (num != 0 && num != 1) {
1765                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1766                         "value must be 0 or 1",
1767                         value, key);
1768                 return -1;
1769         }
1770
1771         *i = num;
1772         return 0;
1773 }
1774
1775 static int
1776 parse_u64(const char *key, const char *value, void *args)
1777 {
1778         u64 *num = (u64 *)args;
1779         u64 tmp;
1780
1781         errno = 0;
1782         tmp = strtoull(value, NULL, 16);
1783         if (errno) {
1784                 PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u64",
1785                             key, value);
1786                 return -1;
1787         }
1788
1789         *num = tmp;
1790
1791         return 0;
1792 }
1793
1794 static int
1795 lookup_pps_type(const char *pps_name)
1796 {
1797         static struct {
1798                 const char *name;
1799                 enum pps_type type;
1800         } pps_type_map[] = {
1801                 { "pin",  PPS_PIN  },
1802         };
1803
1804         uint32_t i;
1805
1806         for (i = 0; i < RTE_DIM(pps_type_map); i++) {
1807                 if (strcmp(pps_name, pps_type_map[i].name) == 0)
1808                         return pps_type_map[i].type;
1809         }
1810
1811         return -1;
1812 }
1813
1814 static int
1815 parse_pin_set(const char *input, int pps_type, struct ice_devargs *devargs)
1816 {
1817         const char *str = input;
1818         char *end = NULL;
1819         uint32_t idx;
1820
1821         while (isblank(*str))
1822                 str++;
1823
1824         if (!isdigit(*str))
1825                 return -1;
1826
1827         if (pps_type == PPS_PIN) {
1828                 idx = strtoul(str, &end, 10);
1829                 if (end == NULL || idx >= ICE_MAX_PIN_NUM)
1830                         return -1;
1831
1832                 devargs->pin_idx = idx;
1833                 devargs->pps_out_ena = 1;
1834         }
1835
1836         while (isblank(*end))
1837                 end++;
1838
1839         if (*end != ']')
1840                 return -1;
1841
1842         return 0;
1843 }
1844
1845 static int
1846 parse_pps_out_parameter(const char *pins, struct ice_devargs *devargs)
1847 {
1848         const char *pin_start;
1849         uint32_t idx;
1850         int pps_type;
1851         char pps_name[32];
1852
1853         while (isblank(*pins))
1854                 pins++;
1855
1856         pins++;
1857         while (isblank(*pins))
1858                 pins++;
1859         if (*pins == '\0')
1860                 return -1;
1861
1862         for (idx = 0; ; idx++) {
1863                 if (isblank(pins[idx]) ||
1864                     pins[idx] == ':' ||
1865                     pins[idx] == '\0')
1866                         break;
1867
1868                 pps_name[idx] = pins[idx];
1869         }
1870         pps_name[idx] = '\0';
1871         pps_type = lookup_pps_type(pps_name);
1872         if (pps_type < 0)
1873                 return -1;
1874
1875         pins += idx;
1876
1877         pins += strcspn(pins, ":");
1878         if (*pins++ != ':')
1879                 return -1;
1880         while (isblank(*pins))
1881                 pins++;
1882
1883         pin_start = pins;
1884
1885         while (isblank(*pins))
1886                 pins++;
1887
1888         if (parse_pin_set(pin_start, pps_type, devargs) < 0)
1889                 return -1;
1890
1891         return 0;
1892 }
1893
1894 static int
1895 handle_pps_out_arg(__rte_unused const char *key, const char *value,
1896                    void *extra_args)
1897 {
1898         struct ice_devargs *devargs = extra_args;
1899
1900         if (value == NULL || extra_args == NULL)
1901                 return -EINVAL;
1902
1903         if (parse_pps_out_parameter(value, devargs) < 0) {
1904                 PMD_DRV_LOG(ERR,
1905                             "The GPIO pin parameter is wrong : '%s'",
1906                             value);
1907                 return -1;
1908         }
1909
1910         return 0;
1911 }
1912
1913 static int ice_parse_devargs(struct rte_eth_dev *dev)
1914 {
1915         struct ice_adapter *ad =
1916                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1917         struct rte_devargs *devargs = dev->device->devargs;
1918         struct rte_kvargs *kvlist;
1919         int ret;
1920
1921         if (devargs == NULL)
1922                 return 0;
1923
1924         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1925         if (kvlist == NULL) {
1926                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1927                 return -EINVAL;
1928         }
1929
1930         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1931         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1932                sizeof(ad->devargs.proto_xtr));
1933
1934         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1935                                  &handle_proto_xtr_arg, &ad->devargs);
1936         if (ret)
1937                 goto bail;
1938
1939         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1940                                  &parse_bool, &ad->devargs.safe_mode_support);
1941         if (ret)
1942                 goto bail;
1943
1944         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1945                                  &parse_bool, &ad->devargs.pipe_mode_support);
1946         if (ret)
1947                 goto bail;
1948
1949         ret = rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG,
1950                                  &parse_u64, &ad->hw.debug_mask);
1951         if (ret)
1952                 goto bail;
1953
1954         ret = rte_kvargs_process(kvlist, ICE_ONE_PPS_OUT_ARG,
1955                                  &handle_pps_out_arg, &ad->devargs);
1956         if (ret)
1957                 goto bail;
1958
1959 bail:
1960         rte_kvargs_free(kvlist);
1961         return ret;
1962 }
1963
1964 /* Forward LLDP packets to default VSI by set switch rules */
1965 static int
1966 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1967 {
1968         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1969         struct ice_fltr_list_entry *s_list_itr = NULL;
1970         struct LIST_HEAD_TYPE list_head;
1971         int ret = 0;
1972
1973         INIT_LIST_HEAD(&list_head);
1974
1975         s_list_itr = (struct ice_fltr_list_entry *)
1976                         ice_malloc(hw, sizeof(*s_list_itr));
1977         if (!s_list_itr)
1978                 return -ENOMEM;
1979         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1980         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1981         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1982                         RTE_ETHER_TYPE_LLDP;
1983         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1984         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1985         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1986         LIST_ADD(&s_list_itr->list_entry, &list_head);
1987         if (on)
1988                 ret = ice_add_eth_mac(hw, &list_head);
1989         else
1990                 ret = ice_remove_eth_mac(hw, &list_head);
1991
1992         rte_free(s_list_itr);
1993         return ret;
1994 }
1995
1996 static enum ice_status
1997 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1998                 uint16_t num, uint16_t desc_id,
1999                 uint16_t *prof_buf, uint16_t *num_prof)
2000 {
2001         struct ice_aqc_res_elem *resp_buf;
2002         int ret;
2003         uint16_t buf_len;
2004         bool res_shared = 1;
2005         struct ice_aq_desc aq_desc;
2006         struct ice_sq_cd *cd = NULL;
2007         struct ice_aqc_get_allocd_res_desc *cmd =
2008                         &aq_desc.params.get_res_desc;
2009
2010         buf_len = sizeof(*resp_buf) * num;
2011         resp_buf = ice_malloc(hw, buf_len);
2012         if (!resp_buf)
2013                 return -ENOMEM;
2014
2015         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2016                         ice_aqc_opc_get_allocd_res_desc);
2017
2018         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2019                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2020                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2021         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2022
2023         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2024         if (!ret)
2025                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2026         else
2027                 goto exit;
2028
2029         ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
2030                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2031
2032 exit:
2033         rte_free(resp_buf);
2034         return ret;
2035 }
2036 static int
2037 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2038 {
2039         int ret;
2040         uint16_t prof_id;
2041         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2042         uint16_t first_desc = 1;
2043         uint16_t num_prof = 0;
2044
2045         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2046                         first_desc, prof_buf, &num_prof);
2047         if (ret) {
2048                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2049                 return ret;
2050         }
2051
2052         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2053                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2054                 if (ret) {
2055                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2056                         return ret;
2057                 }
2058         }
2059         return 0;
2060 }
2061
2062 static int
2063 ice_reset_fxp_resource(struct ice_hw *hw)
2064 {
2065         int ret;
2066
2067         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2068         if (ret) {
2069                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2070                 return ret;
2071         }
2072
2073         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2074         if (ret) {
2075                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2076                 return ret;
2077         }
2078
2079         return 0;
2080 }
2081
2082 static void
2083 ice_rss_ctx_init(struct ice_pf *pf)
2084 {
2085         memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
2086 }
2087
2088 static uint64_t
2089 ice_get_supported_rxdid(struct ice_hw *hw)
2090 {
2091         uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2092         uint32_t regval;
2093         int i;
2094
2095         supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2096
2097         for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2098                 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2099                 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2100                         & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2101                         supported_rxdid |= BIT(i);
2102         }
2103         return supported_rxdid;
2104 }
2105
2106 static int
2107 ice_dev_init(struct rte_eth_dev *dev)
2108 {
2109         struct rte_pci_device *pci_dev;
2110         struct rte_intr_handle *intr_handle;
2111         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2113         struct ice_adapter *ad =
2114                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2115         struct ice_vsi *vsi;
2116         int ret;
2117 #ifndef RTE_EXEC_ENV_WINDOWS
2118         off_t pos;
2119         uint32_t dsn_low, dsn_high;
2120         uint64_t dsn;
2121         bool use_dsn;
2122 #endif
2123
2124         dev->dev_ops = &ice_eth_dev_ops;
2125         dev->rx_queue_count = ice_rx_queue_count;
2126         dev->rx_descriptor_status = ice_rx_descriptor_status;
2127         dev->tx_descriptor_status = ice_tx_descriptor_status;
2128         dev->rx_pkt_burst = ice_recv_pkts;
2129         dev->tx_pkt_burst = ice_xmit_pkts;
2130         dev->tx_pkt_prepare = ice_prep_pkts;
2131
2132         /* for secondary processes, we don't initialise any further as primary
2133          * has already done this work.
2134          */
2135         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2136                 ice_set_rx_function(dev);
2137                 ice_set_tx_function(dev);
2138                 return 0;
2139         }
2140
2141         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2142
2143         ice_set_default_ptype_table(dev);
2144         pci_dev = RTE_DEV_TO_PCI(dev->device);
2145         intr_handle = &pci_dev->intr_handle;
2146
2147         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2148         pf->dev_data = dev->data;
2149         hw->back = pf->adapter;
2150         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2151         hw->vendor_id = pci_dev->id.vendor_id;
2152         hw->device_id = pci_dev->id.device_id;
2153         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2154         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2155         hw->bus.device = pci_dev->addr.devid;
2156         hw->bus.func = pci_dev->addr.function;
2157
2158         ret = ice_parse_devargs(dev);
2159         if (ret) {
2160                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2161                 return -EINVAL;
2162         }
2163
2164         ice_init_controlq_parameter(hw);
2165
2166         ret = ice_init_hw(hw);
2167         if (ret) {
2168                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2169                 return -EINVAL;
2170         }
2171
2172 #ifndef RTE_EXEC_ENV_WINDOWS
2173         use_dsn = false;
2174         dsn = 0;
2175         pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
2176         if (pos) {
2177                 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0 ||
2178                                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) {
2179                         PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
2180                 } else {
2181                         use_dsn = true;
2182                         dsn = (uint64_t)dsn_high << 32 | dsn_low;
2183                 }
2184         } else {
2185                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
2186         }
2187
2188         ret = ice_load_pkg(pf->adapter, use_dsn, dsn);
2189         if (ret == 0) {
2190                 ret = ice_init_hw_tbls(hw);
2191                 if (ret) {
2192                         PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", ret);
2193                         rte_free(hw->pkg_copy);
2194                 }
2195         }
2196
2197         if (ret) {
2198                 if (ad->devargs.safe_mode_support == 0) {
2199                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2200                                         "Use safe-mode-support=1 to enter Safe Mode");
2201                         goto err_init_fw;
2202                 }
2203
2204                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2205                                         "Entering Safe Mode");
2206                 ad->is_safe_mode = 1;
2207         }
2208 #endif
2209
2210         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2211                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2212                      hw->api_maj_ver, hw->api_min_ver);
2213
2214         ice_pf_sw_init(dev);
2215         ret = ice_init_mac_address(dev);
2216         if (ret) {
2217                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2218                 goto err_init_mac;
2219         }
2220
2221         ret = ice_res_pool_init(&pf->msix_pool, 1,
2222                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2223         if (ret) {
2224                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2225                 goto err_msix_pool_init;
2226         }
2227
2228         ret = ice_pf_setup(pf);
2229         if (ret) {
2230                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2231                 goto err_pf_setup;
2232         }
2233
2234         ret = ice_send_driver_ver(hw);
2235         if (ret) {
2236                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2237                 goto err_pf_setup;
2238         }
2239
2240         vsi = pf->main_vsi;
2241
2242         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2243         if (ret != ICE_SUCCESS)
2244                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2245         ret = ice_init_dcb(hw, true);
2246         if (ret != ICE_SUCCESS)
2247                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2248         /* Forward LLDP packets to default VSI */
2249         ret = ice_vsi_config_sw_lldp(vsi, true);
2250         if (ret != ICE_SUCCESS)
2251                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2252         /* register callback func to eal lib */
2253         rte_intr_callback_register(intr_handle,
2254                                    ice_interrupt_handler, dev);
2255
2256         ice_pf_enable_irq0(hw);
2257
2258         /* enable uio intr after callback register */
2259         rte_intr_enable(intr_handle);
2260
2261         /* get base queue pairs index  in the device */
2262         ice_base_queue_get(pf);
2263
2264         /* Initialize RSS context for gtpu_eh */
2265         ice_rss_ctx_init(pf);
2266
2267         if (!ad->is_safe_mode) {
2268                 ret = ice_flow_init(ad);
2269                 if (ret) {
2270                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2271                         goto err_flow_init;
2272                 }
2273         }
2274
2275         ret = ice_reset_fxp_resource(hw);
2276         if (ret) {
2277                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2278                 goto err_flow_init;
2279         }
2280
2281         pf->supported_rxdid = ice_get_supported_rxdid(hw);
2282
2283         return 0;
2284
2285 err_flow_init:
2286         ice_flow_uninit(ad);
2287         rte_intr_disable(intr_handle);
2288         ice_pf_disable_irq0(hw);
2289         rte_intr_callback_unregister(intr_handle,
2290                                      ice_interrupt_handler, dev);
2291 err_pf_setup:
2292         ice_res_pool_destroy(&pf->msix_pool);
2293 err_msix_pool_init:
2294         rte_free(dev->data->mac_addrs);
2295         dev->data->mac_addrs = NULL;
2296 err_init_mac:
2297         rte_free(pf->proto_xtr);
2298 #ifndef RTE_EXEC_ENV_WINDOWS
2299 err_init_fw:
2300 #endif
2301         ice_deinit_hw(hw);
2302
2303         return ret;
2304 }
2305
2306 int
2307 ice_release_vsi(struct ice_vsi *vsi)
2308 {
2309         struct ice_hw *hw;
2310         struct ice_vsi_ctx vsi_ctx;
2311         enum ice_status ret;
2312         int error = 0;
2313
2314         if (!vsi)
2315                 return error;
2316
2317         hw = ICE_VSI_TO_HW(vsi);
2318
2319         ice_remove_all_mac_vlan_filters(vsi);
2320
2321         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2322
2323         vsi_ctx.vsi_num = vsi->vsi_id;
2324         vsi_ctx.info = vsi->info;
2325         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2326         if (ret != ICE_SUCCESS) {
2327                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2328                 error = -1;
2329         }
2330
2331         rte_free(vsi->rss_lut);
2332         rte_free(vsi->rss_key);
2333         rte_free(vsi);
2334         return error;
2335 }
2336
2337 void
2338 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2339 {
2340         struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
2341         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2342         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2343         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2344         uint16_t msix_intr, i;
2345
2346         /* disable interrupt and also clear all the exist config */
2347         for (i = 0; i < vsi->nb_qps; i++) {
2348                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2349                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2350                 rte_wmb();
2351         }
2352
2353         if (rte_intr_allow_others(intr_handle))
2354                 /* vfio-pci */
2355                 for (i = 0; i < vsi->nb_msix; i++) {
2356                         msix_intr = vsi->msix_intr + i;
2357                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2358                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2359                 }
2360         else
2361                 /* igb_uio */
2362                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2363 }
2364
2365 static int
2366 ice_dev_stop(struct rte_eth_dev *dev)
2367 {
2368         struct rte_eth_dev_data *data = dev->data;
2369         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2370         struct ice_vsi *main_vsi = pf->main_vsi;
2371         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2372         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2373         uint16_t i;
2374
2375         /* avoid stopping again */
2376         if (pf->adapter_stopped)
2377                 return 0;
2378
2379         /* stop and clear all Rx queues */
2380         for (i = 0; i < data->nb_rx_queues; i++)
2381                 ice_rx_queue_stop(dev, i);
2382
2383         /* stop and clear all Tx queues */
2384         for (i = 0; i < data->nb_tx_queues; i++)
2385                 ice_tx_queue_stop(dev, i);
2386
2387         /* disable all queue interrupts */
2388         ice_vsi_disable_queues_intr(main_vsi);
2389
2390         if (pf->init_link_up)
2391                 ice_dev_set_link_up(dev);
2392         else
2393                 ice_dev_set_link_down(dev);
2394
2395         /* Clean datapath event and queue/vec mapping */
2396         rte_intr_efd_disable(intr_handle);
2397         if (intr_handle->intr_vec) {
2398                 rte_free(intr_handle->intr_vec);
2399                 intr_handle->intr_vec = NULL;
2400         }
2401
2402         pf->adapter_stopped = true;
2403         dev->data->dev_started = 0;
2404
2405         return 0;
2406 }
2407
2408 static int
2409 ice_dev_close(struct rte_eth_dev *dev)
2410 {
2411         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2412         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2414         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2415         struct ice_adapter *ad =
2416                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2417         int ret;
2418         uint32_t val;
2419         uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned;
2420         uint32_t pin_idx = ad->devargs.pin_idx;
2421
2422         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2423                 return 0;
2424
2425         /* Since stop will make link down, then the link event will be
2426          * triggered, disable the irq firstly to avoid the port_infoe etc
2427          * resources deallocation causing the interrupt service thread
2428          * crash.
2429          */
2430         ice_pf_disable_irq0(hw);
2431
2432         ret = ice_dev_stop(dev);
2433
2434         if (!ad->is_safe_mode)
2435                 ice_flow_uninit(ad);
2436
2437         /* release all queue resource */
2438         ice_free_queues(dev);
2439
2440         ice_res_pool_destroy(&pf->msix_pool);
2441         ice_release_vsi(pf->main_vsi);
2442         ice_sched_cleanup_all(hw);
2443         ice_free_hw_tbls(hw);
2444         rte_free(hw->port_info);
2445         hw->port_info = NULL;
2446         ice_shutdown_all_ctrlq(hw);
2447         rte_free(pf->proto_xtr);
2448         pf->proto_xtr = NULL;
2449
2450         if (ad->devargs.pps_out_ena) {
2451                 ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(pin_idx, timer), 0);
2452                 ICE_WRITE_REG(hw, GLTSYN_CLKO(pin_idx, timer), 0);
2453                 ICE_WRITE_REG(hw, GLTSYN_TGT_L(pin_idx, timer), 0);
2454                 ICE_WRITE_REG(hw, GLTSYN_TGT_H(pin_idx, timer), 0);
2455
2456                 val = GLGEN_GPIO_CTL_PIN_DIR_M;
2457                 ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(pin_idx), val);
2458         }
2459
2460         /* disable uio intr before callback unregister */
2461         rte_intr_disable(intr_handle);
2462
2463         /* unregister callback func from eal lib */
2464         rte_intr_callback_unregister(intr_handle,
2465                                      ice_interrupt_handler, dev);
2466
2467         return ret;
2468 }
2469
2470 static int
2471 ice_dev_uninit(struct rte_eth_dev *dev)
2472 {
2473         ice_dev_close(dev);
2474
2475         return 0;
2476 }
2477
2478 static bool
2479 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2480 {
2481         return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2482 }
2483
2484 static void
2485 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2486 {
2487         cfg->hash_flds = 0;
2488         cfg->addl_hdrs = 0;
2489         cfg->symm = 0;
2490         cfg->hdr_type = ICE_RSS_OUTER_HEADERS;
2491 }
2492
2493 static int
2494 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2495 {
2496         enum ice_status status = ICE_SUCCESS;
2497         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2498         struct ice_vsi *vsi = pf->main_vsi;
2499
2500         if (!is_hash_cfg_valid(cfg))
2501                 return -ENOENT;
2502
2503         status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2504         if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2505                 PMD_DRV_LOG(ERR,
2506                             "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2507                             vsi->idx, status);
2508                 return -EBUSY;
2509         }
2510
2511         return 0;
2512 }
2513
2514 static int
2515 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2516 {
2517         enum ice_status status = ICE_SUCCESS;
2518         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2519         struct ice_vsi *vsi = pf->main_vsi;
2520
2521         if (!is_hash_cfg_valid(cfg))
2522                 return -ENOENT;
2523
2524         status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2525         if (status) {
2526                 PMD_DRV_LOG(ERR,
2527                             "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2528                             vsi->idx, status);
2529                 return -EBUSY;
2530         }
2531
2532         return 0;
2533 }
2534
2535 static int
2536 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2537 {
2538         int ret;
2539
2540         ret = ice_hash_moveout(pf, cfg);
2541         if (ret && (ret != -ENOENT))
2542                 return ret;
2543
2544         hash_cfg_reset(cfg);
2545
2546         return 0;
2547 }
2548
2549 static int
2550 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2551                          u8 ctx_idx)
2552 {
2553         int ret;
2554
2555         switch (ctx_idx) {
2556         case ICE_HASH_GTPU_CTX_EH_IP:
2557                 ret = ice_hash_remove(pf,
2558                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2559                 if (ret && (ret != -ENOENT))
2560                         return ret;
2561
2562                 ret = ice_hash_remove(pf,
2563                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2564                 if (ret && (ret != -ENOENT))
2565                         return ret;
2566
2567                 ret = ice_hash_remove(pf,
2568                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2569                 if (ret && (ret != -ENOENT))
2570                         return ret;
2571
2572                 ret = ice_hash_remove(pf,
2573                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2574                 if (ret && (ret != -ENOENT))
2575                         return ret;
2576
2577                 ret = ice_hash_remove(pf,
2578                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2579                 if (ret && (ret != -ENOENT))
2580                         return ret;
2581
2582                 ret = ice_hash_remove(pf,
2583                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2584                 if (ret && (ret != -ENOENT))
2585                         return ret;
2586
2587                 ret = ice_hash_remove(pf,
2588                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2589                 if (ret && (ret != -ENOENT))
2590                         return ret;
2591
2592                 ret = ice_hash_remove(pf,
2593                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2594                 if (ret && (ret != -ENOENT))
2595                         return ret;
2596
2597                 break;
2598         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2599                 ret = ice_hash_remove(pf,
2600                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2601                 if (ret && (ret != -ENOENT))
2602                         return ret;
2603
2604                 ret = ice_hash_remove(pf,
2605                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2606                 if (ret && (ret != -ENOENT))
2607                         return ret;
2608
2609                 ret = ice_hash_moveout(pf,
2610                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2611                 if (ret && (ret != -ENOENT))
2612                         return ret;
2613
2614                 ret = ice_hash_moveout(pf,
2615                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2616                 if (ret && (ret != -ENOENT))
2617                         return ret;
2618
2619                 ret = ice_hash_moveout(pf,
2620                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2621                 if (ret && (ret != -ENOENT))
2622                         return ret;
2623
2624                 ret = ice_hash_moveout(pf,
2625                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2626                 if (ret && (ret != -ENOENT))
2627                         return ret;
2628
2629                 break;
2630         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2631                 ret = ice_hash_remove(pf,
2632                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2633                 if (ret && (ret != -ENOENT))
2634                         return ret;
2635
2636                 ret = ice_hash_remove(pf,
2637                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2638                 if (ret && (ret != -ENOENT))
2639                         return ret;
2640
2641                 ret = ice_hash_moveout(pf,
2642                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2643                 if (ret && (ret != -ENOENT))
2644                         return ret;
2645
2646                 ret = ice_hash_moveout(pf,
2647                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2648                 if (ret && (ret != -ENOENT))
2649                         return ret;
2650
2651                 ret = ice_hash_moveout(pf,
2652                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2653                 if (ret && (ret != -ENOENT))
2654                         return ret;
2655
2656                 ret = ice_hash_moveout(pf,
2657                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2658                 if (ret && (ret != -ENOENT))
2659                         return ret;
2660
2661                 break;
2662         case ICE_HASH_GTPU_CTX_UP_IP:
2663                 ret = ice_hash_remove(pf,
2664                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2665                 if (ret && (ret != -ENOENT))
2666                         return ret;
2667
2668                 ret = ice_hash_remove(pf,
2669                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2670                 if (ret && (ret != -ENOENT))
2671                         return ret;
2672
2673                 ret = ice_hash_moveout(pf,
2674                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2675                 if (ret && (ret != -ENOENT))
2676                         return ret;
2677
2678                 ret = ice_hash_moveout(pf,
2679                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2680                 if (ret && (ret != -ENOENT))
2681                         return ret;
2682
2683                 ret = ice_hash_moveout(pf,
2684                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2685                 if (ret && (ret != -ENOENT))
2686                         return ret;
2687
2688                 break;
2689         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2690         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2691                 ret = ice_hash_moveout(pf,
2692                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2693                 if (ret && (ret != -ENOENT))
2694                         return ret;
2695
2696                 ret = ice_hash_moveout(pf,
2697                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2698                 if (ret && (ret != -ENOENT))
2699                         return ret;
2700
2701                 ret = ice_hash_moveout(pf,
2702                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2703                 if (ret && (ret != -ENOENT))
2704                         return ret;
2705
2706                 break;
2707         case ICE_HASH_GTPU_CTX_DW_IP:
2708                 ret = ice_hash_remove(pf,
2709                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2710                 if (ret && (ret != -ENOENT))
2711                         return ret;
2712
2713                 ret = ice_hash_remove(pf,
2714                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2715                 if (ret && (ret != -ENOENT))
2716                         return ret;
2717
2718                 ret = ice_hash_moveout(pf,
2719                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2720                 if (ret && (ret != -ENOENT))
2721                         return ret;
2722
2723                 ret = ice_hash_moveout(pf,
2724                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2725                 if (ret && (ret != -ENOENT))
2726                         return ret;
2727
2728                 ret = ice_hash_moveout(pf,
2729                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2730                 if (ret && (ret != -ENOENT))
2731                         return ret;
2732
2733                 break;
2734         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2735         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2736                 ret = ice_hash_moveout(pf,
2737                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2738                 if (ret && (ret != -ENOENT))
2739                         return ret;
2740
2741                 ret = ice_hash_moveout(pf,
2742                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2743                 if (ret && (ret != -ENOENT))
2744                         return ret;
2745
2746                 ret = ice_hash_moveout(pf,
2747                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2748                 if (ret && (ret != -ENOENT))
2749                         return ret;
2750
2751                 break;
2752         default:
2753                 break;
2754         }
2755
2756         return 0;
2757 }
2758
2759 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2760 {
2761         u8 eh_idx, ip_idx;
2762
2763         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2764                 eh_idx = 0;
2765         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2766                 eh_idx = 1;
2767         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2768                 eh_idx = 2;
2769         else
2770                 return ICE_HASH_GTPU_CTX_MAX;
2771
2772         ip_idx = 0;
2773         if (hdr & ICE_FLOW_SEG_HDR_UDP)
2774                 ip_idx = 1;
2775         else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2776                 ip_idx = 2;
2777
2778         if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2779                 return eh_idx * 3 + ip_idx;
2780         else
2781                 return ICE_HASH_GTPU_CTX_MAX;
2782 }
2783
2784 static int
2785 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2786 {
2787         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2788
2789         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2790                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2791                                                 gtpu_ctx_idx);
2792         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2793                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2794                                                 gtpu_ctx_idx);
2795
2796         return 0;
2797 }
2798
2799 static int
2800 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2801                           u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2802 {
2803         int ret;
2804
2805         if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2806                 ctx->ctx[ctx_idx] = *cfg;
2807
2808         switch (ctx_idx) {
2809         case ICE_HASH_GTPU_CTX_EH_IP:
2810                 break;
2811         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2812                 ret = ice_hash_moveback(pf,
2813                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2814                 if (ret && (ret != -ENOENT))
2815                         return ret;
2816
2817                 ret = ice_hash_moveback(pf,
2818                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2819                 if (ret && (ret != -ENOENT))
2820                         return ret;
2821
2822                 ret = ice_hash_moveback(pf,
2823                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2824                 if (ret && (ret != -ENOENT))
2825                         return ret;
2826
2827                 ret = ice_hash_moveback(pf,
2828                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2829                 if (ret && (ret != -ENOENT))
2830                         return ret;
2831
2832                 break;
2833         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2834                 ret = ice_hash_moveback(pf,
2835                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2836                 if (ret && (ret != -ENOENT))
2837                         return ret;
2838
2839                 ret = ice_hash_moveback(pf,
2840                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2841                 if (ret && (ret != -ENOENT))
2842                         return ret;
2843
2844                 ret = ice_hash_moveback(pf,
2845                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2846                 if (ret && (ret != -ENOENT))
2847                         return ret;
2848
2849                 ret = ice_hash_moveback(pf,
2850                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2851                 if (ret && (ret != -ENOENT))
2852                         return ret;
2853
2854                 break;
2855         case ICE_HASH_GTPU_CTX_UP_IP:
2856         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2857         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2858         case ICE_HASH_GTPU_CTX_DW_IP:
2859         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2860         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2861                 ret = ice_hash_moveback(pf,
2862                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2863                 if (ret && (ret != -ENOENT))
2864                         return ret;
2865
2866                 ret = ice_hash_moveback(pf,
2867                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2868                 if (ret && (ret != -ENOENT))
2869                         return ret;
2870
2871                 ret = ice_hash_moveback(pf,
2872                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2873                 if (ret && (ret != -ENOENT))
2874                         return ret;
2875
2876                 break;
2877         default:
2878                 break;
2879         }
2880
2881         return 0;
2882 }
2883
2884 static int
2885 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2886 {
2887         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2888
2889         if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2890                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2891                                                  gtpu_ctx_idx, cfg);
2892         else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2893                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2894                                                  gtpu_ctx_idx, cfg);
2895
2896         return 0;
2897 }
2898
2899 static void
2900 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2901 {
2902         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2903
2904         if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2905                 return;
2906
2907         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2908                 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2909         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2910                 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2911 }
2912
2913 int
2914 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2915                      struct ice_rss_hash_cfg *cfg)
2916 {
2917         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2918         int ret;
2919
2920         ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2921         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2922                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2923
2924         ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2925
2926         return 0;
2927 }
2928
2929 int
2930 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2931                      struct ice_rss_hash_cfg *cfg)
2932 {
2933         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2934         int ret;
2935
2936         ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2937         if (ret)
2938                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2939
2940         ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2941         if (ret)
2942                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2943
2944         ret = ice_add_rss_cfg_post(pf, cfg);
2945         if (ret)
2946                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2947
2948         return 0;
2949 }
2950
2951 static void
2952 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2953 {
2954         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2955         struct ice_vsi *vsi = pf->main_vsi;
2956         struct ice_rss_hash_cfg cfg;
2957         int ret;
2958
2959 #define ICE_RSS_HF_ALL ( \
2960         ETH_RSS_IPV4 | \
2961         ETH_RSS_IPV6 | \
2962         ETH_RSS_NONFRAG_IPV4_UDP | \
2963         ETH_RSS_NONFRAG_IPV6_UDP | \
2964         ETH_RSS_NONFRAG_IPV4_TCP | \
2965         ETH_RSS_NONFRAG_IPV6_TCP | \
2966         ETH_RSS_NONFRAG_IPV4_SCTP | \
2967         ETH_RSS_NONFRAG_IPV6_SCTP | \
2968         ETH_RSS_FRAG_IPV4 | \
2969         ETH_RSS_FRAG_IPV6)
2970
2971         ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2972         if (ret)
2973                 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2974                             __func__, ret);
2975
2976         cfg.symm = 0;
2977         cfg.hdr_type = ICE_RSS_OUTER_HEADERS;
2978         /* Configure RSS for IPv4 with src/dst addr as input set */
2979         if (rss_hf & ETH_RSS_IPV4) {
2980                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2981                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2982                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2983                 if (ret)
2984                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2985                                     __func__, ret);
2986         }
2987
2988         /* Configure RSS for IPv6 with src/dst addr as input set */
2989         if (rss_hf & ETH_RSS_IPV6) {
2990                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2991                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2992                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2993                 if (ret)
2994                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2995                                     __func__, ret);
2996         }
2997
2998         /* Configure RSS for udp4 with src/dst addr and port as input set */
2999         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
3000                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
3001                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3002                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
3003                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3004                 if (ret)
3005                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
3006                                     __func__, ret);
3007         }
3008
3009         /* Configure RSS for udp6 with src/dst addr and port as input set */
3010         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
3011                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
3012                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3013                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3014                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3015                 if (ret)
3016                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
3017                                     __func__, ret);
3018         }
3019
3020         /* Configure RSS for tcp4 with src/dst addr and port as input set */
3021         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3022                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
3023                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3024                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3025                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3026                 if (ret)
3027                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
3028                                     __func__, ret);
3029         }
3030
3031         /* Configure RSS for tcp6 with src/dst addr and port as input set */
3032         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3033                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
3034                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3035                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3036                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3037                 if (ret)
3038                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
3039                                     __func__, ret);
3040         }
3041
3042         /* Configure RSS for sctp4 with src/dst addr and port as input set */
3043         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
3044                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
3045                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3046                 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
3047                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3048                 if (ret)
3049                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
3050                                     __func__, ret);
3051         }
3052
3053         /* Configure RSS for sctp6 with src/dst addr and port as input set */
3054         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
3055                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
3056                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3057                 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
3058                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3059                 if (ret)
3060                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
3061                                     __func__, ret);
3062         }
3063
3064         if (rss_hf & ETH_RSS_IPV4) {
3065                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
3066                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3067                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
3068                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3069                 if (ret)
3070                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
3071                                     __func__, ret);
3072         }
3073
3074         if (rss_hf & ETH_RSS_IPV6) {
3075                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
3076                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3077                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
3078                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3079                 if (ret)
3080                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
3081                                     __func__, ret);
3082         }
3083
3084         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
3085                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3086                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3087                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
3088                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3089                 if (ret)
3090                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
3091                                     __func__, ret);
3092         }
3093
3094         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
3095                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3096                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3097                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3098                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3099                 if (ret)
3100                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3101                                     __func__, ret);
3102         }
3103
3104         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3105                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3106                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3107                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3108                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3109                 if (ret)
3110                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3111                                     __func__, ret);
3112         }
3113
3114         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3115                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3116                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3117                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3118                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3119                 if (ret)
3120                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3121                                     __func__, ret);
3122         }
3123
3124         if (rss_hf & ETH_RSS_FRAG_IPV4) {
3125                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_FRAG;
3126                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
3127                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3128                 if (ret)
3129                         PMD_DRV_LOG(ERR, "%s IPV4_FRAG rss flow fail %d",
3130                                     __func__, ret);
3131         }
3132
3133         if (rss_hf & ETH_RSS_FRAG_IPV6) {
3134                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_FRAG;
3135                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
3136                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3137                 if (ret)
3138                         PMD_DRV_LOG(ERR, "%s IPV6_FRAG rss flow fail %d",
3139                                     __func__, ret);
3140         }
3141
3142         pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3143 }
3144
3145 static void
3146 ice_get_default_rss_key(uint8_t *rss_key, uint32_t rss_key_size)
3147 {
3148         static struct ice_aqc_get_set_rss_keys default_key;
3149         static bool default_key_done;
3150         uint8_t *key = (uint8_t *)&default_key;
3151         size_t i;
3152
3153         if (rss_key_size > sizeof(default_key)) {
3154                 PMD_DRV_LOG(WARNING,
3155                             "requested size %u is larger than default %zu, "
3156                             "only %zu bytes are gotten for key\n",
3157                             rss_key_size, sizeof(default_key),
3158                             sizeof(default_key));
3159         }
3160
3161         if (!default_key_done) {
3162                 /* Calculate the default hash key */
3163                 for (i = 0; i < sizeof(default_key); i++)
3164                         key[i] = (uint8_t)rte_rand();
3165                 default_key_done = true;
3166         }
3167         rte_memcpy(rss_key, key, RTE_MIN(rss_key_size, sizeof(default_key)));
3168 }
3169
3170 static int ice_init_rss(struct ice_pf *pf)
3171 {
3172         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3173         struct ice_vsi *vsi = pf->main_vsi;
3174         struct rte_eth_dev_data *dev_data = pf->dev_data;
3175         struct ice_aq_get_set_rss_lut_params lut_params;
3176         struct rte_eth_rss_conf *rss_conf;
3177         struct ice_aqc_get_set_rss_keys key;
3178         uint16_t i, nb_q;
3179         int ret = 0;
3180         bool is_safe_mode = pf->adapter->is_safe_mode;
3181         uint32_t reg;
3182
3183         rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf;
3184         nb_q = dev_data->nb_rx_queues;
3185         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3186         vsi->rss_lut_size = pf->hash_lut_size;
3187
3188         if (nb_q == 0) {
3189                 PMD_DRV_LOG(WARNING,
3190                         "RSS is not supported as rx queues number is zero\n");
3191                 return 0;
3192         }
3193
3194         if (is_safe_mode) {
3195                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3196                 return 0;
3197         }
3198
3199         if (!vsi->rss_key) {
3200                 vsi->rss_key = rte_zmalloc(NULL,
3201                                            vsi->rss_key_size, 0);
3202                 if (vsi->rss_key == NULL) {
3203                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3204                         return -ENOMEM;
3205                 }
3206         }
3207         if (!vsi->rss_lut) {
3208                 vsi->rss_lut = rte_zmalloc(NULL,
3209                                            vsi->rss_lut_size, 0);
3210                 if (vsi->rss_lut == NULL) {
3211                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3212                         rte_free(vsi->rss_key);
3213                         vsi->rss_key = NULL;
3214                         return -ENOMEM;
3215                 }
3216         }
3217         /* configure RSS key */
3218         if (!rss_conf->rss_key)
3219                 ice_get_default_rss_key(vsi->rss_key, vsi->rss_key_size);
3220         else
3221                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3222                            RTE_MIN(rss_conf->rss_key_len,
3223                                    vsi->rss_key_size));
3224
3225         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3226         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3227         if (ret)
3228                 goto out;
3229
3230         /* init RSS LUT table */
3231         for (i = 0; i < vsi->rss_lut_size; i++)
3232                 vsi->rss_lut[i] = i % nb_q;
3233
3234         lut_params.vsi_handle = vsi->idx;
3235         lut_params.lut_size = vsi->rss_lut_size;
3236         lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3237         lut_params.lut = vsi->rss_lut;
3238         lut_params.global_lut_id = 0;
3239         ret = ice_aq_set_rss_lut(hw, &lut_params);
3240         if (ret)
3241                 goto out;
3242
3243         /* Enable registers for symmetric_toeplitz function. */
3244         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3245         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3246                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3247         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3248
3249         /* RSS hash configuration */
3250         ice_rss_hash_set(pf, rss_conf->rss_hf);
3251
3252         return 0;
3253 out:
3254         rte_free(vsi->rss_key);
3255         vsi->rss_key = NULL;
3256         rte_free(vsi->rss_lut);
3257         vsi->rss_lut = NULL;
3258         return -EINVAL;
3259 }
3260
3261 static int
3262 ice_dev_configure(struct rte_eth_dev *dev)
3263 {
3264         struct ice_adapter *ad =
3265                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3266         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3267         int ret;
3268
3269         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3270          * bulk allocation or vector Rx preconditions we will reset it.
3271          */
3272         ad->rx_bulk_alloc_allowed = true;
3273         ad->tx_simple_allowed = true;
3274
3275         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3276                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3277
3278         if (dev->data->nb_rx_queues) {
3279                 ret = ice_init_rss(pf);
3280                 if (ret) {
3281                         PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3282                         return ret;
3283                 }
3284         }
3285
3286         return 0;
3287 }
3288
3289 static void
3290 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3291                        int base_queue, int nb_queue)
3292 {
3293         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3294         uint32_t val, val_tx;
3295         int i;
3296
3297         for (i = 0; i < nb_queue; i++) {
3298                 /*do actual bind*/
3299                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3300                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3301                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3302                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3303
3304                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3305                             base_queue + i, msix_vect);
3306                 /* set ITR0 value */
3307                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3308                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3309                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3310         }
3311 }
3312
3313 void
3314 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3315 {
3316         struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3317         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3318         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3319         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3320         uint16_t msix_vect = vsi->msix_intr;
3321         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3322         uint16_t queue_idx = 0;
3323         int record = 0;
3324         int i;
3325
3326         /* clear Rx/Tx queue interrupt */
3327         for (i = 0; i < vsi->nb_used_qps; i++) {
3328                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3329                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3330         }
3331
3332         /* PF bind interrupt */
3333         if (rte_intr_dp_is_en(intr_handle)) {
3334                 queue_idx = 0;
3335                 record = 1;
3336         }
3337
3338         for (i = 0; i < vsi->nb_used_qps; i++) {
3339                 if (nb_msix <= 1) {
3340                         if (!rte_intr_allow_others(intr_handle))
3341                                 msix_vect = ICE_MISC_VEC_ID;
3342
3343                         /* uio mapping all queue to one msix_vect */
3344                         __vsi_queues_bind_intr(vsi, msix_vect,
3345                                                vsi->base_queue + i,
3346                                                vsi->nb_used_qps - i);
3347
3348                         for (; !!record && i < vsi->nb_used_qps; i++)
3349                                 intr_handle->intr_vec[queue_idx + i] =
3350                                         msix_vect;
3351                         break;
3352                 }
3353
3354                 /* vfio 1:1 queue/msix_vect mapping */
3355                 __vsi_queues_bind_intr(vsi, msix_vect,
3356                                        vsi->base_queue + i, 1);
3357
3358                 if (!!record)
3359                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3360
3361                 msix_vect++;
3362                 nb_msix--;
3363         }
3364 }
3365
3366 void
3367 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3368 {
3369         struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3370         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3371         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3372         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3373         uint16_t msix_intr, i;
3374
3375         if (rte_intr_allow_others(intr_handle))
3376                 for (i = 0; i < vsi->nb_used_qps; i++) {
3377                         msix_intr = vsi->msix_intr + i;
3378                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3379                                       GLINT_DYN_CTL_INTENA_M |
3380                                       GLINT_DYN_CTL_CLEARPBA_M |
3381                                       GLINT_DYN_CTL_ITR_INDX_M |
3382                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3383                 }
3384         else
3385                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3386                               GLINT_DYN_CTL_INTENA_M |
3387                               GLINT_DYN_CTL_CLEARPBA_M |
3388                               GLINT_DYN_CTL_ITR_INDX_M |
3389                               GLINT_DYN_CTL_WB_ON_ITR_M);
3390 }
3391
3392 static int
3393 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3394 {
3395         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3396         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3397         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3398         struct ice_vsi *vsi = pf->main_vsi;
3399         uint32_t intr_vector = 0;
3400
3401         rte_intr_disable(intr_handle);
3402
3403         /* check and configure queue intr-vector mapping */
3404         if ((rte_intr_cap_multiple(intr_handle) ||
3405              !RTE_ETH_DEV_SRIOV(dev).active) &&
3406             dev->data->dev_conf.intr_conf.rxq != 0) {
3407                 intr_vector = dev->data->nb_rx_queues;
3408                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3409                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3410                                     ICE_MAX_INTR_QUEUE_NUM);
3411                         return -ENOTSUP;
3412                 }
3413                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3414                         return -1;
3415         }
3416
3417         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3418                 intr_handle->intr_vec =
3419                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3420                             0);
3421                 if (!intr_handle->intr_vec) {
3422                         PMD_DRV_LOG(ERR,
3423                                     "Failed to allocate %d rx_queues intr_vec",
3424                                     dev->data->nb_rx_queues);
3425                         return -ENOMEM;
3426                 }
3427         }
3428
3429         /* Map queues with MSIX interrupt */
3430         vsi->nb_used_qps = dev->data->nb_rx_queues;
3431         ice_vsi_queues_bind_intr(vsi);
3432
3433         /* Enable interrupts for all the queues */
3434         ice_vsi_enable_queues_intr(vsi);
3435
3436         rte_intr_enable(intr_handle);
3437
3438         return 0;
3439 }
3440
3441 static void
3442 ice_get_init_link_status(struct rte_eth_dev *dev)
3443 {
3444         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3446         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3447         struct ice_link_status link_status;
3448         int ret;
3449
3450         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3451                                    &link_status, NULL);
3452         if (ret != ICE_SUCCESS) {
3453                 PMD_DRV_LOG(ERR, "Failed to get link info");
3454                 pf->init_link_up = false;
3455                 return;
3456         }
3457
3458         if (link_status.link_info & ICE_AQ_LINK_UP)
3459                 pf->init_link_up = true;
3460 }
3461
3462 static int
3463 ice_pps_out_cfg(struct ice_hw *hw, int idx, int timer)
3464 {
3465         uint64_t current_time, start_time;
3466         uint32_t hi, lo, lo2, func, val;
3467
3468         lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3469         hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer));
3470         lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3471
3472         if (lo2 < lo) {
3473                 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3474                 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer));
3475         }
3476
3477         current_time = ((uint64_t)hi << 32) | lo;
3478
3479         start_time = (current_time + NSEC_PER_SEC) /
3480                         NSEC_PER_SEC * NSEC_PER_SEC;
3481         start_time = start_time - PPS_OUT_DELAY_NS;
3482
3483         func = 8 + idx + timer * 4;
3484         val = GLGEN_GPIO_CTL_PIN_DIR_M |
3485                 ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) &
3486                 GLGEN_GPIO_CTL_PIN_FUNC_M);
3487
3488         /* Write clkout with half of period value */
3489         ICE_WRITE_REG(hw, GLTSYN_CLKO(idx, timer), NSEC_PER_SEC / 2);
3490
3491         /* Write TARGET time register */
3492         ICE_WRITE_REG(hw, GLTSYN_TGT_L(idx, timer), start_time & 0xffffffff);
3493         ICE_WRITE_REG(hw, GLTSYN_TGT_H(idx, timer), start_time >> 32);
3494
3495         /* Write AUX_OUT register */
3496         ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(idx, timer),
3497                       GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M);
3498
3499         /* Write GPIO CTL register */
3500         ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(idx), val);
3501
3502         return 0;
3503 }
3504
3505 static int
3506 ice_dev_start(struct rte_eth_dev *dev)
3507 {
3508         struct rte_eth_dev_data *data = dev->data;
3509         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3511         struct ice_vsi *vsi = pf->main_vsi;
3512         struct ice_adapter *ad =
3513                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3514         uint16_t nb_rxq = 0;
3515         uint16_t nb_txq, i;
3516         uint16_t max_frame_size;
3517         int mask, ret;
3518         uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned;
3519         uint32_t pin_idx = ad->devargs.pin_idx;
3520
3521         /* program Tx queues' context in hardware */
3522         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3523                 ret = ice_tx_queue_start(dev, nb_txq);
3524                 if (ret) {
3525                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3526                         goto tx_err;
3527                 }
3528         }
3529
3530         /* program Rx queues' context in hardware*/
3531         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3532                 ret = ice_rx_queue_start(dev, nb_rxq);
3533                 if (ret) {
3534                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3535                         goto rx_err;
3536                 }
3537         }
3538
3539         ice_set_rx_function(dev);
3540         ice_set_tx_function(dev);
3541
3542         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3543                         ETH_VLAN_EXTEND_MASK;
3544         ret = ice_vlan_offload_set(dev, mask);
3545         if (ret) {
3546                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3547                 goto rx_err;
3548         }
3549
3550         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3551         if (ice_rxq_intr_setup(dev))
3552                 return -EIO;
3553
3554         /* Enable receiving broadcast packets and transmitting packets */
3555         ret = ice_set_vsi_promisc(hw, vsi->idx,
3556                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3557                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3558                                   0);
3559         if (ret != ICE_SUCCESS)
3560                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3561
3562         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3563                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3564                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3565                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3566                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3567                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3568                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3569                                      NULL);
3570         if (ret != ICE_SUCCESS)
3571                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3572
3573         ice_get_init_link_status(dev);
3574
3575         ice_dev_set_link_up(dev);
3576
3577         /* Call get_link_info aq commond to enable/disable LSE */
3578         ice_link_update(dev, 0);
3579
3580         pf->adapter_stopped = false;
3581
3582         /* Set the max frame size to default value*/
3583         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3584                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3585                 ICE_FRAME_SIZE_MAX;
3586
3587         /* Set the max frame size to HW*/
3588         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3589
3590         if (ad->devargs.pps_out_ena) {
3591                 ret = ice_pps_out_cfg(hw, pin_idx, timer);
3592                 if (ret) {
3593                         PMD_DRV_LOG(ERR, "Fail to configure 1pps out");
3594                         goto rx_err;
3595                 }
3596         }
3597
3598         return 0;
3599
3600         /* stop the started queues if failed to start all queues */
3601 rx_err:
3602         for (i = 0; i < nb_rxq; i++)
3603                 ice_rx_queue_stop(dev, i);
3604 tx_err:
3605         for (i = 0; i < nb_txq; i++)
3606                 ice_tx_queue_stop(dev, i);
3607
3608         return -EIO;
3609 }
3610
3611 static int
3612 ice_dev_reset(struct rte_eth_dev *dev)
3613 {
3614         int ret;
3615
3616         if (dev->data->sriov.active)
3617                 return -ENOTSUP;
3618
3619         ret = ice_dev_uninit(dev);
3620         if (ret) {
3621                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3622                 return -ENXIO;
3623         }
3624
3625         ret = ice_dev_init(dev);
3626         if (ret) {
3627                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3628                 return -ENXIO;
3629         }
3630
3631         return 0;
3632 }
3633
3634 static int
3635 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3636 {
3637         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3638         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639         struct ice_vsi *vsi = pf->main_vsi;
3640         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3641         bool is_safe_mode = pf->adapter->is_safe_mode;
3642         u64 phy_type_low;
3643         u64 phy_type_high;
3644
3645         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3646         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3647         dev_info->max_rx_queues = vsi->nb_qps;
3648         dev_info->max_tx_queues = vsi->nb_qps;
3649         dev_info->max_mac_addrs = vsi->max_macaddrs;
3650         dev_info->max_vfs = pci_dev->max_vfs;
3651         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3652         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3653
3654         dev_info->rx_offload_capa =
3655                 DEV_RX_OFFLOAD_VLAN_STRIP |
3656                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3657                 DEV_RX_OFFLOAD_KEEP_CRC |
3658                 DEV_RX_OFFLOAD_SCATTER |
3659                 DEV_RX_OFFLOAD_VLAN_FILTER;
3660         dev_info->tx_offload_capa =
3661                 DEV_TX_OFFLOAD_VLAN_INSERT |
3662                 DEV_TX_OFFLOAD_TCP_TSO |
3663                 DEV_TX_OFFLOAD_MULTI_SEGS |
3664                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3665         dev_info->flow_type_rss_offloads = 0;
3666
3667         if (!is_safe_mode) {
3668                 dev_info->rx_offload_capa |=
3669                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3670                         DEV_RX_OFFLOAD_UDP_CKSUM |
3671                         DEV_RX_OFFLOAD_TCP_CKSUM |
3672                         DEV_RX_OFFLOAD_QINQ_STRIP |
3673                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3674                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3675                         DEV_RX_OFFLOAD_RSS_HASH;
3676                 dev_info->tx_offload_capa |=
3677                         DEV_TX_OFFLOAD_QINQ_INSERT |
3678                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3679                         DEV_TX_OFFLOAD_UDP_CKSUM |
3680                         DEV_TX_OFFLOAD_TCP_CKSUM |
3681                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3682                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3683                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3684                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3685         }
3686
3687         dev_info->rx_queue_offload_capa = 0;
3688         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3689
3690         dev_info->reta_size = pf->hash_lut_size;
3691         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3692
3693         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3694                 .rx_thresh = {
3695                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3696                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3697                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3698                 },
3699                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3700                 .rx_drop_en = 0,
3701                 .offloads = 0,
3702         };
3703
3704         dev_info->default_txconf = (struct rte_eth_txconf) {
3705                 .tx_thresh = {
3706                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3707                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3708                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3709                 },
3710                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3711                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3712                 .offloads = 0,
3713         };
3714
3715         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3716                 .nb_max = ICE_MAX_RING_DESC,
3717                 .nb_min = ICE_MIN_RING_DESC,
3718                 .nb_align = ICE_ALIGN_RING_DESC,
3719         };
3720
3721         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3722                 .nb_max = ICE_MAX_RING_DESC,
3723                 .nb_min = ICE_MIN_RING_DESC,
3724                 .nb_align = ICE_ALIGN_RING_DESC,
3725         };
3726
3727         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3728                                ETH_LINK_SPEED_100M |
3729                                ETH_LINK_SPEED_1G |
3730                                ETH_LINK_SPEED_2_5G |
3731                                ETH_LINK_SPEED_5G |
3732                                ETH_LINK_SPEED_10G |
3733                                ETH_LINK_SPEED_20G |
3734                                ETH_LINK_SPEED_25G;
3735
3736         phy_type_low = hw->port_info->phy.phy_type_low;
3737         phy_type_high = hw->port_info->phy.phy_type_high;
3738
3739         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3740                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3741
3742         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3743                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3744                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3745
3746         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3747         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3748
3749         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3750         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3751         dev_info->default_rxportconf.nb_queues = 1;
3752         dev_info->default_txportconf.nb_queues = 1;
3753         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3754         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3755
3756         return 0;
3757 }
3758
3759 static inline int
3760 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3761                             struct rte_eth_link *link)
3762 {
3763         struct rte_eth_link *dst = link;
3764         struct rte_eth_link *src = &dev->data->dev_link;
3765
3766         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3767                                 *(uint64_t *)src) == 0)
3768                 return -1;
3769
3770         return 0;
3771 }
3772
3773 static inline int
3774 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3775                              struct rte_eth_link *link)
3776 {
3777         struct rte_eth_link *dst = &dev->data->dev_link;
3778         struct rte_eth_link *src = link;
3779
3780         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3781                                 *(uint64_t *)src) == 0)
3782                 return -1;
3783
3784         return 0;
3785 }
3786
3787 static int
3788 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3789 {
3790 #define CHECK_INTERVAL 100  /* 100ms */
3791 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3792         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3793         struct ice_link_status link_status;
3794         struct rte_eth_link link, old;
3795         int status;
3796         unsigned int rep_cnt = MAX_REPEAT_TIME;
3797         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3798
3799         memset(&link, 0, sizeof(link));
3800         memset(&old, 0, sizeof(old));
3801         memset(&link_status, 0, sizeof(link_status));
3802         ice_atomic_read_link_status(dev, &old);
3803
3804         do {
3805                 /* Get link status information from hardware */
3806                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3807                                               &link_status, NULL);
3808                 if (status != ICE_SUCCESS) {
3809                         link.link_speed = ETH_SPEED_NUM_100M;
3810                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3811                         PMD_DRV_LOG(ERR, "Failed to get link info");
3812                         goto out;
3813                 }
3814
3815                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3816                 if (!wait_to_complete || link.link_status)
3817                         break;
3818
3819                 rte_delay_ms(CHECK_INTERVAL);
3820         } while (--rep_cnt);
3821
3822         if (!link.link_status)
3823                 goto out;
3824
3825         /* Full-duplex operation at all supported speeds */
3826         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3827
3828         /* Parse the link status */
3829         switch (link_status.link_speed) {
3830         case ICE_AQ_LINK_SPEED_10MB:
3831                 link.link_speed = ETH_SPEED_NUM_10M;
3832                 break;
3833         case ICE_AQ_LINK_SPEED_100MB:
3834                 link.link_speed = ETH_SPEED_NUM_100M;
3835                 break;
3836         case ICE_AQ_LINK_SPEED_1000MB:
3837                 link.link_speed = ETH_SPEED_NUM_1G;
3838                 break;
3839         case ICE_AQ_LINK_SPEED_2500MB:
3840                 link.link_speed = ETH_SPEED_NUM_2_5G;
3841                 break;
3842         case ICE_AQ_LINK_SPEED_5GB:
3843                 link.link_speed = ETH_SPEED_NUM_5G;
3844                 break;
3845         case ICE_AQ_LINK_SPEED_10GB:
3846                 link.link_speed = ETH_SPEED_NUM_10G;
3847                 break;
3848         case ICE_AQ_LINK_SPEED_20GB:
3849                 link.link_speed = ETH_SPEED_NUM_20G;
3850                 break;
3851         case ICE_AQ_LINK_SPEED_25GB:
3852                 link.link_speed = ETH_SPEED_NUM_25G;
3853                 break;
3854         case ICE_AQ_LINK_SPEED_40GB:
3855                 link.link_speed = ETH_SPEED_NUM_40G;
3856                 break;
3857         case ICE_AQ_LINK_SPEED_50GB:
3858                 link.link_speed = ETH_SPEED_NUM_50G;
3859                 break;
3860         case ICE_AQ_LINK_SPEED_100GB:
3861                 link.link_speed = ETH_SPEED_NUM_100G;
3862                 break;
3863         case ICE_AQ_LINK_SPEED_UNKNOWN:
3864                 PMD_DRV_LOG(ERR, "Unknown link speed");
3865                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3866                 break;
3867         default:
3868                 PMD_DRV_LOG(ERR, "None link speed");
3869                 link.link_speed = ETH_SPEED_NUM_NONE;
3870                 break;
3871         }
3872
3873         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3874                               ETH_LINK_SPEED_FIXED);
3875
3876 out:
3877         ice_atomic_write_link_status(dev, &link);
3878         if (link.link_status == old.link_status)
3879                 return -1;
3880
3881         return 0;
3882 }
3883
3884 /* Force the physical link state by getting the current PHY capabilities from
3885  * hardware and setting the PHY config based on the determined capabilities. If
3886  * link changes, link event will be triggered because both the Enable Automatic
3887  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3888  */
3889 static enum ice_status
3890 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3891 {
3892         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3893         struct ice_aqc_get_phy_caps_data *pcaps;
3894         struct ice_port_info *pi;
3895         enum ice_status status;
3896
3897         if (!hw || !hw->port_info)
3898                 return ICE_ERR_PARAM;
3899
3900         pi = hw->port_info;
3901
3902         pcaps = (struct ice_aqc_get_phy_caps_data *)
3903                 ice_malloc(hw, sizeof(*pcaps));
3904         if (!pcaps)
3905                 return ICE_ERR_NO_MEMORY;
3906
3907         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3908                                      pcaps, NULL);
3909         if (status)
3910                 goto out;
3911
3912         /* No change in link */
3913         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3914             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3915                 goto out;
3916
3917         cfg.phy_type_low = pcaps->phy_type_low;
3918         cfg.phy_type_high = pcaps->phy_type_high;
3919         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3920         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3921         cfg.eee_cap = pcaps->eee_cap;
3922         cfg.eeer_value = pcaps->eeer_value;
3923         cfg.link_fec_opt = pcaps->link_fec_options;
3924         if (link_up)
3925                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3926         else
3927                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3928
3929         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3930
3931 out:
3932         ice_free(hw, pcaps);
3933         return status;
3934 }
3935
3936 static int
3937 ice_dev_set_link_up(struct rte_eth_dev *dev)
3938 {
3939         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3940
3941         return ice_force_phys_link_state(hw, true);
3942 }
3943
3944 static int
3945 ice_dev_set_link_down(struct rte_eth_dev *dev)
3946 {
3947         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3948
3949         return ice_force_phys_link_state(hw, false);
3950 }
3951
3952 static int
3953 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3954 {
3955         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3956         struct rte_eth_dev_data *dev_data = pf->dev_data;
3957         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3958
3959         /* check if mtu is within the allowed range */
3960         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3961                 return -EINVAL;
3962
3963         /* mtu setting is forbidden if port is start */
3964         if (dev_data->dev_started) {
3965                 PMD_DRV_LOG(ERR,
3966                             "port %d must be stopped before configuration",
3967                             dev_data->port_id);
3968                 return -EBUSY;
3969         }
3970
3971         if (frame_size > ICE_ETH_MAX_LEN)
3972                 dev_data->dev_conf.rxmode.offloads |=
3973                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3974         else
3975                 dev_data->dev_conf.rxmode.offloads &=
3976                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3977
3978         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3979
3980         return 0;
3981 }
3982
3983 static int ice_macaddr_set(struct rte_eth_dev *dev,
3984                            struct rte_ether_addr *mac_addr)
3985 {
3986         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3987         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3988         struct ice_vsi *vsi = pf->main_vsi;
3989         struct ice_mac_filter *f;
3990         uint8_t flags = 0;
3991         int ret;
3992
3993         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3994                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3995                 return -EINVAL;
3996         }
3997
3998         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3999                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
4000                         break;
4001         }
4002
4003         if (!f) {
4004                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
4005                 return -EIO;
4006         }
4007
4008         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
4009         if (ret != ICE_SUCCESS) {
4010                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
4011                 return -EIO;
4012         }
4013         ret = ice_add_mac_filter(vsi, mac_addr);
4014         if (ret != ICE_SUCCESS) {
4015                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
4016                 return -EIO;
4017         }
4018         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
4019
4020         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
4021         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
4022         if (ret != ICE_SUCCESS)
4023                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
4024
4025         return 0;
4026 }
4027
4028 /* Add a MAC address, and update filters */
4029 static int
4030 ice_macaddr_add(struct rte_eth_dev *dev,
4031                 struct rte_ether_addr *mac_addr,
4032                 __rte_unused uint32_t index,
4033                 __rte_unused uint32_t pool)
4034 {
4035         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4036         struct ice_vsi *vsi = pf->main_vsi;
4037         int ret;
4038
4039         ret = ice_add_mac_filter(vsi, mac_addr);
4040         if (ret != ICE_SUCCESS) {
4041                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
4042                 return -EINVAL;
4043         }
4044
4045         return ICE_SUCCESS;
4046 }
4047
4048 /* Remove a MAC address, and update filters */
4049 static void
4050 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4051 {
4052         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4053         struct ice_vsi *vsi = pf->main_vsi;
4054         struct rte_eth_dev_data *data = dev->data;
4055         struct rte_ether_addr *macaddr;
4056         int ret;
4057
4058         macaddr = &data->mac_addrs[index];
4059         ret = ice_remove_mac_filter(vsi, macaddr);
4060         if (ret) {
4061                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
4062                 return;
4063         }
4064 }
4065
4066 static int
4067 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4068 {
4069         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4070         struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
4071         struct ice_vsi *vsi = pf->main_vsi;
4072         int ret;
4073
4074         PMD_INIT_FUNC_TRACE();
4075
4076         /**
4077          * Vlan 0 is the generic filter for untagged packets
4078          * and can't be removed or added by user.
4079          */
4080         if (vlan_id == 0)
4081                 return 0;
4082
4083         if (on) {
4084                 ret = ice_add_vlan_filter(vsi, &vlan);
4085                 if (ret < 0) {
4086                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
4087                         return -EINVAL;
4088                 }
4089         } else {
4090                 ret = ice_remove_vlan_filter(vsi, &vlan);
4091                 if (ret < 0) {
4092                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
4093                         return -EINVAL;
4094                 }
4095         }
4096
4097         return 0;
4098 }
4099
4100 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
4101  * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
4102  * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
4103  * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
4104  *
4105  * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
4106  * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
4107  * traffic in SVM, since the VLAN TPID isn't part of filtering.
4108  *
4109  * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
4110  * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
4111  * part of filtering.
4112  */
4113 static int
4114 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
4115 {
4116         struct ice_vlan vlan;
4117         int err;
4118
4119         vlan = ICE_VLAN(0, 0);
4120         err = ice_add_vlan_filter(vsi, &vlan);
4121         if (err) {
4122                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
4123                 return err;
4124         }
4125
4126         /* in SVM both VLAN 0 filters are identical */
4127         if (!ice_is_dvm_ena(&vsi->adapter->hw))
4128                 return 0;
4129
4130         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4131         err = ice_add_vlan_filter(vsi, &vlan);
4132         if (err) {
4133                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
4134                 return err;
4135         }
4136
4137         return 0;
4138 }
4139
4140 /*
4141  * Delete the VLAN 0 filters in the same manner that they were added in
4142  * ice_vsi_add_vlan_zero.
4143  */
4144 static int
4145 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
4146 {
4147         struct ice_vlan vlan;
4148         int err;
4149
4150         vlan = ICE_VLAN(0, 0);
4151         err = ice_remove_vlan_filter(vsi, &vlan);
4152         if (err) {
4153                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
4154                 return err;
4155         }
4156
4157         /* in SVM both VLAN 0 filters are identical */
4158         if (!ice_is_dvm_ena(&vsi->adapter->hw))
4159                 return 0;
4160
4161         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4162         err = ice_remove_vlan_filter(vsi, &vlan);
4163         if (err) {
4164                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
4165                 return err;
4166         }
4167
4168         return 0;
4169 }
4170
4171 /* Configure vlan filter on or off */
4172 static int
4173 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4174 {
4175         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4176         struct ice_vsi_ctx ctxt;
4177         uint8_t sw_flags2;
4178         int ret = 0;
4179
4180         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4181
4182         if (on)
4183                 vsi->info.sw_flags2 |= sw_flags2;
4184         else
4185                 vsi->info.sw_flags2 &= ~sw_flags2;
4186
4187         vsi->info.sw_id = hw->port_info->sw_id;
4188         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4189         ctxt.info.valid_sections =
4190                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4191                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
4192         ctxt.vsi_num = vsi->vsi_id;
4193
4194         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4195         if (ret) {
4196                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4197                             on ? "enable" : "disable");
4198                 return -EINVAL;
4199         } else {
4200                 vsi->info.valid_sections |=
4201                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4202                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
4203         }
4204
4205         /* consist with other drivers, allow untagged packet when vlan filter on */
4206         if (on)
4207                 ret = ice_vsi_add_vlan_zero(vsi);
4208         else
4209                 ret = ice_vsi_del_vlan_zero(vsi);
4210
4211         return 0;
4212 }
4213
4214 /* Manage VLAN stripping for the VSI for Rx */
4215 static int
4216 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4217 {
4218         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4219         struct ice_vsi_ctx ctxt;
4220         enum ice_status status;
4221         int err = 0;
4222
4223         /* do not allow modifying VLAN stripping when a port VLAN is configured
4224          * on this VSI
4225          */
4226         if (vsi->info.port_based_inner_vlan)
4227                 return 0;
4228
4229         memset(&ctxt, 0, sizeof(ctxt));
4230
4231         if (ena)
4232                 /* Strip VLAN tag from Rx packet and put it in the desc */
4233                 ctxt.info.inner_vlan_flags =
4234                                         ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4235         else
4236                 /* Disable stripping. Leave tag in packet */
4237                 ctxt.info.inner_vlan_flags =
4238                                         ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4239
4240         /* Allow all packets untagged/tagged */
4241         ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4242
4243         ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4244
4245         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4246         if (status) {
4247                 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4248                             ena ? "enable" : "disable");
4249                 err = -EIO;
4250         } else {
4251                 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4252         }
4253
4254         return err;
4255 }
4256
4257 static int
4258 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4259 {
4260         return ice_vsi_manage_vlan_stripping(vsi, true);
4261 }
4262
4263 static int
4264 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4265 {
4266         return ice_vsi_manage_vlan_stripping(vsi, false);
4267 }
4268
4269 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4270 {
4271         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4272         struct ice_vsi_ctx ctxt;
4273         enum ice_status status;
4274         int err = 0;
4275
4276         /* do not allow modifying VLAN stripping when a port VLAN is configured
4277          * on this VSI
4278          */
4279         if (vsi->info.port_based_outer_vlan)
4280                 return 0;
4281
4282         memset(&ctxt, 0, sizeof(ctxt));
4283
4284         ctxt.info.valid_sections =
4285                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4286         /* clear current outer VLAN strip settings */
4287         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4288                 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4289         ctxt.info.outer_vlan_flags |=
4290                 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4291                  ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4292                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4293                  ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4294
4295         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4296         if (status) {
4297                 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4298                 err = -EIO;
4299         } else {
4300                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4301         }
4302
4303         return err;
4304 }
4305
4306 static int
4307 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4308 {
4309         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4310         struct ice_vsi_ctx ctxt;
4311         enum ice_status status;
4312         int err = 0;
4313
4314         if (vsi->info.port_based_outer_vlan)
4315                 return 0;
4316
4317         memset(&ctxt, 0, sizeof(ctxt));
4318
4319         ctxt.info.valid_sections =
4320                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4321         /* clear current outer VLAN strip settings */
4322         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4323                 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4324         ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4325                 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4326
4327         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4328         if (status) {
4329                 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4330                 err = -EIO;
4331         } else {
4332                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4333         }
4334
4335         return err;
4336 }
4337
4338 static int
4339 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4340 {
4341         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4342         int ret;
4343
4344         if (ice_is_dvm_ena(hw)) {
4345                 if (ena)
4346                         ret = ice_vsi_ena_outer_stripping(vsi);
4347                 else
4348                         ret = ice_vsi_dis_outer_stripping(vsi);
4349         } else {
4350                 if (ena)
4351                         ret = ice_vsi_ena_inner_stripping(vsi);
4352                 else
4353                         ret = ice_vsi_dis_inner_stripping(vsi);
4354         }
4355
4356         return ret;
4357 }
4358
4359 static int
4360 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4361 {
4362         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4363         struct ice_vsi *vsi = pf->main_vsi;
4364         struct rte_eth_rxmode *rxmode;
4365
4366         rxmode = &dev->data->dev_conf.rxmode;
4367         if (mask & ETH_VLAN_FILTER_MASK) {
4368                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4369                         ice_vsi_config_vlan_filter(vsi, true);
4370                 else
4371                         ice_vsi_config_vlan_filter(vsi, false);
4372         }
4373
4374         if (mask & ETH_VLAN_STRIP_MASK) {
4375                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4376                         ice_vsi_config_vlan_stripping(vsi, true);
4377                 else
4378                         ice_vsi_config_vlan_stripping(vsi, false);
4379         }
4380
4381         return 0;
4382 }
4383
4384 static int
4385 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4386 {
4387         struct ice_aq_get_set_rss_lut_params lut_params;
4388         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4389         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4390         int ret;
4391
4392         if (!lut)
4393                 return -EINVAL;
4394
4395         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4396                 lut_params.vsi_handle = vsi->idx;
4397                 lut_params.lut_size = lut_size;
4398                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4399                 lut_params.lut = lut;
4400                 lut_params.global_lut_id = 0;
4401                 ret = ice_aq_get_rss_lut(hw, &lut_params);
4402                 if (ret) {
4403                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4404                         return -EINVAL;
4405                 }
4406         } else {
4407                 uint64_t *lut_dw = (uint64_t *)lut;
4408                 uint16_t i, lut_size_dw = lut_size / 4;
4409
4410                 for (i = 0; i < lut_size_dw; i++)
4411                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4412         }
4413
4414         return 0;
4415 }
4416
4417 static int
4418 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4419 {
4420         struct ice_aq_get_set_rss_lut_params lut_params;
4421         struct ice_pf *pf;
4422         struct ice_hw *hw;
4423         int ret;
4424
4425         if (!vsi || !lut)
4426                 return -EINVAL;
4427
4428         pf = ICE_VSI_TO_PF(vsi);
4429         hw = ICE_VSI_TO_HW(vsi);
4430
4431         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4432                 lut_params.vsi_handle = vsi->idx;
4433                 lut_params.lut_size = lut_size;
4434                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4435                 lut_params.lut = lut;
4436                 lut_params.global_lut_id = 0;
4437                 ret = ice_aq_set_rss_lut(hw, &lut_params);
4438                 if (ret) {
4439                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4440                         return -EINVAL;
4441                 }
4442         } else {
4443                 uint64_t *lut_dw = (uint64_t *)lut;
4444                 uint16_t i, lut_size_dw = lut_size / 4;
4445
4446                 for (i = 0; i < lut_size_dw; i++)
4447                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4448
4449                 ice_flush(hw);
4450         }
4451
4452         return 0;
4453 }
4454
4455 static int
4456 ice_rss_reta_update(struct rte_eth_dev *dev,
4457                     struct rte_eth_rss_reta_entry64 *reta_conf,
4458                     uint16_t reta_size)
4459 {
4460         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4461         uint16_t i, lut_size = pf->hash_lut_size;
4462         uint16_t idx, shift;
4463         uint8_t *lut;
4464         int ret;
4465
4466         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4467             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4468             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4469                 PMD_DRV_LOG(ERR,
4470                             "The size of hash lookup table configured (%d)"
4471                             "doesn't match the number hardware can "
4472                             "supported (128, 512, 2048)",
4473                             reta_size);
4474                 return -EINVAL;
4475         }
4476
4477         /* It MUST use the current LUT size to get the RSS lookup table,
4478          * otherwise if will fail with -100 error code.
4479          */
4480         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4481         if (!lut) {
4482                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4483                 return -ENOMEM;
4484         }
4485         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4486         if (ret)
4487                 goto out;
4488
4489         for (i = 0; i < reta_size; i++) {
4490                 idx = i / RTE_RETA_GROUP_SIZE;
4491                 shift = i % RTE_RETA_GROUP_SIZE;
4492                 if (reta_conf[idx].mask & (1ULL << shift))
4493                         lut[i] = reta_conf[idx].reta[shift];
4494         }
4495         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4496         if (ret == 0 && lut_size != reta_size) {
4497                 PMD_DRV_LOG(INFO,
4498                             "The size of hash lookup table is changed from (%d) to (%d)",
4499                             lut_size, reta_size);
4500                 pf->hash_lut_size = reta_size;
4501         }
4502
4503 out:
4504         rte_free(lut);
4505
4506         return ret;
4507 }
4508
4509 static int
4510 ice_rss_reta_query(struct rte_eth_dev *dev,
4511                    struct rte_eth_rss_reta_entry64 *reta_conf,
4512                    uint16_t reta_size)
4513 {
4514         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4515         uint16_t i, lut_size = pf->hash_lut_size;
4516         uint16_t idx, shift;
4517         uint8_t *lut;
4518         int ret;
4519
4520         if (reta_size != lut_size) {
4521                 PMD_DRV_LOG(ERR,
4522                             "The size of hash lookup table configured (%d)"
4523                             "doesn't match the number hardware can "
4524                             "supported (%d)",
4525                             reta_size, lut_size);
4526                 return -EINVAL;
4527         }
4528
4529         lut = rte_zmalloc(NULL, reta_size, 0);
4530         if (!lut) {
4531                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4532                 return -ENOMEM;
4533         }
4534
4535         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4536         if (ret)
4537                 goto out;
4538
4539         for (i = 0; i < reta_size; i++) {
4540                 idx = i / RTE_RETA_GROUP_SIZE;
4541                 shift = i % RTE_RETA_GROUP_SIZE;
4542                 if (reta_conf[idx].mask & (1ULL << shift))
4543                         reta_conf[idx].reta[shift] = lut[i];
4544         }
4545
4546 out:
4547         rte_free(lut);
4548
4549         return ret;
4550 }
4551
4552 static int
4553 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4554 {
4555         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4556         int ret = 0;
4557
4558         if (!key || key_len == 0) {
4559                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4560                 return 0;
4561         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4562                    sizeof(uint32_t)) {
4563                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4564                 return -EINVAL;
4565         }
4566
4567         struct ice_aqc_get_set_rss_keys *key_dw =
4568                 (struct ice_aqc_get_set_rss_keys *)key;
4569
4570         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4571         if (ret) {
4572                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4573                 ret = -EINVAL;
4574         }
4575
4576         return ret;
4577 }
4578
4579 static int
4580 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4581 {
4582         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4583         int ret;
4584
4585         if (!key || !key_len)
4586                 return -EINVAL;
4587
4588         ret = ice_aq_get_rss_key
4589                 (hw, vsi->idx,
4590                  (struct ice_aqc_get_set_rss_keys *)key);
4591         if (ret) {
4592                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4593                 return -EINVAL;
4594         }
4595         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4596
4597         return 0;
4598 }
4599
4600 static int
4601 ice_rss_hash_update(struct rte_eth_dev *dev,
4602                     struct rte_eth_rss_conf *rss_conf)
4603 {
4604         enum ice_status status = ICE_SUCCESS;
4605         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4606         struct ice_vsi *vsi = pf->main_vsi;
4607
4608         /* set hash key */
4609         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4610         if (status)
4611                 return status;
4612
4613         if (rss_conf->rss_hf == 0) {
4614                 pf->rss_hf = 0;
4615                 return 0;
4616         }
4617
4618         /* RSS hash configuration */
4619         ice_rss_hash_set(pf, rss_conf->rss_hf);
4620
4621         return 0;
4622 }
4623
4624 static int
4625 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4626                       struct rte_eth_rss_conf *rss_conf)
4627 {
4628         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4629         struct ice_vsi *vsi = pf->main_vsi;
4630
4631         ice_get_rss_key(vsi, rss_conf->rss_key,
4632                         &rss_conf->rss_key_len);
4633
4634         rss_conf->rss_hf = pf->rss_hf;
4635         return 0;
4636 }
4637
4638 static int
4639 ice_promisc_enable(struct rte_eth_dev *dev)
4640 {
4641         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4642         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4643         struct ice_vsi *vsi = pf->main_vsi;
4644         enum ice_status status;
4645         uint8_t pmask;
4646         int ret = 0;
4647
4648         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4649                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4650
4651         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4652         switch (status) {
4653         case ICE_ERR_ALREADY_EXISTS:
4654                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4655         case ICE_SUCCESS:
4656                 break;
4657         default:
4658                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4659                 ret = -EAGAIN;
4660         }
4661
4662         return ret;
4663 }
4664
4665 static int
4666 ice_promisc_disable(struct rte_eth_dev *dev)
4667 {
4668         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4669         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4670         struct ice_vsi *vsi = pf->main_vsi;
4671         enum ice_status status;
4672         uint8_t pmask;
4673         int ret = 0;
4674
4675         if (dev->data->all_multicast == 1)
4676                 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX;
4677         else
4678                 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4679                         ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4680
4681         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4682         if (status != ICE_SUCCESS) {
4683                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4684                 ret = -EAGAIN;
4685         }
4686
4687         return ret;
4688 }
4689
4690 static int
4691 ice_allmulti_enable(struct rte_eth_dev *dev)
4692 {
4693         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4694         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695         struct ice_vsi *vsi = pf->main_vsi;
4696         enum ice_status status;
4697         uint8_t pmask;
4698         int ret = 0;
4699
4700         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4701
4702         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4703
4704         switch (status) {
4705         case ICE_ERR_ALREADY_EXISTS:
4706                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4707         case ICE_SUCCESS:
4708                 break;
4709         default:
4710                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4711                 ret = -EAGAIN;
4712         }
4713
4714         return ret;
4715 }
4716
4717 static int
4718 ice_allmulti_disable(struct rte_eth_dev *dev)
4719 {
4720         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4721         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4722         struct ice_vsi *vsi = pf->main_vsi;
4723         enum ice_status status;
4724         uint8_t pmask;
4725         int ret = 0;
4726
4727         if (dev->data->promiscuous == 1)
4728                 return 0; /* must remain in all_multicast mode */
4729
4730         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4731
4732         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4733         if (status != ICE_SUCCESS) {
4734                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4735                 ret = -EAGAIN;
4736         }
4737
4738         return ret;
4739 }
4740
4741 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4742                                     uint16_t queue_id)
4743 {
4744         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4745         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4746         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4747         uint32_t val;
4748         uint16_t msix_intr;
4749
4750         msix_intr = intr_handle->intr_vec[queue_id];
4751
4752         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4753               GLINT_DYN_CTL_ITR_INDX_M;
4754         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4755
4756         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4757         rte_intr_ack(&pci_dev->intr_handle);
4758
4759         return 0;
4760 }
4761
4762 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4763                                      uint16_t queue_id)
4764 {
4765         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4766         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4767         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4768         uint16_t msix_intr;
4769
4770         msix_intr = intr_handle->intr_vec[queue_id];
4771
4772         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4773
4774         return 0;
4775 }
4776
4777 static int
4778 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4779 {
4780         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4781         u8 ver, patch;
4782         u16 build;
4783         int ret;
4784
4785         ver = hw->flash.orom.major;
4786         patch = hw->flash.orom.patch;
4787         build = hw->flash.orom.build;
4788
4789         ret = snprintf(fw_version, fw_size,
4790                         "%x.%02x 0x%08x %d.%d.%d",
4791                         hw->flash.nvm.major,
4792                         hw->flash.nvm.minor,
4793                         hw->flash.nvm.eetrack,
4794                         ver, build, patch);
4795         if (ret < 0)
4796                 return -EINVAL;
4797
4798         /* add the size of '\0' */
4799         ret += 1;
4800         if (fw_size < (size_t)ret)
4801                 return ret;
4802         else
4803                 return 0;
4804 }
4805
4806 static int
4807 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4808 {
4809         struct ice_hw *hw;
4810         struct ice_vsi_ctx ctxt;
4811         uint8_t vlan_flags = 0;
4812         int ret;
4813
4814         if (!vsi || !info) {
4815                 PMD_DRV_LOG(ERR, "invalid parameters");
4816                 return -EINVAL;
4817         }
4818
4819         if (info->on) {
4820                 vsi->info.port_based_inner_vlan = info->config.pvid;
4821                 /**
4822                  * If insert pvid is enabled, only tagged pkts are
4823                  * allowed to be sent out.
4824                  */
4825                 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4826                              ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4827         } else {
4828                 vsi->info.port_based_inner_vlan = 0;
4829                 if (info->config.reject.tagged == 0)
4830                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4831
4832                 if (info->config.reject.untagged == 0)
4833                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4834         }
4835         vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4836                                   ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4837         vsi->info.inner_vlan_flags |= vlan_flags;
4838         memset(&ctxt, 0, sizeof(ctxt));
4839         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4840         ctxt.info.valid_sections =
4841                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4842         ctxt.vsi_num = vsi->vsi_id;
4843
4844         hw = ICE_VSI_TO_HW(vsi);
4845         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4846         if (ret != ICE_SUCCESS) {
4847                 PMD_DRV_LOG(ERR,
4848                             "update VSI for VLAN insert failed, err %d",
4849                             ret);
4850                 return -EINVAL;
4851         }
4852
4853         vsi->info.valid_sections |=
4854                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4855
4856         return ret;
4857 }
4858
4859 static int
4860 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4861 {
4862         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4863         struct ice_vsi *vsi = pf->main_vsi;
4864         struct rte_eth_dev_data *data = pf->dev_data;
4865         struct ice_vsi_vlan_pvid_info info;
4866         int ret;
4867
4868         memset(&info, 0, sizeof(info));
4869         info.on = on;
4870         if (info.on) {
4871                 info.config.pvid = pvid;
4872         } else {
4873                 info.config.reject.tagged =
4874                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4875                 info.config.reject.untagged =
4876                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4877         }
4878
4879         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4880         if (ret < 0) {
4881                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4882                 return -EINVAL;
4883         }
4884
4885         return 0;
4886 }
4887
4888 static int
4889 ice_get_eeprom_length(struct rte_eth_dev *dev)
4890 {
4891         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4892
4893         return hw->flash.flash_size;
4894 }
4895
4896 static int
4897 ice_get_eeprom(struct rte_eth_dev *dev,
4898                struct rte_dev_eeprom_info *eeprom)
4899 {
4900         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4901         enum ice_status status = ICE_SUCCESS;
4902         uint8_t *data = eeprom->data;
4903
4904         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4905
4906         status = ice_acquire_nvm(hw, ICE_RES_READ);
4907         if (status) {
4908                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4909                 return -EIO;
4910         }
4911
4912         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4913                                    data, false);
4914
4915         ice_release_nvm(hw);
4916
4917         if (status) {
4918                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4919                 return -EIO;
4920         }
4921
4922         return 0;
4923 }
4924
4925 static void
4926 ice_stat_update_32(struct ice_hw *hw,
4927                    uint32_t reg,
4928                    bool offset_loaded,
4929                    uint64_t *offset,
4930                    uint64_t *stat)
4931 {
4932         uint64_t new_data;
4933
4934         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4935         if (!offset_loaded)
4936                 *offset = new_data;
4937
4938         if (new_data >= *offset)
4939                 *stat = (uint64_t)(new_data - *offset);
4940         else
4941                 *stat = (uint64_t)((new_data +
4942                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4943                                    - *offset);
4944 }
4945
4946 static void
4947 ice_stat_update_40(struct ice_hw *hw,
4948                    uint32_t hireg,
4949                    uint32_t loreg,
4950                    bool offset_loaded,
4951                    uint64_t *offset,
4952                    uint64_t *stat)
4953 {
4954         uint64_t new_data;
4955
4956         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4957         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4958                     ICE_32_BIT_WIDTH;
4959
4960         if (!offset_loaded)
4961                 *offset = new_data;
4962
4963         if (new_data >= *offset)
4964                 *stat = new_data - *offset;
4965         else
4966                 *stat = (uint64_t)((new_data +
4967                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4968                                    *offset);
4969
4970         *stat &= ICE_40_BIT_MASK;
4971 }
4972
4973 /* Get all the statistics of a VSI */
4974 static void
4975 ice_update_vsi_stats(struct ice_vsi *vsi)
4976 {
4977         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4978         struct ice_eth_stats *nes = &vsi->eth_stats;
4979         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4980         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4981
4982         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4983                            vsi->offset_loaded, &oes->rx_bytes,
4984                            &nes->rx_bytes);
4985         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4986                            vsi->offset_loaded, &oes->rx_unicast,
4987                            &nes->rx_unicast);
4988         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4989                            vsi->offset_loaded, &oes->rx_multicast,
4990                            &nes->rx_multicast);
4991         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4992                            vsi->offset_loaded, &oes->rx_broadcast,
4993                            &nes->rx_broadcast);
4994         /* enlarge the limitation when rx_bytes overflowed */
4995         if (vsi->offset_loaded) {
4996                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4997                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4998                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4999         }
5000         vsi->old_rx_bytes = nes->rx_bytes;
5001         /* exclude CRC bytes */
5002         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
5003                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
5004
5005         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
5006                            &oes->rx_discards, &nes->rx_discards);
5007         /* GLV_REPC not supported */
5008         /* GLV_RMPC not supported */
5009         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
5010                            &oes->rx_unknown_protocol,
5011                            &nes->rx_unknown_protocol);
5012         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
5013                            vsi->offset_loaded, &oes->tx_bytes,
5014                            &nes->tx_bytes);
5015         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
5016                            vsi->offset_loaded, &oes->tx_unicast,
5017                            &nes->tx_unicast);
5018         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
5019                            vsi->offset_loaded, &oes->tx_multicast,
5020                            &nes->tx_multicast);
5021         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
5022                            vsi->offset_loaded,  &oes->tx_broadcast,
5023                            &nes->tx_broadcast);
5024         /* GLV_TDPC not supported */
5025         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
5026                            &oes->tx_errors, &nes->tx_errors);
5027         /* enlarge the limitation when tx_bytes overflowed */
5028         if (vsi->offset_loaded) {
5029                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
5030                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5031                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
5032         }
5033         vsi->old_tx_bytes = nes->tx_bytes;
5034         vsi->offset_loaded = true;
5035
5036         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
5037                     vsi->vsi_id);
5038         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
5039         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
5040         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
5041         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
5042         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
5043         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5044                     nes->rx_unknown_protocol);
5045         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
5046         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
5047         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
5048         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
5049         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
5050         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
5051         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
5052                     vsi->vsi_id);
5053 }
5054
5055 static void
5056 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
5057 {
5058         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5059         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
5060
5061         /* Get statistics of struct ice_eth_stats */
5062         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
5063                            GLPRT_GORCL(hw->port_info->lport),
5064                            pf->offset_loaded, &os->eth.rx_bytes,
5065                            &ns->eth.rx_bytes);
5066         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
5067                            GLPRT_UPRCL(hw->port_info->lport),
5068                            pf->offset_loaded, &os->eth.rx_unicast,
5069                            &ns->eth.rx_unicast);
5070         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
5071                            GLPRT_MPRCL(hw->port_info->lport),
5072                            pf->offset_loaded, &os->eth.rx_multicast,
5073                            &ns->eth.rx_multicast);
5074         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
5075                            GLPRT_BPRCL(hw->port_info->lport),
5076                            pf->offset_loaded, &os->eth.rx_broadcast,
5077                            &ns->eth.rx_broadcast);
5078         ice_stat_update_32(hw, PRTRPB_RDPC,
5079                            pf->offset_loaded, &os->eth.rx_discards,
5080                            &ns->eth.rx_discards);
5081         /* enlarge the limitation when rx_bytes overflowed */
5082         if (pf->offset_loaded) {
5083                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
5084                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5085                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
5086         }
5087         pf->old_rx_bytes = ns->eth.rx_bytes;
5088
5089         /* Workaround: CRC size should not be included in byte statistics,
5090          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
5091          * packet.
5092          */
5093         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
5094                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
5095
5096         /* GLPRT_REPC not supported */
5097         /* GLPRT_RMPC not supported */
5098         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
5099                            pf->offset_loaded,
5100                            &os->eth.rx_unknown_protocol,
5101                            &ns->eth.rx_unknown_protocol);
5102         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
5103                            GLPRT_GOTCL(hw->port_info->lport),
5104                            pf->offset_loaded, &os->eth.tx_bytes,
5105                            &ns->eth.tx_bytes);
5106         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
5107                            GLPRT_UPTCL(hw->port_info->lport),
5108                            pf->offset_loaded, &os->eth.tx_unicast,
5109                            &ns->eth.tx_unicast);
5110         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
5111                            GLPRT_MPTCL(hw->port_info->lport),
5112                            pf->offset_loaded, &os->eth.tx_multicast,
5113                            &ns->eth.tx_multicast);
5114         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
5115                            GLPRT_BPTCL(hw->port_info->lport),
5116                            pf->offset_loaded, &os->eth.tx_broadcast,
5117                            &ns->eth.tx_broadcast);
5118         /* enlarge the limitation when tx_bytes overflowed */
5119         if (pf->offset_loaded) {
5120                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
5121                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5122                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
5123         }
5124         pf->old_tx_bytes = ns->eth.tx_bytes;
5125         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
5126                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
5127
5128         /* GLPRT_TEPC not supported */
5129
5130         /* additional port specific stats */
5131         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
5132                            pf->offset_loaded, &os->tx_dropped_link_down,
5133                            &ns->tx_dropped_link_down);
5134         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
5135                            pf->offset_loaded, &os->crc_errors,
5136                            &ns->crc_errors);
5137         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
5138                            pf->offset_loaded, &os->illegal_bytes,
5139                            &ns->illegal_bytes);
5140         /* GLPRT_ERRBC not supported */
5141         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
5142                            pf->offset_loaded, &os->mac_local_faults,
5143                            &ns->mac_local_faults);
5144         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
5145                            pf->offset_loaded, &os->mac_remote_faults,
5146                            &ns->mac_remote_faults);
5147
5148         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
5149                            pf->offset_loaded, &os->rx_len_errors,
5150                            &ns->rx_len_errors);
5151
5152         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
5153                            pf->offset_loaded, &os->link_xon_rx,
5154                            &ns->link_xon_rx);
5155         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
5156                            pf->offset_loaded, &os->link_xoff_rx,
5157                            &ns->link_xoff_rx);
5158         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
5159                            pf->offset_loaded, &os->link_xon_tx,
5160                            &ns->link_xon_tx);
5161         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
5162                            pf->offset_loaded, &os->link_xoff_tx,
5163                            &ns->link_xoff_tx);
5164         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
5165                            GLPRT_PRC64L(hw->port_info->lport),
5166                            pf->offset_loaded, &os->rx_size_64,
5167                            &ns->rx_size_64);
5168         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
5169                            GLPRT_PRC127L(hw->port_info->lport),
5170                            pf->offset_loaded, &os->rx_size_127,
5171                            &ns->rx_size_127);
5172         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
5173                            GLPRT_PRC255L(hw->port_info->lport),
5174                            pf->offset_loaded, &os->rx_size_255,
5175                            &ns->rx_size_255);
5176         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
5177                            GLPRT_PRC511L(hw->port_info->lport),
5178                            pf->offset_loaded, &os->rx_size_511,
5179                            &ns->rx_size_511);
5180         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
5181                            GLPRT_PRC1023L(hw->port_info->lport),
5182                            pf->offset_loaded, &os->rx_size_1023,
5183                            &ns->rx_size_1023);
5184         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
5185                            GLPRT_PRC1522L(hw->port_info->lport),
5186                            pf->offset_loaded, &os->rx_size_1522,
5187                            &ns->rx_size_1522);
5188         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
5189                            GLPRT_PRC9522L(hw->port_info->lport),
5190                            pf->offset_loaded, &os->rx_size_big,
5191                            &ns->rx_size_big);
5192         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
5193                            pf->offset_loaded, &os->rx_undersize,
5194                            &ns->rx_undersize);
5195         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
5196                            pf->offset_loaded, &os->rx_fragments,
5197                            &ns->rx_fragments);
5198         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5199                            pf->offset_loaded, &os->rx_oversize,
5200                            &ns->rx_oversize);
5201         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5202                            pf->offset_loaded, &os->rx_jabber,
5203                            &ns->rx_jabber);
5204         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5205                            GLPRT_PTC64L(hw->port_info->lport),
5206                            pf->offset_loaded, &os->tx_size_64,
5207                            &ns->tx_size_64);
5208         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5209                            GLPRT_PTC127L(hw->port_info->lport),
5210                            pf->offset_loaded, &os->tx_size_127,
5211                            &ns->tx_size_127);
5212         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5213                            GLPRT_PTC255L(hw->port_info->lport),
5214                            pf->offset_loaded, &os->tx_size_255,
5215                            &ns->tx_size_255);
5216         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5217                            GLPRT_PTC511L(hw->port_info->lport),
5218                            pf->offset_loaded, &os->tx_size_511,
5219                            &ns->tx_size_511);
5220         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5221                            GLPRT_PTC1023L(hw->port_info->lport),
5222                            pf->offset_loaded, &os->tx_size_1023,
5223                            &ns->tx_size_1023);
5224         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5225                            GLPRT_PTC1522L(hw->port_info->lport),
5226                            pf->offset_loaded, &os->tx_size_1522,
5227                            &ns->tx_size_1522);
5228         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5229                            GLPRT_PTC9522L(hw->port_info->lport),
5230                            pf->offset_loaded, &os->tx_size_big,
5231                            &ns->tx_size_big);
5232
5233         /* GLPRT_MSPDC not supported */
5234         /* GLPRT_XEC not supported */
5235
5236         pf->offset_loaded = true;
5237
5238         if (pf->main_vsi)
5239                 ice_update_vsi_stats(pf->main_vsi);
5240 }
5241
5242 /* Get all statistics of a port */
5243 static int
5244 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5245 {
5246         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5247         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5248         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5249
5250         /* call read registers - updates values, now write them to struct */
5251         ice_read_stats_registers(pf, hw);
5252
5253         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5254                           pf->main_vsi->eth_stats.rx_multicast +
5255                           pf->main_vsi->eth_stats.rx_broadcast -
5256                           pf->main_vsi->eth_stats.rx_discards;
5257         stats->opackets = ns->eth.tx_unicast +
5258                           ns->eth.tx_multicast +
5259                           ns->eth.tx_broadcast;
5260         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
5261         stats->obytes   = ns->eth.tx_bytes;
5262         stats->oerrors  = ns->eth.tx_errors +
5263                           pf->main_vsi->eth_stats.tx_errors;
5264
5265         /* Rx Errors */
5266         stats->imissed  = ns->eth.rx_discards +
5267                           pf->main_vsi->eth_stats.rx_discards;
5268         stats->ierrors  = ns->crc_errors +
5269                           ns->rx_undersize +
5270                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5271
5272         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5273         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
5274         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5275         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5276         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5277         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5278         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5279                     pf->main_vsi->eth_stats.rx_discards);
5280         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
5281                     ns->eth.rx_unknown_protocol);
5282         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
5283         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5284         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5285         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5286         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5287         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5288                     pf->main_vsi->eth_stats.tx_discards);
5289         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
5290
5291         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
5292                     ns->tx_dropped_link_down);
5293         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5294         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
5295                     ns->illegal_bytes);
5296         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
5297         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
5298                     ns->mac_local_faults);
5299         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
5300                     ns->mac_remote_faults);
5301         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
5302         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
5303         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
5304         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
5305         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
5306         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
5307         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
5308         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
5309         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
5310         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
5311         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
5312         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
5313         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
5314         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
5315         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
5316         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
5317         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
5318         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
5319         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
5320         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
5321         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
5322         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
5323         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
5324         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5325         return 0;
5326 }
5327
5328 /* Reset the statistics */
5329 static int
5330 ice_stats_reset(struct rte_eth_dev *dev)
5331 {
5332         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5333         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5334
5335         /* Mark PF and VSI stats to update the offset, aka "reset" */
5336         pf->offset_loaded = false;
5337         if (pf->main_vsi)
5338                 pf->main_vsi->offset_loaded = false;
5339
5340         /* read the stats, reading current register values into offset */
5341         ice_read_stats_registers(pf, hw);
5342
5343         return 0;
5344 }
5345
5346 static uint32_t
5347 ice_xstats_calc_num(void)
5348 {
5349         uint32_t num;
5350
5351         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5352
5353         return num;
5354 }
5355
5356 static int
5357 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5358                unsigned int n)
5359 {
5360         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5361         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5362         unsigned int i;
5363         unsigned int count;
5364         struct ice_hw_port_stats *hw_stats = &pf->stats;
5365
5366         count = ice_xstats_calc_num();
5367         if (n < count)
5368                 return count;
5369
5370         ice_read_stats_registers(pf, hw);
5371
5372         if (!xstats)
5373                 return 0;
5374
5375         count = 0;
5376
5377         /* Get stats from ice_eth_stats struct */
5378         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5379                 xstats[count].value =
5380                         *(uint64_t *)((char *)&hw_stats->eth +
5381                                       ice_stats_strings[i].offset);
5382                 xstats[count].id = count;
5383                 count++;
5384         }
5385
5386         /* Get individiual stats from ice_hw_port struct */
5387         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5388                 xstats[count].value =
5389                         *(uint64_t *)((char *)hw_stats +
5390                                       ice_hw_port_strings[i].offset);
5391                 xstats[count].id = count;
5392                 count++;
5393         }
5394
5395         return count;
5396 }
5397
5398 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5399                                 struct rte_eth_xstat_name *xstats_names,
5400                                 __rte_unused unsigned int limit)
5401 {
5402         unsigned int count = 0;
5403         unsigned int i;
5404
5405         if (!xstats_names)
5406                 return ice_xstats_calc_num();
5407
5408         /* Note: limit checked in rte_eth_xstats_names() */
5409
5410         /* Get stats from ice_eth_stats struct */
5411         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5412                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5413                         sizeof(xstats_names[count].name));
5414                 count++;
5415         }
5416
5417         /* Get individiual stats from ice_hw_port struct */
5418         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5419                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5420                         sizeof(xstats_names[count].name));
5421                 count++;
5422         }
5423
5424         return count;
5425 }
5426
5427 static int
5428 ice_dev_flow_ops_get(struct rte_eth_dev *dev,
5429                      const struct rte_flow_ops **ops)
5430 {
5431         if (!dev)
5432                 return -EINVAL;
5433
5434         *ops = &ice_flow_ops;
5435         return 0;
5436 }
5437
5438 /* Add UDP tunneling port */
5439 static int
5440 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5441                              struct rte_eth_udp_tunnel *udp_tunnel)
5442 {
5443         int ret = 0;
5444         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5445
5446         if (udp_tunnel == NULL)
5447                 return -EINVAL;
5448
5449         switch (udp_tunnel->prot_type) {
5450         case RTE_TUNNEL_TYPE_VXLAN:
5451                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5452                 break;
5453         default:
5454                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5455                 ret = -EINVAL;
5456                 break;
5457         }
5458
5459         return ret;
5460 }
5461
5462 /* Delete UDP tunneling port */
5463 static int
5464 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5465                              struct rte_eth_udp_tunnel *udp_tunnel)
5466 {
5467         int ret = 0;
5468         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5469
5470         if (udp_tunnel == NULL)
5471                 return -EINVAL;
5472
5473         switch (udp_tunnel->prot_type) {
5474         case RTE_TUNNEL_TYPE_VXLAN:
5475                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5476                 break;
5477         default:
5478                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5479                 ret = -EINVAL;
5480                 break;
5481         }
5482
5483         return ret;
5484 }
5485
5486 static int
5487 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5488               struct rte_pci_device *pci_dev)
5489 {
5490         return rte_eth_dev_pci_generic_probe(pci_dev,
5491                                              sizeof(struct ice_adapter),
5492                                              ice_dev_init);
5493 }
5494
5495 static int
5496 ice_pci_remove(struct rte_pci_device *pci_dev)
5497 {
5498         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5499 }
5500
5501 static struct rte_pci_driver rte_ice_pmd = {
5502         .id_table = pci_id_ice_map,
5503         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5504         .probe = ice_pci_probe,
5505         .remove = ice_pci_remove,
5506 };
5507
5508 /**
5509  * Driver initialization routine.
5510  * Invoked once at EAL init time.
5511  * Register itself as the [Poll Mode] Driver of PCI devices.
5512  */
5513 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5514 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5515 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5516 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5517                               ICE_HW_DEBUG_MASK_ARG "=0xXXX"
5518                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5519                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5520                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5521
5522 RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE);
5523 RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE);
5524 #ifdef RTE_ETHDEV_DEBUG_RX
5525 RTE_LOG_REGISTER_SUFFIX(ice_logtype_rx, rx, DEBUG);
5526 #endif
5527 #ifdef RTE_ETHDEV_DEBUG_TX
5528 RTE_LOG_REGISTER_SUFFIX(ice_logtype_tx, tx, DEBUG);
5529 #endif